fwohci.c revision 111942
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 111942 2003-03-06 05:06:44Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45109890Ssimokawa#include <sys/proc.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/types.h> 48103285Sikob#include <sys/mbuf.h> 49103285Sikob#include <sys/mman.h> 50103285Sikob#include <sys/socket.h> 51103285Sikob#include <sys/socketvar.h> 52103285Sikob#include <sys/signalvar.h> 53103285Sikob#include <sys/malloc.h> 54103285Sikob#include <sys/uio.h> 55103285Sikob#include <sys/sockio.h> 56103285Sikob#include <sys/bus.h> 57103285Sikob#include <sys/kernel.h> 58103285Sikob#include <sys/conf.h> 59103285Sikob 60103285Sikob#include <machine/bus.h> 61103285Sikob#include <machine/resource.h> 62103285Sikob#include <sys/rman.h> 63103285Sikob 64103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65103285Sikob#include <machine/clock.h> 66103285Sikob#include <pci/pcivar.h> 67103285Sikob#include <pci/pcireg.h> 68103285Sikob#include <vm/vm.h> 69103285Sikob#include <vm/vm_extern.h> 70103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 71103285Sikob 72103285Sikob#include <dev/firewire/firewire.h> 73103285Sikob#include <dev/firewire/firewirereg.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77103285Sikob 78109179Ssimokawa#include <dev/firewire/iec68113.h> 79109179Ssimokawa 80103285Sikob#undef OHCI_DEBUG 81106802Ssimokawa 82103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83103285Sikob "STOR","LOAD","NOP ","STOP",}; 84103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85103285Sikob "UNDEF","REG","SYS","DEV"}; 86103285Sikobchar fwohcicode[32][0x20]={ 87103285Sikob "No stat","Undef","long","miss Ack err", 88103285Sikob "underrun","overrun","desc err", "data read err", 89103285Sikob "data write err","bus reset","timeout","tcode err", 90103285Sikob "Undef","Undef","unknown event","flushed", 91103285Sikob "Undef","ack complete","ack pend","Undef", 92103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 93103285Sikob "Undef","Undef","Undef","ack tardy", 94103285Sikob "Undef","ack data_err","ack type_err",""}; 95103285Sikob#define MAX_SPEED 2 96103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 97103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99103285Sikob 100103285Sikobstatic struct tcode_info tinfo[] = { 101103285Sikob/* hdr_len block flag*/ 102103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104103285Sikob/* 2 WRES */ {12, FWTI_RES}, 105103285Sikob/* 3 XXX */ { 0, 0}, 106103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 109103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110103285Sikob/* 8 CYCS */ { 0, 0}, 111103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114103285Sikob/* c XXX */ { 0, 0}, 115103285Sikob/* d XXX */ { 0, 0}, 116103285Sikob/* e PHY */ {12, FWTI_REQ}, 117103285Sikob/* f XXX */ { 0, 0} 118103285Sikob}; 119103285Sikob 120103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 121103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 122103285Sikob 123103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125103285Sikob 126103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 127103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 128103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 129106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 134103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 146103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 149103285Sikobstatic void fwohci_timeout __P((void *)); 150103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 151103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 152103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 155103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161103285Sikob 162103285Sikob/* 163103285Sikob * memory allocated for DMA programs 164103285Sikob */ 165103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166103285Sikob 167103285Sikob/* #define NDB 1024 */ 168103285Sikob#define NDB FWMAXQUEUE 169103285Sikob#define NDVDB (DVBUF * NDB) 170103285Sikob 171103285Sikob#define OHCI_VERSION 0x00 172103285Sikob#define OHCI_CROMHDR 0x18 173103285Sikob#define OHCI_BUS_OPT 0x20 174103285Sikob#define OHCI_BUSIRMC (1 << 31) 175103285Sikob#define OHCI_BUSCMC (1 << 30) 176103285Sikob#define OHCI_BUSISC (1 << 29) 177103285Sikob#define OHCI_BUSBMC (1 << 28) 178103285Sikob#define OHCI_BUSPMC (1 << 27) 179103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 180103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 181103285Sikob 182103285Sikob#define OHCI_EUID_HI 0x24 183103285Sikob#define OHCI_EUID_LO 0x28 184103285Sikob 185103285Sikob#define OHCI_CROMPTR 0x34 186103285Sikob#define OHCI_HCCCTL 0x50 187103285Sikob#define OHCI_HCCCTLCLR 0x54 188103285Sikob#define OHCI_AREQHI 0x100 189103285Sikob#define OHCI_AREQHICLR 0x104 190103285Sikob#define OHCI_AREQLO 0x108 191103285Sikob#define OHCI_AREQLOCLR 0x10c 192103285Sikob#define OHCI_PREQHI 0x110 193103285Sikob#define OHCI_PREQHICLR 0x114 194103285Sikob#define OHCI_PREQLO 0x118 195103285Sikob#define OHCI_PREQLOCLR 0x11c 196103285Sikob#define OHCI_PREQUPPER 0x120 197103285Sikob 198103285Sikob#define OHCI_SID_BUF 0x64 199103285Sikob#define OHCI_SID_CNT 0x68 200103285Sikob#define OHCI_SID_CNT_MASK 0xffc 201103285Sikob 202103285Sikob#define OHCI_IT_STAT 0x90 203103285Sikob#define OHCI_IT_STATCLR 0x94 204103285Sikob#define OHCI_IT_MASK 0x98 205103285Sikob#define OHCI_IT_MASKCLR 0x9c 206103285Sikob 207103285Sikob#define OHCI_IR_STAT 0xa0 208103285Sikob#define OHCI_IR_STATCLR 0xa4 209103285Sikob#define OHCI_IR_MASK 0xa8 210103285Sikob#define OHCI_IR_MASKCLR 0xac 211103285Sikob 212103285Sikob#define OHCI_LNKCTL 0xe0 213103285Sikob#define OHCI_LNKCTLCLR 0xe4 214103285Sikob 215103285Sikob#define OHCI_PHYACCESS 0xec 216103285Sikob#define OHCI_CYCLETIMER 0xf0 217103285Sikob 218103285Sikob#define OHCI_DMACTL(off) (off) 219103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 220103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 221103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 222103285Sikob 223103285Sikob#define OHCI_ATQOFF 0x180 224103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 225103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228103285Sikob 229103285Sikob#define OHCI_ATSOFF 0x1a0 230103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 231103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234103285Sikob 235103285Sikob#define OHCI_ARQOFF 0x1c0 236103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 237103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240103285Sikob 241103285Sikob#define OHCI_ARSOFF 0x1e0 242103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 243103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246103285Sikob 247103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251103285Sikob 252103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257103285Sikob 258103285Sikobd_ioctl_t fwohci_ioctl; 259103285Sikob 260103285Sikob/* 261103285Sikob * Communication with PHY device 262103285Sikob */ 263106790Ssimokawastatic u_int32_t 264106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265103285Sikob{ 266103285Sikob u_int32_t fun; 267103285Sikob 268103285Sikob addr &= 0xf; 269103285Sikob data &= 0xff; 270103285Sikob 271103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 273103285Sikob DELAY(100); 274103285Sikob 275103285Sikob return(fwphy_rddata( sc, addr)); 276103285Sikob} 277103285Sikob 278103285Sikobstatic u_int32_t 279103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280103285Sikob{ 281103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282103285Sikob int i; 283103285Sikob u_int32_t bm; 284103285Sikob 285103285Sikob#define OHCI_CSR_DATA 0x0c 286103285Sikob#define OHCI_CSR_COMP 0x10 287103285Sikob#define OHCI_CSR_CONT 0x14 288103285Sikob#define OHCI_BUS_MANAGER_ID 0 289103285Sikob 290103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 291103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294109280Ssimokawa DELAY(10); 295103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 296107653Ssimokawa if((bm & 0x3f) == 0x3f) 297103285Sikob bm = node; 298107653Ssimokawa if (bootverbose) 299107653Ssimokawa device_printf(sc->fc.dev, 300107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301103285Sikob 302103285Sikob return(bm); 303103285Sikob} 304103285Sikob 305106790Ssimokawastatic u_int32_t 306106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 307103285Sikob{ 308108500Ssimokawa u_int32_t fun, stat; 309108500Ssimokawa u_int i, retry = 0; 310103285Sikob 311103285Sikob addr &= 0xf; 312108500Ssimokawa#define MAX_RETRY 100 313108500Ssimokawaagain: 314108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 317108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 319103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320103285Sikob break; 321109280Ssimokawa DELAY(100); 322103285Sikob } 323108500Ssimokawa if(i >= MAX_RETRY) { 324109280Ssimokawa if (bootverbose) 325109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 326108527Ssimokawa if (++retry < MAX_RETRY) { 327109280Ssimokawa DELAY(100); 328108527Ssimokawa goto again; 329108527Ssimokawa } 330108500Ssimokawa } 331108500Ssimokawa /* Make sure that SCLK is started */ 332108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 333108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 334108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335109280Ssimokawa if (bootverbose) 336109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 337108500Ssimokawa if (++retry < MAX_RETRY) { 338109280Ssimokawa DELAY(100); 339108500Ssimokawa goto again; 340108500Ssimokawa } 341108500Ssimokawa } 342108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 343108500Ssimokawa device_printf(sc->fc.dev, 344108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345108500Ssimokawa#undef MAX_RETRY 346103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 347103285Sikob} 348103285Sikob/* Device specific ioctl. */ 349103285Sikobint 350103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351103285Sikob{ 352103285Sikob struct firewire_softc *sc; 353103285Sikob struct fwohci_softc *fc; 354103285Sikob int unit = DEV2UNIT(dev); 355103285Sikob int err = 0; 356103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357103285Sikob u_int32_t *dmach = (u_int32_t *) data; 358103285Sikob 359103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 360103285Sikob if(sc == NULL){ 361103285Sikob return(EINVAL); 362103285Sikob } 363103285Sikob fc = (struct fwohci_softc *)sc->fc; 364103285Sikob 365103285Sikob if (!data) 366103285Sikob return(EINVAL); 367103285Sikob 368103285Sikob switch (cmd) { 369103285Sikob case FWOHCI_WRREG: 370103285Sikob#define OHCI_MAX_REG 0x800 371103285Sikob if(reg->addr <= OHCI_MAX_REG){ 372103285Sikob OWRITE(fc, reg->addr, reg->data); 373103285Sikob reg->data = OREAD(fc, reg->addr); 374103285Sikob }else{ 375103285Sikob err = EINVAL; 376103285Sikob } 377103285Sikob break; 378103285Sikob case FWOHCI_RDREG: 379103285Sikob if(reg->addr <= OHCI_MAX_REG){ 380103285Sikob reg->data = OREAD(fc, reg->addr); 381103285Sikob }else{ 382103285Sikob err = EINVAL; 383103285Sikob } 384103285Sikob break; 385103285Sikob/* Read DMA descriptors for debug */ 386103285Sikob case DUMPDMA: 387103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 388103285Sikob dump_dma(fc, *dmach); 389103285Sikob dump_db(fc, *dmach); 390103285Sikob }else{ 391103285Sikob err = EINVAL; 392103285Sikob } 393103285Sikob break; 394103285Sikob default: 395103285Sikob break; 396103285Sikob } 397103285Sikob return err; 398103285Sikob} 399106790Ssimokawa 400108530Ssimokawastatic int 401108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402103285Sikob{ 403108530Ssimokawa u_int32_t reg, reg2; 404108530Ssimokawa int e1394a = 1; 405108530Ssimokawa/* 406108530Ssimokawa * probe PHY parameters 407108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 408108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 409108530Ssimokawa * number of port supported by core-logic. 410108530Ssimokawa * It is not actually available port on your PC . 411108530Ssimokawa */ 412108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413108530Ssimokawa#if 0 414108530Ssimokawa /* XXX wait for SCLK. */ 415108530Ssimokawa DELAY(100000); 416108530Ssimokawa#endif 417108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418108530Ssimokawa 419108530Ssimokawa if((reg >> 5) != 7 ){ 420108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 421108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 422108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 423108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 424108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 425108530Ssimokawa sc->fc.speed, MAX_SPEED); 426108530Ssimokawa sc->fc.speed = MAX_SPEED; 427108530Ssimokawa } 428108530Ssimokawa device_printf(dev, 429108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 430108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 431108530Ssimokawa }else{ 432108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433108530Ssimokawa sc->fc.mode |= FWPHYASYST; 434108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 435108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 437108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 438108530Ssimokawa sc->fc.speed, MAX_SPEED); 439108530Ssimokawa sc->fc.speed = MAX_SPEED; 440108530Ssimokawa } 441108530Ssimokawa device_printf(dev, 442108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 443108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 444108530Ssimokawa 445108530Ssimokawa /* check programPhyEnable */ 446108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 447108530Ssimokawa#if 0 448108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449108530Ssimokawa#else /* XXX force to enable 1394a */ 450108530Ssimokawa if (e1394a) { 451108530Ssimokawa#endif 452108530Ssimokawa if (bootverbose) 453108530Ssimokawa device_printf(dev, 454108530Ssimokawa "Enable 1394a Enhancements\n"); 455108530Ssimokawa /* enable EAA EMC */ 456108530Ssimokawa reg2 |= 0x03; 457108530Ssimokawa /* set aPhyEnhanceEnable */ 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460108530Ssimokawa } else { 461108530Ssimokawa /* for safe */ 462108530Ssimokawa reg2 &= ~0x83; 463108530Ssimokawa } 464108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 465108530Ssimokawa } 466108530Ssimokawa 467108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468108530Ssimokawa if((reg >> 5) == 7 ){ 469108530Ssimokawa reg = fwphy_rddata(sc, 4); 470108530Ssimokawa reg |= 1 << 6; 471108530Ssimokawa fwphy_wrdata(sc, 4, reg); 472108530Ssimokawa reg = fwphy_rddata(sc, 4); 473108530Ssimokawa } 474108530Ssimokawa return 0; 475108530Ssimokawa} 476108530Ssimokawa 477108530Ssimokawa 478108530Ssimokawavoid 479108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 480108530Ssimokawa{ 481108701Ssimokawa int i, max_rec, speed; 482103285Sikob u_int32_t reg, reg2; 483103285Sikob struct fwohcidb_tr *db_tr; 484103285Sikob 485108701Ssimokawa /* Disable interrupt */ 486108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487108530Ssimokawa 488108701Ssimokawa /* Now stopping all DMA channel */ 489108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa 494108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498108530Ssimokawa } 499108530Ssimokawa 500108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 501108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502108530Ssimokawa if (bootverbose) 503108530Ssimokawa device_printf(dev, "resetting OHCI..."); 504108530Ssimokawa i = 0; 505108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506108530Ssimokawa if (i++ > 100) break; 507108530Ssimokawa DELAY(1000); 508108530Ssimokawa } 509108530Ssimokawa if (bootverbose) 510108530Ssimokawa printf("done (loop=%d)\n", i); 511108530Ssimokawa 512108701Ssimokawa /* Probe phy */ 513108701Ssimokawa fwohci_probe_phy(sc, dev); 514108701Ssimokawa 515108701Ssimokawa /* Probe link */ 516108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 517108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 518108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 519108701Ssimokawa speed = (reg & 0x00000007); 520108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 521108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 522108701Ssimokawa /* XXX fix max_rec */ 523108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 524108701Ssimokawa if (max_rec != sc->fc.maxrec) { 525108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 527108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528108701Ssimokawa } 529108530Ssimokawa if (bootverbose) 530108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 532108530Ssimokawa 533108701Ssimokawa /* Initialize registers */ 534108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535108530Ssimokawa OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538108642Ssimokawa OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540108701Ssimokawa fw_busreset(&sc->fc); 541108530Ssimokawa 542108701Ssimokawa /* Enable link */ 543108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544108642Ssimokawa 545108701Ssimokawa /* Force to start async RX DMA */ 546108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 549108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 550108530Ssimokawa 551108701Ssimokawa /* Initialize async TX */ 552108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554108701Ssimokawa /* AT Retries */ 555108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 556108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560108530Ssimokawa db_tr->xfer = NULL; 561108530Ssimokawa } 562108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564108530Ssimokawa db_tr->xfer = NULL; 565108530Ssimokawa } 566108530Ssimokawa 567108701Ssimokawa 568108701Ssimokawa /* Enable interrupt */ 569108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 570108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 571108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 575108530Ssimokawa 576108530Ssimokawa} 577108530Ssimokawa 578108530Ssimokawaint 579108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 580108530Ssimokawa{ 581108530Ssimokawa int i; 582108530Ssimokawa u_int32_t reg; 583109814Ssimokawa u_int8_t ui[8]; 584108530Ssimokawa 585103285Sikob reg = OREAD(sc, OHCI_VERSION); 586103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 587103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 588103285Sikob 589110045Ssimokawa/* Available Isochrounous DMA channel probe */ 590110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 591110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 592110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 593110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 594110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 595110045Ssimokawa for (i = 0; i < 0x20; i++) 596110045Ssimokawa if ((reg & (1 << i)) == 0) 597110045Ssimokawa break; 598103285Sikob sc->fc.nisodma = i; 599103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 600103285Sikob 601103285Sikob sc->fc.arq = &sc->arrq.xferq; 602103285Sikob sc->fc.ars = &sc->arrs.xferq; 603103285Sikob sc->fc.atq = &sc->atrq.xferq; 604103285Sikob sc->fc.ats = &sc->atrs.xferq; 605103285Sikob 606103285Sikob sc->arrq.xferq.start = NULL; 607103285Sikob sc->arrs.xferq.start = NULL; 608103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 609103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 610103285Sikob 611103285Sikob sc->arrq.xferq.drain = NULL; 612103285Sikob sc->arrs.xferq.drain = NULL; 613103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 614103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 615103285Sikob 616103285Sikob sc->arrq.ndesc = 1; 617103285Sikob sc->arrs.ndesc = 1; 618110593Ssimokawa sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 619110593Ssimokawa sc->atrs.ndesc = 2; 620103285Sikob 621103285Sikob sc->arrq.ndb = NDB; 622103285Sikob sc->arrs.ndb = NDB / 2; 623103285Sikob sc->atrq.ndb = NDB; 624103285Sikob sc->atrs.ndb = NDB / 2; 625103285Sikob 626103285Sikob sc->arrq.dummy = NULL; 627103285Sikob sc->arrs.dummy = NULL; 628103285Sikob sc->atrq.dummy = NULL; 629103285Sikob sc->atrs.dummy = NULL; 630103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 631103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 632103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 633103285Sikob sc->it[i].ndb = 0; 634103285Sikob sc->ir[i].ndb = 0; 635103285Sikob } 636103285Sikob 637103285Sikob sc->fc.tcode = tinfo; 638103285Sikob 639110195Ssimokawa sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_FW, M_NOWAIT); 640103285Sikob 641103285Sikob if(sc->cromptr == NULL){ 642108527Ssimokawa device_printf(dev, "cromptr alloc failed."); 643103285Sikob return ENOMEM; 644103285Sikob } 645103285Sikob sc->fc.dev = dev; 646103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647103285Sikob 648103285Sikob sc->fc.config_rom[1] = 0x31333934; 649103285Sikob sc->fc.config_rom[2] = 0xf000a002; 650103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652103285Sikob sc->fc.config_rom[5] = 0; 653103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654103285Sikob 655103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656103285Sikob 657103285Sikob 658103285Sikob/* SID recieve buffer must allign 2^11 */ 659103285Sikob#define OHCI_SIDSIZE (1 << 11) 660110195Ssimokawa sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 661108527Ssimokawa if (sc->fc.sid_buf == NULL) { 662108527Ssimokawa device_printf(dev, "sid_buf alloc failed.\n"); 663108527Ssimokawa return ENOMEM; 664108527Ssimokawa } 665110016Ssimokawa if (((vm_offset_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 666109736Ssimokawa device_printf(dev, "sid_buf(%p) not aligned.\n", 667109736Ssimokawa sc->fc.sid_buf); 668109736Ssimokawa return ENOMEM; 669109736Ssimokawa } 670108530Ssimokawa 671103285Sikob fwohci_db_init(&sc->arrq); 672108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 673108527Ssimokawa return ENOMEM; 674108527Ssimokawa 675103285Sikob fwohci_db_init(&sc->arrs); 676108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 677108527Ssimokawa return ENOMEM; 678103285Sikob 679103285Sikob fwohci_db_init(&sc->atrq); 680108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 681108527Ssimokawa return ENOMEM; 682108527Ssimokawa 683103285Sikob fwohci_db_init(&sc->atrs); 684108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 685108527Ssimokawa return ENOMEM; 686103285Sikob 687109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 688109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 689109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 690109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 691103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 693109814Ssimokawa 694103285Sikob sc->fc.ioctl = fwohci_ioctl; 695103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 696103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 697103285Sikob sc->fc.ibr = fwohci_ibr; 698103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 699103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 700103285Sikob 701103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 702103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 703103285Sikob sc->fc.irx_post = fwohci_irx_post; 704103285Sikob sc->fc.itx_post = NULL; 705103285Sikob sc->fc.timeout = fwohci_timeout; 706103285Sikob sc->fc.poll = fwohci_poll; 707103285Sikob sc->fc.set_intr = fwohci_set_intr; 708106790Ssimokawa 709108530Ssimokawa fw_init(&sc->fc); 710108530Ssimokawa fwohci_reset(sc, dev); 711103285Sikob 712108530Ssimokawa return 0; 713103285Sikob} 714106790Ssimokawa 715106790Ssimokawavoid 716106790Ssimokawafwohci_timeout(void *arg) 717103285Sikob{ 718103285Sikob struct fwohci_softc *sc; 719103285Sikob 720103285Sikob sc = (struct fwohci_softc *)arg; 721103285Sikob} 722106790Ssimokawa 723106790Ssimokawau_int32_t 724106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 725103285Sikob{ 726103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 727103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 728103285Sikob} 729103285Sikob 730108527Ssimokawaint 731108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 732108527Ssimokawa{ 733108527Ssimokawa int i; 734108527Ssimokawa 735108527Ssimokawa if (sc->fc.sid_buf != NULL) 736110195Ssimokawa free((void *)(uintptr_t)sc->fc.sid_buf, M_FW); 737108527Ssimokawa if (sc->cromptr != NULL) 738110195Ssimokawa free((void *)sc->cromptr, M_FW); 739108527Ssimokawa 740108527Ssimokawa fwohci_db_free(&sc->arrq); 741108527Ssimokawa fwohci_db_free(&sc->arrs); 742108527Ssimokawa 743108527Ssimokawa fwohci_db_free(&sc->atrq); 744108527Ssimokawa fwohci_db_free(&sc->atrs); 745108527Ssimokawa 746108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 747108527Ssimokawa fwohci_db_free(&sc->it[i]); 748108527Ssimokawa fwohci_db_free(&sc->ir[i]); 749108527Ssimokawa } 750108527Ssimokawa 751108527Ssimokawa return 0; 752108527Ssimokawa} 753108527Ssimokawa 754108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 755108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 756108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 757108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 758108655Ssimokawa} while (0) 759108655Ssimokawa 760106790Ssimokawastatic void 761106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 762103285Sikob{ 763103285Sikob int i, s; 764103285Sikob int tcode, hdr_len, hdr_off, len; 765103285Sikob int fsegment = -1; 766103285Sikob u_int32_t off; 767103285Sikob struct fw_xfer *xfer; 768103285Sikob struct fw_pkt *fp; 769103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 770103285Sikob struct fwohcidb_tr *db_tr; 771103285Sikob volatile struct fwohcidb *db; 772103285Sikob struct mbuf *m; 773103285Sikob struct tcode_info *info; 774108655Ssimokawa static int maxdesc=0; 775103285Sikob 776103285Sikob if(&sc->atrq == dbch){ 777103285Sikob off = OHCI_ATQOFF; 778103285Sikob }else if(&sc->atrs == dbch){ 779103285Sikob off = OHCI_ATSOFF; 780103285Sikob }else{ 781103285Sikob return; 782103285Sikob } 783103285Sikob 784103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 785103285Sikob return; 786103285Sikob 787103285Sikob s = splfw(); 788103285Sikob db_tr = dbch->top; 789103285Sikobtxloop: 790103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 791103285Sikob if(xfer == NULL){ 792103285Sikob goto kick; 793103285Sikob } 794103285Sikob if(dbch->xferq.queued == 0 ){ 795103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 796103285Sikob } 797103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 798103285Sikob db_tr->xfer = xfer; 799103285Sikob xfer->state = FWXF_START; 800103285Sikob dbch->xferq.packets++; 801103285Sikob 802103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 803103285Sikob tcode = fp->mode.common.tcode; 804103285Sikob 805103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 806103285Sikob info = &tinfo[tcode]; 807103285Sikob hdr_len = hdr_off = info->hdr_len; 808103285Sikob /* fw_asyreq must pass valid send.len */ 809103285Sikob len = xfer->send.len; 810103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 811103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 812103285Sikob } 813103285Sikob ohcifp->mode.common.spd = xfer->spd; 814103285Sikob if (tcode == FWTCODE_STREAM ){ 815103285Sikob hdr_len = 8; 816103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 817103285Sikob } else if (tcode == FWTCODE_PHY) { 818103285Sikob hdr_len = 12; 819103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 820103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 821103285Sikob ohcifp->mode.common.spd = 0; 822103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 823103285Sikob } else { 824103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 825103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 826103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 827103285Sikob } 828103285Sikob db = &db_tr->db[0]; 829109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 830109892Ssimokawa db->db.desc.reqcount = hdr_len; 831103285Sikob db->db.desc.status = 0; 832103285Sikob/* Specify bound timer of asy. responce */ 833103285Sikob if(&sc->atrs == dbch){ 834103285Sikob db->db.desc.count 835103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 836103285Sikob } 837103285Sikob 838111942Ssimokawaagain: 839103285Sikob db_tr->dbcnt = 2; 840103285Sikob db = &db_tr->db[db_tr->dbcnt]; 841103285Sikob if(len > hdr_off){ 842103285Sikob if (xfer->mbuf == NULL) { 843103285Sikob db->db.desc.addr 844103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 845109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE; 846109892Ssimokawa db->db.desc.reqcount = len - hdr_off; 847103285Sikob db->db.desc.status = 0; 848103285Sikob 849103285Sikob db_tr->dbcnt++; 850103285Sikob } else { 851109890Ssimokawa int mchain=0; 852111942Ssimokawa /* XXX we can handle only 6 (=8-2) mbuf chains */ 853108655Ssimokawa for (m = xfer->mbuf; m != NULL; m = m->m_next) { 854108655Ssimokawa if (m->m_len == 0) 855109890Ssimokawa /* unrecoverable error could occur. */ 856108655Ssimokawa continue; 857109890Ssimokawa mchain++; 858109890Ssimokawa if (db_tr->dbcnt >= dbch->ndesc) 859109890Ssimokawa continue; 860103285Sikob db->db.desc.addr 861103285Sikob = vtophys(mtod(m, caddr_t)); 862109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE; 863109892Ssimokawa db->db.desc.reqcount = m->m_len; 864103285Sikob db->db.desc.status = 0; 865103285Sikob db++; 866103285Sikob db_tr->dbcnt++; 867108655Ssimokawa } 868111942Ssimokawa if (mchain > dbch->ndesc - 2) { 869111942Ssimokawa struct mbuf *m_new; 870111942Ssimokawa if (bootverbose) 871111942Ssimokawa device_printf(sc->fc.dev, 872111942Ssimokawa "too long mbuf chain(%d)\n", 873111942Ssimokawa mchain); 874111942Ssimokawa m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 875111942Ssimokawa if (m_new != NULL) { 876111942Ssimokawa m_copydata(xfer->mbuf, 0, 877111942Ssimokawa xfer->mbuf->m_pkthdr.len, 878111942Ssimokawa mtod(m_new, caddr_t)); 879111942Ssimokawa m_new->m_pkthdr.len = m_new->m_len = 880111942Ssimokawa xfer->mbuf->m_pkthdr.len; 881111942Ssimokawa m_freem(xfer->mbuf); 882111942Ssimokawa xfer->mbuf = m_new; 883111942Ssimokawa goto again; 884111942Ssimokawa } 885111942Ssimokawa device_printf(sc->fc.dev, "m_getcl failed.\n"); 886111942Ssimokawa } 887103285Sikob } 888103285Sikob } 889108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 890108655Ssimokawa maxdesc = db_tr->dbcnt; 891108655Ssimokawa if (bootverbose) 892108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 893108655Ssimokawa } 894103285Sikob /* last db */ 895103285Sikob LAST_DB(db_tr, db); 896109892Ssimokawa db->db.desc.control |= OHCI_OUTPUT_LAST 897103285Sikob | OHCI_INTERRUPT_ALWAYS 898103285Sikob | OHCI_BRANCH_ALWAYS; 899103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 900103285Sikob 901103285Sikob if(fsegment == -1 ) 902103285Sikob fsegment = db_tr->dbcnt; 903103285Sikob if (dbch->pdb_tr != NULL) { 904103285Sikob LAST_DB(dbch->pdb_tr, db); 905103285Sikob db->db.desc.depend |= db_tr->dbcnt; 906103285Sikob } 907103285Sikob dbch->pdb_tr = db_tr; 908103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 909103285Sikob if(db_tr != dbch->bottom){ 910103285Sikob goto txloop; 911103285Sikob } else { 912107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 913103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 914103285Sikob } 915103285Sikobkick: 916103285Sikob /* kick asy q */ 917103285Sikob 918103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 919103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 920103285Sikob } else { 921107653Ssimokawa if (bootverbose) 922107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 923103285Sikob OREAD(sc, OHCI_DMACTL(off))); 924103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 925103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 926103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 927103285Sikob } 928106790Ssimokawa 929103285Sikob dbch->top = db_tr; 930103285Sikob splx(s); 931103285Sikob return; 932103285Sikob} 933106790Ssimokawa 934106790Ssimokawastatic void 935106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 936103285Sikob{ 937103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 938103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 939103285Sikob return; 940103285Sikob} 941106790Ssimokawa 942106790Ssimokawastatic void 943106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 944103285Sikob{ 945103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 946103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 947103285Sikob return; 948103285Sikob} 949106790Ssimokawa 950106790Ssimokawastatic void 951106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 952103285Sikob{ 953103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 954103285Sikob fwohci_start( sc, &(sc->atrq)); 955103285Sikob return; 956103285Sikob} 957106790Ssimokawa 958106790Ssimokawastatic void 959106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 960103285Sikob{ 961103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 962103285Sikob fwohci_start( sc, &(sc->atrs)); 963103285Sikob return; 964103285Sikob} 965106790Ssimokawa 966106790Ssimokawavoid 967106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 968103285Sikob{ 969103285Sikob int s, err = 0; 970103285Sikob struct fwohcidb_tr *tr; 971103285Sikob volatile struct fwohcidb *db; 972103285Sikob struct fw_xfer *xfer; 973103285Sikob u_int32_t off; 974103285Sikob u_int stat; 975103285Sikob int packets; 976103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 977103285Sikob if(&sc->atrq == dbch){ 978103285Sikob off = OHCI_ATQOFF; 979103285Sikob }else if(&sc->atrs == dbch){ 980103285Sikob off = OHCI_ATSOFF; 981103285Sikob }else{ 982103285Sikob return; 983103285Sikob } 984103285Sikob s = splfw(); 985103285Sikob tr = dbch->bottom; 986103285Sikob packets = 0; 987103285Sikob while(dbch->xferq.queued > 0){ 988103285Sikob LAST_DB(tr, db); 989103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 990103285Sikob if (fc->status != FWBUSRESET) 991103285Sikob /* maybe out of order?? */ 992103285Sikob goto out; 993103285Sikob } 994103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 995103285Sikob#ifdef OHCI_DEBUG 996103285Sikob dump_dma(sc, ch); 997103285Sikob dump_db(sc, ch); 998103285Sikob#endif 999103285Sikob/* Stop DMA */ 1000103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1001103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 1002103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1003103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 1004103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 1005103285Sikob } 1006103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 1007103285Sikob switch(stat){ 1008110577Ssimokawa case FWOHCIEV_ACKPEND: 1009103285Sikob case FWOHCIEV_ACKCOMPL: 1010103285Sikob err = 0; 1011103285Sikob break; 1012103285Sikob case FWOHCIEV_ACKBSA: 1013103285Sikob case FWOHCIEV_ACKBSB: 1014110577Ssimokawa case FWOHCIEV_ACKBSX: 1015103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1016103285Sikob err = EBUSY; 1017103285Sikob break; 1018103285Sikob case FWOHCIEV_FLUSHED: 1019103285Sikob case FWOHCIEV_ACKTARD: 1020103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1021103285Sikob err = EAGAIN; 1022103285Sikob break; 1023103285Sikob case FWOHCIEV_MISSACK: 1024103285Sikob case FWOHCIEV_UNDRRUN: 1025103285Sikob case FWOHCIEV_OVRRUN: 1026103285Sikob case FWOHCIEV_DESCERR: 1027103285Sikob case FWOHCIEV_DTRDERR: 1028103285Sikob case FWOHCIEV_TIMEOUT: 1029103285Sikob case FWOHCIEV_TCODERR: 1030103285Sikob case FWOHCIEV_UNKNOWN: 1031103285Sikob case FWOHCIEV_ACKDERR: 1032103285Sikob case FWOHCIEV_ACKTERR: 1033103285Sikob default: 1034103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1035103285Sikob stat, fwohcicode[stat]); 1036103285Sikob err = EINVAL; 1037103285Sikob break; 1038103285Sikob } 1039110577Ssimokawa if (tr->xfer != NULL) { 1040103285Sikob xfer = tr->xfer; 1041103285Sikob xfer->state = FWXF_SENT; 1042110577Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1043103285Sikob xfer->state = FWXF_BUSY; 1044110577Ssimokawa switch (xfer->act_type) { 1045103285Sikob case FWACT_XFER: 1046103285Sikob xfer->resp = err; 1047110577Ssimokawa if (xfer->retry_req != NULL) 1048103285Sikob xfer->retry_req(xfer); 1049110577Ssimokawa else 1050110577Ssimokawa fw_xfer_done(xfer); 1051103285Sikob break; 1052103285Sikob default: 1053103285Sikob break; 1054103285Sikob } 1055110577Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1056103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1057103285Sikob xfer->state = FWXF_SENTERR; 1058103285Sikob xfer->resp = err; 1059110577Ssimokawa switch (xfer->act_type) { 1060103285Sikob case FWACT_XFER: 1061103285Sikob fw_xfer_done(xfer); 1062103285Sikob break; 1063103285Sikob default: 1064103285Sikob break; 1065103285Sikob } 1066103285Sikob } 1067110577Ssimokawa /* 1068110577Ssimokawa * The watchdog timer takes care of split 1069110577Ssimokawa * transcation timeout for ACKPEND case. 1070110577Ssimokawa */ 1071103285Sikob } 1072110269Ssimokawa dbch->xferq.queued --; 1073103285Sikob tr->xfer = NULL; 1074103285Sikob 1075103285Sikob packets ++; 1076103285Sikob tr = STAILQ_NEXT(tr, link); 1077103285Sikob dbch->bottom = tr; 1078103285Sikob } 1079103285Sikobout: 1080103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1081103285Sikob printf("make free slot\n"); 1082103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1083103285Sikob fwohci_start(sc, dbch); 1084103285Sikob } 1085103285Sikob splx(s); 1086103285Sikob} 1087106790Ssimokawa 1088106790Ssimokawastatic void 1089106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1090103285Sikob{ 1091110269Ssimokawa int i, s, found=0; 1092103285Sikob struct fwohcidb_tr *tr; 1093103285Sikob 1094103285Sikob if(xfer->state != FWXF_START) return; 1095103285Sikob 1096103285Sikob s = splfw(); 1097103285Sikob tr = dbch->bottom; 1098110269Ssimokawa for (i = 0; i < dbch->xferq.queued; i ++) { 1099103285Sikob if(tr->xfer == xfer){ 1100103285Sikob tr->xfer = NULL; 1101110269Ssimokawa#if 0 1102103285Sikob dbch->xferq.queued --; 1103103285Sikob /* XXX */ 1104103285Sikob if (tr == dbch->bottom) 1105103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1106103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1107103285Sikob printf("fwohci_drain: make slot\n"); 1108103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1109103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1110103285Sikob } 1111110269Ssimokawa#endif 1112110269Ssimokawa found ++; 1113103285Sikob break; 1114103285Sikob } 1115103285Sikob tr = STAILQ_NEXT(tr, link); 1116103285Sikob } 1117103285Sikob splx(s); 1118110269Ssimokawa if (!found) 1119110269Ssimokawa device_printf(fc->dev, "fwochi_drain: xfer not found\n"); 1120103285Sikob return; 1121103285Sikob} 1122103285Sikob 1123106790Ssimokawastatic void 1124106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1125103285Sikob{ 1126103285Sikob struct fwohcidb_tr *db_tr; 1127109379Ssimokawa int idb, i; 1128103285Sikob 1129108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1130108527Ssimokawa return; 1131108527Ssimokawa 1132103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1133103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1134103285Sikob idb < dbch->ndb; 1135103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1136108527Ssimokawa if (db_tr->buf != NULL) { 1137110195Ssimokawa free(db_tr->buf, M_FW); 1138108527Ssimokawa db_tr->buf = NULL; 1139108527Ssimokawa } 1140103285Sikob } 1141103285Sikob } 1142103285Sikob dbch->ndb = 0; 1143103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1144109379Ssimokawa for (i = 0; i < dbch->npages; i++) 1145110195Ssimokawa free(dbch->pages[i], M_FW); 1146110195Ssimokawa free(db_tr, M_FW); 1147103285Sikob STAILQ_INIT(&dbch->db_trq); 1148108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1149103285Sikob} 1150106790Ssimokawa 1151106790Ssimokawastatic void 1152106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1153103285Sikob{ 1154103285Sikob int idb; 1155103285Sikob struct fwohcidb_tr *db_tr; 1156109379Ssimokawa int ndbpp, i, j; 1157108642Ssimokawa 1158108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1159108642Ssimokawa goto out; 1160108642Ssimokawa 1161103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1162103285Sikob /* DB entry must start at 16 bytes bounary. */ 1163103285Sikob STAILQ_INIT(&dbch->db_trq); 1164103285Sikob db_tr = (struct fwohcidb_tr *) 1165103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1166110273Ssimokawa M_FW, M_ZERO); 1167103285Sikob if(db_tr == NULL){ 1168109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1169103285Sikob return; 1170103285Sikob } 1171109379Ssimokawa 1172109379Ssimokawa ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1173109379Ssimokawa dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1174109403Ssimokawa if (firewire_debug) 1175109403Ssimokawa printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1176109403Ssimokawa dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1177109379Ssimokawa if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1178109379Ssimokawa printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1179109379Ssimokawa dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1180103285Sikob return; 1181103285Sikob } 1182109379Ssimokawa for (i = 0; i < dbch->npages; i++) { 1183110273Ssimokawa dbch->pages[i] = malloc(PAGE_SIZE, M_FW, M_ZERO); 1184109379Ssimokawa if (dbch->pages[i] == NULL) { 1185109379Ssimokawa printf("fwohci_db_init: malloc(2) failed\n"); 1186109379Ssimokawa for (j = 0; j < i; j ++) 1187110195Ssimokawa free(dbch->pages[j], M_FW); 1188110195Ssimokawa free(db_tr, M_FW); 1189109379Ssimokawa return; 1190109379Ssimokawa } 1191109379Ssimokawa } 1192103285Sikob /* Attach DB to DMA ch. */ 1193103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1194103285Sikob db_tr->dbcnt = 0; 1195109379Ssimokawa db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1196109379Ssimokawa + dbch->ndesc * (idb % ndbpp); 1197103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1198108530Ssimokawa if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1199108530Ssimokawa dbch->xferq.bnpacket != 0) { 1200108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1201108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1202108530Ssimokawa ].start = (caddr_t)db_tr; 1203108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1204108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1205108530Ssimokawa ].end = (caddr_t)db_tr; 1206103285Sikob } 1207103285Sikob db_tr++; 1208103285Sikob } 1209103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1210103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1211108642Ssimokawaout: 1212108642Ssimokawa dbch->frag.buf = NULL; 1213108642Ssimokawa dbch->frag.len = 0; 1214108642Ssimokawa dbch->frag.plen = 0; 1215108642Ssimokawa dbch->xferq.queued = 0; 1216108642Ssimokawa dbch->pdb_tr = NULL; 1217103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1218103285Sikob dbch->bottom = dbch->top; 1219108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1220103285Sikob} 1221106790Ssimokawa 1222106790Ssimokawastatic int 1223106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1224103285Sikob{ 1225103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1226109890Ssimokawa int dummy; 1227109890Ssimokawa 1228103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1229103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1230103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1231109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1232109890Ssimokawa tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1233103285Sikob fwohci_db_free(&sc->it[dmach]); 1234103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1235103285Sikob return 0; 1236103285Sikob} 1237106790Ssimokawa 1238106790Ssimokawastatic int 1239106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1240103285Sikob{ 1241103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1242109890Ssimokawa int dummy; 1243103285Sikob 1244103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1245103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1246103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1247109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1248109890Ssimokawa tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1249103285Sikob if(sc->ir[dmach].dummy != NULL){ 1250110195Ssimokawa free(sc->ir[dmach].dummy, M_FW); 1251103285Sikob } 1252103285Sikob sc->ir[dmach].dummy = NULL; 1253103285Sikob fwohci_db_free(&sc->ir[dmach]); 1254103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1255103285Sikob return 0; 1256103285Sikob} 1257106790Ssimokawa 1258106790Ssimokawastatic void 1259106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1260103285Sikob{ 1261103285Sikob qld[0] = ntohl(qld[0]); 1262103285Sikob return; 1263103285Sikob} 1264106790Ssimokawa 1265106790Ssimokawastatic int 1266106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1267103285Sikob{ 1268103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1269103285Sikob int err = 0; 1270103285Sikob unsigned short tag, ich; 1271103285Sikob 1272103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1273103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1274103285Sikob 1275103285Sikob#if 0 1276103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1277103285Sikob wakeup(fc->ir[dmach]); 1278103285Sikob return err; 1279103285Sikob } 1280103285Sikob#endif 1281103285Sikob 1282103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1283103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1284103285Sikob sc->ir[dmach].xferq.queued = 0; 1285103285Sikob sc->ir[dmach].ndb = NDB; 1286109379Ssimokawa sc->ir[dmach].xferq.psize = PAGE_SIZE; 1287103285Sikob sc->ir[dmach].ndesc = 1; 1288103285Sikob fwohci_db_init(&sc->ir[dmach]); 1289109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1290109179Ssimokawa return ENOMEM; 1291103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1292103285Sikob } 1293103285Sikob if(err){ 1294103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1295103285Sikob return err; 1296103285Sikob } 1297103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1298103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1299103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1300103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1301103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1302103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1303103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1304103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1305103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1306103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1307103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1308103285Sikob } 1309103285Sikob return err; 1310103285Sikob} 1311106790Ssimokawa 1312106790Ssimokawastatic int 1313106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1314103285Sikob{ 1315103285Sikob int err = 0; 1316103285Sikob int idb, z, i, dmach = 0; 1317103285Sikob u_int32_t off = NULL; 1318103285Sikob struct fwohcidb_tr *db_tr; 1319109892Ssimokawa volatile struct fwohcidb *db; 1320103285Sikob 1321103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1322103285Sikob err = EINVAL; 1323103285Sikob return err; 1324103285Sikob } 1325103285Sikob z = dbch->ndesc; 1326103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1327103285Sikob if( &sc->it[dmach] == dbch){ 1328103285Sikob off = OHCI_ITOFF(dmach); 1329103285Sikob break; 1330103285Sikob } 1331103285Sikob } 1332103285Sikob if(off == NULL){ 1333103285Sikob err = EINVAL; 1334103285Sikob return err; 1335103285Sikob } 1336103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1337103285Sikob return err; 1338103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1339103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1340103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1341103285Sikob } 1342103285Sikob db_tr = dbch->top; 1343103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1344103285Sikob fwohci_add_tx_buf(db_tr, 1345103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1346103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1347103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1348103285Sikob break; 1349103285Sikob } 1350109892Ssimokawa db = db_tr->db; 1351109892Ssimokawa db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend 1352103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1353103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1354103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1355109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control 1356103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1357109280Ssimokawa /* OHCI 1.1 and above */ 1358109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 1359109892Ssimokawa#if 0 1360109892Ssimokawa db[0].db.desc.depend &= ~0xf; 1361109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf; 1362109892Ssimokawa#endif 1363103285Sikob } 1364103285Sikob } 1365103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1366103285Sikob } 1367103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1368103285Sikob return err; 1369103285Sikob} 1370106790Ssimokawa 1371106790Ssimokawastatic int 1372106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1373103285Sikob{ 1374103285Sikob int err = 0; 1375109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1376103285Sikob u_int32_t off = NULL; 1377103285Sikob struct fwohcidb_tr *db_tr; 1378109892Ssimokawa volatile struct fwohcidb *db; 1379103285Sikob 1380103285Sikob z = dbch->ndesc; 1381103285Sikob if(&sc->arrq == dbch){ 1382103285Sikob off = OHCI_ARQOFF; 1383103285Sikob }else if(&sc->arrs == dbch){ 1384103285Sikob off = OHCI_ARSOFF; 1385103285Sikob }else{ 1386103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1387103285Sikob if( &sc->ir[dmach] == dbch){ 1388103285Sikob off = OHCI_IROFF(dmach); 1389103285Sikob break; 1390103285Sikob } 1391103285Sikob } 1392103285Sikob } 1393103285Sikob if(off == NULL){ 1394103285Sikob err = EINVAL; 1395103285Sikob return err; 1396103285Sikob } 1397103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1398103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1399103285Sikob return err; 1400103285Sikob }else{ 1401103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1402103285Sikob err = EBUSY; 1403103285Sikob return err; 1404103285Sikob } 1405103285Sikob } 1406103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1407108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1408103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1409103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1410103285Sikob } 1411103285Sikob db_tr = dbch->top; 1412103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1413103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1414103285Sikob fwohci_add_rx_buf(db_tr, 1415103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1416103285Sikob }else{ 1417103285Sikob fwohci_add_rx_buf(db_tr, 1418103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1419111942Ssimokawa dbch->xferq.bulkxfer[idb 1420111942Ssimokawa / dbch->xferq.bnpacket].buf 1421111942Ssimokawa + dbch->xferq.psize * 1422111942Ssimokawa (idb % dbch->xferq.bnpacket), 1423103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1424103285Sikob } 1425103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1426103285Sikob break; 1427103285Sikob } 1428109892Ssimokawa db = db_tr->db; 1429109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1430109892Ssimokawa db[ldesc].db.desc.depend 1431103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1432103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1433103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1434109892Ssimokawa db[ldesc].db.desc.control 1435103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1436109892Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1437103285Sikob } 1438103285Sikob } 1439103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1440103285Sikob } 1441103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1442103285Sikob dbch->buf_offset = 0; 1443103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1444103285Sikob return err; 1445103285Sikob }else{ 1446103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1447103285Sikob } 1448103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1449103285Sikob return err; 1450103285Sikob} 1451106790Ssimokawa 1452106790Ssimokawastatic int 1453109890Ssimokawafwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1454109890Ssimokawa{ 1455109890Ssimokawa int sec, cycle, cycle_match; 1456109890Ssimokawa 1457109890Ssimokawa cycle = cycle_now & 0x1fff; 1458109890Ssimokawa sec = cycle_now >> 13; 1459109890Ssimokawa#define CYCLE_MOD 0x10 1460109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1461109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1462109890Ssimokawa if (cycle >= 8000) { 1463109890Ssimokawa sec ++; 1464109890Ssimokawa cycle -= 8000; 1465109890Ssimokawa } 1466109890Ssimokawa cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1467109890Ssimokawa if (cycle >= 8000) { 1468109890Ssimokawa sec ++; 1469109890Ssimokawa if (cycle == 8000) 1470109890Ssimokawa cycle = 0; 1471109890Ssimokawa else 1472109890Ssimokawa cycle = CYCLE_MOD; 1473109890Ssimokawa } 1474109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1475109890Ssimokawa 1476109890Ssimokawa return(cycle_match); 1477109890Ssimokawa} 1478109890Ssimokawa 1479109890Ssimokawastatic int 1480106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1481103285Sikob{ 1482103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1483103285Sikob int err = 0; 1484103285Sikob unsigned short tag, ich; 1485103285Sikob struct fwohci_dbch *dbch; 1486109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1487109356Ssimokawa u_int32_t stat; 1488109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1489109890Ssimokawa struct fw_xferq *it; 1490103285Sikob 1491103285Sikob dbch = &sc->it[dmach]; 1492109890Ssimokawa it = &dbch->xferq; 1493109890Ssimokawa 1494109890Ssimokawa tag = (it->flag >> 6) & 3; 1495109890Ssimokawa ich = it->flag & 0x3f; 1496109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1497109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1498103285Sikob dbch->ndesc = 3; 1499103285Sikob fwohci_db_init(dbch); 1500109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1501109179Ssimokawa return ENOMEM; 1502103285Sikob err = fwohci_tx_enable(sc, dbch); 1503103285Sikob } 1504103285Sikob if(err) 1505103285Sikob return err; 1506109890Ssimokawa 1507109892Ssimokawa ldesc = dbch->ndesc - 1; 1508109890Ssimokawa s = splfw(); 1509109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1510109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1511109890Ssimokawa volatile struct fwohcidb *db; 1512109890Ssimokawa 1513109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1514109892Ssimokawa#if 0 1515109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1516109890Ssimokawa db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1517109890Ssimokawa db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1518109890Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1519109890Ssimokawa db[0].db.desc.depend &= ~0xf; 1520109892Ssimokawa#endif 1521109890Ssimokawa if (prev != NULL) { 1522109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1523109892Ssimokawa db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS; 1524109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1525109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1526109890Ssimokawa vtophys(((struct fwohcidb_tr *) 1527109890Ssimokawa (chunk->start))->db) | dbch->ndesc; 1528109892Ssimokawa#else 1529109892Ssimokawa db[0].db.desc.depend |= dbch->ndesc; 1530109892Ssimokawa db[ldesc].db.desc.depend |= dbch->ndesc; 1531109892Ssimokawa#endif 1532103285Sikob } 1533109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1534109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1535109890Ssimokawa prev = chunk; 1536109403Ssimokawa } 1537109890Ssimokawa splx(s); 1538109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1539109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1540109890Ssimokawa return 0; 1541109890Ssimokawa 1542109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1543109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1544109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1545109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1546109890Ssimokawa 1547109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1548109890Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1549109890Ssimokawa (first->start))->db) | dbch->ndesc); 1550109890Ssimokawa if (firewire_debug) 1551109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1552109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1553109890Ssimokawa#if 1 1554109890Ssimokawa /* Don't start until all chunks are buffered */ 1555109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1556109890Ssimokawa goto out; 1557109890Ssimokawa#endif 1558109802Ssimokawa#ifdef FWXFERQ_DV 1559109890Ssimokawa#define CYCLE_OFFSET 1 1560103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1561109802Ssimokawa struct fw_pkt *fp; 1562109802Ssimokawa struct fwohcidb_tr *db_tr; 1563109802Ssimokawa 1564103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1565103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1566109356Ssimokawa dbch->xferq.dvoffset = CYCLE_OFFSET; 1567109179Ssimokawa fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1568103285Sikob } 1569109802Ssimokawa#endif 1570109890Ssimokawa /* Clear cycle match counter bits */ 1571109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1572109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1573109890Ssimokawa 1574109356Ssimokawa /* 2bit second + 13bit cycle */ 1575109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1576109890Ssimokawa cycle_match = fwochi_next_cycle(fc, cycle_now); 1577109890Ssimokawa 1578109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1579109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1580109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1581109403Ssimokawa if (firewire_debug) 1582109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1583109403Ssimokawa cycle_now, cycle_match); 1584109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1585109890Ssimokawa device_printf(sc->fc.dev, 1586109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1587109403Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1588103285Sikob } 1589109890Ssimokawaout: 1590103285Sikob return err; 1591103285Sikob} 1592106790Ssimokawa 1593106790Ssimokawastatic int 1594106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1595103285Sikob{ 1596103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1597109890Ssimokawa int err = 0, s, ldesc; 1598103285Sikob unsigned short tag, ich; 1599109736Ssimokawa u_int32_t stat; 1600109890Ssimokawa struct fwohci_dbch *dbch; 1601109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1602109890Ssimokawa struct fw_xferq *ir; 1603103285Sikob 1604109890Ssimokawa dbch = &sc->ir[dmach]; 1605109890Ssimokawa ir = &dbch->xferq; 1606109890Ssimokawa 1607109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1608109890Ssimokawa tag = (ir->flag >> 6) & 3; 1609109890Ssimokawa ich = ir->flag & 0x3f; 1610108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1611108995Ssimokawa 1612109890Ssimokawa ir->queued = 0; 1613109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1614109890Ssimokawa dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1615110273Ssimokawa M_FW, 0); 1616109890Ssimokawa if (dbch->dummy == NULL) { 1617103285Sikob err = ENOMEM; 1618103285Sikob return err; 1619103285Sikob } 1620109890Ssimokawa dbch->ndesc = 2; 1621109890Ssimokawa fwohci_db_init(dbch); 1622109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1623109179Ssimokawa return ENOMEM; 1624109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1625103285Sikob } 1626103285Sikob if(err) 1627103285Sikob return err; 1628103285Sikob 1629109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1630109890Ssimokawa if (first == NULL) { 1631109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1632109890Ssimokawa return 0; 1633109890Ssimokawa } 1634109890Ssimokawa 1635111892Ssimokawa ldesc = dbch->ndesc - 1; 1636111892Ssimokawa s = splfw(); 1637109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1638109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1639109890Ssimokawa volatile struct fwohcidb *db; 1640109890Ssimokawa 1641111942Ssimokawa#if 1 /* XXX for if_fwe */ 1642111942Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 1643111942Ssimokawa db[ldesc].db.desc.addr = vtophys(chunk->buf); 1644111942Ssimokawa#endif 1645109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1646109890Ssimokawa db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1647109890Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1648109890Ssimokawa if (prev != NULL) { 1649109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1650109892Ssimokawa#if 0 1651109890Ssimokawa db[ldesc].db.desc.depend = 1652109890Ssimokawa vtophys(((struct fwohcidb_tr *) 1653109890Ssimokawa (chunk->start))->db) | dbch->ndesc; 1654109892Ssimokawa#else 1655109892Ssimokawa db[ldesc].db.desc.depend |= dbch->ndesc; 1656109892Ssimokawa#endif 1657103285Sikob } 1658109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1659109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1660109890Ssimokawa prev = chunk; 1661103285Sikob } 1662109890Ssimokawa splx(s); 1663109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1664109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1665109890Ssimokawa return 0; 1666109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1667109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1668109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1669109890Ssimokawa } 1670109890Ssimokawa 1671109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1672109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1673109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1674109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1675109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1676109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1677109890Ssimokawa vtophys(((struct fwohcidb_tr *)(first->start))->db) 1678109890Ssimokawa | dbch->ndesc); 1679109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1680109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1681103285Sikob return err; 1682103285Sikob} 1683106790Ssimokawa 1684106790Ssimokawastatic int 1685106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1686103285Sikob{ 1687103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1688103285Sikob int err = 0; 1689103285Sikob 1690103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1691103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1692103285Sikob return err; 1693103285Sikob }else{ 1694103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1695103285Sikob return err; 1696103285Sikob } 1697103285Sikob} 1698106790Ssimokawa 1699106790Ssimokawaint 1700110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1701103285Sikob{ 1702103285Sikob u_int i; 1703103285Sikob 1704103285Sikob/* Now stopping all DMA channel */ 1705103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1706103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1707103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1708103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1709103285Sikob 1710103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1711103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1712103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1713103285Sikob } 1714103285Sikob 1715103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1716103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1717103285Sikob 1718103285Sikob/* Stop interrupt */ 1719103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1720103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1721103285Sikob | OHCI_INT_PHY_INT 1722103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1723103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1724103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1725103285Sikob | OHCI_INT_PHY_BUS_R); 1726108642Ssimokawa/* XXX Link down? Bus reset? */ 1727103285Sikob return 0; 1728103285Sikob} 1729103285Sikob 1730108642Ssimokawaint 1731108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1732108642Ssimokawa{ 1733108642Ssimokawa int i; 1734108642Ssimokawa 1735108642Ssimokawa fwohci_reset(sc, dev); 1736108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1737108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1738108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1739108642Ssimokawa device_printf(sc->fc.dev, 1740108642Ssimokawa "resume iso receive ch: %d\n", i); 1741108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1742108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1743108642Ssimokawa } 1744108642Ssimokawa } 1745108642Ssimokawa 1746108642Ssimokawa bus_generic_resume(dev); 1747108642Ssimokawa sc->fc.ibr(&sc->fc); 1748108642Ssimokawa return 0; 1749108642Ssimokawa} 1750108642Ssimokawa 1751103285Sikob#define ACK_ALL 1752103285Sikobstatic void 1753106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1754103285Sikob{ 1755103285Sikob u_int32_t irstat, itstat; 1756103285Sikob u_int i; 1757103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1758103285Sikob 1759103285Sikob#ifdef OHCI_DEBUG 1760103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1761103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1762103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1763103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1764103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1765103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1766103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1767103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1768103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1769103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1770103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1771103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1772103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1773103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1774103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1775103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1776103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1777103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1778103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1779103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1780103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1781103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1782103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1783103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1784103285Sikob ); 1785103285Sikob#endif 1786103285Sikob/* Bus reset */ 1787103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1788111074Ssimokawa if (fc->status == FWBUSRESET) 1789111074Ssimokawa goto busresetout; 1790111074Ssimokawa /* Disable bus reset interrupt until sid recv. */ 1791111074Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 1792111074Ssimokawa 1793103285Sikob device_printf(fc->dev, "BUS reset\n"); 1794103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1795103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1796103285Sikob 1797103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1798103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1799103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1800103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1801103285Sikob 1802103285Sikob#ifndef ACK_ALL 1803103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1804103285Sikob#endif 1805110798Ssimokawa fw_busreset(fc); 1806103285Sikob } 1807111074Ssimokawabusresetout: 1808103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1809103285Sikob#ifndef ACK_ALL 1810103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1811103285Sikob#endif 1812103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1813109280Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 1814103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1815109644Ssimokawa struct fwohci_dbch *dbch; 1816109644Ssimokawa 1817103285Sikob if((irstat & (1 << i)) != 0){ 1818109644Ssimokawa dbch = &sc->ir[i]; 1819109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1820109644Ssimokawa device_printf(sc->fc.dev, 1821109644Ssimokawa "dma(%d) not active\n", i); 1822109644Ssimokawa continue; 1823109644Ssimokawa } 1824109644Ssimokawa if (dbch->xferq.flag & FWXFERQ_PACKET) { 1825109644Ssimokawa fwohci_ircv(sc, dbch, count); 1826109644Ssimokawa } else { 1827103285Sikob fwohci_rbuf_update(sc, i); 1828103285Sikob } 1829103285Sikob } 1830103285Sikob } 1831103285Sikob } 1832103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1833103285Sikob#ifndef ACK_ALL 1834103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1835103285Sikob#endif 1836103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1837109280Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 1838103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1839103285Sikob if((itstat & (1 << i)) != 0){ 1840103285Sikob fwohci_tbuf_update(sc, i); 1841103285Sikob } 1842103285Sikob } 1843103285Sikob } 1844103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1845103285Sikob#ifndef ACK_ALL 1846103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1847103285Sikob#endif 1848103285Sikob#if 0 1849103285Sikob dump_dma(sc, ARRS_CH); 1850103285Sikob dump_db(sc, ARRS_CH); 1851103285Sikob#endif 1852106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1853103285Sikob } 1854103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1855103285Sikob#ifndef ACK_ALL 1856103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1857103285Sikob#endif 1858103285Sikob#if 0 1859103285Sikob dump_dma(sc, ARRQ_CH); 1860103285Sikob dump_db(sc, ARRQ_CH); 1861103285Sikob#endif 1862106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1863103285Sikob } 1864103285Sikob if(stat & OHCI_INT_PHY_SID){ 1865103285Sikob caddr_t buf; 1866103285Sikob int plen; 1867103285Sikob 1868103285Sikob#ifndef ACK_ALL 1869103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1870103285Sikob#endif 1871111074Ssimokawa /* Enable bus reset interrupt */ 1872111074Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1873111787Ssimokawa /* Allow async. request to us */ 1874111787Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 1875111787Ssimokawa /* XXX insecure ?? */ 1876111787Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1877111787Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1878111787Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1879103285Sikob/* 1880103285Sikob** Checking whether the node is root or not. If root, turn on 1881103285Sikob** cycle master. 1882103285Sikob*/ 1883103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1884103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1885103285Sikob printf("Bus reset failure\n"); 1886103285Sikob goto sidout; 1887103285Sikob } 1888103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1889103285Sikob printf("CYCLEMASTER mode\n"); 1890103285Sikob OWRITE(sc, OHCI_LNKCTL, 1891103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1892103285Sikob }else{ 1893103285Sikob printf("non CYCLEMASTER mode\n"); 1894103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1895103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1896103285Sikob } 1897103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1898103285Sikob 1899103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1900109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1901109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1902109736Ssimokawa goto sidout; 1903109736Ssimokawa } 1904103285Sikob plen -= 4; /* chop control info */ 1905110195Ssimokawa buf = malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1906103285Sikob if(buf == NULL) goto sidout; 1907108530Ssimokawa bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1908103285Sikob buf, plen); 1909110269Ssimokawa#if 1 1910110269Ssimokawa /* pending all pre-bus_reset packets */ 1911110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1912110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1913110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1914110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1915110798Ssimokawa fw_drain_txq(fc); 1916110269Ssimokawa#endif 1917103285Sikob fw_sidrcv(fc, buf, plen, 0); 1918103285Sikob } 1919103285Sikobsidout: 1920103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1921103285Sikob#ifndef ACK_ALL 1922103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1923103285Sikob#endif 1924103285Sikob fwohci_txd(sc, &(sc->atrq)); 1925103285Sikob } 1926103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1927103285Sikob#ifndef ACK_ALL 1928103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1929103285Sikob#endif 1930103285Sikob fwohci_txd(sc, &(sc->atrs)); 1931103285Sikob } 1932103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1933103285Sikob#ifndef ACK_ALL 1934103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1935103285Sikob#endif 1936103285Sikob device_printf(fc->dev, "posted write error\n"); 1937103285Sikob } 1938103285Sikob if((stat & OHCI_INT_ERR )){ 1939103285Sikob#ifndef ACK_ALL 1940103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1941103285Sikob#endif 1942103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1943103285Sikob } 1944103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1945103285Sikob#ifndef ACK_ALL 1946103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1947103285Sikob#endif 1948103285Sikob device_printf(fc->dev, "phy int\n"); 1949103285Sikob } 1950103285Sikob 1951103285Sikob return; 1952103285Sikob} 1953103285Sikob 1954103285Sikobvoid 1955103285Sikobfwohci_intr(void *arg) 1956103285Sikob{ 1957103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1958111074Ssimokawa u_int32_t stat, bus_reset = 0; 1959103285Sikob 1960103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1961103285Sikob /* polling mode */ 1962103285Sikob return; 1963103285Sikob } 1964103285Sikob 1965103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1966103285Sikob if (stat == 0xffffffff) { 1967103285Sikob device_printf(sc->fc.dev, 1968103285Sikob "device physically ejected?\n"); 1969103285Sikob return; 1970103285Sikob } 1971103285Sikob#ifdef ACK_ALL 1972103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1973103285Sikob#endif 1974111074Ssimokawa /* We cannot clear bus reset event during bus reset phase */ 1975111074Ssimokawa if ((stat & ~bus_reset) == 0) 1976111074Ssimokawa return; 1977111074Ssimokawa bus_reset = stat & OHCI_INT_PHY_BUS_R; 1978106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1979103285Sikob } 1980103285Sikob} 1981103285Sikob 1982103285Sikobstatic void 1983103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1984103285Sikob{ 1985103285Sikob int s; 1986103285Sikob u_int32_t stat; 1987103285Sikob struct fwohci_softc *sc; 1988103285Sikob 1989103285Sikob 1990103285Sikob sc = (struct fwohci_softc *)fc; 1991103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1992103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1993103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1994103285Sikob#if 0 1995103285Sikob if (!quick) { 1996103285Sikob#else 1997103285Sikob if (1) { 1998103285Sikob#endif 1999103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 2000103285Sikob if (stat == 0) 2001103285Sikob return; 2002103285Sikob if (stat == 0xffffffff) { 2003103285Sikob device_printf(sc->fc.dev, 2004103285Sikob "device physically ejected?\n"); 2005103285Sikob return; 2006103285Sikob } 2007103285Sikob#ifdef ACK_ALL 2008103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 2009103285Sikob#endif 2010103285Sikob } 2011103285Sikob s = splfw(); 2012106789Ssimokawa fwohci_intr_body(sc, stat, count); 2013103285Sikob splx(s); 2014103285Sikob} 2015103285Sikob 2016103285Sikobstatic void 2017103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2018103285Sikob{ 2019103285Sikob struct fwohci_softc *sc; 2020103285Sikob 2021103285Sikob sc = (struct fwohci_softc *)fc; 2022107653Ssimokawa if (bootverbose) 2023108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2024103285Sikob if (enable) { 2025103285Sikob sc->intmask |= OHCI_INT_EN; 2026103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2027103285Sikob } else { 2028103285Sikob sc->intmask &= ~OHCI_INT_EN; 2029103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2030103285Sikob } 2031103285Sikob} 2032103285Sikob 2033106790Ssimokawastatic void 2034106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2035103285Sikob{ 2036103285Sikob struct firewire_comm *fc = &sc->fc; 2037109890Ssimokawa volatile struct fwohcidb *db; 2038109890Ssimokawa struct fw_bulkxfer *chunk; 2039109890Ssimokawa struct fw_xferq *it; 2040109890Ssimokawa u_int32_t stat, count; 2041109890Ssimokawa int s, w=0; 2042103285Sikob 2043109890Ssimokawa it = fc->it[dmach]; 2044109890Ssimokawa s = splfw(); /* unnecessary ? */ 2045109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2046109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2047109890Ssimokawa stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2048109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2049109890Ssimokawa count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2050109890Ssimokawa if (stat == 0) 2051109890Ssimokawa break; 2052109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2053109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2054109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2055109890Ssimokawa#if 0 2056109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2057109179Ssimokawa#endif 2058109890Ssimokawa break; 2059109890Ssimokawa default: 2060109423Ssimokawa device_printf(fc->dev, 2061109890Ssimokawa "Isochronous transmit err %02x\n", stat); 2062109890Ssimokawa } 2063109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2064109890Ssimokawa w++; 2065109403Ssimokawa } 2066109890Ssimokawa splx(s); 2067109890Ssimokawa if (w) 2068109890Ssimokawa wakeup(it); 2069103285Sikob} 2070106790Ssimokawa 2071106790Ssimokawastatic void 2072106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2073103285Sikob{ 2074109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2075109890Ssimokawa volatile struct fwohcidb *db; 2076109890Ssimokawa struct fw_bulkxfer *chunk; 2077109890Ssimokawa struct fw_xferq *ir; 2078109890Ssimokawa u_int32_t stat; 2079109890Ssimokawa int s, w=0; 2080109179Ssimokawa 2081109890Ssimokawa ir = fc->ir[dmach]; 2082109890Ssimokawa s = splfw(); 2083109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2084109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2085109890Ssimokawa stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2086109890Ssimokawa if (stat == 0) 2087109890Ssimokawa break; 2088109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2089109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2090109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2091109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2092111942Ssimokawa chunk->resp = 0; 2093109890Ssimokawa break; 2094109890Ssimokawa default: 2095111942Ssimokawa chunk->resp = EINVAL; 2096109890Ssimokawa device_printf(fc->dev, 2097109890Ssimokawa "Isochronous receive err %02x\n", stat); 2098109890Ssimokawa } 2099109890Ssimokawa w++; 2100103285Sikob } 2101109890Ssimokawa splx(s); 2102111942Ssimokawa if (w) { 2103111942Ssimokawa if (ir->flag & FWXFERQ_HANDLER) 2104111942Ssimokawa ir->hand(ir); 2105111942Ssimokawa else 2106111942Ssimokawa wakeup(ir); 2107111942Ssimokawa } 2108103285Sikob} 2109106790Ssimokawa 2110106790Ssimokawavoid 2111106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2112106790Ssimokawa{ 2113103285Sikob u_int32_t off, cntl, stat, cmd, match; 2114103285Sikob 2115103285Sikob if(ch == 0){ 2116103285Sikob off = OHCI_ATQOFF; 2117103285Sikob }else if(ch == 1){ 2118103285Sikob off = OHCI_ATSOFF; 2119103285Sikob }else if(ch == 2){ 2120103285Sikob off = OHCI_ARQOFF; 2121103285Sikob }else if(ch == 3){ 2122103285Sikob off = OHCI_ARSOFF; 2123103285Sikob }else if(ch < IRX_CH){ 2124103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2125103285Sikob }else{ 2126103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2127103285Sikob } 2128103285Sikob cntl = stat = OREAD(sc, off); 2129103285Sikob cmd = OREAD(sc, off + 0xc); 2130103285Sikob match = OREAD(sc, off + 0x10); 2131103285Sikob 2132103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2133103285Sikob ch, 2134103285Sikob cntl, 2135103285Sikob stat, 2136103285Sikob cmd, 2137103285Sikob match); 2138103285Sikob stat &= 0xffff ; 2139103285Sikob if(stat & 0xff00){ 2140103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2141103285Sikob ch, 2142103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2143103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2144103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2145103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2146103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2147103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2148103285Sikob fwohcicode[stat & 0x1f], 2149103285Sikob stat & 0x1f 2150103285Sikob ); 2151103285Sikob }else{ 2152103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2153103285Sikob } 2154103285Sikob} 2155106790Ssimokawa 2156106790Ssimokawavoid 2157106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2158106790Ssimokawa{ 2159103285Sikob struct fwohci_dbch *dbch; 2160103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 2161103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2162103285Sikob int idb, jdb; 2163103285Sikob u_int32_t cmd, off; 2164103285Sikob if(ch == 0){ 2165103285Sikob off = OHCI_ATQOFF; 2166103285Sikob dbch = &sc->atrq; 2167103285Sikob }else if(ch == 1){ 2168103285Sikob off = OHCI_ATSOFF; 2169103285Sikob dbch = &sc->atrs; 2170103285Sikob }else if(ch == 2){ 2171103285Sikob off = OHCI_ARQOFF; 2172103285Sikob dbch = &sc->arrq; 2173103285Sikob }else if(ch == 3){ 2174103285Sikob off = OHCI_ARSOFF; 2175103285Sikob dbch = &sc->arrs; 2176103285Sikob }else if(ch < IRX_CH){ 2177103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2178103285Sikob dbch = &sc->it[ch - ITX_CH]; 2179103285Sikob }else { 2180103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2181103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2182103285Sikob } 2183103285Sikob cmd = OREAD(sc, off + 0xc); 2184103285Sikob 2185103285Sikob if( dbch->ndb == 0 ){ 2186103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2187103285Sikob return; 2188103285Sikob } 2189103285Sikob pp = dbch->top; 2190103285Sikob prev = pp->db; 2191103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2192103285Sikob if(pp == NULL){ 2193103285Sikob curr = NULL; 2194103285Sikob goto outdb; 2195103285Sikob } 2196103285Sikob cp = STAILQ_NEXT(pp, link); 2197103285Sikob if(cp == NULL){ 2198103285Sikob curr = NULL; 2199103285Sikob goto outdb; 2200103285Sikob } 2201103285Sikob np = STAILQ_NEXT(cp, link); 2202103285Sikob if(cp == NULL) break; 2203103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2204103285Sikob if((cmd & 0xfffffff0) 2205103285Sikob == vtophys(&(cp->db[jdb]))){ 2206103285Sikob curr = cp->db; 2207103285Sikob if(np != NULL){ 2208103285Sikob next = np->db; 2209103285Sikob }else{ 2210103285Sikob next = NULL; 2211103285Sikob } 2212103285Sikob goto outdb; 2213103285Sikob } 2214103285Sikob } 2215103285Sikob pp = STAILQ_NEXT(pp, link); 2216103285Sikob prev = pp->db; 2217103285Sikob } 2218103285Sikoboutdb: 2219103285Sikob if( curr != NULL){ 2220103285Sikob printf("Prev DB %d\n", ch); 2221103285Sikob print_db(prev, ch, dbch->ndesc); 2222103285Sikob printf("Current DB %d\n", ch); 2223103285Sikob print_db(curr, ch, dbch->ndesc); 2224103285Sikob printf("Next DB %d\n", ch); 2225103285Sikob print_db(next, ch, dbch->ndesc); 2226103285Sikob }else{ 2227103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2228103285Sikob } 2229103285Sikob return; 2230103285Sikob} 2231106790Ssimokawa 2232106790Ssimokawavoid 2233106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2234106790Ssimokawa{ 2235103285Sikob fwohcireg_t stat; 2236103285Sikob int i, key; 2237103285Sikob 2238103285Sikob if(db == NULL){ 2239103285Sikob printf("No Descriptor is found\n"); 2240103285Sikob return; 2241103285Sikob } 2242103285Sikob 2243103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2244103285Sikob ch, 2245103285Sikob "Current", 2246103285Sikob "OP ", 2247103285Sikob "KEY", 2248103285Sikob "INT", 2249103285Sikob "BR ", 2250103285Sikob "len", 2251103285Sikob "Addr", 2252103285Sikob "Depend", 2253103285Sikob "Stat", 2254103285Sikob "Cnt"); 2255103285Sikob for( i = 0 ; i <= max ; i ++){ 2256109892Ssimokawa key = db[i].db.desc.control & OHCI_KEY_MASK; 2257108712Ssimokawa#if __FreeBSD_version >= 500000 2258106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2259108712Ssimokawa#else 2260108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2261108712Ssimokawa#endif 2262103285Sikob vtophys(&db[i]), 2263109892Ssimokawa dbcode[(db[i].db.desc.control >> 12) & 0xf], 2264109892Ssimokawa dbkey[(db[i].db.desc.control >> 8) & 0x7], 2265109892Ssimokawa dbcond[(db[i].db.desc.control >> 4) & 0x3], 2266109892Ssimokawa dbcond[(db[i].db.desc.control >> 2) & 0x3], 2267109892Ssimokawa db[i].db.desc.reqcount, 2268103285Sikob db[i].db.desc.addr, 2269103285Sikob db[i].db.desc.depend, 2270103285Sikob db[i].db.desc.status, 2271103285Sikob db[i].db.desc.count); 2272103285Sikob stat = db[i].db.desc.status; 2273103285Sikob if(stat & 0xff00){ 2274103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2275103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2276103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2277103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2278103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2279103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2280103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2281103285Sikob fwohcicode[stat & 0x1f], 2282103285Sikob stat & 0x1f 2283103285Sikob ); 2284103285Sikob }else{ 2285103285Sikob printf(" Nostat\n"); 2286103285Sikob } 2287103285Sikob if(key == OHCI_KEY_ST2 ){ 2288103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2289103285Sikob db[i+1].db.immed[0], 2290103285Sikob db[i+1].db.immed[1], 2291103285Sikob db[i+1].db.immed[2], 2292103285Sikob db[i+1].db.immed[3]); 2293103285Sikob } 2294103285Sikob if(key == OHCI_KEY_DEVICE){ 2295103285Sikob return; 2296103285Sikob } 2297109892Ssimokawa if((db[i].db.desc.control & OHCI_BRANCH_MASK) 2298103285Sikob == OHCI_BRANCH_ALWAYS){ 2299103285Sikob return; 2300103285Sikob } 2301109892Ssimokawa if((db[i].db.desc.control & OHCI_CMD_MASK) 2302103285Sikob == OHCI_OUTPUT_LAST){ 2303103285Sikob return; 2304103285Sikob } 2305109892Ssimokawa if((db[i].db.desc.control & OHCI_CMD_MASK) 2306103285Sikob == OHCI_INPUT_LAST){ 2307103285Sikob return; 2308103285Sikob } 2309103285Sikob if(key == OHCI_KEY_ST2 ){ 2310103285Sikob i++; 2311103285Sikob } 2312103285Sikob } 2313103285Sikob return; 2314103285Sikob} 2315106790Ssimokawa 2316106790Ssimokawavoid 2317106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2318103285Sikob{ 2319103285Sikob struct fwohci_softc *sc; 2320103285Sikob u_int32_t fun; 2321103285Sikob 2322110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2323103285Sikob sc = (struct fwohci_softc *)fc; 2324108276Ssimokawa 2325108276Ssimokawa /* 2326108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2327108276Ssimokawa * shouldn't became the root node. 2328108276Ssimokawa */ 2329103285Sikob#if 1 2330103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2331109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2332103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2333109280Ssimokawa#else /* Short bus reset */ 2334103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2335109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2336103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2337103285Sikob#endif 2338103285Sikob} 2339106790Ssimokawa 2340106790Ssimokawavoid 2341106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2342103285Sikob{ 2343103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2344103285Sikob struct fwohci_dbch *dbch; 2345109892Ssimokawa volatile struct fwohcidb *db; 2346103285Sikob struct fw_pkt *fp; 2347103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2348103285Sikob unsigned short chtag; 2349103285Sikob int idb; 2350103285Sikob 2351103285Sikob dbch = &sc->it[dmach]; 2352103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2353103285Sikob 2354103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2355103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2356103285Sikob/* 2357103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2358103285Sikob*/ 2359103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2360109892Ssimokawa db = db_tr->db; 2361109892Ssimokawa#if 0 2362109892Ssimokawa db[0].db.desc.control 2363109892Ssimokawa = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2364109892Ssimokawa db[0].db.desc.reqcount = 8; 2365109892Ssimokawa#endif 2366103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2367109892Ssimokawa ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2368103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2369103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2370103285Sikob ohcifp->mode.stream.chtag = chtag; 2371103285Sikob ohcifp->mode.stream.tcode = 0xa; 2372109890Ssimokawa ohcifp->mode.stream.spd = 0; 2373103285Sikob 2374109892Ssimokawa db[2].db.desc.reqcount = ntohs(fp->mode.stream.len); 2375109892Ssimokawa db[2].db.desc.status = 0; 2376109892Ssimokawa db[2].db.desc.count = 0; 2377109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2378109892Ssimokawa db[2].db.desc.control = OHCI_OUTPUT_LAST 2379103285Sikob | OHCI_UPDATE 2380109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2381109892Ssimokawa db[0].db.desc.depend = 2382109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2383109280Ssimokawa = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2384109892Ssimokawa#else 2385109892Ssimokawa db[0].db.desc.depend |= dbch->ndesc; 2386109892Ssimokawa db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc; 2387109892Ssimokawa#endif 2388103285Sikob bulkxfer->end = (caddr_t)db_tr; 2389103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2390103285Sikob } 2391109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2392109892Ssimokawa db[0].db.desc.depend &= ~0xf; 2393109892Ssimokawa db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2394109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2395109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2396109280Ssimokawa /* OHCI 1.1 and above */ 2397109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2398109892Ssimokawa#endif 2399109892Ssimokawa/* 2400103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2401103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2402103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2403103285Sikob*/ 2404103285Sikob return; 2405103285Sikob} 2406106790Ssimokawa 2407106790Ssimokawastatic int 2408106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2409106790Ssimokawa int mode, void *buf) 2410103285Sikob{ 2411103285Sikob volatile struct fwohcidb *db = db_tr->db; 2412103285Sikob int err = 0; 2413103285Sikob if(buf == 0){ 2414103285Sikob err = EINVAL; 2415103285Sikob return err; 2416103285Sikob } 2417103285Sikob db_tr->buf = buf; 2418103285Sikob db_tr->dbcnt = 3; 2419103285Sikob db_tr->dummy = NULL; 2420103285Sikob 2421109892Ssimokawa db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2422109892Ssimokawa db[0].db.desc.reqcount = 8; 2423103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2424109892Ssimokawa db[2].db.desc.control = 2425109892Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; 2426109892Ssimokawa#if 1 2427103285Sikob db[0].db.desc.status = 0; 2428103285Sikob db[0].db.desc.count = 0; 2429103285Sikob db[2].db.desc.status = 0; 2430103285Sikob db[2].db.desc.count = 0; 2431109892Ssimokawa#endif 2432103285Sikob if( mode & FWXFERQ_STREAM ){ 2433103285Sikob if(mode & FWXFERQ_PACKET ){ 2434109892Ssimokawa db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2435103285Sikob } 2436109892Ssimokawa } else { 2437109892Ssimokawa printf("fwohci_add_tx_buf: who calls me?"); 2438103285Sikob } 2439103285Sikob return 1; 2440103285Sikob} 2441106790Ssimokawa 2442106790Ssimokawaint 2443106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2444106790Ssimokawa void *buf, void *dummy) 2445103285Sikob{ 2446103285Sikob volatile struct fwohcidb *db = db_tr->db; 2447103285Sikob int i; 2448103285Sikob void *dbuf[2]; 2449103285Sikob int dsiz[2]; 2450103285Sikob 2451103285Sikob if(buf == 0){ 2452110195Ssimokawa buf = malloc(size, M_FW, M_NOWAIT); 2453103285Sikob if(buf == NULL) return 0; 2454103285Sikob db_tr->buf = buf; 2455103285Sikob db_tr->dbcnt = 1; 2456103285Sikob db_tr->dummy = NULL; 2457103285Sikob dsiz[0] = size; 2458103285Sikob dbuf[0] = buf; 2459103285Sikob }else if(dummy == NULL){ 2460103285Sikob db_tr->buf = buf; 2461103285Sikob db_tr->dbcnt = 1; 2462103285Sikob db_tr->dummy = NULL; 2463103285Sikob dsiz[0] = size; 2464103285Sikob dbuf[0] = buf; 2465103285Sikob }else{ 2466103285Sikob db_tr->buf = buf; 2467103285Sikob db_tr->dbcnt = 2; 2468103285Sikob db_tr->dummy = dummy; 2469103285Sikob dsiz[0] = sizeof(u_int32_t); 2470103285Sikob dsiz[1] = size; 2471103285Sikob dbuf[0] = dummy; 2472103285Sikob dbuf[1] = buf; 2473103285Sikob } 2474103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2475103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2476109892Ssimokawa db[i].db.desc.control = OHCI_INPUT_MORE; 2477109892Ssimokawa db[i].db.desc.reqcount = dsiz[i]; 2478103285Sikob if( mode & FWXFERQ_STREAM ){ 2479109892Ssimokawa db[i].db.desc.control |= OHCI_UPDATE; 2480103285Sikob } 2481103285Sikob db[i].db.desc.status = 0; 2482103285Sikob db[i].db.desc.count = dsiz[i]; 2483103285Sikob } 2484103285Sikob if( mode & FWXFERQ_STREAM ){ 2485109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST; 2486103285Sikob if(mode & FWXFERQ_PACKET ){ 2487109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control 2488103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2489103285Sikob } 2490103285Sikob } 2491109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS; 2492103285Sikob return 1; 2493103285Sikob} 2494106790Ssimokawa 2495106790Ssimokawastatic void 2496106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2497103285Sikob{ 2498103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2499103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2500103285Sikob int z = 1; 2501103285Sikob struct fw_pkt *fp; 2502103285Sikob u_int8_t *ld; 2503103285Sikob u_int32_t off = NULL; 2504103285Sikob u_int32_t stat; 2505103285Sikob u_int32_t *qld; 2506103285Sikob u_int32_t reg; 2507103285Sikob u_int spd; 2508103285Sikob u_int dmach; 2509103285Sikob int len, i, plen; 2510103285Sikob caddr_t buf; 2511103285Sikob 2512103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2513103285Sikob if( &sc->ir[dmach] == dbch){ 2514103285Sikob off = OHCI_IROFF(dmach); 2515103285Sikob break; 2516103285Sikob } 2517103285Sikob } 2518103285Sikob if(off == NULL){ 2519103285Sikob return; 2520103285Sikob } 2521103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2522103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2523103285Sikob return; 2524103285Sikob } 2525103285Sikob 2526103285Sikob odb_tr = NULL; 2527103285Sikob db_tr = dbch->top; 2528103285Sikob i = 0; 2529103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2530106789Ssimokawa if (count >= 0 && count-- == 0) 2531106789Ssimokawa break; 2532103285Sikob ld = (u_int8_t *)db_tr->buf; 2533103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2534103285Sikob /* skip timeStamp */ 2535103285Sikob ld += sizeof(struct fwohci_trailer); 2536103285Sikob } 2537103285Sikob qld = (u_int32_t *)ld; 2538103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2539103285Sikob/* 2540103285Sikob{ 2541103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2542103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2543103285Sikob} 2544103285Sikob*/ 2545103285Sikob fp=(struct fw_pkt *)ld; 2546103285Sikob qld[0] = htonl(qld[0]); 2547103285Sikob plen = sizeof(struct fw_isohdr) 2548103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2549103285Sikob ld += plen; 2550103285Sikob len -= plen; 2551103285Sikob buf = db_tr->buf; 2552103285Sikob db_tr->buf = NULL; 2553103285Sikob stat = reg & 0x1f; 2554103285Sikob spd = reg & 0x3; 2555103285Sikob switch(stat){ 2556103285Sikob case FWOHCIEV_ACKCOMPL: 2557103285Sikob case FWOHCIEV_ACKPEND: 2558103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2559103285Sikob break; 2560103285Sikob default: 2561110195Ssimokawa free(buf, M_FW); 2562103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2563103285Sikob break; 2564103285Sikob } 2565103285Sikob i++; 2566103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2567103285Sikob dbch->xferq.flag, 0, NULL); 2568103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2569103285Sikob if(dbch->pdb_tr != NULL){ 2570103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2571103285Sikob } else { 2572103285Sikob /* XXX should be rewritten in better way */ 2573103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2574103285Sikob } 2575103285Sikob dbch->pdb_tr = db_tr; 2576103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2577103285Sikob } 2578103285Sikob dbch->top = db_tr; 2579103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2580103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2581103285Sikob return; 2582103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2583103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2584103285Sikob dbch->top = db_tr; 2585103285Sikob fwohci_irx_enable(fc, dmach); 2586103285Sikob} 2587103285Sikob 2588110798Ssimokawa#define PLEN(x) roundup2(ntohs(x), sizeof(u_int32_t)) 2589103285Sikobstatic int 2590110798Ssimokawafwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp, int hlen) 2591103285Sikob{ 2592110798Ssimokawa int i, r; 2593103285Sikob 2594103285Sikob for( i = 4; i < hlen ; i+=4){ 2595103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2596103285Sikob } 2597103285Sikob 2598103285Sikob switch(fp->mode.common.tcode){ 2599103285Sikob case FWTCODE_RREQQ: 2600110798Ssimokawa r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2601110798Ssimokawa break; 2602103285Sikob case FWTCODE_WRES: 2603110798Ssimokawa r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2604110798Ssimokawa break; 2605103285Sikob case FWTCODE_WREQQ: 2606110798Ssimokawa r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2607110798Ssimokawa break; 2608103285Sikob case FWTCODE_RREQB: 2609110798Ssimokawa r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2610110798Ssimokawa break; 2611103285Sikob case FWTCODE_RRESQ: 2612110798Ssimokawa r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2613110798Ssimokawa break; 2614103285Sikob case FWTCODE_WREQB: 2615110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2616103285Sikob + sizeof(u_int32_t); 2617110798Ssimokawa break; 2618103285Sikob case FWTCODE_LREQ: 2619110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2620103285Sikob + sizeof(u_int32_t); 2621110798Ssimokawa break; 2622103285Sikob case FWTCODE_RRESB: 2623110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2624103285Sikob + sizeof(u_int32_t); 2625110798Ssimokawa break; 2626103285Sikob case FWTCODE_LRES: 2627110798Ssimokawa r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2628103285Sikob + sizeof(u_int32_t); 2629110798Ssimokawa break; 2630103285Sikob case FWOHCITCODE_PHY: 2631110798Ssimokawa r = 16; 2632110798Ssimokawa break; 2633110798Ssimokawa default: 2634110798Ssimokawa device_printf(sc->fc.dev, "Unknown tcode %d\n", 2635110798Ssimokawa fp->mode.common.tcode); 2636110798Ssimokawa r = 0; 2637103285Sikob } 2638110798Ssimokawa if (r > dbch->xferq.psize) { 2639110798Ssimokawa device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2640110798Ssimokawa /* panic ? */ 2641110798Ssimokawa } 2642110798Ssimokawa return r; 2643103285Sikob} 2644103285Sikob 2645106790Ssimokawastatic void 2646106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2647103285Sikob{ 2648103285Sikob struct fwohcidb_tr *db_tr; 2649103285Sikob int z = 1; 2650103285Sikob struct fw_pkt *fp; 2651103285Sikob u_int8_t *ld; 2652103285Sikob u_int32_t stat, off; 2653103285Sikob u_int spd; 2654103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2655103285Sikob int s; 2656103285Sikob caddr_t buf; 2657103285Sikob int resCount; 2658103285Sikob 2659103285Sikob if(&sc->arrq == dbch){ 2660103285Sikob off = OHCI_ARQOFF; 2661103285Sikob }else if(&sc->arrs == dbch){ 2662103285Sikob off = OHCI_ARSOFF; 2663103285Sikob }else{ 2664103285Sikob return; 2665103285Sikob } 2666103285Sikob 2667103285Sikob s = splfw(); 2668103285Sikob db_tr = dbch->top; 2669103285Sikob pcnt = 0; 2670103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2671103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2672103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2673103285Sikob resCount = db_tr->db[0].db.desc.count; 2674103285Sikob len = dbch->xferq.psize - resCount 2675103285Sikob - dbch->buf_offset; 2676103285Sikob while (len > 0 ) { 2677106789Ssimokawa if (count >= 0 && count-- == 0) 2678106789Ssimokawa goto out; 2679103285Sikob if(dbch->frag.buf != NULL){ 2680103285Sikob buf = dbch->frag.buf; 2681103285Sikob if (dbch->frag.plen < 0) { 2682103285Sikob /* incomplete header */ 2683103285Sikob int hlen; 2684103285Sikob 2685103285Sikob hlen = - dbch->frag.plen; 2686103285Sikob rlen = hlen - dbch->frag.len; 2687103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2688103285Sikob ld += rlen; 2689103285Sikob len -= rlen; 2690103285Sikob dbch->frag.len += rlen; 2691103285Sikob#if 0 2692103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2693103285Sikob#endif 2694103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2695103285Sikob dbch->frag.plen 2696110798Ssimokawa = fwohci_get_plen(sc, 2697110798Ssimokawa dbch, fp, hlen); 2698103285Sikob if (dbch->frag.plen == 0) 2699103285Sikob goto out; 2700103285Sikob } 2701103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2702103285Sikob#if 0 2703103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2704103285Sikob#endif 2705103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2706103285Sikob rlen); 2707103285Sikob ld += rlen; 2708103285Sikob len -= rlen; 2709103285Sikob plen = dbch->frag.plen; 2710103285Sikob dbch->frag.buf = NULL; 2711103285Sikob dbch->frag.plen = 0; 2712103285Sikob dbch->frag.len = 0; 2713103285Sikob poff = 0; 2714103285Sikob }else{ 2715103285Sikob fp=(struct fw_pkt *)ld; 2716103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2717103285Sikob switch(fp->mode.common.tcode){ 2718103285Sikob case FWTCODE_RREQQ: 2719103285Sikob case FWTCODE_WRES: 2720103285Sikob case FWTCODE_WREQQ: 2721103285Sikob case FWTCODE_RRESQ: 2722103285Sikob case FWOHCITCODE_PHY: 2723103285Sikob hlen = 12; 2724103285Sikob break; 2725103285Sikob case FWTCODE_RREQB: 2726103285Sikob case FWTCODE_WREQB: 2727103285Sikob case FWTCODE_LREQ: 2728103285Sikob case FWTCODE_RRESB: 2729103285Sikob case FWTCODE_LRES: 2730103285Sikob hlen = 16; 2731103285Sikob break; 2732103285Sikob default: 2733103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2734103285Sikob goto out; 2735103285Sikob } 2736103285Sikob if (len >= hlen) { 2737110798Ssimokawa plen = fwohci_get_plen(sc, 2738110798Ssimokawa dbch, fp, hlen); 2739103285Sikob if (plen == 0) 2740103285Sikob goto out; 2741103285Sikob plen = (plen + 3) & ~3; 2742103285Sikob len -= plen; 2743103285Sikob } else { 2744103285Sikob plen = -hlen; 2745103285Sikob len -= hlen; 2746103285Sikob } 2747103285Sikob if(resCount > 0 || len > 0){ 2748110798Ssimokawa buf = malloc(plen, M_FW, M_NOWAIT); 2749103285Sikob if(buf == NULL){ 2750103285Sikob printf("cannot malloc!\n"); 2751110195Ssimokawa free(db_tr->buf, M_FW); 2752103285Sikob goto out; 2753103285Sikob } 2754103285Sikob bcopy(ld, buf, plen); 2755103285Sikob poff = 0; 2756103285Sikob dbch->frag.buf = NULL; 2757103285Sikob dbch->frag.plen = 0; 2758103285Sikob dbch->frag.len = 0; 2759103285Sikob }else if(len < 0){ 2760103285Sikob dbch->frag.buf = db_tr->buf; 2761103285Sikob if (plen < 0) { 2762103285Sikob#if 0 2763103285Sikob printf("plen < 0:" 2764103285Sikob "hlen: %d len: %d\n", 2765103285Sikob hlen, len); 2766103285Sikob#endif 2767103285Sikob dbch->frag.len = hlen + len; 2768103285Sikob dbch->frag.plen = -hlen; 2769103285Sikob } else { 2770103285Sikob dbch->frag.len = plen + len; 2771103285Sikob dbch->frag.plen = plen; 2772103285Sikob } 2773103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2774103285Sikob buf = NULL; 2775103285Sikob }else{ 2776103285Sikob buf = db_tr->buf; 2777103285Sikob poff = ld - (u_int8_t *)buf; 2778103285Sikob dbch->frag.buf = NULL; 2779103285Sikob dbch->frag.plen = 0; 2780103285Sikob dbch->frag.len = 0; 2781103285Sikob } 2782103285Sikob ld += plen; 2783103285Sikob } 2784103285Sikob if( buf != NULL){ 2785103285Sikob/* DMA result-code will be written at the tail of packet */ 2786103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2787103285Sikob spd = (stat >> 5) & 0x3; 2788103285Sikob stat &= 0x1f; 2789103285Sikob switch(stat){ 2790103285Sikob case FWOHCIEV_ACKPEND: 2791110577Ssimokawa#if 0 2792103285Sikob printf("fwohci_arcv: ack pending..\n"); 2793103285Sikob#endif 2794103285Sikob /* fall through */ 2795103285Sikob case FWOHCIEV_ACKCOMPL: 2796103285Sikob if( poff != 0 ) 2797103285Sikob bcopy(buf+poff, buf, plen - 4); 2798103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2799103285Sikob break; 2800103285Sikob case FWOHCIEV_BUSRST: 2801110195Ssimokawa free(buf, M_FW); 2802103285Sikob if (sc->fc.status != FWBUSRESET) 2803103285Sikob printf("got BUSRST packet!?\n"); 2804103285Sikob break; 2805103285Sikob default: 2806103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2807103285Sikob#if 0 /* XXX */ 2808103285Sikob goto out; 2809103285Sikob#endif 2810103285Sikob break; 2811103285Sikob } 2812103285Sikob } 2813103285Sikob pcnt ++; 2814103285Sikob }; 2815103285Sikobout: 2816103285Sikob if (resCount == 0) { 2817103285Sikob /* done on this buffer */ 2818103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2819103285Sikob dbch->xferq.flag, 0, NULL); 2820103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2821103285Sikob dbch->bottom = db_tr; 2822103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2823103285Sikob dbch->top = db_tr; 2824103285Sikob dbch->buf_offset = 0; 2825103285Sikob } else { 2826103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2827103285Sikob break; 2828103285Sikob } 2829103285Sikob /* XXX make sure DMA is not dead */ 2830103285Sikob } 2831103285Sikob#if 0 2832103285Sikob if (pcnt < 1) 2833103285Sikob printf("fwohci_arcv: no packets\n"); 2834103285Sikob#endif 2835103285Sikob splx(s); 2836103285Sikob} 2837