fwohci.c revision 110798
1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 110798 2003-02-13 13:35:57Z simokawa $ 34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/proc.h> 46#include <sys/systm.h> 47#include <sys/types.h> 48#include <sys/mbuf.h> 49#include <sys/mman.h> 50#include <sys/socket.h> 51#include <sys/socketvar.h> 52#include <sys/signalvar.h> 53#include <sys/malloc.h> 54#include <sys/uio.h> 55#include <sys/sockio.h> 56#include <sys/bus.h> 57#include <sys/kernel.h> 58#include <sys/conf.h> 59 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/rman.h> 63 64#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65#include <machine/clock.h> 66#include <pci/pcivar.h> 67#include <pci/pcireg.h> 68#include <vm/vm.h> 69#include <vm/vm_extern.h> 70#include <vm/pmap.h> /* for vtophys proto */ 71 72#include <dev/firewire/firewire.h> 73#include <dev/firewire/firewirereg.h> 74#include <dev/firewire/fwohcireg.h> 75#include <dev/firewire/fwohcivar.h> 76#include <dev/firewire/firewire_phy.h> 77 78#include <dev/firewire/iec68113.h> 79 80#undef OHCI_DEBUG 81 82static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83 "STOR","LOAD","NOP ","STOP",}; 84static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85 "UNDEF","REG","SYS","DEV"}; 86char fwohcicode[32][0x20]={ 87 "No stat","Undef","long","miss Ack err", 88 "underrun","overrun","desc err", "data read err", 89 "data write err","bus reset","timeout","tcode err", 90 "Undef","Undef","unknown event","flushed", 91 "Undef","ack complete","ack pend","Undef", 92 "ack busy_X","ack busy_A","ack busy_B","Undef", 93 "Undef","Undef","Undef","ack tardy", 94 "Undef","ack data_err","ack type_err",""}; 95#define MAX_SPEED 2 96extern char linkspeed[MAX_SPEED+1][0x10]; 97static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99 100static struct tcode_info tinfo[] = { 101/* hdr_len block flag*/ 102/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104/* 2 WRES */ {12, FWTI_RES}, 105/* 3 XXX */ { 0, 0}, 106/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108/* 6 RRESQ */ {16, FWTI_RES}, 109/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110/* 8 CYCS */ { 0, 0}, 111/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114/* c XXX */ { 0, 0}, 115/* d XXX */ { 0, 0}, 116/* e PHY */ {12, FWTI_REQ}, 117/* f XXX */ { 0, 0} 118}; 119 120#define OHCI_WRITE_SIGMASK 0xffff0000 121#define OHCI_READ_SIGMASK 0xffff0000 122 123#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125 126static void fwohci_ibr __P((struct firewire_comm *)); 127static void fwohci_db_init __P((struct fwohci_dbch *)); 128static void fwohci_db_free __P((struct fwohci_dbch *)); 129static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132static void fwohci_start_atq __P((struct firewire_comm *)); 133static void fwohci_start_ats __P((struct firewire_comm *)); 134static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142static int fwohci_irx_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145static int fwohci_irx_disable __P((struct firewire_comm *, int)); 146static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148static int fwohci_itx_disable __P((struct firewire_comm *, int)); 149static void fwohci_timeout __P((void *)); 150static void fwohci_poll __P((struct firewire_comm *, int, int)); 151static void fwohci_set_intr __P((struct firewire_comm *, int)); 152static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154static void dump_db __P((struct fwohci_softc *, u_int32_t)); 155static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161 162/* 163 * memory allocated for DMA programs 164 */ 165#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166 167/* #define NDB 1024 */ 168#define NDB FWMAXQUEUE 169#define NDVDB (DVBUF * NDB) 170 171#define OHCI_VERSION 0x00 172#define OHCI_CROMHDR 0x18 173#define OHCI_BUS_OPT 0x20 174#define OHCI_BUSIRMC (1 << 31) 175#define OHCI_BUSCMC (1 << 30) 176#define OHCI_BUSISC (1 << 29) 177#define OHCI_BUSBMC (1 << 28) 178#define OHCI_BUSPMC (1 << 27) 179#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 180 OHCI_BUSBMC | OHCI_BUSPMC 181 182#define OHCI_EUID_HI 0x24 183#define OHCI_EUID_LO 0x28 184 185#define OHCI_CROMPTR 0x34 186#define OHCI_HCCCTL 0x50 187#define OHCI_HCCCTLCLR 0x54 188#define OHCI_AREQHI 0x100 189#define OHCI_AREQHICLR 0x104 190#define OHCI_AREQLO 0x108 191#define OHCI_AREQLOCLR 0x10c 192#define OHCI_PREQHI 0x110 193#define OHCI_PREQHICLR 0x114 194#define OHCI_PREQLO 0x118 195#define OHCI_PREQLOCLR 0x11c 196#define OHCI_PREQUPPER 0x120 197 198#define OHCI_SID_BUF 0x64 199#define OHCI_SID_CNT 0x68 200#define OHCI_SID_CNT_MASK 0xffc 201 202#define OHCI_IT_STAT 0x90 203#define OHCI_IT_STATCLR 0x94 204#define OHCI_IT_MASK 0x98 205#define OHCI_IT_MASKCLR 0x9c 206 207#define OHCI_IR_STAT 0xa0 208#define OHCI_IR_STATCLR 0xa4 209#define OHCI_IR_MASK 0xa8 210#define OHCI_IR_MASKCLR 0xac 211 212#define OHCI_LNKCTL 0xe0 213#define OHCI_LNKCTLCLR 0xe4 214 215#define OHCI_PHYACCESS 0xec 216#define OHCI_CYCLETIMER 0xf0 217 218#define OHCI_DMACTL(off) (off) 219#define OHCI_DMACTLCLR(off) (off + 4) 220#define OHCI_DMACMD(off) (off + 0xc) 221#define OHCI_DMAMATCH(off) (off + 0x10) 222 223#define OHCI_ATQOFF 0x180 224#define OHCI_ATQCTL OHCI_ATQOFF 225#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228 229#define OHCI_ATSOFF 0x1a0 230#define OHCI_ATSCTL OHCI_ATSOFF 231#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234 235#define OHCI_ARQOFF 0x1c0 236#define OHCI_ARQCTL OHCI_ARQOFF 237#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240 241#define OHCI_ARSOFF 0x1e0 242#define OHCI_ARSCTL OHCI_ARSOFF 243#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246 247#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251 252#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257 258d_ioctl_t fwohci_ioctl; 259 260/* 261 * Communication with PHY device 262 */ 263static u_int32_t 264fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265{ 266 u_int32_t fun; 267 268 addr &= 0xf; 269 data &= 0xff; 270 271 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272 OWRITE(sc, OHCI_PHYACCESS, fun); 273 DELAY(100); 274 275 return(fwphy_rddata( sc, addr)); 276} 277 278static u_int32_t 279fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280{ 281 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282 int i; 283 u_int32_t bm; 284 285#define OHCI_CSR_DATA 0x0c 286#define OHCI_CSR_COMP 0x10 287#define OHCI_CSR_CONT 0x14 288#define OHCI_BUS_MANAGER_ID 0 289 290 OWRITE(sc, OHCI_CSR_DATA, node); 291 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294 DELAY(10); 295 bm = OREAD(sc, OHCI_CSR_DATA); 296 if((bm & 0x3f) == 0x3f) 297 bm = node; 298 if (bootverbose) 299 device_printf(sc->fc.dev, 300 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301 302 return(bm); 303} 304 305static u_int32_t 306fwphy_rddata(struct fwohci_softc *sc, u_int addr) 307{ 308 u_int32_t fun, stat; 309 u_int i, retry = 0; 310 311 addr &= 0xf; 312#define MAX_RETRY 100 313again: 314 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316 OWRITE(sc, OHCI_PHYACCESS, fun); 317 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318 fun = OREAD(sc, OHCI_PHYACCESS); 319 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320 break; 321 DELAY(100); 322 } 323 if(i >= MAX_RETRY) { 324 if (bootverbose) 325 device_printf(sc->fc.dev, "phy read failed(1).\n"); 326 if (++retry < MAX_RETRY) { 327 DELAY(100); 328 goto again; 329 } 330 } 331 /* Make sure that SCLK is started */ 332 stat = OREAD(sc, FWOHCI_INTSTAT); 333 if ((stat & OHCI_INT_REG_FAIL) != 0 || 334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335 if (bootverbose) 336 device_printf(sc->fc.dev, "phy read failed(2).\n"); 337 if (++retry < MAX_RETRY) { 338 DELAY(100); 339 goto again; 340 } 341 } 342 if (bootverbose || retry >= MAX_RETRY) 343 device_printf(sc->fc.dev, 344 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345#undef MAX_RETRY 346 return((fun >> PHYDEV_RDDATA )& 0xff); 347} 348/* Device specific ioctl. */ 349int 350fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351{ 352 struct firewire_softc *sc; 353 struct fwohci_softc *fc; 354 int unit = DEV2UNIT(dev); 355 int err = 0; 356 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357 u_int32_t *dmach = (u_int32_t *) data; 358 359 sc = devclass_get_softc(firewire_devclass, unit); 360 if(sc == NULL){ 361 return(EINVAL); 362 } 363 fc = (struct fwohci_softc *)sc->fc; 364 365 if (!data) 366 return(EINVAL); 367 368 switch (cmd) { 369 case FWOHCI_WRREG: 370#define OHCI_MAX_REG 0x800 371 if(reg->addr <= OHCI_MAX_REG){ 372 OWRITE(fc, reg->addr, reg->data); 373 reg->data = OREAD(fc, reg->addr); 374 }else{ 375 err = EINVAL; 376 } 377 break; 378 case FWOHCI_RDREG: 379 if(reg->addr <= OHCI_MAX_REG){ 380 reg->data = OREAD(fc, reg->addr); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385/* Read DMA descriptors for debug */ 386 case DUMPDMA: 387 if(*dmach <= OHCI_MAX_DMA_CH ){ 388 dump_dma(fc, *dmach); 389 dump_db(fc, *dmach); 390 }else{ 391 err = EINVAL; 392 } 393 break; 394 default: 395 break; 396 } 397 return err; 398} 399 400static int 401fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402{ 403 u_int32_t reg, reg2; 404 int e1394a = 1; 405/* 406 * probe PHY parameters 407 * 0. to prove PHY version, whether compliance of 1394a. 408 * 1. to probe maximum speed supported by the PHY and 409 * number of port supported by core-logic. 410 * It is not actually available port on your PC . 411 */ 412 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413#if 0 414 /* XXX wait for SCLK. */ 415 DELAY(100000); 416#endif 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 device_printf(dev, 429 "Phy 1394 only %s, %d ports.\n", 430 linkspeed[sc->fc.speed], sc->fc.nport); 431 }else{ 432 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433 sc->fc.mode |= FWPHYASYST; 434 sc->fc.nport = reg & FW_PHY_NP; 435 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436 if (sc->fc.speed > MAX_SPEED) { 437 device_printf(dev, "invalid speed %d (fixed to %d).\n", 438 sc->fc.speed, MAX_SPEED); 439 sc->fc.speed = MAX_SPEED; 440 } 441 device_printf(dev, 442 "Phy 1394a available %s, %d ports.\n", 443 linkspeed[sc->fc.speed], sc->fc.nport); 444 445 /* check programPhyEnable */ 446 reg2 = fwphy_rddata(sc, 5); 447#if 0 448 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449#else /* XXX force to enable 1394a */ 450 if (e1394a) { 451#endif 452 if (bootverbose) 453 device_printf(dev, 454 "Enable 1394a Enhancements\n"); 455 /* enable EAA EMC */ 456 reg2 |= 0x03; 457 /* set aPhyEnhanceEnable */ 458 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460 } else { 461 /* for safe */ 462 reg2 &= ~0x83; 463 } 464 reg2 = fwphy_wrdata(sc, 5, reg2); 465 } 466 467 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468 if((reg >> 5) == 7 ){ 469 reg = fwphy_rddata(sc, 4); 470 reg |= 1 << 6; 471 fwphy_wrdata(sc, 4, reg); 472 reg = fwphy_rddata(sc, 4); 473 } 474 return 0; 475} 476 477 478void 479fwohci_reset(struct fwohci_softc *sc, device_t dev) 480{ 481 int i, max_rec, speed; 482 u_int32_t reg, reg2; 483 struct fwohcidb_tr *db_tr; 484 485 /* Disable interrupt */ 486 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487 488 /* Now stopping all DMA channel */ 489 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493 494 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498 } 499 500 /* FLUSH FIFO and reset Transmitter/Reciever */ 501 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502 if (bootverbose) 503 device_printf(dev, "resetting OHCI..."); 504 i = 0; 505 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506 if (i++ > 100) break; 507 DELAY(1000); 508 } 509 if (bootverbose) 510 printf("done (loop=%d)\n", i); 511 512 /* Probe phy */ 513 fwohci_probe_phy(sc, dev); 514 515 /* Probe link */ 516 reg = OREAD(sc, OHCI_BUS_OPT); 517 reg2 = reg | OHCI_BUSFNC; 518 max_rec = (reg & 0x0000f000) >> 12; 519 speed = (reg & 0x00000007); 520 device_printf(dev, "Link %s, max_rec %d bytes.\n", 521 linkspeed[speed], MAXREC(max_rec)); 522 /* XXX fix max_rec */ 523 sc->fc.maxrec = sc->fc.speed + 8; 524 if (max_rec != sc->fc.maxrec) { 525 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526 device_printf(dev, "max_rec %d -> %d\n", 527 MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528 } 529 if (bootverbose) 530 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531 OWRITE(sc, OHCI_BUS_OPT, reg2); 532 533 /* Initialize registers */ 534 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540 fw_busreset(&sc->fc); 541 542 /* Enable link */ 543 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544 545 /* Force to start async RX DMA */ 546 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548 fwohci_rx_enable(sc, &sc->arrq); 549 fwohci_rx_enable(sc, &sc->arrs); 550 551 /* Initialize async TX */ 552 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554 /* AT Retries */ 555 OWRITE(sc, FWOHCI_RETRY, 556 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560 db_tr->xfer = NULL; 561 } 562 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564 db_tr->xfer = NULL; 565 } 566 567 568 /* Enable interrupt */ 569 OWRITE(sc, FWOHCI_INTMASK, 570 OHCI_INT_ERR | OHCI_INT_PHY_SID 571 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574 fwohci_set_intr(&sc->fc, 1); 575 576} 577 578int 579fwohci_init(struct fwohci_softc *sc, device_t dev) 580{ 581 int i; 582 u_int32_t reg; 583 u_int8_t ui[8]; 584 585 reg = OREAD(sc, OHCI_VERSION); 586 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 587 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 588 589/* Available Isochrounous DMA channel probe */ 590 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 591 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 592 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 593 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 594 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 595 for (i = 0; i < 0x20; i++) 596 if ((reg & (1 << i)) == 0) 597 break; 598 sc->fc.nisodma = i; 599 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 600 601 sc->fc.arq = &sc->arrq.xferq; 602 sc->fc.ars = &sc->arrs.xferq; 603 sc->fc.atq = &sc->atrq.xferq; 604 sc->fc.ats = &sc->atrs.xferq; 605 606 sc->arrq.xferq.start = NULL; 607 sc->arrs.xferq.start = NULL; 608 sc->atrq.xferq.start = fwohci_start_atq; 609 sc->atrs.xferq.start = fwohci_start_ats; 610 611 sc->arrq.xferq.drain = NULL; 612 sc->arrs.xferq.drain = NULL; 613 sc->atrq.xferq.drain = fwohci_drain_atq; 614 sc->atrs.xferq.drain = fwohci_drain_ats; 615 616 sc->arrq.ndesc = 1; 617 sc->arrs.ndesc = 1; 618 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ 619 sc->atrs.ndesc = 2; 620 621 sc->arrq.ndb = NDB; 622 sc->arrs.ndb = NDB / 2; 623 sc->atrq.ndb = NDB; 624 sc->atrs.ndb = NDB / 2; 625 626 sc->arrq.dummy = NULL; 627 sc->arrs.dummy = NULL; 628 sc->atrq.dummy = NULL; 629 sc->atrs.dummy = NULL; 630 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 631 sc->fc.it[i] = &sc->it[i].xferq; 632 sc->fc.ir[i] = &sc->ir[i].xferq; 633 sc->it[i].ndb = 0; 634 sc->ir[i].ndb = 0; 635 } 636 637 sc->fc.tcode = tinfo; 638 639 sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_FW, M_NOWAIT); 640 641 if(sc->cromptr == NULL){ 642 device_printf(dev, "cromptr alloc failed."); 643 return ENOMEM; 644 } 645 sc->fc.dev = dev; 646 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647 648 sc->fc.config_rom[1] = 0x31333934; 649 sc->fc.config_rom[2] = 0xf000a002; 650 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652 sc->fc.config_rom[5] = 0; 653 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654 655 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656 657 658/* SID recieve buffer must allign 2^11 */ 659#define OHCI_SIDSIZE (1 << 11) 660 sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 661 if (sc->fc.sid_buf == NULL) { 662 device_printf(dev, "sid_buf alloc failed.\n"); 663 return ENOMEM; 664 } 665 if (((vm_offset_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 666 device_printf(dev, "sid_buf(%p) not aligned.\n", 667 sc->fc.sid_buf); 668 return ENOMEM; 669 } 670 671 fwohci_db_init(&sc->arrq); 672 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 673 return ENOMEM; 674 675 fwohci_db_init(&sc->arrs); 676 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 677 return ENOMEM; 678 679 fwohci_db_init(&sc->atrq); 680 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 681 return ENOMEM; 682 683 fwohci_db_init(&sc->atrs); 684 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 685 return ENOMEM; 686 687 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 688 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 689 for( i = 0 ; i < 8 ; i ++) 690 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 691 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 693 694 sc->fc.ioctl = fwohci_ioctl; 695 sc->fc.cyctimer = fwohci_cyctimer; 696 sc->fc.set_bmr = fwohci_set_bus_manager; 697 sc->fc.ibr = fwohci_ibr; 698 sc->fc.irx_enable = fwohci_irx_enable; 699 sc->fc.irx_disable = fwohci_irx_disable; 700 701 sc->fc.itx_enable = fwohci_itxbuf_enable; 702 sc->fc.itx_disable = fwohci_itx_disable; 703 sc->fc.irx_post = fwohci_irx_post; 704 sc->fc.itx_post = NULL; 705 sc->fc.timeout = fwohci_timeout; 706 sc->fc.poll = fwohci_poll; 707 sc->fc.set_intr = fwohci_set_intr; 708 709 fw_init(&sc->fc); 710 fwohci_reset(sc, dev); 711 712 return 0; 713} 714 715void 716fwohci_timeout(void *arg) 717{ 718 struct fwohci_softc *sc; 719 720 sc = (struct fwohci_softc *)arg; 721} 722 723u_int32_t 724fwohci_cyctimer(struct firewire_comm *fc) 725{ 726 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 727 return(OREAD(sc, OHCI_CYCLETIMER)); 728} 729 730int 731fwohci_detach(struct fwohci_softc *sc, device_t dev) 732{ 733 int i; 734 735 if (sc->fc.sid_buf != NULL) 736 free((void *)(uintptr_t)sc->fc.sid_buf, M_FW); 737 if (sc->cromptr != NULL) 738 free((void *)sc->cromptr, M_FW); 739 740 fwohci_db_free(&sc->arrq); 741 fwohci_db_free(&sc->arrs); 742 743 fwohci_db_free(&sc->atrq); 744 fwohci_db_free(&sc->atrs); 745 746 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 747 fwohci_db_free(&sc->it[i]); 748 fwohci_db_free(&sc->ir[i]); 749 } 750 751 return 0; 752} 753 754#define LAST_DB(dbtr, db) do { \ 755 struct fwohcidb_tr *_dbtr = (dbtr); \ 756 int _cnt = _dbtr->dbcnt; \ 757 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 758} while (0) 759 760static void 761fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 762{ 763 int i, s; 764 int tcode, hdr_len, hdr_off, len; 765 int fsegment = -1; 766 u_int32_t off; 767 struct fw_xfer *xfer; 768 struct fw_pkt *fp; 769 volatile struct fwohci_txpkthdr *ohcifp; 770 struct fwohcidb_tr *db_tr; 771 volatile struct fwohcidb *db; 772 struct mbuf *m; 773 struct tcode_info *info; 774 static int maxdesc=0; 775 776 if(&sc->atrq == dbch){ 777 off = OHCI_ATQOFF; 778 }else if(&sc->atrs == dbch){ 779 off = OHCI_ATSOFF; 780 }else{ 781 return; 782 } 783 784 if (dbch->flags & FWOHCI_DBCH_FULL) 785 return; 786 787 s = splfw(); 788 db_tr = dbch->top; 789txloop: 790 xfer = STAILQ_FIRST(&dbch->xferq.q); 791 if(xfer == NULL){ 792 goto kick; 793 } 794 if(dbch->xferq.queued == 0 ){ 795 device_printf(sc->fc.dev, "TX queue empty\n"); 796 } 797 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 798 db_tr->xfer = xfer; 799 xfer->state = FWXF_START; 800 dbch->xferq.packets++; 801 802 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 803 tcode = fp->mode.common.tcode; 804 805 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 806 info = &tinfo[tcode]; 807 hdr_len = hdr_off = info->hdr_len; 808 /* fw_asyreq must pass valid send.len */ 809 len = xfer->send.len; 810 for( i = 0 ; i < hdr_off ; i+= 4){ 811 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 812 } 813 ohcifp->mode.common.spd = xfer->spd; 814 if (tcode == FWTCODE_STREAM ){ 815 hdr_len = 8; 816 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 817 } else if (tcode == FWTCODE_PHY) { 818 hdr_len = 12; 819 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 820 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 821 ohcifp->mode.common.spd = 0; 822 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 823 } else { 824 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 825 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 826 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 827 } 828 db = &db_tr->db[0]; 829 db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 830 db->db.desc.reqcount = hdr_len; 831 db->db.desc.status = 0; 832/* Specify bound timer of asy. responce */ 833 if(&sc->atrs == dbch){ 834 db->db.desc.count 835 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 836 } 837 838 db_tr->dbcnt = 2; 839 db = &db_tr->db[db_tr->dbcnt]; 840 if(len > hdr_off){ 841 if (xfer->mbuf == NULL) { 842 db->db.desc.addr 843 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 844 db->db.desc.control = OHCI_OUTPUT_MORE; 845 db->db.desc.reqcount = len - hdr_off; 846 db->db.desc.status = 0; 847 848 db_tr->dbcnt++; 849 } else { 850 int mchain=0; 851 /* XXX we assume mbuf chain is shorter than ndesc */ 852 for (m = xfer->mbuf; m != NULL; m = m->m_next) { 853 if (m->m_len == 0) 854 /* unrecoverable error could occur. */ 855 continue; 856 mchain++; 857 if (db_tr->dbcnt >= dbch->ndesc) 858 continue; 859 db->db.desc.addr 860 = vtophys(mtod(m, caddr_t)); 861 db->db.desc.control = OHCI_OUTPUT_MORE; 862 db->db.desc.reqcount = m->m_len; 863 db->db.desc.status = 0; 864 db++; 865 db_tr->dbcnt++; 866 } 867 if (mchain > dbch->ndesc - 2) 868 device_printf(sc->fc.dev, 869 "dbch->ndesc(%d) is too small for" 870 " mbuf chain(%d), trancated.\n", 871 dbch->ndesc, mchain); 872 } 873 } 874 if (maxdesc < db_tr->dbcnt) { 875 maxdesc = db_tr->dbcnt; 876 if (bootverbose) 877 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 878 } 879 /* last db */ 880 LAST_DB(db_tr, db); 881 db->db.desc.control |= OHCI_OUTPUT_LAST 882 | OHCI_INTERRUPT_ALWAYS 883 | OHCI_BRANCH_ALWAYS; 884 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 885 886 if(fsegment == -1 ) 887 fsegment = db_tr->dbcnt; 888 if (dbch->pdb_tr != NULL) { 889 LAST_DB(dbch->pdb_tr, db); 890 db->db.desc.depend |= db_tr->dbcnt; 891 } 892 dbch->pdb_tr = db_tr; 893 db_tr = STAILQ_NEXT(db_tr, link); 894 if(db_tr != dbch->bottom){ 895 goto txloop; 896 } else { 897 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 898 dbch->flags |= FWOHCI_DBCH_FULL; 899 } 900kick: 901 /* kick asy q */ 902 903 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 904 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 905 } else { 906 if (bootverbose) 907 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 908 OREAD(sc, OHCI_DMACTL(off))); 909 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 910 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 911 dbch->xferq.flag |= FWXFERQ_RUNNING; 912 } 913 914 dbch->top = db_tr; 915 splx(s); 916 return; 917} 918 919static void 920fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 921{ 922 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 923 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 924 return; 925} 926 927static void 928fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 929{ 930 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 931 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 932 return; 933} 934 935static void 936fwohci_start_atq(struct firewire_comm *fc) 937{ 938 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 939 fwohci_start( sc, &(sc->atrq)); 940 return; 941} 942 943static void 944fwohci_start_ats(struct firewire_comm *fc) 945{ 946 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 947 fwohci_start( sc, &(sc->atrs)); 948 return; 949} 950 951void 952fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 953{ 954 int s, err = 0; 955 struct fwohcidb_tr *tr; 956 volatile struct fwohcidb *db; 957 struct fw_xfer *xfer; 958 u_int32_t off; 959 u_int stat; 960 int packets; 961 struct firewire_comm *fc = (struct firewire_comm *)sc; 962 if(&sc->atrq == dbch){ 963 off = OHCI_ATQOFF; 964 }else if(&sc->atrs == dbch){ 965 off = OHCI_ATSOFF; 966 }else{ 967 return; 968 } 969 s = splfw(); 970 tr = dbch->bottom; 971 packets = 0; 972 while(dbch->xferq.queued > 0){ 973 LAST_DB(tr, db); 974 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 975 if (fc->status != FWBUSRESET) 976 /* maybe out of order?? */ 977 goto out; 978 } 979 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 980#ifdef OHCI_DEBUG 981 dump_dma(sc, ch); 982 dump_db(sc, ch); 983#endif 984/* Stop DMA */ 985 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 986 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 987 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 988 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 989 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 990 } 991 stat = db->db.desc.status & FWOHCIEV_MASK; 992 switch(stat){ 993 case FWOHCIEV_ACKPEND: 994 case FWOHCIEV_ACKCOMPL: 995 err = 0; 996 break; 997 case FWOHCIEV_ACKBSA: 998 case FWOHCIEV_ACKBSB: 999 case FWOHCIEV_ACKBSX: 1000 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1001 err = EBUSY; 1002 break; 1003 case FWOHCIEV_FLUSHED: 1004 case FWOHCIEV_ACKTARD: 1005 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1006 err = EAGAIN; 1007 break; 1008 case FWOHCIEV_MISSACK: 1009 case FWOHCIEV_UNDRRUN: 1010 case FWOHCIEV_OVRRUN: 1011 case FWOHCIEV_DESCERR: 1012 case FWOHCIEV_DTRDERR: 1013 case FWOHCIEV_TIMEOUT: 1014 case FWOHCIEV_TCODERR: 1015 case FWOHCIEV_UNKNOWN: 1016 case FWOHCIEV_ACKDERR: 1017 case FWOHCIEV_ACKTERR: 1018 default: 1019 device_printf(sc->fc.dev, "txd err=%2x %s\n", 1020 stat, fwohcicode[stat]); 1021 err = EINVAL; 1022 break; 1023 } 1024 if (tr->xfer != NULL) { 1025 xfer = tr->xfer; 1026 xfer->state = FWXF_SENT; 1027 if (err == EBUSY && fc->status != FWBUSRESET) { 1028 xfer->state = FWXF_BUSY; 1029 switch (xfer->act_type) { 1030 case FWACT_XFER: 1031 xfer->resp = err; 1032 if (xfer->retry_req != NULL) 1033 xfer->retry_req(xfer); 1034 else 1035 fw_xfer_done(xfer); 1036 break; 1037 default: 1038 break; 1039 } 1040 } else if (stat != FWOHCIEV_ACKPEND) { 1041 if (stat != FWOHCIEV_ACKCOMPL) 1042 xfer->state = FWXF_SENTERR; 1043 xfer->resp = err; 1044 switch (xfer->act_type) { 1045 case FWACT_XFER: 1046 fw_xfer_done(xfer); 1047 break; 1048 default: 1049 break; 1050 } 1051 } 1052 /* 1053 * The watchdog timer takes care of split 1054 * transcation timeout for ACKPEND case. 1055 */ 1056 } 1057 dbch->xferq.queued --; 1058 tr->xfer = NULL; 1059 1060 packets ++; 1061 tr = STAILQ_NEXT(tr, link); 1062 dbch->bottom = tr; 1063 } 1064out: 1065 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1066 printf("make free slot\n"); 1067 dbch->flags &= ~FWOHCI_DBCH_FULL; 1068 fwohci_start(sc, dbch); 1069 } 1070 splx(s); 1071} 1072 1073static void 1074fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1075{ 1076 int i, s, found=0; 1077 struct fwohcidb_tr *tr; 1078 1079 if(xfer->state != FWXF_START) return; 1080 1081 s = splfw(); 1082 tr = dbch->bottom; 1083 for (i = 0; i < dbch->xferq.queued; i ++) { 1084 if(tr->xfer == xfer){ 1085 tr->xfer = NULL; 1086#if 0 1087 dbch->xferq.queued --; 1088 /* XXX */ 1089 if (tr == dbch->bottom) 1090 dbch->bottom = STAILQ_NEXT(tr, link); 1091 if (dbch->flags & FWOHCI_DBCH_FULL) { 1092 printf("fwohci_drain: make slot\n"); 1093 dbch->flags &= ~FWOHCI_DBCH_FULL; 1094 fwohci_start((struct fwohci_softc *)fc, dbch); 1095 } 1096#endif 1097 found ++; 1098 break; 1099 } 1100 tr = STAILQ_NEXT(tr, link); 1101 } 1102 splx(s); 1103 if (!found) 1104 device_printf(fc->dev, "fwochi_drain: xfer not found\n"); 1105 return; 1106} 1107 1108static void 1109fwohci_db_free(struct fwohci_dbch *dbch) 1110{ 1111 struct fwohcidb_tr *db_tr; 1112 int idb, i; 1113 1114 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1115 return; 1116 1117 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1118 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1119 idb < dbch->ndb; 1120 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1121 if (db_tr->buf != NULL) { 1122 free(db_tr->buf, M_FW); 1123 db_tr->buf = NULL; 1124 } 1125 } 1126 } 1127 dbch->ndb = 0; 1128 db_tr = STAILQ_FIRST(&dbch->db_trq); 1129 for (i = 0; i < dbch->npages; i++) 1130 free(dbch->pages[i], M_FW); 1131 free(db_tr, M_FW); 1132 STAILQ_INIT(&dbch->db_trq); 1133 dbch->flags &= ~FWOHCI_DBCH_INIT; 1134} 1135 1136static void 1137fwohci_db_init(struct fwohci_dbch *dbch) 1138{ 1139 int idb; 1140 struct fwohcidb_tr *db_tr; 1141 int ndbpp, i, j; 1142 1143 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1144 goto out; 1145 1146 /* allocate DB entries and attach one to each DMA channels */ 1147 /* DB entry must start at 16 bytes bounary. */ 1148 STAILQ_INIT(&dbch->db_trq); 1149 db_tr = (struct fwohcidb_tr *) 1150 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1151 M_FW, M_ZERO); 1152 if(db_tr == NULL){ 1153 printf("fwohci_db_init: malloc(1) failed\n"); 1154 return; 1155 } 1156 1157 ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1158 dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1159 if (firewire_debug) 1160 printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1161 dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1162 if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1163 printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1164 dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1165 return; 1166 } 1167 for (i = 0; i < dbch->npages; i++) { 1168 dbch->pages[i] = malloc(PAGE_SIZE, M_FW, M_ZERO); 1169 if (dbch->pages[i] == NULL) { 1170 printf("fwohci_db_init: malloc(2) failed\n"); 1171 for (j = 0; j < i; j ++) 1172 free(dbch->pages[j], M_FW); 1173 free(db_tr, M_FW); 1174 return; 1175 } 1176 } 1177 /* Attach DB to DMA ch. */ 1178 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1179 db_tr->dbcnt = 0; 1180 db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1181 + dbch->ndesc * (idb % ndbpp); 1182 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1183 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1184 dbch->xferq.bnpacket != 0) { 1185 if (idb % dbch->xferq.bnpacket == 0) 1186 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1187 ].start = (caddr_t)db_tr; 1188 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1189 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1190 ].end = (caddr_t)db_tr; 1191 } 1192 db_tr++; 1193 } 1194 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1195 = STAILQ_FIRST(&dbch->db_trq); 1196out: 1197 dbch->frag.buf = NULL; 1198 dbch->frag.len = 0; 1199 dbch->frag.plen = 0; 1200 dbch->xferq.queued = 0; 1201 dbch->pdb_tr = NULL; 1202 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1203 dbch->bottom = dbch->top; 1204 dbch->flags = FWOHCI_DBCH_INIT; 1205} 1206 1207static int 1208fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1209{ 1210 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1211 int dummy; 1212 1213 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1214 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1215 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1216 /* XXX we cannot free buffers until the DMA really stops */ 1217 tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1218 fwohci_db_free(&sc->it[dmach]); 1219 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1220 return 0; 1221} 1222 1223static int 1224fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1225{ 1226 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1227 int dummy; 1228 1229 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1230 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1231 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1232 /* XXX we cannot free buffers until the DMA really stops */ 1233 tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1234 if(sc->ir[dmach].dummy != NULL){ 1235 free(sc->ir[dmach].dummy, M_FW); 1236 } 1237 sc->ir[dmach].dummy = NULL; 1238 fwohci_db_free(&sc->ir[dmach]); 1239 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1240 return 0; 1241} 1242 1243static void 1244fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1245{ 1246 qld[0] = ntohl(qld[0]); 1247 return; 1248} 1249 1250static int 1251fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1252{ 1253 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1254 int err = 0; 1255 unsigned short tag, ich; 1256 1257 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1258 ich = sc->ir[dmach].xferq.flag & 0x3f; 1259 1260#if 0 1261 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1262 wakeup(fc->ir[dmach]); 1263 return err; 1264 } 1265#endif 1266 1267 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1268 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1269 sc->ir[dmach].xferq.queued = 0; 1270 sc->ir[dmach].ndb = NDB; 1271 sc->ir[dmach].xferq.psize = PAGE_SIZE; 1272 sc->ir[dmach].ndesc = 1; 1273 fwohci_db_init(&sc->ir[dmach]); 1274 if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1275 return ENOMEM; 1276 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1277 } 1278 if(err){ 1279 device_printf(sc->fc.dev, "err in IRX setting\n"); 1280 return err; 1281 } 1282 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1283 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1284 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1285 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1286 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1287 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1288 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1289 OWRITE(sc, OHCI_IRCMD(dmach), 1290 vtophys(sc->ir[dmach].top->db) | 1); 1291 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1292 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1293 } 1294 return err; 1295} 1296 1297static int 1298fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1299{ 1300 int err = 0; 1301 int idb, z, i, dmach = 0; 1302 u_int32_t off = NULL; 1303 struct fwohcidb_tr *db_tr; 1304 volatile struct fwohcidb *db; 1305 1306 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1307 err = EINVAL; 1308 return err; 1309 } 1310 z = dbch->ndesc; 1311 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1312 if( &sc->it[dmach] == dbch){ 1313 off = OHCI_ITOFF(dmach); 1314 break; 1315 } 1316 } 1317 if(off == NULL){ 1318 err = EINVAL; 1319 return err; 1320 } 1321 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1322 return err; 1323 dbch->xferq.flag |= FWXFERQ_RUNNING; 1324 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1325 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1326 } 1327 db_tr = dbch->top; 1328 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1329 fwohci_add_tx_buf(db_tr, 1330 dbch->xferq.psize, dbch->xferq.flag, 1331 dbch->xferq.buf + dbch->xferq.psize * idb); 1332 if(STAILQ_NEXT(db_tr, link) == NULL){ 1333 break; 1334 } 1335 db = db_tr->db; 1336 db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend 1337 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1338 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1339 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1340 db[db_tr->dbcnt - 1].db.desc.control 1341 |= OHCI_INTERRUPT_ALWAYS; 1342 /* OHCI 1.1 and above */ 1343 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 1344#if 0 1345 db[0].db.desc.depend &= ~0xf; 1346 db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf; 1347#endif 1348 } 1349 } 1350 db_tr = STAILQ_NEXT(db_tr, link); 1351 } 1352 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1353 return err; 1354} 1355 1356static int 1357fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1358{ 1359 int err = 0; 1360 int idb, z, i, dmach = 0, ldesc; 1361 u_int32_t off = NULL; 1362 struct fwohcidb_tr *db_tr; 1363 volatile struct fwohcidb *db; 1364 1365 z = dbch->ndesc; 1366 if(&sc->arrq == dbch){ 1367 off = OHCI_ARQOFF; 1368 }else if(&sc->arrs == dbch){ 1369 off = OHCI_ARSOFF; 1370 }else{ 1371 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1372 if( &sc->ir[dmach] == dbch){ 1373 off = OHCI_IROFF(dmach); 1374 break; 1375 } 1376 } 1377 } 1378 if(off == NULL){ 1379 err = EINVAL; 1380 return err; 1381 } 1382 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1383 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1384 return err; 1385 }else{ 1386 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1387 err = EBUSY; 1388 return err; 1389 } 1390 } 1391 dbch->xferq.flag |= FWXFERQ_RUNNING; 1392 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1393 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1394 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1395 } 1396 db_tr = dbch->top; 1397 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1398 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1399 fwohci_add_rx_buf(db_tr, 1400 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1401 }else{ 1402 fwohci_add_rx_buf(db_tr, 1403 dbch->xferq.psize, dbch->xferq.flag, 1404 dbch->xferq.buf + dbch->xferq.psize * idb, 1405 dbch->dummy + sizeof(u_int32_t) * idb); 1406 } 1407 if(STAILQ_NEXT(db_tr, link) == NULL){ 1408 break; 1409 } 1410 db = db_tr->db; 1411 ldesc = db_tr->dbcnt - 1; 1412 db[ldesc].db.desc.depend 1413 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1414 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1415 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1416 db[ldesc].db.desc.control 1417 |= OHCI_INTERRUPT_ALWAYS; 1418 db[ldesc].db.desc.depend &= ~0xf; 1419 } 1420 } 1421 db_tr = STAILQ_NEXT(db_tr, link); 1422 } 1423 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1424 dbch->buf_offset = 0; 1425 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1426 return err; 1427 }else{ 1428 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1429 } 1430 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1431 return err; 1432} 1433 1434static int 1435fwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1436{ 1437 int sec, cycle, cycle_match; 1438 1439 cycle = cycle_now & 0x1fff; 1440 sec = cycle_now >> 13; 1441#define CYCLE_MOD 0x10 1442#define CYCLE_DELAY 8 /* min delay to start DMA */ 1443 cycle = cycle + CYCLE_DELAY; 1444 if (cycle >= 8000) { 1445 sec ++; 1446 cycle -= 8000; 1447 } 1448 cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1449 if (cycle >= 8000) { 1450 sec ++; 1451 if (cycle == 8000) 1452 cycle = 0; 1453 else 1454 cycle = CYCLE_MOD; 1455 } 1456 cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1457 1458 return(cycle_match); 1459} 1460 1461static int 1462fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1463{ 1464 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1465 int err = 0; 1466 unsigned short tag, ich; 1467 struct fwohci_dbch *dbch; 1468 int cycle_match, cycle_now, s, ldesc; 1469 u_int32_t stat; 1470 struct fw_bulkxfer *first, *chunk, *prev; 1471 struct fw_xferq *it; 1472 1473 dbch = &sc->it[dmach]; 1474 it = &dbch->xferq; 1475 1476 tag = (it->flag >> 6) & 3; 1477 ich = it->flag & 0x3f; 1478 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1479 dbch->ndb = it->bnpacket * it->bnchunk; 1480 dbch->ndesc = 3; 1481 fwohci_db_init(dbch); 1482 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1483 return ENOMEM; 1484 err = fwohci_tx_enable(sc, dbch); 1485 } 1486 if(err) 1487 return err; 1488 1489 ldesc = dbch->ndesc - 1; 1490 s = splfw(); 1491 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1492 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1493 volatile struct fwohcidb *db; 1494 1495 fwohci_txbufdb(sc, dmach, chunk); 1496#if 0 1497 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1498 db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1499 db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1500 db[ldesc].db.desc.depend &= ~0xf; 1501 db[0].db.desc.depend &= ~0xf; 1502#endif 1503 if (prev != NULL) { 1504 db = ((struct fwohcidb_tr *)(prev->end))->db; 1505 db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS; 1506#if 0 /* if bulkxfer->npacket changes */ 1507 db[ldesc].db.desc.depend = db[0].db.desc.depend = 1508 vtophys(((struct fwohcidb_tr *) 1509 (chunk->start))->db) | dbch->ndesc; 1510#else 1511 db[0].db.desc.depend |= dbch->ndesc; 1512 db[ldesc].db.desc.depend |= dbch->ndesc; 1513#endif 1514 } 1515 STAILQ_REMOVE_HEAD(&it->stvalid, link); 1516 STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1517 prev = chunk; 1518 } 1519 splx(s); 1520 stat = OREAD(sc, OHCI_ITCTL(dmach)); 1521 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1522 return 0; 1523 1524 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1525 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1526 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1527 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1528 1529 first = STAILQ_FIRST(&it->stdma); 1530 OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1531 (first->start))->db) | dbch->ndesc); 1532 if (firewire_debug) 1533 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1534 if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1535#if 1 1536 /* Don't start until all chunks are buffered */ 1537 if (STAILQ_FIRST(&it->stfree) != NULL) 1538 goto out; 1539#endif 1540#ifdef FWXFERQ_DV 1541#define CYCLE_OFFSET 1 1542 if(dbch->xferq.flag & FWXFERQ_DV){ 1543 struct fw_pkt *fp; 1544 struct fwohcidb_tr *db_tr; 1545 1546 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1547 fp = (struct fw_pkt *)db_tr->buf; 1548 dbch->xferq.dvoffset = CYCLE_OFFSET; 1549 fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1550 } 1551#endif 1552 /* Clear cycle match counter bits */ 1553 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1554 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1555 1556 /* 2bit second + 13bit cycle */ 1557 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1558 cycle_match = fwochi_next_cycle(fc, cycle_now); 1559 1560 OWRITE(sc, OHCI_ITCTL(dmach), 1561 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1562 | OHCI_CNTL_DMA_RUN); 1563 if (firewire_debug) 1564 printf("cycle_match: 0x%04x->0x%04x\n", 1565 cycle_now, cycle_match); 1566 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1567 device_printf(sc->fc.dev, 1568 "IT DMA underrun (0x%08x)\n", stat); 1569 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1570 } 1571out: 1572 return err; 1573} 1574 1575static int 1576fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1577{ 1578 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1579 int err = 0, s, ldesc; 1580 unsigned short tag, ich; 1581 u_int32_t stat; 1582 struct fwohci_dbch *dbch; 1583 struct fw_bulkxfer *first, *prev, *chunk; 1584 struct fw_xferq *ir; 1585 1586 dbch = &sc->ir[dmach]; 1587 ir = &dbch->xferq; 1588 ldesc = dbch->ndesc - 1; 1589 1590 if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1591 tag = (ir->flag >> 6) & 3; 1592 ich = ir->flag & 0x3f; 1593 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1594 1595 ir->queued = 0; 1596 dbch->ndb = ir->bnpacket * ir->bnchunk; 1597 dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1598 M_FW, 0); 1599 if (dbch->dummy == NULL) { 1600 err = ENOMEM; 1601 return err; 1602 } 1603 dbch->ndesc = 2; 1604 fwohci_db_init(dbch); 1605 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1606 return ENOMEM; 1607 err = fwohci_rx_enable(sc, dbch); 1608 } 1609 if(err) 1610 return err; 1611 1612 s = splfw(); 1613 1614 first = STAILQ_FIRST(&ir->stfree); 1615 if (first == NULL) { 1616 device_printf(fc->dev, "IR DMA no free chunk\n"); 1617 splx(s); 1618 return 0; 1619 } 1620 1621 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1622 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1623 volatile struct fwohcidb *db; 1624 1625 db = ((struct fwohcidb_tr *)(chunk->end))->db; 1626 db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1627 db[ldesc].db.desc.depend &= ~0xf; 1628 if (prev != NULL) { 1629 db = ((struct fwohcidb_tr *)(prev->end))->db; 1630#if 0 1631 db[ldesc].db.desc.depend = 1632 vtophys(((struct fwohcidb_tr *) 1633 (chunk->start))->db) | dbch->ndesc; 1634#else 1635 db[ldesc].db.desc.depend |= dbch->ndesc; 1636#endif 1637 } 1638 STAILQ_REMOVE_HEAD(&ir->stfree, link); 1639 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1640 prev = chunk; 1641 } 1642 splx(s); 1643 stat = OREAD(sc, OHCI_IRCTL(dmach)); 1644 if (stat & OHCI_CNTL_DMA_ACTIVE) 1645 return 0; 1646 if (stat & OHCI_CNTL_DMA_RUN) { 1647 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1648 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1649 } 1650 1651 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1652 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1653 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1654 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1655 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1656 OWRITE(sc, OHCI_IRCMD(dmach), 1657 vtophys(((struct fwohcidb_tr *)(first->start))->db) 1658 | dbch->ndesc); 1659 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1660 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1661 return err; 1662} 1663 1664static int 1665fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1666{ 1667 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1668 int err = 0; 1669 1670 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1671 err = fwohci_irxpp_enable(fc, dmach); 1672 return err; 1673 }else{ 1674 err = fwohci_irxbuf_enable(fc, dmach); 1675 return err; 1676 } 1677} 1678 1679int 1680fwohci_stop(struct fwohci_softc *sc, device_t dev) 1681{ 1682 u_int i; 1683 1684/* Now stopping all DMA channel */ 1685 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1686 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1687 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1688 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1689 1690 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1691 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1692 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1693 } 1694 1695/* FLUSH FIFO and reset Transmitter/Reciever */ 1696 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1697 1698/* Stop interrupt */ 1699 OWRITE(sc, FWOHCI_INTMASKCLR, 1700 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1701 | OHCI_INT_PHY_INT 1702 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1703 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1704 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1705 | OHCI_INT_PHY_BUS_R); 1706/* XXX Link down? Bus reset? */ 1707 return 0; 1708} 1709 1710int 1711fwohci_resume(struct fwohci_softc *sc, device_t dev) 1712{ 1713 int i; 1714 1715 fwohci_reset(sc, dev); 1716 /* XXX resume isochronus receive automatically. (how about TX?) */ 1717 for(i = 0; i < sc->fc.nisodma; i ++) { 1718 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1719 device_printf(sc->fc.dev, 1720 "resume iso receive ch: %d\n", i); 1721 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1722 sc->fc.irx_enable(&sc->fc, i); 1723 } 1724 } 1725 1726 bus_generic_resume(dev); 1727 sc->fc.ibr(&sc->fc); 1728 return 0; 1729} 1730 1731#define ACK_ALL 1732static void 1733fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1734{ 1735 u_int32_t irstat, itstat; 1736 u_int i; 1737 struct firewire_comm *fc = (struct firewire_comm *)sc; 1738 1739#ifdef OHCI_DEBUG 1740 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1741 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1742 stat & OHCI_INT_EN ? "DMA_EN ":"", 1743 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1744 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1745 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1746 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1747 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1748 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1749 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1750 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1751 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1752 stat & OHCI_INT_PHY_SID ? "SID ":"", 1753 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1754 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1755 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1756 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1757 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1758 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1759 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1760 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1761 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1762 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1763 stat, OREAD(sc, FWOHCI_INTMASK) 1764 ); 1765#endif 1766/* Bus reset */ 1767 if(stat & OHCI_INT_PHY_BUS_R ){ 1768 device_printf(fc->dev, "BUS reset\n"); 1769 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1770 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1771 1772 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1773 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1774 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1775 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1776 1777#ifndef ACK_ALL 1778 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1779#endif 1780 fw_busreset(fc); 1781 1782 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1783 /* XXX insecure ?? */ 1784 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1785 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1786 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1787 1788 } 1789 if((stat & OHCI_INT_DMA_IR )){ 1790#ifndef ACK_ALL 1791 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1792#endif 1793 irstat = OREAD(sc, OHCI_IR_STAT); 1794 OWRITE(sc, OHCI_IR_STATCLR, irstat); 1795 for(i = 0; i < fc->nisodma ; i++){ 1796 struct fwohci_dbch *dbch; 1797 1798 if((irstat & (1 << i)) != 0){ 1799 dbch = &sc->ir[i]; 1800 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1801 device_printf(sc->fc.dev, 1802 "dma(%d) not active\n", i); 1803 continue; 1804 } 1805 if (dbch->xferq.flag & FWXFERQ_PACKET) { 1806 fwohci_ircv(sc, dbch, count); 1807 } else { 1808 fwohci_rbuf_update(sc, i); 1809 } 1810 } 1811 } 1812 } 1813 if((stat & OHCI_INT_DMA_IT )){ 1814#ifndef ACK_ALL 1815 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1816#endif 1817 itstat = OREAD(sc, OHCI_IT_STAT); 1818 OWRITE(sc, OHCI_IT_STATCLR, itstat); 1819 for(i = 0; i < fc->nisodma ; i++){ 1820 if((itstat & (1 << i)) != 0){ 1821 fwohci_tbuf_update(sc, i); 1822 } 1823 } 1824 } 1825 if((stat & OHCI_INT_DMA_PRRS )){ 1826#ifndef ACK_ALL 1827 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1828#endif 1829#if 0 1830 dump_dma(sc, ARRS_CH); 1831 dump_db(sc, ARRS_CH); 1832#endif 1833 fwohci_arcv(sc, &sc->arrs, count); 1834 } 1835 if((stat & OHCI_INT_DMA_PRRQ )){ 1836#ifndef ACK_ALL 1837 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1838#endif 1839#if 0 1840 dump_dma(sc, ARRQ_CH); 1841 dump_db(sc, ARRQ_CH); 1842#endif 1843 fwohci_arcv(sc, &sc->arrq, count); 1844 } 1845 if(stat & OHCI_INT_PHY_SID){ 1846 caddr_t buf; 1847 int plen; 1848 1849#ifndef ACK_ALL 1850 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1851#endif 1852/* 1853** Checking whether the node is root or not. If root, turn on 1854** cycle master. 1855*/ 1856 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1857 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1858 printf("Bus reset failure\n"); 1859 goto sidout; 1860 } 1861 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1862 printf("CYCLEMASTER mode\n"); 1863 OWRITE(sc, OHCI_LNKCTL, 1864 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1865 }else{ 1866 printf("non CYCLEMASTER mode\n"); 1867 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1868 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1869 } 1870 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1871 1872 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1873 if (plen < 4 || plen > OHCI_SIDSIZE) { 1874 device_printf(fc->dev, "invalid SID len = %d\n", plen); 1875 goto sidout; 1876 } 1877 plen -= 4; /* chop control info */ 1878 buf = malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1879 if(buf == NULL) goto sidout; 1880 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1881 buf, plen); 1882#if 1 1883 /* pending all pre-bus_reset packets */ 1884 fwohci_txd(sc, &sc->atrq); 1885 fwohci_txd(sc, &sc->atrs); 1886 fwohci_arcv(sc, &sc->arrs, -1); 1887 fwohci_arcv(sc, &sc->arrq, -1); 1888 fw_drain_txq(fc); 1889#endif 1890 fw_sidrcv(fc, buf, plen, 0); 1891 } 1892sidout: 1893 if((stat & OHCI_INT_DMA_ATRQ )){ 1894#ifndef ACK_ALL 1895 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1896#endif 1897 fwohci_txd(sc, &(sc->atrq)); 1898 } 1899 if((stat & OHCI_INT_DMA_ATRS )){ 1900#ifndef ACK_ALL 1901 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1902#endif 1903 fwohci_txd(sc, &(sc->atrs)); 1904 } 1905 if((stat & OHCI_INT_PW_ERR )){ 1906#ifndef ACK_ALL 1907 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1908#endif 1909 device_printf(fc->dev, "posted write error\n"); 1910 } 1911 if((stat & OHCI_INT_ERR )){ 1912#ifndef ACK_ALL 1913 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1914#endif 1915 device_printf(fc->dev, "unrecoverable error\n"); 1916 } 1917 if((stat & OHCI_INT_PHY_INT)) { 1918#ifndef ACK_ALL 1919 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1920#endif 1921 device_printf(fc->dev, "phy int\n"); 1922 } 1923 1924 return; 1925} 1926 1927void 1928fwohci_intr(void *arg) 1929{ 1930 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1931 u_int32_t stat; 1932 1933 if (!(sc->intmask & OHCI_INT_EN)) { 1934 /* polling mode */ 1935 return; 1936 } 1937 1938 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1939 if (stat == 0xffffffff) { 1940 device_printf(sc->fc.dev, 1941 "device physically ejected?\n"); 1942 return; 1943 } 1944#ifdef ACK_ALL 1945 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1946#endif 1947 fwohci_intr_body(sc, stat, -1); 1948 } 1949} 1950 1951static void 1952fwohci_poll(struct firewire_comm *fc, int quick, int count) 1953{ 1954 int s; 1955 u_int32_t stat; 1956 struct fwohci_softc *sc; 1957 1958 1959 sc = (struct fwohci_softc *)fc; 1960 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1961 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1962 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1963#if 0 1964 if (!quick) { 1965#else 1966 if (1) { 1967#endif 1968 stat = OREAD(sc, FWOHCI_INTSTAT); 1969 if (stat == 0) 1970 return; 1971 if (stat == 0xffffffff) { 1972 device_printf(sc->fc.dev, 1973 "device physically ejected?\n"); 1974 return; 1975 } 1976#ifdef ACK_ALL 1977 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1978#endif 1979 } 1980 s = splfw(); 1981 fwohci_intr_body(sc, stat, count); 1982 splx(s); 1983} 1984 1985static void 1986fwohci_set_intr(struct firewire_comm *fc, int enable) 1987{ 1988 struct fwohci_softc *sc; 1989 1990 sc = (struct fwohci_softc *)fc; 1991 if (bootverbose) 1992 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1993 if (enable) { 1994 sc->intmask |= OHCI_INT_EN; 1995 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1996 } else { 1997 sc->intmask &= ~OHCI_INT_EN; 1998 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1999 } 2000} 2001 2002static void 2003fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2004{ 2005 struct firewire_comm *fc = &sc->fc; 2006 volatile struct fwohcidb *db; 2007 struct fw_bulkxfer *chunk; 2008 struct fw_xferq *it; 2009 u_int32_t stat, count; 2010 int s, w=0; 2011 2012 it = fc->it[dmach]; 2013 s = splfw(); /* unnecessary ? */ 2014 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2015 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2016 stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2017 db = ((struct fwohcidb_tr *)(chunk->start))->db; 2018 count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2019 if (stat == 0) 2020 break; 2021 STAILQ_REMOVE_HEAD(&it->stdma, link); 2022 switch (stat & FWOHCIEV_MASK){ 2023 case FWOHCIEV_ACKCOMPL: 2024#if 0 2025 device_printf(fc->dev, "0x%08x\n", count); 2026#endif 2027 break; 2028 default: 2029 device_printf(fc->dev, 2030 "Isochronous transmit err %02x\n", stat); 2031 } 2032 STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2033 w++; 2034 } 2035 splx(s); 2036 if (w) 2037 wakeup(it); 2038} 2039 2040static void 2041fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2042{ 2043 struct firewire_comm *fc = &sc->fc; 2044 volatile struct fwohcidb *db; 2045 struct fw_bulkxfer *chunk; 2046 struct fw_xferq *ir; 2047 u_int32_t stat; 2048 int s, w=0; 2049 2050 ir = fc->ir[dmach]; 2051 s = splfw(); 2052 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2053 db = ((struct fwohcidb_tr *)(chunk->end))->db; 2054 stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2055 if (stat == 0) 2056 break; 2057 STAILQ_REMOVE_HEAD(&ir->stdma, link); 2058 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2059 switch (stat & FWOHCIEV_MASK) { 2060 case FWOHCIEV_ACKCOMPL: 2061 break; 2062 default: 2063 device_printf(fc->dev, 2064 "Isochronous receive err %02x\n", stat); 2065 } 2066 w++; 2067 } 2068 splx(s); 2069 if (w) 2070 wakeup(ir); 2071} 2072 2073void 2074dump_dma(struct fwohci_softc *sc, u_int32_t ch) 2075{ 2076 u_int32_t off, cntl, stat, cmd, match; 2077 2078 if(ch == 0){ 2079 off = OHCI_ATQOFF; 2080 }else if(ch == 1){ 2081 off = OHCI_ATSOFF; 2082 }else if(ch == 2){ 2083 off = OHCI_ARQOFF; 2084 }else if(ch == 3){ 2085 off = OHCI_ARSOFF; 2086 }else if(ch < IRX_CH){ 2087 off = OHCI_ITCTL(ch - ITX_CH); 2088 }else{ 2089 off = OHCI_IRCTL(ch - IRX_CH); 2090 } 2091 cntl = stat = OREAD(sc, off); 2092 cmd = OREAD(sc, off + 0xc); 2093 match = OREAD(sc, off + 0x10); 2094 2095 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2096 ch, 2097 cntl, 2098 stat, 2099 cmd, 2100 match); 2101 stat &= 0xffff ; 2102 if(stat & 0xff00){ 2103 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2104 ch, 2105 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2106 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2107 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2108 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2109 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2110 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2111 fwohcicode[stat & 0x1f], 2112 stat & 0x1f 2113 ); 2114 }else{ 2115 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2116 } 2117} 2118 2119void 2120dump_db(struct fwohci_softc *sc, u_int32_t ch) 2121{ 2122 struct fwohci_dbch *dbch; 2123 struct fwohcidb_tr *cp = NULL, *pp, *np; 2124 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2125 int idb, jdb; 2126 u_int32_t cmd, off; 2127 if(ch == 0){ 2128 off = OHCI_ATQOFF; 2129 dbch = &sc->atrq; 2130 }else if(ch == 1){ 2131 off = OHCI_ATSOFF; 2132 dbch = &sc->atrs; 2133 }else if(ch == 2){ 2134 off = OHCI_ARQOFF; 2135 dbch = &sc->arrq; 2136 }else if(ch == 3){ 2137 off = OHCI_ARSOFF; 2138 dbch = &sc->arrs; 2139 }else if(ch < IRX_CH){ 2140 off = OHCI_ITCTL(ch - ITX_CH); 2141 dbch = &sc->it[ch - ITX_CH]; 2142 }else { 2143 off = OHCI_IRCTL(ch - IRX_CH); 2144 dbch = &sc->ir[ch - IRX_CH]; 2145 } 2146 cmd = OREAD(sc, off + 0xc); 2147 2148 if( dbch->ndb == 0 ){ 2149 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2150 return; 2151 } 2152 pp = dbch->top; 2153 prev = pp->db; 2154 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2155 if(pp == NULL){ 2156 curr = NULL; 2157 goto outdb; 2158 } 2159 cp = STAILQ_NEXT(pp, link); 2160 if(cp == NULL){ 2161 curr = NULL; 2162 goto outdb; 2163 } 2164 np = STAILQ_NEXT(cp, link); 2165 if(cp == NULL) break; 2166 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2167 if((cmd & 0xfffffff0) 2168 == vtophys(&(cp->db[jdb]))){ 2169 curr = cp->db; 2170 if(np != NULL){ 2171 next = np->db; 2172 }else{ 2173 next = NULL; 2174 } 2175 goto outdb; 2176 } 2177 } 2178 pp = STAILQ_NEXT(pp, link); 2179 prev = pp->db; 2180 } 2181outdb: 2182 if( curr != NULL){ 2183 printf("Prev DB %d\n", ch); 2184 print_db(prev, ch, dbch->ndesc); 2185 printf("Current DB %d\n", ch); 2186 print_db(curr, ch, dbch->ndesc); 2187 printf("Next DB %d\n", ch); 2188 print_db(next, ch, dbch->ndesc); 2189 }else{ 2190 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2191 } 2192 return; 2193} 2194 2195void 2196print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2197{ 2198 fwohcireg_t stat; 2199 int i, key; 2200 2201 if(db == NULL){ 2202 printf("No Descriptor is found\n"); 2203 return; 2204 } 2205 2206 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2207 ch, 2208 "Current", 2209 "OP ", 2210 "KEY", 2211 "INT", 2212 "BR ", 2213 "len", 2214 "Addr", 2215 "Depend", 2216 "Stat", 2217 "Cnt"); 2218 for( i = 0 ; i <= max ; i ++){ 2219 key = db[i].db.desc.control & OHCI_KEY_MASK; 2220#if __FreeBSD_version >= 500000 2221 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2222#else 2223 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2224#endif 2225 vtophys(&db[i]), 2226 dbcode[(db[i].db.desc.control >> 12) & 0xf], 2227 dbkey[(db[i].db.desc.control >> 8) & 0x7], 2228 dbcond[(db[i].db.desc.control >> 4) & 0x3], 2229 dbcond[(db[i].db.desc.control >> 2) & 0x3], 2230 db[i].db.desc.reqcount, 2231 db[i].db.desc.addr, 2232 db[i].db.desc.depend, 2233 db[i].db.desc.status, 2234 db[i].db.desc.count); 2235 stat = db[i].db.desc.status; 2236 if(stat & 0xff00){ 2237 printf(" %s%s%s%s%s%s %s(%x)\n", 2238 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2239 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2240 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2241 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2242 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2243 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2244 fwohcicode[stat & 0x1f], 2245 stat & 0x1f 2246 ); 2247 }else{ 2248 printf(" Nostat\n"); 2249 } 2250 if(key == OHCI_KEY_ST2 ){ 2251 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2252 db[i+1].db.immed[0], 2253 db[i+1].db.immed[1], 2254 db[i+1].db.immed[2], 2255 db[i+1].db.immed[3]); 2256 } 2257 if(key == OHCI_KEY_DEVICE){ 2258 return; 2259 } 2260 if((db[i].db.desc.control & OHCI_BRANCH_MASK) 2261 == OHCI_BRANCH_ALWAYS){ 2262 return; 2263 } 2264 if((db[i].db.desc.control & OHCI_CMD_MASK) 2265 == OHCI_OUTPUT_LAST){ 2266 return; 2267 } 2268 if((db[i].db.desc.control & OHCI_CMD_MASK) 2269 == OHCI_INPUT_LAST){ 2270 return; 2271 } 2272 if(key == OHCI_KEY_ST2 ){ 2273 i++; 2274 } 2275 } 2276 return; 2277} 2278 2279void 2280fwohci_ibr(struct firewire_comm *fc) 2281{ 2282 struct fwohci_softc *sc; 2283 u_int32_t fun; 2284 2285 device_printf(fc->dev, "Initiate bus reset\n"); 2286 sc = (struct fwohci_softc *)fc; 2287 2288 /* 2289 * Set root hold-off bit so that non cyclemaster capable node 2290 * shouldn't became the root node. 2291 */ 2292#if 1 2293 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2294 fun |= FW_PHY_IBR | FW_PHY_RHB; 2295 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2296#else /* Short bus reset */ 2297 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2298 fun |= FW_PHY_ISBR | FW_PHY_RHB; 2299 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2300#endif 2301} 2302 2303void 2304fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2305{ 2306 struct fwohcidb_tr *db_tr, *fdb_tr; 2307 struct fwohci_dbch *dbch; 2308 volatile struct fwohcidb *db; 2309 struct fw_pkt *fp; 2310 volatile struct fwohci_txpkthdr *ohcifp; 2311 unsigned short chtag; 2312 int idb; 2313 2314 dbch = &sc->it[dmach]; 2315 chtag = sc->it[dmach].xferq.flag & 0xff; 2316 2317 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2318 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2319/* 2320device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2321*/ 2322 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2323 db = db_tr->db; 2324#if 0 2325 db[0].db.desc.control 2326 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2327 db[0].db.desc.reqcount = 8; 2328#endif 2329 fp = (struct fw_pkt *)db_tr->buf; 2330 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2331 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2332 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2333 ohcifp->mode.stream.chtag = chtag; 2334 ohcifp->mode.stream.tcode = 0xa; 2335 ohcifp->mode.stream.spd = 0; 2336 2337 db[2].db.desc.reqcount = ntohs(fp->mode.stream.len); 2338 db[2].db.desc.status = 0; 2339 db[2].db.desc.count = 0; 2340#if 0 /* if bulkxfer->npackets changes */ 2341 db[2].db.desc.control = OHCI_OUTPUT_LAST 2342 | OHCI_UPDATE 2343 | OHCI_BRANCH_ALWAYS; 2344 db[0].db.desc.depend = 2345 = db[dbch->ndesc - 1].db.desc.depend 2346 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2347#else 2348 db[0].db.desc.depend |= dbch->ndesc; 2349 db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc; 2350#endif 2351 bulkxfer->end = (caddr_t)db_tr; 2352 db_tr = STAILQ_NEXT(db_tr, link); 2353 } 2354 db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2355 db[0].db.desc.depend &= ~0xf; 2356 db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2357#if 0 /* if bulkxfer->npackets changes */ 2358 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2359 /* OHCI 1.1 and above */ 2360 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2361#endif 2362/* 2363 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2364 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2365device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2366*/ 2367 return; 2368} 2369 2370static int 2371fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2372 int mode, void *buf) 2373{ 2374 volatile struct fwohcidb *db = db_tr->db; 2375 int err = 0; 2376 if(buf == 0){ 2377 err = EINVAL; 2378 return err; 2379 } 2380 db_tr->buf = buf; 2381 db_tr->dbcnt = 3; 2382 db_tr->dummy = NULL; 2383 2384 db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2385 db[0].db.desc.reqcount = 8; 2386 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2387 db[2].db.desc.control = 2388 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; 2389#if 1 2390 db[0].db.desc.status = 0; 2391 db[0].db.desc.count = 0; 2392 db[2].db.desc.status = 0; 2393 db[2].db.desc.count = 0; 2394#endif 2395 if( mode & FWXFERQ_STREAM ){ 2396 if(mode & FWXFERQ_PACKET ){ 2397 db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2398 } 2399 } else { 2400 printf("fwohci_add_tx_buf: who calls me?"); 2401 } 2402 return 1; 2403} 2404 2405int 2406fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2407 void *buf, void *dummy) 2408{ 2409 volatile struct fwohcidb *db = db_tr->db; 2410 int i; 2411 void *dbuf[2]; 2412 int dsiz[2]; 2413 2414 if(buf == 0){ 2415 buf = malloc(size, M_FW, M_NOWAIT); 2416 if(buf == NULL) return 0; 2417 db_tr->buf = buf; 2418 db_tr->dbcnt = 1; 2419 db_tr->dummy = NULL; 2420 dsiz[0] = size; 2421 dbuf[0] = buf; 2422 }else if(dummy == NULL){ 2423 db_tr->buf = buf; 2424 db_tr->dbcnt = 1; 2425 db_tr->dummy = NULL; 2426 dsiz[0] = size; 2427 dbuf[0] = buf; 2428 }else{ 2429 db_tr->buf = buf; 2430 db_tr->dbcnt = 2; 2431 db_tr->dummy = dummy; 2432 dsiz[0] = sizeof(u_int32_t); 2433 dsiz[1] = size; 2434 dbuf[0] = dummy; 2435 dbuf[1] = buf; 2436 } 2437 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2438 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2439 db[i].db.desc.control = OHCI_INPUT_MORE; 2440 db[i].db.desc.reqcount = dsiz[i]; 2441 if( mode & FWXFERQ_STREAM ){ 2442 db[i].db.desc.control |= OHCI_UPDATE; 2443 } 2444 db[i].db.desc.status = 0; 2445 db[i].db.desc.count = dsiz[i]; 2446 } 2447 if( mode & FWXFERQ_STREAM ){ 2448 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST; 2449 if(mode & FWXFERQ_PACKET ){ 2450 db[db_tr->dbcnt - 1].db.desc.control 2451 |= OHCI_INTERRUPT_ALWAYS; 2452 } 2453 } 2454 db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS; 2455 return 1; 2456} 2457 2458static void 2459fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2460{ 2461 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2462 struct firewire_comm *fc = (struct firewire_comm *)sc; 2463 int z = 1; 2464 struct fw_pkt *fp; 2465 u_int8_t *ld; 2466 u_int32_t off = NULL; 2467 u_int32_t stat; 2468 u_int32_t *qld; 2469 u_int32_t reg; 2470 u_int spd; 2471 u_int dmach; 2472 int len, i, plen; 2473 caddr_t buf; 2474 2475 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2476 if( &sc->ir[dmach] == dbch){ 2477 off = OHCI_IROFF(dmach); 2478 break; 2479 } 2480 } 2481 if(off == NULL){ 2482 return; 2483 } 2484 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2485 fwohci_irx_disable(&sc->fc, dmach); 2486 return; 2487 } 2488 2489 odb_tr = NULL; 2490 db_tr = dbch->top; 2491 i = 0; 2492 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2493 if (count >= 0 && count-- == 0) 2494 break; 2495 ld = (u_int8_t *)db_tr->buf; 2496 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2497 /* skip timeStamp */ 2498 ld += sizeof(struct fwohci_trailer); 2499 } 2500 qld = (u_int32_t *)ld; 2501 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2502/* 2503{ 2504device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2505 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2506} 2507*/ 2508 fp=(struct fw_pkt *)ld; 2509 qld[0] = htonl(qld[0]); 2510 plen = sizeof(struct fw_isohdr) 2511 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2512 ld += plen; 2513 len -= plen; 2514 buf = db_tr->buf; 2515 db_tr->buf = NULL; 2516 stat = reg & 0x1f; 2517 spd = reg & 0x3; 2518 switch(stat){ 2519 case FWOHCIEV_ACKCOMPL: 2520 case FWOHCIEV_ACKPEND: 2521 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2522 break; 2523 default: 2524 free(buf, M_FW); 2525 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2526 break; 2527 } 2528 i++; 2529 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2530 dbch->xferq.flag, 0, NULL); 2531 db_tr->db[0].db.desc.depend &= ~0xf; 2532 if(dbch->pdb_tr != NULL){ 2533 dbch->pdb_tr->db[0].db.desc.depend |= z; 2534 } else { 2535 /* XXX should be rewritten in better way */ 2536 dbch->bottom->db[0].db.desc.depend |= z; 2537 } 2538 dbch->pdb_tr = db_tr; 2539 db_tr = STAILQ_NEXT(db_tr, link); 2540 } 2541 dbch->top = db_tr; 2542 reg = OREAD(sc, OHCI_DMACTL(off)); 2543 if (reg & OHCI_CNTL_DMA_ACTIVE) 2544 return; 2545 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2546 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2547 dbch->top = db_tr; 2548 fwohci_irx_enable(fc, dmach); 2549} 2550 2551#define PLEN(x) roundup2(ntohs(x), sizeof(u_int32_t)) 2552static int 2553fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp, int hlen) 2554{ 2555 int i, r; 2556 2557 for( i = 4; i < hlen ; i+=4){ 2558 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2559 } 2560 2561 switch(fp->mode.common.tcode){ 2562 case FWTCODE_RREQQ: 2563 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2564 break; 2565 case FWTCODE_WRES: 2566 r = sizeof(fp->mode.wres) + sizeof(u_int32_t); 2567 break; 2568 case FWTCODE_WREQQ: 2569 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2570 break; 2571 case FWTCODE_RREQB: 2572 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2573 break; 2574 case FWTCODE_RRESQ: 2575 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2576 break; 2577 case FWTCODE_WREQB: 2578 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2579 + sizeof(u_int32_t); 2580 break; 2581 case FWTCODE_LREQ: 2582 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2583 + sizeof(u_int32_t); 2584 break; 2585 case FWTCODE_RRESB: 2586 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2587 + sizeof(u_int32_t); 2588 break; 2589 case FWTCODE_LRES: 2590 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2591 + sizeof(u_int32_t); 2592 break; 2593 case FWOHCITCODE_PHY: 2594 r = 16; 2595 break; 2596 default: 2597 device_printf(sc->fc.dev, "Unknown tcode %d\n", 2598 fp->mode.common.tcode); 2599 r = 0; 2600 } 2601 if (r > dbch->xferq.psize) { 2602 device_printf(sc->fc.dev, "Invalid packet length %d\n", r); 2603 /* panic ? */ 2604 } 2605 return r; 2606} 2607 2608static void 2609fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2610{ 2611 struct fwohcidb_tr *db_tr; 2612 int z = 1; 2613 struct fw_pkt *fp; 2614 u_int8_t *ld; 2615 u_int32_t stat, off; 2616 u_int spd; 2617 int len, plen, hlen, pcnt, poff = 0, rlen; 2618 int s; 2619 caddr_t buf; 2620 int resCount; 2621 2622 if(&sc->arrq == dbch){ 2623 off = OHCI_ARQOFF; 2624 }else if(&sc->arrs == dbch){ 2625 off = OHCI_ARSOFF; 2626 }else{ 2627 return; 2628 } 2629 2630 s = splfw(); 2631 db_tr = dbch->top; 2632 pcnt = 0; 2633 /* XXX we cannot handle a packet which lies in more than two buf */ 2634 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2635 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2636 resCount = db_tr->db[0].db.desc.count; 2637 len = dbch->xferq.psize - resCount 2638 - dbch->buf_offset; 2639 while (len > 0 ) { 2640 if (count >= 0 && count-- == 0) 2641 goto out; 2642 if(dbch->frag.buf != NULL){ 2643 buf = dbch->frag.buf; 2644 if (dbch->frag.plen < 0) { 2645 /* incomplete header */ 2646 int hlen; 2647 2648 hlen = - dbch->frag.plen; 2649 rlen = hlen - dbch->frag.len; 2650 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2651 ld += rlen; 2652 len -= rlen; 2653 dbch->frag.len += rlen; 2654#if 0 2655 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2656#endif 2657 fp=(struct fw_pkt *)dbch->frag.buf; 2658 dbch->frag.plen 2659 = fwohci_get_plen(sc, 2660 dbch, fp, hlen); 2661 if (dbch->frag.plen == 0) 2662 goto out; 2663 } 2664 rlen = dbch->frag.plen - dbch->frag.len; 2665#if 0 2666 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2667#endif 2668 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2669 rlen); 2670 ld += rlen; 2671 len -= rlen; 2672 plen = dbch->frag.plen; 2673 dbch->frag.buf = NULL; 2674 dbch->frag.plen = 0; 2675 dbch->frag.len = 0; 2676 poff = 0; 2677 }else{ 2678 fp=(struct fw_pkt *)ld; 2679 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2680 switch(fp->mode.common.tcode){ 2681 case FWTCODE_RREQQ: 2682 case FWTCODE_WRES: 2683 case FWTCODE_WREQQ: 2684 case FWTCODE_RRESQ: 2685 case FWOHCITCODE_PHY: 2686 hlen = 12; 2687 break; 2688 case FWTCODE_RREQB: 2689 case FWTCODE_WREQB: 2690 case FWTCODE_LREQ: 2691 case FWTCODE_RRESB: 2692 case FWTCODE_LRES: 2693 hlen = 16; 2694 break; 2695 default: 2696 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2697 goto out; 2698 } 2699 if (len >= hlen) { 2700 plen = fwohci_get_plen(sc, 2701 dbch, fp, hlen); 2702 if (plen == 0) 2703 goto out; 2704 plen = (plen + 3) & ~3; 2705 len -= plen; 2706 } else { 2707 plen = -hlen; 2708 len -= hlen; 2709 } 2710 if(resCount > 0 || len > 0){ 2711 buf = malloc(plen, M_FW, M_NOWAIT); 2712 if(buf == NULL){ 2713 printf("cannot malloc!\n"); 2714 free(db_tr->buf, M_FW); 2715 goto out; 2716 } 2717 bcopy(ld, buf, plen); 2718 poff = 0; 2719 dbch->frag.buf = NULL; 2720 dbch->frag.plen = 0; 2721 dbch->frag.len = 0; 2722 }else if(len < 0){ 2723 dbch->frag.buf = db_tr->buf; 2724 if (plen < 0) { 2725#if 0 2726 printf("plen < 0:" 2727 "hlen: %d len: %d\n", 2728 hlen, len); 2729#endif 2730 dbch->frag.len = hlen + len; 2731 dbch->frag.plen = -hlen; 2732 } else { 2733 dbch->frag.len = plen + len; 2734 dbch->frag.plen = plen; 2735 } 2736 bcopy(ld, db_tr->buf, dbch->frag.len); 2737 buf = NULL; 2738 }else{ 2739 buf = db_tr->buf; 2740 poff = ld - (u_int8_t *)buf; 2741 dbch->frag.buf = NULL; 2742 dbch->frag.plen = 0; 2743 dbch->frag.len = 0; 2744 } 2745 ld += plen; 2746 } 2747 if( buf != NULL){ 2748/* DMA result-code will be written at the tail of packet */ 2749 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2750 spd = (stat >> 5) & 0x3; 2751 stat &= 0x1f; 2752 switch(stat){ 2753 case FWOHCIEV_ACKPEND: 2754#if 0 2755 printf("fwohci_arcv: ack pending..\n"); 2756#endif 2757 /* fall through */ 2758 case FWOHCIEV_ACKCOMPL: 2759 if( poff != 0 ) 2760 bcopy(buf+poff, buf, plen - 4); 2761 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2762 break; 2763 case FWOHCIEV_BUSRST: 2764 free(buf, M_FW); 2765 if (sc->fc.status != FWBUSRESET) 2766 printf("got BUSRST packet!?\n"); 2767 break; 2768 default: 2769 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2770#if 0 /* XXX */ 2771 goto out; 2772#endif 2773 break; 2774 } 2775 } 2776 pcnt ++; 2777 }; 2778out: 2779 if (resCount == 0) { 2780 /* done on this buffer */ 2781 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2782 dbch->xferq.flag, 0, NULL); 2783 dbch->bottom->db[0].db.desc.depend |= z; 2784 dbch->bottom = db_tr; 2785 db_tr = STAILQ_NEXT(db_tr, link); 2786 dbch->top = db_tr; 2787 dbch->buf_offset = 0; 2788 } else { 2789 dbch->buf_offset = dbch->xferq.psize - resCount; 2790 break; 2791 } 2792 /* XXX make sure DMA is not dead */ 2793 } 2794#if 0 2795 if (pcnt < 1) 2796 printf("fwohci_arcv: no packets\n"); 2797#endif 2798 splx(s); 2799} 2800