fwohci.c revision 110577
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 110577 2003-02-09 07:16:01Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45109890Ssimokawa#include <sys/proc.h> 46103285Sikob#include <sys/systm.h> 47103285Sikob#include <sys/types.h> 48103285Sikob#include <sys/mbuf.h> 49103285Sikob#include <sys/mman.h> 50103285Sikob#include <sys/socket.h> 51103285Sikob#include <sys/socketvar.h> 52103285Sikob#include <sys/signalvar.h> 53103285Sikob#include <sys/malloc.h> 54103285Sikob#include <sys/uio.h> 55103285Sikob#include <sys/sockio.h> 56103285Sikob#include <sys/bus.h> 57103285Sikob#include <sys/kernel.h> 58103285Sikob#include <sys/conf.h> 59103285Sikob 60103285Sikob#include <machine/bus.h> 61103285Sikob#include <machine/resource.h> 62103285Sikob#include <sys/rman.h> 63103285Sikob 64103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 65103285Sikob#include <machine/clock.h> 66103285Sikob#include <pci/pcivar.h> 67103285Sikob#include <pci/pcireg.h> 68103285Sikob#include <vm/vm.h> 69103285Sikob#include <vm/vm_extern.h> 70103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 71103285Sikob 72103285Sikob#include <dev/firewire/firewire.h> 73103285Sikob#include <dev/firewire/firewirereg.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77103285Sikob 78109179Ssimokawa#include <dev/firewire/iec68113.h> 79109179Ssimokawa 80103285Sikob#undef OHCI_DEBUG 81106802Ssimokawa 82103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 83103285Sikob "STOR","LOAD","NOP ","STOP",}; 84103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 85103285Sikob "UNDEF","REG","SYS","DEV"}; 86103285Sikobchar fwohcicode[32][0x20]={ 87103285Sikob "No stat","Undef","long","miss Ack err", 88103285Sikob "underrun","overrun","desc err", "data read err", 89103285Sikob "data write err","bus reset","timeout","tcode err", 90103285Sikob "Undef","Undef","unknown event","flushed", 91103285Sikob "Undef","ack complete","ack pend","Undef", 92103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 93103285Sikob "Undef","Undef","Undef","ack tardy", 94103285Sikob "Undef","ack data_err","ack type_err",""}; 95103285Sikob#define MAX_SPEED 2 96103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 97103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 98103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 99103285Sikob 100103285Sikobstatic struct tcode_info tinfo[] = { 101103285Sikob/* hdr_len block flag*/ 102103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 103103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 104103285Sikob/* 2 WRES */ {12, FWTI_RES}, 105103285Sikob/* 3 XXX */ { 0, 0}, 106103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 108103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 109103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 110103285Sikob/* 8 CYCS */ { 0, 0}, 111103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 112103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 113103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 114103285Sikob/* c XXX */ { 0, 0}, 115103285Sikob/* d XXX */ { 0, 0}, 116103285Sikob/* e PHY */ {12, FWTI_REQ}, 117103285Sikob/* f XXX */ { 0, 0} 118103285Sikob}; 119103285Sikob 120103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 121103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 122103285Sikob 123103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 124103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 125103285Sikob 126103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 127103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 128103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 129106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 131103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 132103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 134103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 135103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 137103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 138103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 139103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 140103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 142103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 145103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 146103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 147103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 148103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 149103285Sikobstatic void fwohci_timeout __P((void *)); 150103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 151103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 152103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 153103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 154103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 155103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 156103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 157103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 158103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 160103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 161103285Sikob 162103285Sikob/* 163103285Sikob * memory allocated for DMA programs 164103285Sikob */ 165103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 166103285Sikob 167103285Sikob/* #define NDB 1024 */ 168103285Sikob#define NDB FWMAXQUEUE 169103285Sikob#define NDVDB (DVBUF * NDB) 170103285Sikob 171103285Sikob#define OHCI_VERSION 0x00 172103285Sikob#define OHCI_CROMHDR 0x18 173103285Sikob#define OHCI_BUS_OPT 0x20 174103285Sikob#define OHCI_BUSIRMC (1 << 31) 175103285Sikob#define OHCI_BUSCMC (1 << 30) 176103285Sikob#define OHCI_BUSISC (1 << 29) 177103285Sikob#define OHCI_BUSBMC (1 << 28) 178103285Sikob#define OHCI_BUSPMC (1 << 27) 179103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 180103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 181103285Sikob 182103285Sikob#define OHCI_EUID_HI 0x24 183103285Sikob#define OHCI_EUID_LO 0x28 184103285Sikob 185103285Sikob#define OHCI_CROMPTR 0x34 186103285Sikob#define OHCI_HCCCTL 0x50 187103285Sikob#define OHCI_HCCCTLCLR 0x54 188103285Sikob#define OHCI_AREQHI 0x100 189103285Sikob#define OHCI_AREQHICLR 0x104 190103285Sikob#define OHCI_AREQLO 0x108 191103285Sikob#define OHCI_AREQLOCLR 0x10c 192103285Sikob#define OHCI_PREQHI 0x110 193103285Sikob#define OHCI_PREQHICLR 0x114 194103285Sikob#define OHCI_PREQLO 0x118 195103285Sikob#define OHCI_PREQLOCLR 0x11c 196103285Sikob#define OHCI_PREQUPPER 0x120 197103285Sikob 198103285Sikob#define OHCI_SID_BUF 0x64 199103285Sikob#define OHCI_SID_CNT 0x68 200103285Sikob#define OHCI_SID_CNT_MASK 0xffc 201103285Sikob 202103285Sikob#define OHCI_IT_STAT 0x90 203103285Sikob#define OHCI_IT_STATCLR 0x94 204103285Sikob#define OHCI_IT_MASK 0x98 205103285Sikob#define OHCI_IT_MASKCLR 0x9c 206103285Sikob 207103285Sikob#define OHCI_IR_STAT 0xa0 208103285Sikob#define OHCI_IR_STATCLR 0xa4 209103285Sikob#define OHCI_IR_MASK 0xa8 210103285Sikob#define OHCI_IR_MASKCLR 0xac 211103285Sikob 212103285Sikob#define OHCI_LNKCTL 0xe0 213103285Sikob#define OHCI_LNKCTLCLR 0xe4 214103285Sikob 215103285Sikob#define OHCI_PHYACCESS 0xec 216103285Sikob#define OHCI_CYCLETIMER 0xf0 217103285Sikob 218103285Sikob#define OHCI_DMACTL(off) (off) 219103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 220103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 221103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 222103285Sikob 223103285Sikob#define OHCI_ATQOFF 0x180 224103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 225103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 226103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 227103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 228103285Sikob 229103285Sikob#define OHCI_ATSOFF 0x1a0 230103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 231103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 232103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 233103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 234103285Sikob 235103285Sikob#define OHCI_ARQOFF 0x1c0 236103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 237103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 238103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 239103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 240103285Sikob 241103285Sikob#define OHCI_ARSOFF 0x1e0 242103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 243103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 244103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 245103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 246103285Sikob 247103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 248103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 249103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 250103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 251103285Sikob 252103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 253103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 254103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 255103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 256103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 257103285Sikob 258103285Sikobd_ioctl_t fwohci_ioctl; 259103285Sikob 260103285Sikob/* 261103285Sikob * Communication with PHY device 262103285Sikob */ 263106790Ssimokawastatic u_int32_t 264106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 265103285Sikob{ 266103285Sikob u_int32_t fun; 267103285Sikob 268103285Sikob addr &= 0xf; 269103285Sikob data &= 0xff; 270103285Sikob 271103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 272103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 273103285Sikob DELAY(100); 274103285Sikob 275103285Sikob return(fwphy_rddata( sc, addr)); 276103285Sikob} 277103285Sikob 278103285Sikobstatic u_int32_t 279103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 280103285Sikob{ 281103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 282103285Sikob int i; 283103285Sikob u_int32_t bm; 284103285Sikob 285103285Sikob#define OHCI_CSR_DATA 0x0c 286103285Sikob#define OHCI_CSR_COMP 0x10 287103285Sikob#define OHCI_CSR_CONT 0x14 288103285Sikob#define OHCI_BUS_MANAGER_ID 0 289103285Sikob 290103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 291103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 292103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 293103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 294109280Ssimokawa DELAY(10); 295103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 296107653Ssimokawa if((bm & 0x3f) == 0x3f) 297103285Sikob bm = node; 298107653Ssimokawa if (bootverbose) 299107653Ssimokawa device_printf(sc->fc.dev, 300107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 301103285Sikob 302103285Sikob return(bm); 303103285Sikob} 304103285Sikob 305106790Ssimokawastatic u_int32_t 306106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 307103285Sikob{ 308108500Ssimokawa u_int32_t fun, stat; 309108500Ssimokawa u_int i, retry = 0; 310103285Sikob 311103285Sikob addr &= 0xf; 312108500Ssimokawa#define MAX_RETRY 100 313108500Ssimokawaagain: 314108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 315103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 316103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 317108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 318103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 319103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 320103285Sikob break; 321109280Ssimokawa DELAY(100); 322103285Sikob } 323108500Ssimokawa if(i >= MAX_RETRY) { 324109280Ssimokawa if (bootverbose) 325109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 326108527Ssimokawa if (++retry < MAX_RETRY) { 327109280Ssimokawa DELAY(100); 328108527Ssimokawa goto again; 329108527Ssimokawa } 330108500Ssimokawa } 331108500Ssimokawa /* Make sure that SCLK is started */ 332108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 333108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 334108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 335109280Ssimokawa if (bootverbose) 336109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 337108500Ssimokawa if (++retry < MAX_RETRY) { 338109280Ssimokawa DELAY(100); 339108500Ssimokawa goto again; 340108500Ssimokawa } 341108500Ssimokawa } 342108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 343108500Ssimokawa device_printf(sc->fc.dev, 344108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345108500Ssimokawa#undef MAX_RETRY 346103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 347103285Sikob} 348103285Sikob/* Device specific ioctl. */ 349103285Sikobint 350103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351103285Sikob{ 352103285Sikob struct firewire_softc *sc; 353103285Sikob struct fwohci_softc *fc; 354103285Sikob int unit = DEV2UNIT(dev); 355103285Sikob int err = 0; 356103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357103285Sikob u_int32_t *dmach = (u_int32_t *) data; 358103285Sikob 359103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 360103285Sikob if(sc == NULL){ 361103285Sikob return(EINVAL); 362103285Sikob } 363103285Sikob fc = (struct fwohci_softc *)sc->fc; 364103285Sikob 365103285Sikob if (!data) 366103285Sikob return(EINVAL); 367103285Sikob 368103285Sikob switch (cmd) { 369103285Sikob case FWOHCI_WRREG: 370103285Sikob#define OHCI_MAX_REG 0x800 371103285Sikob if(reg->addr <= OHCI_MAX_REG){ 372103285Sikob OWRITE(fc, reg->addr, reg->data); 373103285Sikob reg->data = OREAD(fc, reg->addr); 374103285Sikob }else{ 375103285Sikob err = EINVAL; 376103285Sikob } 377103285Sikob break; 378103285Sikob case FWOHCI_RDREG: 379103285Sikob if(reg->addr <= OHCI_MAX_REG){ 380103285Sikob reg->data = OREAD(fc, reg->addr); 381103285Sikob }else{ 382103285Sikob err = EINVAL; 383103285Sikob } 384103285Sikob break; 385103285Sikob/* Read DMA descriptors for debug */ 386103285Sikob case DUMPDMA: 387103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 388103285Sikob dump_dma(fc, *dmach); 389103285Sikob dump_db(fc, *dmach); 390103285Sikob }else{ 391103285Sikob err = EINVAL; 392103285Sikob } 393103285Sikob break; 394103285Sikob default: 395103285Sikob break; 396103285Sikob } 397103285Sikob return err; 398103285Sikob} 399106790Ssimokawa 400108530Ssimokawastatic int 401108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402103285Sikob{ 403108530Ssimokawa u_int32_t reg, reg2; 404108530Ssimokawa int e1394a = 1; 405108530Ssimokawa/* 406108530Ssimokawa * probe PHY parameters 407108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 408108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 409108530Ssimokawa * number of port supported by core-logic. 410108530Ssimokawa * It is not actually available port on your PC . 411108530Ssimokawa */ 412108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413108530Ssimokawa#if 0 414108530Ssimokawa /* XXX wait for SCLK. */ 415108530Ssimokawa DELAY(100000); 416108530Ssimokawa#endif 417108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418108530Ssimokawa 419108530Ssimokawa if((reg >> 5) != 7 ){ 420108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 421108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 422108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 423108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 424108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 425108530Ssimokawa sc->fc.speed, MAX_SPEED); 426108530Ssimokawa sc->fc.speed = MAX_SPEED; 427108530Ssimokawa } 428108530Ssimokawa device_printf(dev, 429108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 430108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 431108530Ssimokawa }else{ 432108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 433108530Ssimokawa sc->fc.mode |= FWPHYASYST; 434108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 435108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 436108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 437108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 438108530Ssimokawa sc->fc.speed, MAX_SPEED); 439108530Ssimokawa sc->fc.speed = MAX_SPEED; 440108530Ssimokawa } 441108530Ssimokawa device_printf(dev, 442108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 443108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 444108530Ssimokawa 445108530Ssimokawa /* check programPhyEnable */ 446108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 447108530Ssimokawa#if 0 448108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 449108530Ssimokawa#else /* XXX force to enable 1394a */ 450108530Ssimokawa if (e1394a) { 451108530Ssimokawa#endif 452108530Ssimokawa if (bootverbose) 453108530Ssimokawa device_printf(dev, 454108530Ssimokawa "Enable 1394a Enhancements\n"); 455108530Ssimokawa /* enable EAA EMC */ 456108530Ssimokawa reg2 |= 0x03; 457108530Ssimokawa /* set aPhyEnhanceEnable */ 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 459108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 460108530Ssimokawa } else { 461108530Ssimokawa /* for safe */ 462108530Ssimokawa reg2 &= ~0x83; 463108530Ssimokawa } 464108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 465108530Ssimokawa } 466108530Ssimokawa 467108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 468108530Ssimokawa if((reg >> 5) == 7 ){ 469108530Ssimokawa reg = fwphy_rddata(sc, 4); 470108530Ssimokawa reg |= 1 << 6; 471108530Ssimokawa fwphy_wrdata(sc, 4, reg); 472108530Ssimokawa reg = fwphy_rddata(sc, 4); 473108530Ssimokawa } 474108530Ssimokawa return 0; 475108530Ssimokawa} 476108530Ssimokawa 477108530Ssimokawa 478108530Ssimokawavoid 479108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 480108530Ssimokawa{ 481108701Ssimokawa int i, max_rec, speed; 482103285Sikob u_int32_t reg, reg2; 483103285Sikob struct fwohcidb_tr *db_tr; 484103285Sikob 485108701Ssimokawa /* Disable interrupt */ 486108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 487108530Ssimokawa 488108701Ssimokawa /* Now stopping all DMA channel */ 489108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa 494108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 495108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 496108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 498108530Ssimokawa } 499108530Ssimokawa 500108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 501108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 502108530Ssimokawa if (bootverbose) 503108530Ssimokawa device_printf(dev, "resetting OHCI..."); 504108530Ssimokawa i = 0; 505108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 506108530Ssimokawa if (i++ > 100) break; 507108530Ssimokawa DELAY(1000); 508108530Ssimokawa } 509108530Ssimokawa if (bootverbose) 510108530Ssimokawa printf("done (loop=%d)\n", i); 511108530Ssimokawa 512108701Ssimokawa /* Probe phy */ 513108701Ssimokawa fwohci_probe_phy(sc, dev); 514108701Ssimokawa 515108701Ssimokawa /* Probe link */ 516108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 517108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 518108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 519108701Ssimokawa speed = (reg & 0x00000007); 520108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 521108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 522108701Ssimokawa /* XXX fix max_rec */ 523108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 524108701Ssimokawa if (max_rec != sc->fc.maxrec) { 525108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 526108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 527108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 528108701Ssimokawa } 529108530Ssimokawa if (bootverbose) 530108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 531108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 532108530Ssimokawa 533108701Ssimokawa /* Initialize registers */ 534108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 535108530Ssimokawa OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 537108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 538108642Ssimokawa OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 539108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 540108701Ssimokawa fw_busreset(&sc->fc); 541108530Ssimokawa 542108701Ssimokawa /* Enable link */ 543108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 544108642Ssimokawa 545108701Ssimokawa /* Force to start async RX DMA */ 546108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 547108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 549108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 550108530Ssimokawa 551108701Ssimokawa /* Initialize async TX */ 552108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 554108701Ssimokawa /* AT Retries */ 555108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 556108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 557108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 558108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 559108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 560108530Ssimokawa db_tr->xfer = NULL; 561108530Ssimokawa } 562108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 563108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 564108530Ssimokawa db_tr->xfer = NULL; 565108530Ssimokawa } 566108530Ssimokawa 567108701Ssimokawa 568108701Ssimokawa /* Enable interrupt */ 569108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 570108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 571108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 572108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 573108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 574108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 575108530Ssimokawa 576108530Ssimokawa} 577108530Ssimokawa 578108530Ssimokawaint 579108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 580108530Ssimokawa{ 581108530Ssimokawa int i; 582108530Ssimokawa u_int32_t reg; 583109814Ssimokawa u_int8_t ui[8]; 584108530Ssimokawa 585103285Sikob reg = OREAD(sc, OHCI_VERSION); 586103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 587103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 588103285Sikob 589110045Ssimokawa/* Available Isochrounous DMA channel probe */ 590110045Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 591110045Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 592110045Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 593110045Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 594110045Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 595110045Ssimokawa for (i = 0; i < 0x20; i++) 596110045Ssimokawa if ((reg & (1 << i)) == 0) 597110045Ssimokawa break; 598103285Sikob sc->fc.nisodma = i; 599103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 600103285Sikob 601103285Sikob sc->fc.arq = &sc->arrq.xferq; 602103285Sikob sc->fc.ars = &sc->arrs.xferq; 603103285Sikob sc->fc.atq = &sc->atrq.xferq; 604103285Sikob sc->fc.ats = &sc->atrs.xferq; 605103285Sikob 606103285Sikob sc->arrq.xferq.start = NULL; 607103285Sikob sc->arrs.xferq.start = NULL; 608103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 609103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 610103285Sikob 611103285Sikob sc->arrq.xferq.drain = NULL; 612103285Sikob sc->arrs.xferq.drain = NULL; 613103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 614103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 615103285Sikob 616103285Sikob sc->arrq.ndesc = 1; 617103285Sikob sc->arrs.ndesc = 1; 618108655Ssimokawa sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 619108655Ssimokawa sc->atrs.ndesc = 6 / 2; 620103285Sikob 621103285Sikob sc->arrq.ndb = NDB; 622103285Sikob sc->arrs.ndb = NDB / 2; 623103285Sikob sc->atrq.ndb = NDB; 624103285Sikob sc->atrs.ndb = NDB / 2; 625103285Sikob 626103285Sikob sc->arrq.dummy = NULL; 627103285Sikob sc->arrs.dummy = NULL; 628103285Sikob sc->atrq.dummy = NULL; 629103285Sikob sc->atrs.dummy = NULL; 630103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 631103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 632103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 633103285Sikob sc->it[i].ndb = 0; 634103285Sikob sc->ir[i].ndb = 0; 635103285Sikob } 636103285Sikob 637103285Sikob sc->fc.tcode = tinfo; 638103285Sikob 639110195Ssimokawa sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_FW, M_NOWAIT); 640103285Sikob 641103285Sikob if(sc->cromptr == NULL){ 642108527Ssimokawa device_printf(dev, "cromptr alloc failed."); 643103285Sikob return ENOMEM; 644103285Sikob } 645103285Sikob sc->fc.dev = dev; 646103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 647103285Sikob 648103285Sikob sc->fc.config_rom[1] = 0x31333934; 649103285Sikob sc->fc.config_rom[2] = 0xf000a002; 650103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 651103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 652103285Sikob sc->fc.config_rom[5] = 0; 653103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 654103285Sikob 655103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 656103285Sikob 657103285Sikob 658103285Sikob/* SID recieve buffer must allign 2^11 */ 659103285Sikob#define OHCI_SIDSIZE (1 << 11) 660110195Ssimokawa sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 661108527Ssimokawa if (sc->fc.sid_buf == NULL) { 662108527Ssimokawa device_printf(dev, "sid_buf alloc failed.\n"); 663108527Ssimokawa return ENOMEM; 664108527Ssimokawa } 665110016Ssimokawa if (((vm_offset_t) sc->fc.sid_buf & (OHCI_SIDSIZE - 1)) != 0) { 666109736Ssimokawa device_printf(dev, "sid_buf(%p) not aligned.\n", 667109736Ssimokawa sc->fc.sid_buf); 668109736Ssimokawa return ENOMEM; 669109736Ssimokawa } 670108530Ssimokawa 671103285Sikob fwohci_db_init(&sc->arrq); 672108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 673108527Ssimokawa return ENOMEM; 674108527Ssimokawa 675103285Sikob fwohci_db_init(&sc->arrs); 676108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 677108527Ssimokawa return ENOMEM; 678103285Sikob 679103285Sikob fwohci_db_init(&sc->atrq); 680108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 681108527Ssimokawa return ENOMEM; 682108527Ssimokawa 683103285Sikob fwohci_db_init(&sc->atrs); 684108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 685108527Ssimokawa return ENOMEM; 686103285Sikob 687109814Ssimokawa sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); 688109814Ssimokawa sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); 689109814Ssimokawa for( i = 0 ; i < 8 ; i ++) 690109814Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); 691103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692109814Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 693109814Ssimokawa 694103285Sikob sc->fc.ioctl = fwohci_ioctl; 695103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 696103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 697103285Sikob sc->fc.ibr = fwohci_ibr; 698103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 699103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 700103285Sikob 701103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 702103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 703103285Sikob sc->fc.irx_post = fwohci_irx_post; 704103285Sikob sc->fc.itx_post = NULL; 705103285Sikob sc->fc.timeout = fwohci_timeout; 706103285Sikob sc->fc.poll = fwohci_poll; 707103285Sikob sc->fc.set_intr = fwohci_set_intr; 708106790Ssimokawa 709108530Ssimokawa fw_init(&sc->fc); 710108530Ssimokawa fwohci_reset(sc, dev); 711103285Sikob 712108530Ssimokawa return 0; 713103285Sikob} 714106790Ssimokawa 715106790Ssimokawavoid 716106790Ssimokawafwohci_timeout(void *arg) 717103285Sikob{ 718103285Sikob struct fwohci_softc *sc; 719103285Sikob 720103285Sikob sc = (struct fwohci_softc *)arg; 721103285Sikob} 722106790Ssimokawa 723106790Ssimokawau_int32_t 724106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 725103285Sikob{ 726103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 727103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 728103285Sikob} 729103285Sikob 730108527Ssimokawaint 731108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 732108527Ssimokawa{ 733108527Ssimokawa int i; 734108527Ssimokawa 735108527Ssimokawa if (sc->fc.sid_buf != NULL) 736110195Ssimokawa free((void *)(uintptr_t)sc->fc.sid_buf, M_FW); 737108527Ssimokawa if (sc->cromptr != NULL) 738110195Ssimokawa free((void *)sc->cromptr, M_FW); 739108527Ssimokawa 740108527Ssimokawa fwohci_db_free(&sc->arrq); 741108527Ssimokawa fwohci_db_free(&sc->arrs); 742108527Ssimokawa 743108527Ssimokawa fwohci_db_free(&sc->atrq); 744108527Ssimokawa fwohci_db_free(&sc->atrs); 745108527Ssimokawa 746108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 747108527Ssimokawa fwohci_db_free(&sc->it[i]); 748108527Ssimokawa fwohci_db_free(&sc->ir[i]); 749108527Ssimokawa } 750108527Ssimokawa 751108527Ssimokawa return 0; 752108527Ssimokawa} 753108527Ssimokawa 754108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 755108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 756108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 757108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 758108655Ssimokawa} while (0) 759108655Ssimokawa 760106790Ssimokawastatic void 761106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 762103285Sikob{ 763103285Sikob int i, s; 764103285Sikob int tcode, hdr_len, hdr_off, len; 765103285Sikob int fsegment = -1; 766103285Sikob u_int32_t off; 767103285Sikob struct fw_xfer *xfer; 768103285Sikob struct fw_pkt *fp; 769103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 770103285Sikob struct fwohcidb_tr *db_tr; 771103285Sikob volatile struct fwohcidb *db; 772103285Sikob struct mbuf *m; 773103285Sikob struct tcode_info *info; 774108655Ssimokawa static int maxdesc=0; 775103285Sikob 776103285Sikob if(&sc->atrq == dbch){ 777103285Sikob off = OHCI_ATQOFF; 778103285Sikob }else if(&sc->atrs == dbch){ 779103285Sikob off = OHCI_ATSOFF; 780103285Sikob }else{ 781103285Sikob return; 782103285Sikob } 783103285Sikob 784103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 785103285Sikob return; 786103285Sikob 787103285Sikob s = splfw(); 788103285Sikob db_tr = dbch->top; 789103285Sikobtxloop: 790103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 791103285Sikob if(xfer == NULL){ 792103285Sikob goto kick; 793103285Sikob } 794103285Sikob if(dbch->xferq.queued == 0 ){ 795103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 796103285Sikob } 797103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 798103285Sikob db_tr->xfer = xfer; 799103285Sikob xfer->state = FWXF_START; 800103285Sikob dbch->xferq.packets++; 801103285Sikob 802103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 803103285Sikob tcode = fp->mode.common.tcode; 804103285Sikob 805103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 806103285Sikob info = &tinfo[tcode]; 807103285Sikob hdr_len = hdr_off = info->hdr_len; 808103285Sikob /* fw_asyreq must pass valid send.len */ 809103285Sikob len = xfer->send.len; 810103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 811103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 812103285Sikob } 813103285Sikob ohcifp->mode.common.spd = xfer->spd; 814103285Sikob if (tcode == FWTCODE_STREAM ){ 815103285Sikob hdr_len = 8; 816103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 817103285Sikob } else if (tcode == FWTCODE_PHY) { 818103285Sikob hdr_len = 12; 819103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 820103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 821103285Sikob ohcifp->mode.common.spd = 0; 822103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 823103285Sikob } else { 824103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 825103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 826103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 827103285Sikob } 828103285Sikob db = &db_tr->db[0]; 829109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 830109892Ssimokawa db->db.desc.reqcount = hdr_len; 831103285Sikob db->db.desc.status = 0; 832103285Sikob/* Specify bound timer of asy. responce */ 833103285Sikob if(&sc->atrs == dbch){ 834103285Sikob db->db.desc.count 835103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 836103285Sikob } 837103285Sikob 838103285Sikob db_tr->dbcnt = 2; 839103285Sikob db = &db_tr->db[db_tr->dbcnt]; 840103285Sikob if(len > hdr_off){ 841103285Sikob if (xfer->mbuf == NULL) { 842103285Sikob db->db.desc.addr 843103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 844109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE; 845109892Ssimokawa db->db.desc.reqcount = len - hdr_off; 846103285Sikob db->db.desc.status = 0; 847103285Sikob 848103285Sikob db_tr->dbcnt++; 849103285Sikob } else { 850109890Ssimokawa int mchain=0; 851103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 852108655Ssimokawa for (m = xfer->mbuf; m != NULL; m = m->m_next) { 853108655Ssimokawa if (m->m_len == 0) 854109890Ssimokawa /* unrecoverable error could occur. */ 855108655Ssimokawa continue; 856109890Ssimokawa mchain++; 857109890Ssimokawa if (db_tr->dbcnt >= dbch->ndesc) 858109890Ssimokawa continue; 859103285Sikob db->db.desc.addr 860103285Sikob = vtophys(mtod(m, caddr_t)); 861109892Ssimokawa db->db.desc.control = OHCI_OUTPUT_MORE; 862109892Ssimokawa db->db.desc.reqcount = m->m_len; 863103285Sikob db->db.desc.status = 0; 864103285Sikob db++; 865103285Sikob db_tr->dbcnt++; 866108655Ssimokawa } 867109890Ssimokawa if (mchain > dbch->ndesc - 2) 868109890Ssimokawa device_printf(sc->fc.dev, 869109890Ssimokawa "dbch->ndesc(%d) is too small for" 870109890Ssimokawa " mbuf chain(%d), trancated.\n", 871109890Ssimokawa dbch->ndesc, mchain); 872103285Sikob } 873103285Sikob } 874108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 875108655Ssimokawa maxdesc = db_tr->dbcnt; 876108655Ssimokawa if (bootverbose) 877108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 878108655Ssimokawa } 879103285Sikob /* last db */ 880103285Sikob LAST_DB(db_tr, db); 881109892Ssimokawa db->db.desc.control |= OHCI_OUTPUT_LAST 882103285Sikob | OHCI_INTERRUPT_ALWAYS 883103285Sikob | OHCI_BRANCH_ALWAYS; 884103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 885103285Sikob 886103285Sikob if(fsegment == -1 ) 887103285Sikob fsegment = db_tr->dbcnt; 888103285Sikob if (dbch->pdb_tr != NULL) { 889103285Sikob LAST_DB(dbch->pdb_tr, db); 890103285Sikob db->db.desc.depend |= db_tr->dbcnt; 891103285Sikob } 892103285Sikob dbch->pdb_tr = db_tr; 893103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 894103285Sikob if(db_tr != dbch->bottom){ 895103285Sikob goto txloop; 896103285Sikob } else { 897107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 898103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 899103285Sikob } 900103285Sikobkick: 901103285Sikob /* kick asy q */ 902103285Sikob 903103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 904103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 905103285Sikob } else { 906107653Ssimokawa if (bootverbose) 907107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 908103285Sikob OREAD(sc, OHCI_DMACTL(off))); 909103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 910103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 911103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 912103285Sikob } 913106790Ssimokawa 914103285Sikob dbch->top = db_tr; 915103285Sikob splx(s); 916103285Sikob return; 917103285Sikob} 918106790Ssimokawa 919106790Ssimokawastatic void 920106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 921103285Sikob{ 922103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 923103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 924103285Sikob return; 925103285Sikob} 926106790Ssimokawa 927106790Ssimokawastatic void 928106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 929103285Sikob{ 930103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 931103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 932103285Sikob return; 933103285Sikob} 934106790Ssimokawa 935106790Ssimokawastatic void 936106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 937103285Sikob{ 938103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 939103285Sikob fwohci_start( sc, &(sc->atrq)); 940103285Sikob return; 941103285Sikob} 942106790Ssimokawa 943106790Ssimokawastatic void 944106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 945103285Sikob{ 946103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 947103285Sikob fwohci_start( sc, &(sc->atrs)); 948103285Sikob return; 949103285Sikob} 950106790Ssimokawa 951106790Ssimokawavoid 952106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 953103285Sikob{ 954103285Sikob int s, err = 0; 955103285Sikob struct fwohcidb_tr *tr; 956103285Sikob volatile struct fwohcidb *db; 957103285Sikob struct fw_xfer *xfer; 958103285Sikob u_int32_t off; 959103285Sikob u_int stat; 960103285Sikob int packets; 961103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 962103285Sikob if(&sc->atrq == dbch){ 963103285Sikob off = OHCI_ATQOFF; 964103285Sikob }else if(&sc->atrs == dbch){ 965103285Sikob off = OHCI_ATSOFF; 966103285Sikob }else{ 967103285Sikob return; 968103285Sikob } 969103285Sikob s = splfw(); 970103285Sikob tr = dbch->bottom; 971103285Sikob packets = 0; 972103285Sikob while(dbch->xferq.queued > 0){ 973103285Sikob LAST_DB(tr, db); 974103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 975103285Sikob if (fc->status != FWBUSRESET) 976103285Sikob /* maybe out of order?? */ 977103285Sikob goto out; 978103285Sikob } 979103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 980103285Sikob#ifdef OHCI_DEBUG 981103285Sikob dump_dma(sc, ch); 982103285Sikob dump_db(sc, ch); 983103285Sikob#endif 984103285Sikob/* Stop DMA */ 985103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 986103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 987103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 988103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 989103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 990103285Sikob } 991103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 992103285Sikob switch(stat){ 993110577Ssimokawa case FWOHCIEV_ACKPEND: 994103285Sikob case FWOHCIEV_ACKCOMPL: 995103285Sikob err = 0; 996103285Sikob break; 997103285Sikob case FWOHCIEV_ACKBSA: 998103285Sikob case FWOHCIEV_ACKBSB: 999110577Ssimokawa case FWOHCIEV_ACKBSX: 1000103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1001103285Sikob err = EBUSY; 1002103285Sikob break; 1003103285Sikob case FWOHCIEV_FLUSHED: 1004103285Sikob case FWOHCIEV_ACKTARD: 1005103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1006103285Sikob err = EAGAIN; 1007103285Sikob break; 1008103285Sikob case FWOHCIEV_MISSACK: 1009103285Sikob case FWOHCIEV_UNDRRUN: 1010103285Sikob case FWOHCIEV_OVRRUN: 1011103285Sikob case FWOHCIEV_DESCERR: 1012103285Sikob case FWOHCIEV_DTRDERR: 1013103285Sikob case FWOHCIEV_TIMEOUT: 1014103285Sikob case FWOHCIEV_TCODERR: 1015103285Sikob case FWOHCIEV_UNKNOWN: 1016103285Sikob case FWOHCIEV_ACKDERR: 1017103285Sikob case FWOHCIEV_ACKTERR: 1018103285Sikob default: 1019103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1020103285Sikob stat, fwohcicode[stat]); 1021103285Sikob err = EINVAL; 1022103285Sikob break; 1023103285Sikob } 1024110577Ssimokawa if (tr->xfer != NULL) { 1025103285Sikob xfer = tr->xfer; 1026103285Sikob xfer->state = FWXF_SENT; 1027110577Ssimokawa if (err == EBUSY && fc->status != FWBUSRESET) { 1028103285Sikob xfer->state = FWXF_BUSY; 1029110577Ssimokawa switch (xfer->act_type) { 1030103285Sikob case FWACT_XFER: 1031103285Sikob xfer->resp = err; 1032110577Ssimokawa if (xfer->retry_req != NULL) 1033103285Sikob xfer->retry_req(xfer); 1034110577Ssimokawa else 1035110577Ssimokawa fw_xfer_done(xfer); 1036103285Sikob break; 1037103285Sikob default: 1038103285Sikob break; 1039103285Sikob } 1040110577Ssimokawa } else if (stat != FWOHCIEV_ACKPEND) { 1041103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1042103285Sikob xfer->state = FWXF_SENTERR; 1043103285Sikob xfer->resp = err; 1044110577Ssimokawa switch (xfer->act_type) { 1045103285Sikob case FWACT_XFER: 1046103285Sikob fw_xfer_done(xfer); 1047103285Sikob break; 1048103285Sikob default: 1049103285Sikob break; 1050103285Sikob } 1051103285Sikob } 1052110577Ssimokawa /* 1053110577Ssimokawa * The watchdog timer takes care of split 1054110577Ssimokawa * transcation timeout for ACKPEND case. 1055110577Ssimokawa */ 1056103285Sikob } 1057110269Ssimokawa dbch->xferq.queued --; 1058103285Sikob tr->xfer = NULL; 1059103285Sikob 1060103285Sikob packets ++; 1061103285Sikob tr = STAILQ_NEXT(tr, link); 1062103285Sikob dbch->bottom = tr; 1063103285Sikob } 1064103285Sikobout: 1065103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1066103285Sikob printf("make free slot\n"); 1067103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1068103285Sikob fwohci_start(sc, dbch); 1069103285Sikob } 1070103285Sikob splx(s); 1071103285Sikob} 1072106790Ssimokawa 1073106790Ssimokawastatic void 1074106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1075103285Sikob{ 1076110269Ssimokawa int i, s, found=0; 1077103285Sikob struct fwohcidb_tr *tr; 1078103285Sikob 1079103285Sikob if(xfer->state != FWXF_START) return; 1080103285Sikob 1081103285Sikob s = splfw(); 1082103285Sikob tr = dbch->bottom; 1083110269Ssimokawa for (i = 0; i < dbch->xferq.queued; i ++) { 1084103285Sikob if(tr->xfer == xfer){ 1085103285Sikob tr->xfer = NULL; 1086110269Ssimokawa#if 0 1087103285Sikob dbch->xferq.queued --; 1088103285Sikob /* XXX */ 1089103285Sikob if (tr == dbch->bottom) 1090103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1091103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1092103285Sikob printf("fwohci_drain: make slot\n"); 1093103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1094103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1095103285Sikob } 1096110269Ssimokawa#endif 1097110269Ssimokawa found ++; 1098103285Sikob break; 1099103285Sikob } 1100103285Sikob tr = STAILQ_NEXT(tr, link); 1101103285Sikob } 1102103285Sikob splx(s); 1103110269Ssimokawa if (!found) 1104110269Ssimokawa device_printf(fc->dev, "fwochi_drain: xfer not found\n"); 1105103285Sikob return; 1106103285Sikob} 1107103285Sikob 1108106790Ssimokawastatic void 1109106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1110103285Sikob{ 1111103285Sikob struct fwohcidb_tr *db_tr; 1112109379Ssimokawa int idb, i; 1113103285Sikob 1114108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1115108527Ssimokawa return; 1116108527Ssimokawa 1117103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1118103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1119103285Sikob idb < dbch->ndb; 1120103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1121108527Ssimokawa if (db_tr->buf != NULL) { 1122110195Ssimokawa free(db_tr->buf, M_FW); 1123108527Ssimokawa db_tr->buf = NULL; 1124108527Ssimokawa } 1125103285Sikob } 1126103285Sikob } 1127103285Sikob dbch->ndb = 0; 1128103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1129109379Ssimokawa for (i = 0; i < dbch->npages; i++) 1130110195Ssimokawa free(dbch->pages[i], M_FW); 1131110195Ssimokawa free(db_tr, M_FW); 1132103285Sikob STAILQ_INIT(&dbch->db_trq); 1133108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1134103285Sikob} 1135106790Ssimokawa 1136106790Ssimokawastatic void 1137106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1138103285Sikob{ 1139103285Sikob int idb; 1140103285Sikob struct fwohcidb_tr *db_tr; 1141109379Ssimokawa int ndbpp, i, j; 1142108642Ssimokawa 1143108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1144108642Ssimokawa goto out; 1145108642Ssimokawa 1146103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1147103285Sikob /* DB entry must start at 16 bytes bounary. */ 1148103285Sikob STAILQ_INIT(&dbch->db_trq); 1149103285Sikob db_tr = (struct fwohcidb_tr *) 1150103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1151110273Ssimokawa M_FW, M_ZERO); 1152103285Sikob if(db_tr == NULL){ 1153109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1154103285Sikob return; 1155103285Sikob } 1156109379Ssimokawa 1157109379Ssimokawa ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1158109379Ssimokawa dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1159109403Ssimokawa if (firewire_debug) 1160109403Ssimokawa printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1161109403Ssimokawa dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1162109379Ssimokawa if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1163109379Ssimokawa printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1164109379Ssimokawa dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1165103285Sikob return; 1166103285Sikob } 1167109379Ssimokawa for (i = 0; i < dbch->npages; i++) { 1168110273Ssimokawa dbch->pages[i] = malloc(PAGE_SIZE, M_FW, M_ZERO); 1169109379Ssimokawa if (dbch->pages[i] == NULL) { 1170109379Ssimokawa printf("fwohci_db_init: malloc(2) failed\n"); 1171109379Ssimokawa for (j = 0; j < i; j ++) 1172110195Ssimokawa free(dbch->pages[j], M_FW); 1173110195Ssimokawa free(db_tr, M_FW); 1174109379Ssimokawa return; 1175109379Ssimokawa } 1176109379Ssimokawa } 1177103285Sikob /* Attach DB to DMA ch. */ 1178103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1179103285Sikob db_tr->dbcnt = 0; 1180109379Ssimokawa db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1181109379Ssimokawa + dbch->ndesc * (idb % ndbpp); 1182103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1183108530Ssimokawa if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1184108530Ssimokawa dbch->xferq.bnpacket != 0) { 1185108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1186108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1187108530Ssimokawa ].start = (caddr_t)db_tr; 1188108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1189108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1190108530Ssimokawa ].end = (caddr_t)db_tr; 1191103285Sikob } 1192103285Sikob db_tr++; 1193103285Sikob } 1194103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1195103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1196108642Ssimokawaout: 1197108642Ssimokawa dbch->frag.buf = NULL; 1198108642Ssimokawa dbch->frag.len = 0; 1199108642Ssimokawa dbch->frag.plen = 0; 1200108642Ssimokawa dbch->xferq.queued = 0; 1201108642Ssimokawa dbch->pdb_tr = NULL; 1202103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1203103285Sikob dbch->bottom = dbch->top; 1204108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1205103285Sikob} 1206106790Ssimokawa 1207106790Ssimokawastatic int 1208106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1209103285Sikob{ 1210103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1211109890Ssimokawa int dummy; 1212109890Ssimokawa 1213103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1214103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1215103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1216109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1217109890Ssimokawa tsleep((void *)&dummy, FWPRI, "fwitxd", hz); 1218103285Sikob fwohci_db_free(&sc->it[dmach]); 1219103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1220103285Sikob return 0; 1221103285Sikob} 1222106790Ssimokawa 1223106790Ssimokawastatic int 1224106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1225103285Sikob{ 1226103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1227109890Ssimokawa int dummy; 1228103285Sikob 1229103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1230103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1231103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1232109890Ssimokawa /* XXX we cannot free buffers until the DMA really stops */ 1233109890Ssimokawa tsleep((void *)&dummy, FWPRI, "fwirxd", hz); 1234103285Sikob if(sc->ir[dmach].dummy != NULL){ 1235110195Ssimokawa free(sc->ir[dmach].dummy, M_FW); 1236103285Sikob } 1237103285Sikob sc->ir[dmach].dummy = NULL; 1238103285Sikob fwohci_db_free(&sc->ir[dmach]); 1239103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1240103285Sikob return 0; 1241103285Sikob} 1242106790Ssimokawa 1243106790Ssimokawastatic void 1244106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1245103285Sikob{ 1246103285Sikob qld[0] = ntohl(qld[0]); 1247103285Sikob return; 1248103285Sikob} 1249106790Ssimokawa 1250106790Ssimokawastatic int 1251106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1252103285Sikob{ 1253103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1254103285Sikob int err = 0; 1255103285Sikob unsigned short tag, ich; 1256103285Sikob 1257103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1258103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1259103285Sikob 1260103285Sikob#if 0 1261103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1262103285Sikob wakeup(fc->ir[dmach]); 1263103285Sikob return err; 1264103285Sikob } 1265103285Sikob#endif 1266103285Sikob 1267103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1268103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1269103285Sikob sc->ir[dmach].xferq.queued = 0; 1270103285Sikob sc->ir[dmach].ndb = NDB; 1271109379Ssimokawa sc->ir[dmach].xferq.psize = PAGE_SIZE; 1272103285Sikob sc->ir[dmach].ndesc = 1; 1273103285Sikob fwohci_db_init(&sc->ir[dmach]); 1274109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1275109179Ssimokawa return ENOMEM; 1276103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1277103285Sikob } 1278103285Sikob if(err){ 1279103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1280103285Sikob return err; 1281103285Sikob } 1282103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1283103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1284103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1285103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1286103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1287103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1288103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1289103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1290103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1291103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1292103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1293103285Sikob } 1294103285Sikob return err; 1295103285Sikob} 1296106790Ssimokawa 1297106790Ssimokawastatic int 1298106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1299103285Sikob{ 1300103285Sikob int err = 0; 1301103285Sikob int idb, z, i, dmach = 0; 1302103285Sikob u_int32_t off = NULL; 1303103285Sikob struct fwohcidb_tr *db_tr; 1304109892Ssimokawa volatile struct fwohcidb *db; 1305103285Sikob 1306103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1307103285Sikob err = EINVAL; 1308103285Sikob return err; 1309103285Sikob } 1310103285Sikob z = dbch->ndesc; 1311103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1312103285Sikob if( &sc->it[dmach] == dbch){ 1313103285Sikob off = OHCI_ITOFF(dmach); 1314103285Sikob break; 1315103285Sikob } 1316103285Sikob } 1317103285Sikob if(off == NULL){ 1318103285Sikob err = EINVAL; 1319103285Sikob return err; 1320103285Sikob } 1321103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1322103285Sikob return err; 1323103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1324103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1325103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1326103285Sikob } 1327103285Sikob db_tr = dbch->top; 1328103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1329103285Sikob fwohci_add_tx_buf(db_tr, 1330103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1331103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1332103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1333103285Sikob break; 1334103285Sikob } 1335109892Ssimokawa db = db_tr->db; 1336109892Ssimokawa db[0].db.desc.depend = db[db_tr->dbcnt - 1].db.desc.depend 1337103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1338103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1339103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1340109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control 1341103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1342109280Ssimokawa /* OHCI 1.1 and above */ 1343109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 1344109892Ssimokawa#if 0 1345109892Ssimokawa db[0].db.desc.depend &= ~0xf; 1346109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.depend &= ~0xf; 1347109892Ssimokawa#endif 1348103285Sikob } 1349103285Sikob } 1350103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1351103285Sikob } 1352103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1353103285Sikob return err; 1354103285Sikob} 1355106790Ssimokawa 1356106790Ssimokawastatic int 1357106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1358103285Sikob{ 1359103285Sikob int err = 0; 1360109892Ssimokawa int idb, z, i, dmach = 0, ldesc; 1361103285Sikob u_int32_t off = NULL; 1362103285Sikob struct fwohcidb_tr *db_tr; 1363109892Ssimokawa volatile struct fwohcidb *db; 1364103285Sikob 1365103285Sikob z = dbch->ndesc; 1366103285Sikob if(&sc->arrq == dbch){ 1367103285Sikob off = OHCI_ARQOFF; 1368103285Sikob }else if(&sc->arrs == dbch){ 1369103285Sikob off = OHCI_ARSOFF; 1370103285Sikob }else{ 1371103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1372103285Sikob if( &sc->ir[dmach] == dbch){ 1373103285Sikob off = OHCI_IROFF(dmach); 1374103285Sikob break; 1375103285Sikob } 1376103285Sikob } 1377103285Sikob } 1378103285Sikob if(off == NULL){ 1379103285Sikob err = EINVAL; 1380103285Sikob return err; 1381103285Sikob } 1382103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1383103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1384103285Sikob return err; 1385103285Sikob }else{ 1386103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1387103285Sikob err = EBUSY; 1388103285Sikob return err; 1389103285Sikob } 1390103285Sikob } 1391103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1392108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1393103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1394103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1395103285Sikob } 1396103285Sikob db_tr = dbch->top; 1397103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1398103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1399103285Sikob fwohci_add_rx_buf(db_tr, 1400103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1401103285Sikob }else{ 1402103285Sikob fwohci_add_rx_buf(db_tr, 1403103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1404103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1405103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1406103285Sikob } 1407103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1408103285Sikob break; 1409103285Sikob } 1410109892Ssimokawa db = db_tr->db; 1411109892Ssimokawa ldesc = db_tr->dbcnt - 1; 1412109892Ssimokawa db[ldesc].db.desc.depend 1413103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1414103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1415103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1416109892Ssimokawa db[ldesc].db.desc.control 1417103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1418109892Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1419103285Sikob } 1420103285Sikob } 1421103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1422103285Sikob } 1423103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1424103285Sikob dbch->buf_offset = 0; 1425103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1426103285Sikob return err; 1427103285Sikob }else{ 1428103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1429103285Sikob } 1430103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1431103285Sikob return err; 1432103285Sikob} 1433106790Ssimokawa 1434106790Ssimokawastatic int 1435109890Ssimokawafwochi_next_cycle(struct firewire_comm *fc, int cycle_now) 1436109890Ssimokawa{ 1437109890Ssimokawa int sec, cycle, cycle_match; 1438109890Ssimokawa 1439109890Ssimokawa cycle = cycle_now & 0x1fff; 1440109890Ssimokawa sec = cycle_now >> 13; 1441109890Ssimokawa#define CYCLE_MOD 0x10 1442109890Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1443109890Ssimokawa cycle = cycle + CYCLE_DELAY; 1444109890Ssimokawa if (cycle >= 8000) { 1445109890Ssimokawa sec ++; 1446109890Ssimokawa cycle -= 8000; 1447109890Ssimokawa } 1448109890Ssimokawa cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1449109890Ssimokawa if (cycle >= 8000) { 1450109890Ssimokawa sec ++; 1451109890Ssimokawa if (cycle == 8000) 1452109890Ssimokawa cycle = 0; 1453109890Ssimokawa else 1454109890Ssimokawa cycle = CYCLE_MOD; 1455109890Ssimokawa } 1456109890Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1457109890Ssimokawa 1458109890Ssimokawa return(cycle_match); 1459109890Ssimokawa} 1460109890Ssimokawa 1461109890Ssimokawastatic int 1462106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1463103285Sikob{ 1464103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1465103285Sikob int err = 0; 1466103285Sikob unsigned short tag, ich; 1467103285Sikob struct fwohci_dbch *dbch; 1468109890Ssimokawa int cycle_match, cycle_now, s, ldesc; 1469109356Ssimokawa u_int32_t stat; 1470109890Ssimokawa struct fw_bulkxfer *first, *chunk, *prev; 1471109890Ssimokawa struct fw_xferq *it; 1472103285Sikob 1473103285Sikob dbch = &sc->it[dmach]; 1474109890Ssimokawa it = &dbch->xferq; 1475109890Ssimokawa 1476109890Ssimokawa tag = (it->flag >> 6) & 3; 1477109890Ssimokawa ich = it->flag & 0x3f; 1478109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1479109890Ssimokawa dbch->ndb = it->bnpacket * it->bnchunk; 1480103285Sikob dbch->ndesc = 3; 1481103285Sikob fwohci_db_init(dbch); 1482109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1483109179Ssimokawa return ENOMEM; 1484103285Sikob err = fwohci_tx_enable(sc, dbch); 1485103285Sikob } 1486103285Sikob if(err) 1487103285Sikob return err; 1488109890Ssimokawa 1489109892Ssimokawa ldesc = dbch->ndesc - 1; 1490109890Ssimokawa s = splfw(); 1491109890Ssimokawa prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); 1492109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { 1493109890Ssimokawa volatile struct fwohcidb *db; 1494109890Ssimokawa 1495109890Ssimokawa fwohci_txbufdb(sc, dmach, chunk); 1496109892Ssimokawa#if 0 1497109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1498109890Ssimokawa db[ldesc].db.desc.status = db[0].db.desc.status = 0; 1499109890Ssimokawa db[ldesc].db.desc.count = db[0].db.desc.count = 0; 1500109890Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1501109890Ssimokawa db[0].db.desc.depend &= ~0xf; 1502109892Ssimokawa#endif 1503109890Ssimokawa if (prev != NULL) { 1504109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1505109892Ssimokawa db[ldesc].db.desc.control |= OHCI_BRANCH_ALWAYS; 1506109892Ssimokawa#if 0 /* if bulkxfer->npacket changes */ 1507109890Ssimokawa db[ldesc].db.desc.depend = db[0].db.desc.depend = 1508109890Ssimokawa vtophys(((struct fwohcidb_tr *) 1509109890Ssimokawa (chunk->start))->db) | dbch->ndesc; 1510109892Ssimokawa#else 1511109892Ssimokawa db[0].db.desc.depend |= dbch->ndesc; 1512109892Ssimokawa db[ldesc].db.desc.depend |= dbch->ndesc; 1513109892Ssimokawa#endif 1514103285Sikob } 1515109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stvalid, link); 1516109890Ssimokawa STAILQ_INSERT_TAIL(&it->stdma, chunk, link); 1517109890Ssimokawa prev = chunk; 1518109403Ssimokawa } 1519109890Ssimokawa splx(s); 1520109890Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1521109890Ssimokawa if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) 1522109890Ssimokawa return 0; 1523109890Ssimokawa 1524109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1525109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1526109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1527109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1528109890Ssimokawa 1529109890Ssimokawa first = STAILQ_FIRST(&it->stdma); 1530109890Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), vtophys(((struct fwohcidb_tr *) 1531109890Ssimokawa (first->start))->db) | dbch->ndesc); 1532109890Ssimokawa if (firewire_debug) 1533109890Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1534109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1535109890Ssimokawa#if 1 1536109890Ssimokawa /* Don't start until all chunks are buffered */ 1537109890Ssimokawa if (STAILQ_FIRST(&it->stfree) != NULL) 1538109890Ssimokawa goto out; 1539109890Ssimokawa#endif 1540109802Ssimokawa#ifdef FWXFERQ_DV 1541109890Ssimokawa#define CYCLE_OFFSET 1 1542103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1543109802Ssimokawa struct fw_pkt *fp; 1544109802Ssimokawa struct fwohcidb_tr *db_tr; 1545109802Ssimokawa 1546103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1547103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1548109356Ssimokawa dbch->xferq.dvoffset = CYCLE_OFFSET; 1549109179Ssimokawa fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1550103285Sikob } 1551109802Ssimokawa#endif 1552109890Ssimokawa /* Clear cycle match counter bits */ 1553109890Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1554109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1555109890Ssimokawa 1556109356Ssimokawa /* 2bit second + 13bit cycle */ 1557109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1558109890Ssimokawa cycle_match = fwochi_next_cycle(fc, cycle_now); 1559109890Ssimokawa 1560109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1561109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1562109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1563109403Ssimokawa if (firewire_debug) 1564109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1565109403Ssimokawa cycle_now, cycle_match); 1566109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1567109890Ssimokawa device_printf(sc->fc.dev, 1568109890Ssimokawa "IT DMA underrun (0x%08x)\n", stat); 1569109403Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1570103285Sikob } 1571109890Ssimokawaout: 1572103285Sikob return err; 1573103285Sikob} 1574106790Ssimokawa 1575106790Ssimokawastatic int 1576106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1577103285Sikob{ 1578103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1579109890Ssimokawa int err = 0, s, ldesc; 1580103285Sikob unsigned short tag, ich; 1581109736Ssimokawa u_int32_t stat; 1582109890Ssimokawa struct fwohci_dbch *dbch; 1583109890Ssimokawa struct fw_bulkxfer *first, *prev, *chunk; 1584109890Ssimokawa struct fw_xferq *ir; 1585103285Sikob 1586109890Ssimokawa dbch = &sc->ir[dmach]; 1587109890Ssimokawa ir = &dbch->xferq; 1588109890Ssimokawa ldesc = dbch->ndesc - 1; 1589109890Ssimokawa 1590109890Ssimokawa if ((ir->flag & FWXFERQ_RUNNING) == 0) { 1591109890Ssimokawa tag = (ir->flag >> 6) & 3; 1592109890Ssimokawa ich = ir->flag & 0x3f; 1593108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1594108995Ssimokawa 1595109890Ssimokawa ir->queued = 0; 1596109890Ssimokawa dbch->ndb = ir->bnpacket * ir->bnchunk; 1597109890Ssimokawa dbch->dummy = malloc(sizeof(u_int32_t) * dbch->ndb, 1598110273Ssimokawa M_FW, 0); 1599109890Ssimokawa if (dbch->dummy == NULL) { 1600103285Sikob err = ENOMEM; 1601103285Sikob return err; 1602103285Sikob } 1603109890Ssimokawa dbch->ndesc = 2; 1604109890Ssimokawa fwohci_db_init(dbch); 1605109890Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1606109179Ssimokawa return ENOMEM; 1607109890Ssimokawa err = fwohci_rx_enable(sc, dbch); 1608103285Sikob } 1609103285Sikob if(err) 1610103285Sikob return err; 1611103285Sikob 1612109890Ssimokawa s = splfw(); 1613103285Sikob 1614109890Ssimokawa first = STAILQ_FIRST(&ir->stfree); 1615109890Ssimokawa if (first == NULL) { 1616109890Ssimokawa device_printf(fc->dev, "IR DMA no free chunk\n"); 1617109890Ssimokawa splx(s); 1618109890Ssimokawa return 0; 1619109890Ssimokawa } 1620109890Ssimokawa 1621109890Ssimokawa prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); 1622109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { 1623109890Ssimokawa volatile struct fwohcidb *db; 1624109890Ssimokawa 1625109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 1626109890Ssimokawa db[ldesc].db.desc.status = db[ldesc].db.desc.count = 0; 1627109890Ssimokawa db[ldesc].db.desc.depend &= ~0xf; 1628109890Ssimokawa if (prev != NULL) { 1629109890Ssimokawa db = ((struct fwohcidb_tr *)(prev->end))->db; 1630109892Ssimokawa#if 0 1631109890Ssimokawa db[ldesc].db.desc.depend = 1632109890Ssimokawa vtophys(((struct fwohcidb_tr *) 1633109890Ssimokawa (chunk->start))->db) | dbch->ndesc; 1634109892Ssimokawa#else 1635109892Ssimokawa db[ldesc].db.desc.depend |= dbch->ndesc; 1636109892Ssimokawa#endif 1637103285Sikob } 1638109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stfree, link); 1639109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); 1640109890Ssimokawa prev = chunk; 1641103285Sikob } 1642109890Ssimokawa splx(s); 1643109890Ssimokawa stat = OREAD(sc, OHCI_IRCTL(dmach)); 1644109890Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) 1645109890Ssimokawa return 0; 1646109890Ssimokawa if (stat & OHCI_CNTL_DMA_RUN) { 1647109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1648109890Ssimokawa device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); 1649109890Ssimokawa } 1650109890Ssimokawa 1651109890Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1652109890Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1653109890Ssimokawa OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1654109890Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1655109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1656109890Ssimokawa OWRITE(sc, OHCI_IRCMD(dmach), 1657109890Ssimokawa vtophys(((struct fwohcidb_tr *)(first->start))->db) 1658109890Ssimokawa | dbch->ndesc); 1659109890Ssimokawa OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1660109890Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1661103285Sikob return err; 1662103285Sikob} 1663106790Ssimokawa 1664106790Ssimokawastatic int 1665106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1666103285Sikob{ 1667103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1668103285Sikob int err = 0; 1669103285Sikob 1670103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1671103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1672103285Sikob return err; 1673103285Sikob }else{ 1674103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1675103285Sikob return err; 1676103285Sikob } 1677103285Sikob} 1678106790Ssimokawa 1679106790Ssimokawaint 1680110145Ssimokawafwohci_stop(struct fwohci_softc *sc, device_t dev) 1681103285Sikob{ 1682103285Sikob u_int i; 1683103285Sikob 1684103285Sikob/* Now stopping all DMA channel */ 1685103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1686103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1687103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1688103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1689103285Sikob 1690103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1691103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1692103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1693103285Sikob } 1694103285Sikob 1695103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1696103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1697103285Sikob 1698103285Sikob/* Stop interrupt */ 1699103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1700103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1701103285Sikob | OHCI_INT_PHY_INT 1702103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1703103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1704103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1705103285Sikob | OHCI_INT_PHY_BUS_R); 1706108642Ssimokawa/* XXX Link down? Bus reset? */ 1707103285Sikob return 0; 1708103285Sikob} 1709103285Sikob 1710108642Ssimokawaint 1711108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1712108642Ssimokawa{ 1713108642Ssimokawa int i; 1714108642Ssimokawa 1715108642Ssimokawa fwohci_reset(sc, dev); 1716108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1717108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1718108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1719108642Ssimokawa device_printf(sc->fc.dev, 1720108642Ssimokawa "resume iso receive ch: %d\n", i); 1721108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1722108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1723108642Ssimokawa } 1724108642Ssimokawa } 1725108642Ssimokawa 1726108642Ssimokawa bus_generic_resume(dev); 1727108642Ssimokawa sc->fc.ibr(&sc->fc); 1728108642Ssimokawa return 0; 1729108642Ssimokawa} 1730108642Ssimokawa 1731103285Sikob#define ACK_ALL 1732103285Sikobstatic void 1733106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1734103285Sikob{ 1735103285Sikob u_int32_t irstat, itstat; 1736103285Sikob u_int i; 1737103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1738103285Sikob 1739103285Sikob#ifdef OHCI_DEBUG 1740103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1741103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1742103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1743103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1744103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1745103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1746103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1747103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1748103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1749103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1750103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1751103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1752103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1753103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1754103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1755103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1756103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1757103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1758103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1759103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1760103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1761103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1762103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1763103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1764103285Sikob ); 1765103285Sikob#endif 1766103285Sikob/* Bus reset */ 1767103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1768103285Sikob device_printf(fc->dev, "BUS reset\n"); 1769103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1770103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1771103285Sikob 1772103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1773103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1774103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1775103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1776103285Sikob 1777103285Sikob#if 0 1778103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1779103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1780103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1781103285Sikob } 1782103285Sikob 1783103285Sikob#endif 1784103285Sikob fw_busreset(fc); 1785103285Sikob 1786103285Sikob /* XXX need to wait DMA to stop */ 1787103285Sikob#ifndef ACK_ALL 1788103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1789103285Sikob#endif 1790110269Ssimokawa#if 0 1791103285Sikob /* pending all pre-bus_reset packets */ 1792103285Sikob fwohci_txd(sc, &sc->atrq); 1793103285Sikob fwohci_txd(sc, &sc->atrs); 1794106789Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1795106789Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1796103285Sikob#endif 1797103285Sikob 1798103285Sikob 1799103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1800103285Sikob /* XXX insecure ?? */ 1801103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1802103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1803103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1804103285Sikob 1805103285Sikob } 1806103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1807103285Sikob#ifndef ACK_ALL 1808103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1809103285Sikob#endif 1810103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1811109280Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 1812103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1813109644Ssimokawa struct fwohci_dbch *dbch; 1814109644Ssimokawa 1815103285Sikob if((irstat & (1 << i)) != 0){ 1816109644Ssimokawa dbch = &sc->ir[i]; 1817109644Ssimokawa if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { 1818109644Ssimokawa device_printf(sc->fc.dev, 1819109644Ssimokawa "dma(%d) not active\n", i); 1820109644Ssimokawa continue; 1821109644Ssimokawa } 1822109644Ssimokawa if (dbch->xferq.flag & FWXFERQ_PACKET) { 1823109644Ssimokawa fwohci_ircv(sc, dbch, count); 1824109644Ssimokawa } else { 1825103285Sikob fwohci_rbuf_update(sc, i); 1826103285Sikob } 1827103285Sikob } 1828103285Sikob } 1829103285Sikob } 1830103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1831103285Sikob#ifndef ACK_ALL 1832103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1833103285Sikob#endif 1834103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1835109280Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 1836103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1837103285Sikob if((itstat & (1 << i)) != 0){ 1838103285Sikob fwohci_tbuf_update(sc, i); 1839103285Sikob } 1840103285Sikob } 1841103285Sikob } 1842103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1843103285Sikob#ifndef ACK_ALL 1844103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1845103285Sikob#endif 1846103285Sikob#if 0 1847103285Sikob dump_dma(sc, ARRS_CH); 1848103285Sikob dump_db(sc, ARRS_CH); 1849103285Sikob#endif 1850106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1851103285Sikob } 1852103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1853103285Sikob#ifndef ACK_ALL 1854103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1855103285Sikob#endif 1856103285Sikob#if 0 1857103285Sikob dump_dma(sc, ARRQ_CH); 1858103285Sikob dump_db(sc, ARRQ_CH); 1859103285Sikob#endif 1860106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1861103285Sikob } 1862103285Sikob if(stat & OHCI_INT_PHY_SID){ 1863103285Sikob caddr_t buf; 1864103285Sikob int plen; 1865103285Sikob 1866103285Sikob#ifndef ACK_ALL 1867103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1868103285Sikob#endif 1869103285Sikob/* 1870103285Sikob** Checking whether the node is root or not. If root, turn on 1871103285Sikob** cycle master. 1872103285Sikob*/ 1873103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1874103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1875103285Sikob printf("Bus reset failure\n"); 1876103285Sikob goto sidout; 1877103285Sikob } 1878103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1879103285Sikob printf("CYCLEMASTER mode\n"); 1880103285Sikob OWRITE(sc, OHCI_LNKCTL, 1881103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1882103285Sikob }else{ 1883103285Sikob printf("non CYCLEMASTER mode\n"); 1884103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1885103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1886103285Sikob } 1887103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1888103285Sikob 1889103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1890109736Ssimokawa if (plen < 4 || plen > OHCI_SIDSIZE) { 1891109736Ssimokawa device_printf(fc->dev, "invalid SID len = %d\n", plen); 1892109736Ssimokawa goto sidout; 1893109736Ssimokawa } 1894103285Sikob plen -= 4; /* chop control info */ 1895110195Ssimokawa buf = malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); 1896103285Sikob if(buf == NULL) goto sidout; 1897108530Ssimokawa bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1898103285Sikob buf, plen); 1899110269Ssimokawa#if 1 1900110269Ssimokawa /* pending all pre-bus_reset packets */ 1901110269Ssimokawa fwohci_txd(sc, &sc->atrq); 1902110269Ssimokawa fwohci_txd(sc, &sc->atrs); 1903110269Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1904110269Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1905110269Ssimokawa#endif 1906103285Sikob fw_sidrcv(fc, buf, plen, 0); 1907103285Sikob } 1908103285Sikobsidout: 1909103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1910103285Sikob#ifndef ACK_ALL 1911103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1912103285Sikob#endif 1913103285Sikob fwohci_txd(sc, &(sc->atrq)); 1914103285Sikob } 1915103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1916103285Sikob#ifndef ACK_ALL 1917103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1918103285Sikob#endif 1919103285Sikob fwohci_txd(sc, &(sc->atrs)); 1920103285Sikob } 1921103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1922103285Sikob#ifndef ACK_ALL 1923103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1924103285Sikob#endif 1925103285Sikob device_printf(fc->dev, "posted write error\n"); 1926103285Sikob } 1927103285Sikob if((stat & OHCI_INT_ERR )){ 1928103285Sikob#ifndef ACK_ALL 1929103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1930103285Sikob#endif 1931103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1932103285Sikob } 1933103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1934103285Sikob#ifndef ACK_ALL 1935103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1936103285Sikob#endif 1937103285Sikob device_printf(fc->dev, "phy int\n"); 1938103285Sikob } 1939103285Sikob 1940103285Sikob return; 1941103285Sikob} 1942103285Sikob 1943103285Sikobvoid 1944103285Sikobfwohci_intr(void *arg) 1945103285Sikob{ 1946103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1947103285Sikob u_int32_t stat; 1948103285Sikob 1949103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1950103285Sikob /* polling mode */ 1951103285Sikob return; 1952103285Sikob } 1953103285Sikob 1954103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1955103285Sikob if (stat == 0xffffffff) { 1956103285Sikob device_printf(sc->fc.dev, 1957103285Sikob "device physically ejected?\n"); 1958103285Sikob return; 1959103285Sikob } 1960103285Sikob#ifdef ACK_ALL 1961103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1962103285Sikob#endif 1963106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1964103285Sikob } 1965103285Sikob} 1966103285Sikob 1967103285Sikobstatic void 1968103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1969103285Sikob{ 1970103285Sikob int s; 1971103285Sikob u_int32_t stat; 1972103285Sikob struct fwohci_softc *sc; 1973103285Sikob 1974103285Sikob 1975103285Sikob sc = (struct fwohci_softc *)fc; 1976103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1977103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1978103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1979103285Sikob#if 0 1980103285Sikob if (!quick) { 1981103285Sikob#else 1982103285Sikob if (1) { 1983103285Sikob#endif 1984103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1985103285Sikob if (stat == 0) 1986103285Sikob return; 1987103285Sikob if (stat == 0xffffffff) { 1988103285Sikob device_printf(sc->fc.dev, 1989103285Sikob "device physically ejected?\n"); 1990103285Sikob return; 1991103285Sikob } 1992103285Sikob#ifdef ACK_ALL 1993103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1994103285Sikob#endif 1995103285Sikob } 1996103285Sikob s = splfw(); 1997106789Ssimokawa fwohci_intr_body(sc, stat, count); 1998103285Sikob splx(s); 1999103285Sikob} 2000103285Sikob 2001103285Sikobstatic void 2002103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 2003103285Sikob{ 2004103285Sikob struct fwohci_softc *sc; 2005103285Sikob 2006103285Sikob sc = (struct fwohci_softc *)fc; 2007107653Ssimokawa if (bootverbose) 2008108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 2009103285Sikob if (enable) { 2010103285Sikob sc->intmask |= OHCI_INT_EN; 2011103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 2012103285Sikob } else { 2013103285Sikob sc->intmask &= ~OHCI_INT_EN; 2014103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 2015103285Sikob } 2016103285Sikob} 2017103285Sikob 2018106790Ssimokawastatic void 2019106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 2020103285Sikob{ 2021103285Sikob struct firewire_comm *fc = &sc->fc; 2022109890Ssimokawa volatile struct fwohcidb *db; 2023109890Ssimokawa struct fw_bulkxfer *chunk; 2024109890Ssimokawa struct fw_xferq *it; 2025109890Ssimokawa u_int32_t stat, count; 2026109890Ssimokawa int s, w=0; 2027103285Sikob 2028109890Ssimokawa it = fc->it[dmach]; 2029109890Ssimokawa s = splfw(); /* unnecessary ? */ 2030109890Ssimokawa while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { 2031109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2032109890Ssimokawa stat = db[sc->it[dmach].ndesc - 1].db.desc.status; 2033109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->start))->db; 2034109890Ssimokawa count = db[sc->it[dmach].ndesc - 1].db.desc.count; 2035109890Ssimokawa if (stat == 0) 2036109890Ssimokawa break; 2037109890Ssimokawa STAILQ_REMOVE_HEAD(&it->stdma, link); 2038109890Ssimokawa switch (stat & FWOHCIEV_MASK){ 2039109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2040109890Ssimokawa#if 0 2041109890Ssimokawa device_printf(fc->dev, "0x%08x\n", count); 2042109179Ssimokawa#endif 2043109890Ssimokawa break; 2044109890Ssimokawa default: 2045109423Ssimokawa device_printf(fc->dev, 2046109890Ssimokawa "Isochronous transmit err %02x\n", stat); 2047109890Ssimokawa } 2048109890Ssimokawa STAILQ_INSERT_TAIL(&it->stfree, chunk, link); 2049109890Ssimokawa w++; 2050109403Ssimokawa } 2051109890Ssimokawa splx(s); 2052109890Ssimokawa if (w) 2053109890Ssimokawa wakeup(it); 2054103285Sikob} 2055106790Ssimokawa 2056106790Ssimokawastatic void 2057106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2058103285Sikob{ 2059109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2060109890Ssimokawa volatile struct fwohcidb *db; 2061109890Ssimokawa struct fw_bulkxfer *chunk; 2062109890Ssimokawa struct fw_xferq *ir; 2063109890Ssimokawa u_int32_t stat; 2064109890Ssimokawa int s, w=0; 2065109179Ssimokawa 2066109890Ssimokawa ir = fc->ir[dmach]; 2067109890Ssimokawa s = splfw(); 2068109890Ssimokawa while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { 2069109890Ssimokawa db = ((struct fwohcidb_tr *)(chunk->end))->db; 2070109890Ssimokawa stat = db[sc->ir[dmach].ndesc - 1].db.desc.status; 2071109890Ssimokawa if (stat == 0) 2072109890Ssimokawa break; 2073109890Ssimokawa STAILQ_REMOVE_HEAD(&ir->stdma, link); 2074109890Ssimokawa STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); 2075109890Ssimokawa switch (stat & FWOHCIEV_MASK) { 2076109890Ssimokawa case FWOHCIEV_ACKCOMPL: 2077109890Ssimokawa break; 2078109890Ssimokawa default: 2079109890Ssimokawa device_printf(fc->dev, 2080109890Ssimokawa "Isochronous receive err %02x\n", stat); 2081109890Ssimokawa } 2082109890Ssimokawa w++; 2083103285Sikob } 2084109890Ssimokawa splx(s); 2085109890Ssimokawa if (w) 2086109890Ssimokawa wakeup(ir); 2087103285Sikob} 2088106790Ssimokawa 2089106790Ssimokawavoid 2090106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2091106790Ssimokawa{ 2092103285Sikob u_int32_t off, cntl, stat, cmd, match; 2093103285Sikob 2094103285Sikob if(ch == 0){ 2095103285Sikob off = OHCI_ATQOFF; 2096103285Sikob }else if(ch == 1){ 2097103285Sikob off = OHCI_ATSOFF; 2098103285Sikob }else if(ch == 2){ 2099103285Sikob off = OHCI_ARQOFF; 2100103285Sikob }else if(ch == 3){ 2101103285Sikob off = OHCI_ARSOFF; 2102103285Sikob }else if(ch < IRX_CH){ 2103103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2104103285Sikob }else{ 2105103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2106103285Sikob } 2107103285Sikob cntl = stat = OREAD(sc, off); 2108103285Sikob cmd = OREAD(sc, off + 0xc); 2109103285Sikob match = OREAD(sc, off + 0x10); 2110103285Sikob 2111103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2112103285Sikob ch, 2113103285Sikob cntl, 2114103285Sikob stat, 2115103285Sikob cmd, 2116103285Sikob match); 2117103285Sikob stat &= 0xffff ; 2118103285Sikob if(stat & 0xff00){ 2119103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2120103285Sikob ch, 2121103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2122103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2123103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2124103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2125103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2126103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2127103285Sikob fwohcicode[stat & 0x1f], 2128103285Sikob stat & 0x1f 2129103285Sikob ); 2130103285Sikob }else{ 2131103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2132103285Sikob } 2133103285Sikob} 2134106790Ssimokawa 2135106790Ssimokawavoid 2136106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2137106790Ssimokawa{ 2138103285Sikob struct fwohci_dbch *dbch; 2139103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 2140103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2141103285Sikob int idb, jdb; 2142103285Sikob u_int32_t cmd, off; 2143103285Sikob if(ch == 0){ 2144103285Sikob off = OHCI_ATQOFF; 2145103285Sikob dbch = &sc->atrq; 2146103285Sikob }else if(ch == 1){ 2147103285Sikob off = OHCI_ATSOFF; 2148103285Sikob dbch = &sc->atrs; 2149103285Sikob }else if(ch == 2){ 2150103285Sikob off = OHCI_ARQOFF; 2151103285Sikob dbch = &sc->arrq; 2152103285Sikob }else if(ch == 3){ 2153103285Sikob off = OHCI_ARSOFF; 2154103285Sikob dbch = &sc->arrs; 2155103285Sikob }else if(ch < IRX_CH){ 2156103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2157103285Sikob dbch = &sc->it[ch - ITX_CH]; 2158103285Sikob }else { 2159103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2160103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2161103285Sikob } 2162103285Sikob cmd = OREAD(sc, off + 0xc); 2163103285Sikob 2164103285Sikob if( dbch->ndb == 0 ){ 2165103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2166103285Sikob return; 2167103285Sikob } 2168103285Sikob pp = dbch->top; 2169103285Sikob prev = pp->db; 2170103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2171103285Sikob if(pp == NULL){ 2172103285Sikob curr = NULL; 2173103285Sikob goto outdb; 2174103285Sikob } 2175103285Sikob cp = STAILQ_NEXT(pp, link); 2176103285Sikob if(cp == NULL){ 2177103285Sikob curr = NULL; 2178103285Sikob goto outdb; 2179103285Sikob } 2180103285Sikob np = STAILQ_NEXT(cp, link); 2181103285Sikob if(cp == NULL) break; 2182103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2183103285Sikob if((cmd & 0xfffffff0) 2184103285Sikob == vtophys(&(cp->db[jdb]))){ 2185103285Sikob curr = cp->db; 2186103285Sikob if(np != NULL){ 2187103285Sikob next = np->db; 2188103285Sikob }else{ 2189103285Sikob next = NULL; 2190103285Sikob } 2191103285Sikob goto outdb; 2192103285Sikob } 2193103285Sikob } 2194103285Sikob pp = STAILQ_NEXT(pp, link); 2195103285Sikob prev = pp->db; 2196103285Sikob } 2197103285Sikoboutdb: 2198103285Sikob if( curr != NULL){ 2199103285Sikob printf("Prev DB %d\n", ch); 2200103285Sikob print_db(prev, ch, dbch->ndesc); 2201103285Sikob printf("Current DB %d\n", ch); 2202103285Sikob print_db(curr, ch, dbch->ndesc); 2203103285Sikob printf("Next DB %d\n", ch); 2204103285Sikob print_db(next, ch, dbch->ndesc); 2205103285Sikob }else{ 2206103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2207103285Sikob } 2208103285Sikob return; 2209103285Sikob} 2210106790Ssimokawa 2211106790Ssimokawavoid 2212106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2213106790Ssimokawa{ 2214103285Sikob fwohcireg_t stat; 2215103285Sikob int i, key; 2216103285Sikob 2217103285Sikob if(db == NULL){ 2218103285Sikob printf("No Descriptor is found\n"); 2219103285Sikob return; 2220103285Sikob } 2221103285Sikob 2222103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2223103285Sikob ch, 2224103285Sikob "Current", 2225103285Sikob "OP ", 2226103285Sikob "KEY", 2227103285Sikob "INT", 2228103285Sikob "BR ", 2229103285Sikob "len", 2230103285Sikob "Addr", 2231103285Sikob "Depend", 2232103285Sikob "Stat", 2233103285Sikob "Cnt"); 2234103285Sikob for( i = 0 ; i <= max ; i ++){ 2235109892Ssimokawa key = db[i].db.desc.control & OHCI_KEY_MASK; 2236108712Ssimokawa#if __FreeBSD_version >= 500000 2237106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2238108712Ssimokawa#else 2239108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2240108712Ssimokawa#endif 2241103285Sikob vtophys(&db[i]), 2242109892Ssimokawa dbcode[(db[i].db.desc.control >> 12) & 0xf], 2243109892Ssimokawa dbkey[(db[i].db.desc.control >> 8) & 0x7], 2244109892Ssimokawa dbcond[(db[i].db.desc.control >> 4) & 0x3], 2245109892Ssimokawa dbcond[(db[i].db.desc.control >> 2) & 0x3], 2246109892Ssimokawa db[i].db.desc.reqcount, 2247103285Sikob db[i].db.desc.addr, 2248103285Sikob db[i].db.desc.depend, 2249103285Sikob db[i].db.desc.status, 2250103285Sikob db[i].db.desc.count); 2251103285Sikob stat = db[i].db.desc.status; 2252103285Sikob if(stat & 0xff00){ 2253103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2254103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2255103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2256103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2257103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2258103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2259103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2260103285Sikob fwohcicode[stat & 0x1f], 2261103285Sikob stat & 0x1f 2262103285Sikob ); 2263103285Sikob }else{ 2264103285Sikob printf(" Nostat\n"); 2265103285Sikob } 2266103285Sikob if(key == OHCI_KEY_ST2 ){ 2267103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2268103285Sikob db[i+1].db.immed[0], 2269103285Sikob db[i+1].db.immed[1], 2270103285Sikob db[i+1].db.immed[2], 2271103285Sikob db[i+1].db.immed[3]); 2272103285Sikob } 2273103285Sikob if(key == OHCI_KEY_DEVICE){ 2274103285Sikob return; 2275103285Sikob } 2276109892Ssimokawa if((db[i].db.desc.control & OHCI_BRANCH_MASK) 2277103285Sikob == OHCI_BRANCH_ALWAYS){ 2278103285Sikob return; 2279103285Sikob } 2280109892Ssimokawa if((db[i].db.desc.control & OHCI_CMD_MASK) 2281103285Sikob == OHCI_OUTPUT_LAST){ 2282103285Sikob return; 2283103285Sikob } 2284109892Ssimokawa if((db[i].db.desc.control & OHCI_CMD_MASK) 2285103285Sikob == OHCI_INPUT_LAST){ 2286103285Sikob return; 2287103285Sikob } 2288103285Sikob if(key == OHCI_KEY_ST2 ){ 2289103285Sikob i++; 2290103285Sikob } 2291103285Sikob } 2292103285Sikob return; 2293103285Sikob} 2294106790Ssimokawa 2295106790Ssimokawavoid 2296106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2297103285Sikob{ 2298103285Sikob struct fwohci_softc *sc; 2299103285Sikob u_int32_t fun; 2300103285Sikob 2301110577Ssimokawa device_printf(fc->dev, "Initiate bus reset\n"); 2302103285Sikob sc = (struct fwohci_softc *)fc; 2303108276Ssimokawa 2304108276Ssimokawa /* 2305108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2306108276Ssimokawa * shouldn't became the root node. 2307108276Ssimokawa */ 2308103285Sikob#if 1 2309103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2310109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2311103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2312109280Ssimokawa#else /* Short bus reset */ 2313103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2314109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2315103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2316103285Sikob#endif 2317103285Sikob} 2318106790Ssimokawa 2319106790Ssimokawavoid 2320106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2321103285Sikob{ 2322103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2323103285Sikob struct fwohci_dbch *dbch; 2324109892Ssimokawa volatile struct fwohcidb *db; 2325103285Sikob struct fw_pkt *fp; 2326103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2327103285Sikob unsigned short chtag; 2328103285Sikob int idb; 2329103285Sikob 2330103285Sikob dbch = &sc->it[dmach]; 2331103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2332103285Sikob 2333103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2334103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2335103285Sikob/* 2336103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2337103285Sikob*/ 2338103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2339109892Ssimokawa db = db_tr->db; 2340109892Ssimokawa#if 0 2341109892Ssimokawa db[0].db.desc.control 2342109892Ssimokawa = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2343109892Ssimokawa db[0].db.desc.reqcount = 8; 2344109892Ssimokawa#endif 2345103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2346109892Ssimokawa ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed; 2347103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2348103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2349103285Sikob ohcifp->mode.stream.chtag = chtag; 2350103285Sikob ohcifp->mode.stream.tcode = 0xa; 2351109890Ssimokawa ohcifp->mode.stream.spd = 0; 2352103285Sikob 2353109892Ssimokawa db[2].db.desc.reqcount = ntohs(fp->mode.stream.len); 2354109892Ssimokawa db[2].db.desc.status = 0; 2355109892Ssimokawa db[2].db.desc.count = 0; 2356109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2357109892Ssimokawa db[2].db.desc.control = OHCI_OUTPUT_LAST 2358103285Sikob | OHCI_UPDATE 2359109892Ssimokawa | OHCI_BRANCH_ALWAYS; 2360109892Ssimokawa db[0].db.desc.depend = 2361109892Ssimokawa = db[dbch->ndesc - 1].db.desc.depend 2362109280Ssimokawa = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2363109892Ssimokawa#else 2364109892Ssimokawa db[0].db.desc.depend |= dbch->ndesc; 2365109892Ssimokawa db[dbch->ndesc - 1].db.desc.depend |= dbch->ndesc; 2366109892Ssimokawa#endif 2367103285Sikob bulkxfer->end = (caddr_t)db_tr; 2368103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2369103285Sikob } 2370109892Ssimokawa db = ((struct fwohcidb_tr *)bulkxfer->end)->db; 2371109892Ssimokawa db[0].db.desc.depend &= ~0xf; 2372109892Ssimokawa db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2373109892Ssimokawa#if 0 /* if bulkxfer->npackets changes */ 2374109892Ssimokawa db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2375109280Ssimokawa /* OHCI 1.1 and above */ 2376109892Ssimokawa db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2377109892Ssimokawa#endif 2378109892Ssimokawa/* 2379103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2380103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2381103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2382103285Sikob*/ 2383103285Sikob return; 2384103285Sikob} 2385106790Ssimokawa 2386106790Ssimokawastatic int 2387106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2388106790Ssimokawa int mode, void *buf) 2389103285Sikob{ 2390103285Sikob volatile struct fwohcidb *db = db_tr->db; 2391103285Sikob int err = 0; 2392103285Sikob if(buf == 0){ 2393103285Sikob err = EINVAL; 2394103285Sikob return err; 2395103285Sikob } 2396103285Sikob db_tr->buf = buf; 2397103285Sikob db_tr->dbcnt = 3; 2398103285Sikob db_tr->dummy = NULL; 2399103285Sikob 2400109892Ssimokawa db[0].db.desc.control = OHCI_OUTPUT_MORE | OHCI_KEY_ST2; 2401109892Ssimokawa db[0].db.desc.reqcount = 8; 2402103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2403109892Ssimokawa db[2].db.desc.control = 2404109892Ssimokawa OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; 2405109892Ssimokawa#if 1 2406103285Sikob db[0].db.desc.status = 0; 2407103285Sikob db[0].db.desc.count = 0; 2408103285Sikob db[2].db.desc.status = 0; 2409103285Sikob db[2].db.desc.count = 0; 2410109892Ssimokawa#endif 2411103285Sikob if( mode & FWXFERQ_STREAM ){ 2412103285Sikob if(mode & FWXFERQ_PACKET ){ 2413109892Ssimokawa db[2].db.desc.control |= OHCI_INTERRUPT_ALWAYS; 2414103285Sikob } 2415109892Ssimokawa } else { 2416109892Ssimokawa printf("fwohci_add_tx_buf: who calls me?"); 2417103285Sikob } 2418103285Sikob return 1; 2419103285Sikob} 2420106790Ssimokawa 2421106790Ssimokawaint 2422106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2423106790Ssimokawa void *buf, void *dummy) 2424103285Sikob{ 2425103285Sikob volatile struct fwohcidb *db = db_tr->db; 2426103285Sikob int i; 2427103285Sikob void *dbuf[2]; 2428103285Sikob int dsiz[2]; 2429103285Sikob 2430103285Sikob if(buf == 0){ 2431110195Ssimokawa buf = malloc(size, M_FW, M_NOWAIT); 2432103285Sikob if(buf == NULL) return 0; 2433103285Sikob db_tr->buf = buf; 2434103285Sikob db_tr->dbcnt = 1; 2435103285Sikob db_tr->dummy = NULL; 2436103285Sikob dsiz[0] = size; 2437103285Sikob dbuf[0] = buf; 2438103285Sikob }else if(dummy == NULL){ 2439103285Sikob db_tr->buf = buf; 2440103285Sikob db_tr->dbcnt = 1; 2441103285Sikob db_tr->dummy = NULL; 2442103285Sikob dsiz[0] = size; 2443103285Sikob dbuf[0] = buf; 2444103285Sikob }else{ 2445103285Sikob db_tr->buf = buf; 2446103285Sikob db_tr->dbcnt = 2; 2447103285Sikob db_tr->dummy = dummy; 2448103285Sikob dsiz[0] = sizeof(u_int32_t); 2449103285Sikob dsiz[1] = size; 2450103285Sikob dbuf[0] = dummy; 2451103285Sikob dbuf[1] = buf; 2452103285Sikob } 2453103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2454103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2455109892Ssimokawa db[i].db.desc.control = OHCI_INPUT_MORE; 2456109892Ssimokawa db[i].db.desc.reqcount = dsiz[i]; 2457103285Sikob if( mode & FWXFERQ_STREAM ){ 2458109892Ssimokawa db[i].db.desc.control |= OHCI_UPDATE; 2459103285Sikob } 2460103285Sikob db[i].db.desc.status = 0; 2461103285Sikob db[i].db.desc.count = dsiz[i]; 2462103285Sikob } 2463103285Sikob if( mode & FWXFERQ_STREAM ){ 2464109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control |= OHCI_INPUT_LAST; 2465103285Sikob if(mode & FWXFERQ_PACKET ){ 2466109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control 2467103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2468103285Sikob } 2469103285Sikob } 2470109892Ssimokawa db[db_tr->dbcnt - 1].db.desc.control |= OHCI_BRANCH_ALWAYS; 2471103285Sikob return 1; 2472103285Sikob} 2473106790Ssimokawa 2474106790Ssimokawastatic void 2475106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2476103285Sikob{ 2477103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2478103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2479103285Sikob int z = 1; 2480103285Sikob struct fw_pkt *fp; 2481103285Sikob u_int8_t *ld; 2482103285Sikob u_int32_t off = NULL; 2483103285Sikob u_int32_t stat; 2484103285Sikob u_int32_t *qld; 2485103285Sikob u_int32_t reg; 2486103285Sikob u_int spd; 2487103285Sikob u_int dmach; 2488103285Sikob int len, i, plen; 2489103285Sikob caddr_t buf; 2490103285Sikob 2491103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2492103285Sikob if( &sc->ir[dmach] == dbch){ 2493103285Sikob off = OHCI_IROFF(dmach); 2494103285Sikob break; 2495103285Sikob } 2496103285Sikob } 2497103285Sikob if(off == NULL){ 2498103285Sikob return; 2499103285Sikob } 2500103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2501103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2502103285Sikob return; 2503103285Sikob } 2504103285Sikob 2505103285Sikob odb_tr = NULL; 2506103285Sikob db_tr = dbch->top; 2507103285Sikob i = 0; 2508103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2509106789Ssimokawa if (count >= 0 && count-- == 0) 2510106789Ssimokawa break; 2511103285Sikob ld = (u_int8_t *)db_tr->buf; 2512103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2513103285Sikob /* skip timeStamp */ 2514103285Sikob ld += sizeof(struct fwohci_trailer); 2515103285Sikob } 2516103285Sikob qld = (u_int32_t *)ld; 2517103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2518103285Sikob/* 2519103285Sikob{ 2520103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2521103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2522103285Sikob} 2523103285Sikob*/ 2524103285Sikob fp=(struct fw_pkt *)ld; 2525103285Sikob qld[0] = htonl(qld[0]); 2526103285Sikob plen = sizeof(struct fw_isohdr) 2527103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2528103285Sikob ld += plen; 2529103285Sikob len -= plen; 2530103285Sikob buf = db_tr->buf; 2531103285Sikob db_tr->buf = NULL; 2532103285Sikob stat = reg & 0x1f; 2533103285Sikob spd = reg & 0x3; 2534103285Sikob switch(stat){ 2535103285Sikob case FWOHCIEV_ACKCOMPL: 2536103285Sikob case FWOHCIEV_ACKPEND: 2537103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2538103285Sikob break; 2539103285Sikob default: 2540110195Ssimokawa free(buf, M_FW); 2541103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2542103285Sikob break; 2543103285Sikob } 2544103285Sikob i++; 2545103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2546103285Sikob dbch->xferq.flag, 0, NULL); 2547103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2548103285Sikob if(dbch->pdb_tr != NULL){ 2549103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2550103285Sikob } else { 2551103285Sikob /* XXX should be rewritten in better way */ 2552103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2553103285Sikob } 2554103285Sikob dbch->pdb_tr = db_tr; 2555103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2556103285Sikob } 2557103285Sikob dbch->top = db_tr; 2558103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2559103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2560103285Sikob return; 2561103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2562103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2563103285Sikob dbch->top = db_tr; 2564103285Sikob fwohci_irx_enable(fc, dmach); 2565103285Sikob} 2566103285Sikob 2567103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2568103285Sikobstatic int 2569103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2570103285Sikob{ 2571103285Sikob int i; 2572103285Sikob 2573103285Sikob for( i = 4; i < hlen ; i+=4){ 2574103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2575103285Sikob } 2576103285Sikob 2577103285Sikob switch(fp->mode.common.tcode){ 2578103285Sikob case FWTCODE_RREQQ: 2579103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2580103285Sikob case FWTCODE_WRES: 2581103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2582103285Sikob case FWTCODE_WREQQ: 2583103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2584103285Sikob case FWTCODE_RREQB: 2585103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2586103285Sikob case FWTCODE_RRESQ: 2587103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2588103285Sikob case FWTCODE_WREQB: 2589103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2590103285Sikob + sizeof(u_int32_t); 2591103285Sikob case FWTCODE_LREQ: 2592103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2593103285Sikob + sizeof(u_int32_t); 2594103285Sikob case FWTCODE_RRESB: 2595103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2596103285Sikob + sizeof(u_int32_t); 2597103285Sikob case FWTCODE_LRES: 2598103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2599103285Sikob + sizeof(u_int32_t); 2600103285Sikob case FWOHCITCODE_PHY: 2601103285Sikob return 16; 2602103285Sikob } 2603103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2604103285Sikob return 0; 2605103285Sikob} 2606103285Sikob 2607106790Ssimokawastatic void 2608106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2609103285Sikob{ 2610103285Sikob struct fwohcidb_tr *db_tr; 2611103285Sikob int z = 1; 2612103285Sikob struct fw_pkt *fp; 2613103285Sikob u_int8_t *ld; 2614103285Sikob u_int32_t stat, off; 2615103285Sikob u_int spd; 2616103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2617103285Sikob int s; 2618103285Sikob caddr_t buf; 2619103285Sikob int resCount; 2620103285Sikob 2621103285Sikob if(&sc->arrq == dbch){ 2622103285Sikob off = OHCI_ARQOFF; 2623103285Sikob }else if(&sc->arrs == dbch){ 2624103285Sikob off = OHCI_ARSOFF; 2625103285Sikob }else{ 2626103285Sikob return; 2627103285Sikob } 2628103285Sikob 2629103285Sikob s = splfw(); 2630103285Sikob db_tr = dbch->top; 2631103285Sikob pcnt = 0; 2632103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2633103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2634103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2635103285Sikob resCount = db_tr->db[0].db.desc.count; 2636103285Sikob len = dbch->xferq.psize - resCount 2637103285Sikob - dbch->buf_offset; 2638103285Sikob while (len > 0 ) { 2639106789Ssimokawa if (count >= 0 && count-- == 0) 2640106789Ssimokawa goto out; 2641103285Sikob if(dbch->frag.buf != NULL){ 2642103285Sikob buf = dbch->frag.buf; 2643103285Sikob if (dbch->frag.plen < 0) { 2644103285Sikob /* incomplete header */ 2645103285Sikob int hlen; 2646103285Sikob 2647103285Sikob hlen = - dbch->frag.plen; 2648103285Sikob rlen = hlen - dbch->frag.len; 2649103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2650103285Sikob ld += rlen; 2651103285Sikob len -= rlen; 2652103285Sikob dbch->frag.len += rlen; 2653103285Sikob#if 0 2654103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2655103285Sikob#endif 2656103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2657103285Sikob dbch->frag.plen 2658103285Sikob = fwohci_get_plen(sc, fp, hlen); 2659103285Sikob if (dbch->frag.plen == 0) 2660103285Sikob goto out; 2661103285Sikob } 2662103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2663103285Sikob#if 0 2664103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2665103285Sikob#endif 2666103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2667103285Sikob rlen); 2668103285Sikob ld += rlen; 2669103285Sikob len -= rlen; 2670103285Sikob plen = dbch->frag.plen; 2671103285Sikob dbch->frag.buf = NULL; 2672103285Sikob dbch->frag.plen = 0; 2673103285Sikob dbch->frag.len = 0; 2674103285Sikob poff = 0; 2675103285Sikob }else{ 2676103285Sikob fp=(struct fw_pkt *)ld; 2677103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2678103285Sikob switch(fp->mode.common.tcode){ 2679103285Sikob case FWTCODE_RREQQ: 2680103285Sikob case FWTCODE_WRES: 2681103285Sikob case FWTCODE_WREQQ: 2682103285Sikob case FWTCODE_RRESQ: 2683103285Sikob case FWOHCITCODE_PHY: 2684103285Sikob hlen = 12; 2685103285Sikob break; 2686103285Sikob case FWTCODE_RREQB: 2687103285Sikob case FWTCODE_WREQB: 2688103285Sikob case FWTCODE_LREQ: 2689103285Sikob case FWTCODE_RRESB: 2690103285Sikob case FWTCODE_LRES: 2691103285Sikob hlen = 16; 2692103285Sikob break; 2693103285Sikob default: 2694103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2695103285Sikob goto out; 2696103285Sikob } 2697103285Sikob if (len >= hlen) { 2698103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2699103285Sikob if (plen == 0) 2700103285Sikob goto out; 2701103285Sikob plen = (plen + 3) & ~3; 2702103285Sikob len -= plen; 2703103285Sikob } else { 2704103285Sikob plen = -hlen; 2705103285Sikob len -= hlen; 2706103285Sikob } 2707103285Sikob if(resCount > 0 || len > 0){ 2708103285Sikob buf = malloc( dbch->xferq.psize, 2709110195Ssimokawa M_FW, M_NOWAIT); 2710103285Sikob if(buf == NULL){ 2711103285Sikob printf("cannot malloc!\n"); 2712110195Ssimokawa free(db_tr->buf, M_FW); 2713103285Sikob goto out; 2714103285Sikob } 2715103285Sikob bcopy(ld, buf, plen); 2716103285Sikob poff = 0; 2717103285Sikob dbch->frag.buf = NULL; 2718103285Sikob dbch->frag.plen = 0; 2719103285Sikob dbch->frag.len = 0; 2720103285Sikob }else if(len < 0){ 2721103285Sikob dbch->frag.buf = db_tr->buf; 2722103285Sikob if (plen < 0) { 2723103285Sikob#if 0 2724103285Sikob printf("plen < 0:" 2725103285Sikob "hlen: %d len: %d\n", 2726103285Sikob hlen, len); 2727103285Sikob#endif 2728103285Sikob dbch->frag.len = hlen + len; 2729103285Sikob dbch->frag.plen = -hlen; 2730103285Sikob } else { 2731103285Sikob dbch->frag.len = plen + len; 2732103285Sikob dbch->frag.plen = plen; 2733103285Sikob } 2734103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2735103285Sikob buf = NULL; 2736103285Sikob }else{ 2737103285Sikob buf = db_tr->buf; 2738103285Sikob poff = ld - (u_int8_t *)buf; 2739103285Sikob dbch->frag.buf = NULL; 2740103285Sikob dbch->frag.plen = 0; 2741103285Sikob dbch->frag.len = 0; 2742103285Sikob } 2743103285Sikob ld += plen; 2744103285Sikob } 2745103285Sikob if( buf != NULL){ 2746103285Sikob/* DMA result-code will be written at the tail of packet */ 2747103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2748103285Sikob spd = (stat >> 5) & 0x3; 2749103285Sikob stat &= 0x1f; 2750103285Sikob switch(stat){ 2751103285Sikob case FWOHCIEV_ACKPEND: 2752110577Ssimokawa#if 0 2753103285Sikob printf("fwohci_arcv: ack pending..\n"); 2754103285Sikob#endif 2755103285Sikob /* fall through */ 2756103285Sikob case FWOHCIEV_ACKCOMPL: 2757103285Sikob if( poff != 0 ) 2758103285Sikob bcopy(buf+poff, buf, plen - 4); 2759103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2760103285Sikob break; 2761103285Sikob case FWOHCIEV_BUSRST: 2762110195Ssimokawa free(buf, M_FW); 2763103285Sikob if (sc->fc.status != FWBUSRESET) 2764103285Sikob printf("got BUSRST packet!?\n"); 2765103285Sikob break; 2766103285Sikob default: 2767103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2768103285Sikob#if 0 /* XXX */ 2769103285Sikob goto out; 2770103285Sikob#endif 2771103285Sikob break; 2772103285Sikob } 2773103285Sikob } 2774103285Sikob pcnt ++; 2775103285Sikob }; 2776103285Sikobout: 2777103285Sikob if (resCount == 0) { 2778103285Sikob /* done on this buffer */ 2779103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2780103285Sikob dbch->xferq.flag, 0, NULL); 2781103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2782103285Sikob dbch->bottom = db_tr; 2783103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2784103285Sikob dbch->top = db_tr; 2785103285Sikob dbch->buf_offset = 0; 2786103285Sikob } else { 2787103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2788103285Sikob break; 2789103285Sikob } 2790103285Sikob /* XXX make sure DMA is not dead */ 2791103285Sikob } 2792103285Sikob#if 0 2793103285Sikob if (pcnt < 1) 2794103285Sikob printf("fwohci_arcv: no packets\n"); 2795103285Sikob#endif 2796103285Sikob splx(s); 2797103285Sikob} 2798