fwohci.c revision 109423
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 109423 2003-01-17 15:03:57Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45103285Sikob#include <sys/systm.h> 46103285Sikob#include <sys/types.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/mman.h> 49103285Sikob#include <sys/socket.h> 50103285Sikob#include <sys/socketvar.h> 51103285Sikob#include <sys/signalvar.h> 52103285Sikob#include <sys/malloc.h> 53103285Sikob#include <sys/uio.h> 54103285Sikob#include <sys/sockio.h> 55103285Sikob#include <sys/bus.h> 56103285Sikob#include <sys/kernel.h> 57103285Sikob#include <sys/conf.h> 58103285Sikob 59103285Sikob#include <machine/bus.h> 60103285Sikob#include <machine/resource.h> 61103285Sikob#include <sys/rman.h> 62103285Sikob 63103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64103285Sikob#include <machine/clock.h> 65103285Sikob#include <pci/pcivar.h> 66103285Sikob#include <pci/pcireg.h> 67103285Sikob#include <vm/vm.h> 68103285Sikob#include <vm/vm_extern.h> 69103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 70103285Sikob 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirereg.h> 73103285Sikob#include <dev/firewire/fwohcireg.h> 74103285Sikob#include <dev/firewire/fwohcivar.h> 75103285Sikob#include <dev/firewire/firewire_phy.h> 76103285Sikob 77109179Ssimokawa#include <dev/firewire/iec68113.h> 78109179Ssimokawa 79103285Sikob#undef OHCI_DEBUG 80106802Ssimokawa 81103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82103285Sikob "STOR","LOAD","NOP ","STOP",}; 83103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84103285Sikob "UNDEF","REG","SYS","DEV"}; 85103285Sikobchar fwohcicode[32][0x20]={ 86103285Sikob "No stat","Undef","long","miss Ack err", 87103285Sikob "underrun","overrun","desc err", "data read err", 88103285Sikob "data write err","bus reset","timeout","tcode err", 89103285Sikob "Undef","Undef","unknown event","flushed", 90103285Sikob "Undef","ack complete","ack pend","Undef", 91103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 92103285Sikob "Undef","Undef","Undef","ack tardy", 93103285Sikob "Undef","ack data_err","ack type_err",""}; 94103285Sikob#define MAX_SPEED 2 95103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 96103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 126103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 127103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 128106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 132103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 142103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 145103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 148103285Sikobstatic void fwohci_timeout __P((void *)); 149103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 150103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 151103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 154103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160103285Sikob 161103285Sikob/* 162103285Sikob * memory allocated for DMA programs 163103285Sikob */ 164103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165103285Sikob 166103285Sikob/* #define NDB 1024 */ 167103285Sikob#define NDB FWMAXQUEUE 168103285Sikob#define NDVDB (DVBUF * NDB) 169103285Sikob 170103285Sikob#define OHCI_VERSION 0x00 171103285Sikob#define OHCI_CROMHDR 0x18 172103285Sikob#define OHCI_BUS_OPT 0x20 173103285Sikob#define OHCI_BUSIRMC (1 << 31) 174103285Sikob#define OHCI_BUSCMC (1 << 30) 175103285Sikob#define OHCI_BUSISC (1 << 29) 176103285Sikob#define OHCI_BUSBMC (1 << 28) 177103285Sikob#define OHCI_BUSPMC (1 << 27) 178103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 180103285Sikob 181103285Sikob#define OHCI_EUID_HI 0x24 182103285Sikob#define OHCI_EUID_LO 0x28 183103285Sikob 184103285Sikob#define OHCI_CROMPTR 0x34 185103285Sikob#define OHCI_HCCCTL 0x50 186103285Sikob#define OHCI_HCCCTLCLR 0x54 187103285Sikob#define OHCI_AREQHI 0x100 188103285Sikob#define OHCI_AREQHICLR 0x104 189103285Sikob#define OHCI_AREQLO 0x108 190103285Sikob#define OHCI_AREQLOCLR 0x10c 191103285Sikob#define OHCI_PREQHI 0x110 192103285Sikob#define OHCI_PREQHICLR 0x114 193103285Sikob#define OHCI_PREQLO 0x118 194103285Sikob#define OHCI_PREQLOCLR 0x11c 195103285Sikob#define OHCI_PREQUPPER 0x120 196103285Sikob 197103285Sikob#define OHCI_SID_BUF 0x64 198103285Sikob#define OHCI_SID_CNT 0x68 199103285Sikob#define OHCI_SID_CNT_MASK 0xffc 200103285Sikob 201103285Sikob#define OHCI_IT_STAT 0x90 202103285Sikob#define OHCI_IT_STATCLR 0x94 203103285Sikob#define OHCI_IT_MASK 0x98 204103285Sikob#define OHCI_IT_MASKCLR 0x9c 205103285Sikob 206103285Sikob#define OHCI_IR_STAT 0xa0 207103285Sikob#define OHCI_IR_STATCLR 0xa4 208103285Sikob#define OHCI_IR_MASK 0xa8 209103285Sikob#define OHCI_IR_MASKCLR 0xac 210103285Sikob 211103285Sikob#define OHCI_LNKCTL 0xe0 212103285Sikob#define OHCI_LNKCTLCLR 0xe4 213103285Sikob 214103285Sikob#define OHCI_PHYACCESS 0xec 215103285Sikob#define OHCI_CYCLETIMER 0xf0 216103285Sikob 217103285Sikob#define OHCI_DMACTL(off) (off) 218103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 219103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 220103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 221103285Sikob 222103285Sikob#define OHCI_ATQOFF 0x180 223103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 224103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227103285Sikob 228103285Sikob#define OHCI_ATSOFF 0x1a0 229103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 230103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233103285Sikob 234103285Sikob#define OHCI_ARQOFF 0x1c0 235103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 236103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239103285Sikob 240103285Sikob#define OHCI_ARSOFF 0x1e0 241103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 242103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245103285Sikob 246103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250103285Sikob 251103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256103285Sikob 257103285Sikobd_ioctl_t fwohci_ioctl; 258103285Sikob 259103285Sikob/* 260103285Sikob * Communication with PHY device 261103285Sikob */ 262106790Ssimokawastatic u_int32_t 263106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264103285Sikob{ 265103285Sikob u_int32_t fun; 266103285Sikob 267103285Sikob addr &= 0xf; 268103285Sikob data &= 0xff; 269103285Sikob 270103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 272103285Sikob DELAY(100); 273103285Sikob 274103285Sikob return(fwphy_rddata( sc, addr)); 275103285Sikob} 276103285Sikob 277103285Sikobstatic u_int32_t 278103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279103285Sikob{ 280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281103285Sikob int i; 282103285Sikob u_int32_t bm; 283103285Sikob 284103285Sikob#define OHCI_CSR_DATA 0x0c 285103285Sikob#define OHCI_CSR_COMP 0x10 286103285Sikob#define OHCI_CSR_CONT 0x14 287103285Sikob#define OHCI_BUS_MANAGER_ID 0 288103285Sikob 289103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 290103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293109280Ssimokawa DELAY(10); 294103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 295107653Ssimokawa if((bm & 0x3f) == 0x3f) 296103285Sikob bm = node; 297107653Ssimokawa if (bootverbose) 298107653Ssimokawa device_printf(sc->fc.dev, 299107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300103285Sikob 301103285Sikob return(bm); 302103285Sikob} 303103285Sikob 304106790Ssimokawastatic u_int32_t 305106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 306103285Sikob{ 307108500Ssimokawa u_int32_t fun, stat; 308108500Ssimokawa u_int i, retry = 0; 309103285Sikob 310103285Sikob addr &= 0xf; 311108500Ssimokawa#define MAX_RETRY 100 312108500Ssimokawaagain: 313108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 316108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 318103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319103285Sikob break; 320109280Ssimokawa DELAY(100); 321103285Sikob } 322108500Ssimokawa if(i >= MAX_RETRY) { 323109280Ssimokawa if (bootverbose) 324109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 325108527Ssimokawa if (++retry < MAX_RETRY) { 326109280Ssimokawa DELAY(100); 327108527Ssimokawa goto again; 328108527Ssimokawa } 329108500Ssimokawa } 330108500Ssimokawa /* Make sure that SCLK is started */ 331108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 332108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 333108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 334109280Ssimokawa if (bootverbose) 335109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 336108500Ssimokawa if (++retry < MAX_RETRY) { 337109280Ssimokawa DELAY(100); 338108500Ssimokawa goto again; 339108500Ssimokawa } 340108500Ssimokawa } 341108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 342108500Ssimokawa device_printf(sc->fc.dev, 343108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 344108500Ssimokawa#undef MAX_RETRY 345103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 346103285Sikob} 347103285Sikob/* Device specific ioctl. */ 348103285Sikobint 349103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 350103285Sikob{ 351103285Sikob struct firewire_softc *sc; 352103285Sikob struct fwohci_softc *fc; 353103285Sikob int unit = DEV2UNIT(dev); 354103285Sikob int err = 0; 355103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 356103285Sikob u_int32_t *dmach = (u_int32_t *) data; 357103285Sikob 358103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 359103285Sikob if(sc == NULL){ 360103285Sikob return(EINVAL); 361103285Sikob } 362103285Sikob fc = (struct fwohci_softc *)sc->fc; 363103285Sikob 364103285Sikob if (!data) 365103285Sikob return(EINVAL); 366103285Sikob 367103285Sikob switch (cmd) { 368103285Sikob case FWOHCI_WRREG: 369103285Sikob#define OHCI_MAX_REG 0x800 370103285Sikob if(reg->addr <= OHCI_MAX_REG){ 371103285Sikob OWRITE(fc, reg->addr, reg->data); 372103285Sikob reg->data = OREAD(fc, reg->addr); 373103285Sikob }else{ 374103285Sikob err = EINVAL; 375103285Sikob } 376103285Sikob break; 377103285Sikob case FWOHCI_RDREG: 378103285Sikob if(reg->addr <= OHCI_MAX_REG){ 379103285Sikob reg->data = OREAD(fc, reg->addr); 380103285Sikob }else{ 381103285Sikob err = EINVAL; 382103285Sikob } 383103285Sikob break; 384103285Sikob/* Read DMA descriptors for debug */ 385103285Sikob case DUMPDMA: 386103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 387103285Sikob dump_dma(fc, *dmach); 388103285Sikob dump_db(fc, *dmach); 389103285Sikob }else{ 390103285Sikob err = EINVAL; 391103285Sikob } 392103285Sikob break; 393103285Sikob default: 394103285Sikob break; 395103285Sikob } 396103285Sikob return err; 397103285Sikob} 398106790Ssimokawa 399108530Ssimokawastatic int 400108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 401103285Sikob{ 402108530Ssimokawa u_int32_t reg, reg2; 403108530Ssimokawa int e1394a = 1; 404108530Ssimokawa/* 405108530Ssimokawa * probe PHY parameters 406108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 407108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 408108530Ssimokawa * number of port supported by core-logic. 409108530Ssimokawa * It is not actually available port on your PC . 410108530Ssimokawa */ 411108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 412108530Ssimokawa#if 0 413108530Ssimokawa /* XXX wait for SCLK. */ 414108530Ssimokawa DELAY(100000); 415108530Ssimokawa#endif 416108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417108530Ssimokawa 418108530Ssimokawa if((reg >> 5) != 7 ){ 419108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 420108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 421108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 422108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 423108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 424108530Ssimokawa sc->fc.speed, MAX_SPEED); 425108530Ssimokawa sc->fc.speed = MAX_SPEED; 426108530Ssimokawa } 427108530Ssimokawa device_printf(dev, 428108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 429108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 430108530Ssimokawa }else{ 431108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432108530Ssimokawa sc->fc.mode |= FWPHYASYST; 433108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 434108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 436108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 437108530Ssimokawa sc->fc.speed, MAX_SPEED); 438108530Ssimokawa sc->fc.speed = MAX_SPEED; 439108530Ssimokawa } 440108530Ssimokawa device_printf(dev, 441108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 442108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 443108530Ssimokawa 444108530Ssimokawa /* check programPhyEnable */ 445108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 446108530Ssimokawa#if 0 447108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448108530Ssimokawa#else /* XXX force to enable 1394a */ 449108530Ssimokawa if (e1394a) { 450108530Ssimokawa#endif 451108530Ssimokawa if (bootverbose) 452108530Ssimokawa device_printf(dev, 453108530Ssimokawa "Enable 1394a Enhancements\n"); 454108530Ssimokawa /* enable EAA EMC */ 455108530Ssimokawa reg2 |= 0x03; 456108530Ssimokawa /* set aPhyEnhanceEnable */ 457108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459108530Ssimokawa } else { 460108530Ssimokawa /* for safe */ 461108530Ssimokawa reg2 &= ~0x83; 462108530Ssimokawa } 463108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 464108530Ssimokawa } 465108530Ssimokawa 466108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467108530Ssimokawa if((reg >> 5) == 7 ){ 468108530Ssimokawa reg = fwphy_rddata(sc, 4); 469108530Ssimokawa reg |= 1 << 6; 470108530Ssimokawa fwphy_wrdata(sc, 4, reg); 471108530Ssimokawa reg = fwphy_rddata(sc, 4); 472108530Ssimokawa } 473108530Ssimokawa return 0; 474108530Ssimokawa} 475108530Ssimokawa 476108530Ssimokawa 477108530Ssimokawavoid 478108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 479108530Ssimokawa{ 480108701Ssimokawa int i, max_rec, speed; 481103285Sikob u_int32_t reg, reg2; 482103285Sikob struct fwohcidb_tr *db_tr; 483103285Sikob 484108701Ssimokawa /* Disable interrupt */ 485108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486108530Ssimokawa 487108701Ssimokawa /* Now stopping all DMA channel */ 488108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa 493108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa } 498108530Ssimokawa 499108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 500108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501108530Ssimokawa if (bootverbose) 502108530Ssimokawa device_printf(dev, "resetting OHCI..."); 503108530Ssimokawa i = 0; 504108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505108530Ssimokawa if (i++ > 100) break; 506108530Ssimokawa DELAY(1000); 507108530Ssimokawa } 508108530Ssimokawa if (bootverbose) 509108530Ssimokawa printf("done (loop=%d)\n", i); 510108530Ssimokawa 511108701Ssimokawa /* Probe phy */ 512108701Ssimokawa fwohci_probe_phy(sc, dev); 513108701Ssimokawa 514108701Ssimokawa /* Probe link */ 515108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 516108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 517108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 518108701Ssimokawa speed = (reg & 0x00000007); 519108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 520108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 521108701Ssimokawa /* XXX fix max_rec */ 522108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 523108701Ssimokawa if (max_rec != sc->fc.maxrec) { 524108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 525108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 526108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 527108701Ssimokawa } 528108530Ssimokawa if (bootverbose) 529108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 531108530Ssimokawa 532108701Ssimokawa /* Initialize registers */ 533108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 534108530Ssimokawa OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 535108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 537108642Ssimokawa OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 538108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539108701Ssimokawa fw_busreset(&sc->fc); 540108530Ssimokawa 541108701Ssimokawa /* Enable link */ 542108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 543108642Ssimokawa 544108701Ssimokawa /* Force to start async RX DMA */ 545108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 546108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 549108530Ssimokawa 550108701Ssimokawa /* Initialize async TX */ 551108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 552108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa /* AT Retries */ 554108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 555108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 556108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559108530Ssimokawa db_tr->xfer = NULL; 560108530Ssimokawa } 561108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563108530Ssimokawa db_tr->xfer = NULL; 564108530Ssimokawa } 565108530Ssimokawa 566108701Ssimokawa 567108701Ssimokawa /* Enable interrupt */ 568108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 569108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 570108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 574108530Ssimokawa 575108530Ssimokawa} 576108530Ssimokawa 577108530Ssimokawaint 578108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 579108530Ssimokawa{ 580108530Ssimokawa int i; 581108530Ssimokawa u_int32_t reg; 582108530Ssimokawa 583103285Sikob reg = OREAD(sc, OHCI_VERSION); 584103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586103285Sikob 587103285Sikob/* XXX: Available Isochrounous DMA channel probe */ 588103285Sikob for( i = 0 ; i < 0x20 ; i ++ ){ 589103285Sikob OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 590103285Sikob reg = OREAD(sc, OHCI_IRCTL(i)); 591103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 592103285Sikob OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 593103285Sikob reg = OREAD(sc, OHCI_ITCTL(i)); 594103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 595103285Sikob } 596103285Sikob sc->fc.nisodma = i; 597103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 598103285Sikob 599103285Sikob sc->fc.arq = &sc->arrq.xferq; 600103285Sikob sc->fc.ars = &sc->arrs.xferq; 601103285Sikob sc->fc.atq = &sc->atrq.xferq; 602103285Sikob sc->fc.ats = &sc->atrs.xferq; 603103285Sikob 604103285Sikob sc->arrq.xferq.start = NULL; 605103285Sikob sc->arrs.xferq.start = NULL; 606103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 607103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 608103285Sikob 609103285Sikob sc->arrq.xferq.drain = NULL; 610103285Sikob sc->arrs.xferq.drain = NULL; 611103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 612103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 613103285Sikob 614103285Sikob sc->arrq.ndesc = 1; 615103285Sikob sc->arrs.ndesc = 1; 616108655Ssimokawa sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 617108655Ssimokawa sc->atrs.ndesc = 6 / 2; 618103285Sikob 619103285Sikob sc->arrq.ndb = NDB; 620103285Sikob sc->arrs.ndb = NDB / 2; 621103285Sikob sc->atrq.ndb = NDB; 622103285Sikob sc->atrs.ndb = NDB / 2; 623103285Sikob 624103285Sikob sc->arrq.dummy = NULL; 625103285Sikob sc->arrs.dummy = NULL; 626103285Sikob sc->atrq.dummy = NULL; 627103285Sikob sc->atrs.dummy = NULL; 628103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 629103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 630103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 631103285Sikob sc->it[i].ndb = 0; 632103285Sikob sc->ir[i].ndb = 0; 633103285Sikob } 634103285Sikob 635103285Sikob sc->fc.tcode = tinfo; 636103285Sikob 637109379Ssimokawa sc->cromptr = (u_int32_t *) malloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT); 638103285Sikob 639103285Sikob if(sc->cromptr == NULL){ 640108527Ssimokawa device_printf(dev, "cromptr alloc failed."); 641103285Sikob return ENOMEM; 642103285Sikob } 643103285Sikob sc->fc.dev = dev; 644103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 645103285Sikob 646103285Sikob sc->fc.config_rom[1] = 0x31333934; 647103285Sikob sc->fc.config_rom[2] = 0xf000a002; 648103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 649103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 650103285Sikob sc->fc.config_rom[5] = 0; 651103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 652103285Sikob 653103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 654103285Sikob 655103285Sikob 656103285Sikob/* SID recieve buffer must allign 2^11 */ 657103285Sikob#define OHCI_SIDSIZE (1 << 11) 658109379Ssimokawa sc->fc.sid_buf = (u_int32_t *) malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 659108527Ssimokawa if (sc->fc.sid_buf == NULL) { 660108527Ssimokawa device_printf(dev, "sid_buf alloc failed.\n"); 661108527Ssimokawa return ENOMEM; 662108527Ssimokawa } 663108527Ssimokawa 664108530Ssimokawa 665103285Sikob fwohci_db_init(&sc->arrq); 666108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 667108527Ssimokawa return ENOMEM; 668108527Ssimokawa 669103285Sikob fwohci_db_init(&sc->arrs); 670108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 671108527Ssimokawa return ENOMEM; 672103285Sikob 673103285Sikob fwohci_db_init(&sc->atrq); 674108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 675108527Ssimokawa return ENOMEM; 676108527Ssimokawa 677103285Sikob fwohci_db_init(&sc->atrs); 678108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 679108527Ssimokawa return ENOMEM; 680103285Sikob 681103285Sikob reg = OREAD(sc, FWOHCIGUID_H); 682103285Sikob for( i = 0 ; i < 4 ; i ++){ 683103285Sikob sc->fc.eui[3 - i] = reg & 0xff; 684103285Sikob reg = reg >> 8; 685103285Sikob } 686103285Sikob reg = OREAD(sc, FWOHCIGUID_L); 687103285Sikob for( i = 0 ; i < 4 ; i ++){ 688103285Sikob sc->fc.eui[7 - i] = reg & 0xff; 689103285Sikob reg = reg >> 8; 690103285Sikob } 691103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 692103285Sikob sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 693103285Sikob sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 694103285Sikob sc->fc.ioctl = fwohci_ioctl; 695103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 696103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 697103285Sikob sc->fc.ibr = fwohci_ibr; 698103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 699103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 700103285Sikob 701103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 702103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 703103285Sikob sc->fc.irx_post = fwohci_irx_post; 704103285Sikob sc->fc.itx_post = NULL; 705103285Sikob sc->fc.timeout = fwohci_timeout; 706103285Sikob sc->fc.poll = fwohci_poll; 707103285Sikob sc->fc.set_intr = fwohci_set_intr; 708106790Ssimokawa 709108530Ssimokawa fw_init(&sc->fc); 710108530Ssimokawa fwohci_reset(sc, dev); 711103285Sikob 712108530Ssimokawa return 0; 713103285Sikob} 714106790Ssimokawa 715106790Ssimokawavoid 716106790Ssimokawafwohci_timeout(void *arg) 717103285Sikob{ 718103285Sikob struct fwohci_softc *sc; 719103285Sikob 720103285Sikob sc = (struct fwohci_softc *)arg; 721103285Sikob sc->fc.timeouthandle = timeout(fwohci_timeout, 722103285Sikob (void *)sc, FW_XFERTIMEOUT * hz * 10); 723103285Sikob} 724106790Ssimokawa 725106790Ssimokawau_int32_t 726106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 727103285Sikob{ 728103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 729103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 730103285Sikob} 731103285Sikob 732108527Ssimokawaint 733108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 734108527Ssimokawa{ 735108527Ssimokawa int i; 736108527Ssimokawa 737108527Ssimokawa if (sc->fc.sid_buf != NULL) 738109379Ssimokawa free((void *)(uintptr_t)sc->fc.sid_buf, M_DEVBUF); 739108527Ssimokawa if (sc->cromptr != NULL) 740109379Ssimokawa free((void *)sc->cromptr, M_DEVBUF); 741108527Ssimokawa 742108527Ssimokawa fwohci_db_free(&sc->arrq); 743108527Ssimokawa fwohci_db_free(&sc->arrs); 744108527Ssimokawa 745108527Ssimokawa fwohci_db_free(&sc->atrq); 746108527Ssimokawa fwohci_db_free(&sc->atrs); 747108527Ssimokawa 748108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 749108527Ssimokawa fwohci_db_free(&sc->it[i]); 750108527Ssimokawa fwohci_db_free(&sc->ir[i]); 751108527Ssimokawa } 752108527Ssimokawa 753108527Ssimokawa return 0; 754108527Ssimokawa} 755108527Ssimokawa 756108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 757108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 758108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 759108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 760108655Ssimokawa} while (0) 761108655Ssimokawa 762106790Ssimokawastatic void 763106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 764103285Sikob{ 765103285Sikob int i, s; 766103285Sikob int tcode, hdr_len, hdr_off, len; 767103285Sikob int fsegment = -1; 768103285Sikob u_int32_t off; 769103285Sikob struct fw_xfer *xfer; 770103285Sikob struct fw_pkt *fp; 771103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 772103285Sikob struct fwohcidb_tr *db_tr; 773103285Sikob volatile struct fwohcidb *db; 774103285Sikob struct mbuf *m; 775103285Sikob struct tcode_info *info; 776108655Ssimokawa static int maxdesc=0; 777103285Sikob 778103285Sikob if(&sc->atrq == dbch){ 779103285Sikob off = OHCI_ATQOFF; 780103285Sikob }else if(&sc->atrs == dbch){ 781103285Sikob off = OHCI_ATSOFF; 782103285Sikob }else{ 783103285Sikob return; 784103285Sikob } 785103285Sikob 786103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 787103285Sikob return; 788103285Sikob 789103285Sikob s = splfw(); 790103285Sikob db_tr = dbch->top; 791103285Sikobtxloop: 792103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 793103285Sikob if(xfer == NULL){ 794103285Sikob goto kick; 795103285Sikob } 796103285Sikob if(dbch->xferq.queued == 0 ){ 797103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 798103285Sikob } 799103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 800103285Sikob db_tr->xfer = xfer; 801103285Sikob xfer->state = FWXF_START; 802103285Sikob dbch->xferq.packets++; 803103285Sikob 804103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 805103285Sikob tcode = fp->mode.common.tcode; 806103285Sikob 807103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 808103285Sikob info = &tinfo[tcode]; 809103285Sikob hdr_len = hdr_off = info->hdr_len; 810103285Sikob /* fw_asyreq must pass valid send.len */ 811103285Sikob len = xfer->send.len; 812103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 813103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 814103285Sikob } 815103285Sikob ohcifp->mode.common.spd = xfer->spd; 816103285Sikob if (tcode == FWTCODE_STREAM ){ 817103285Sikob hdr_len = 8; 818103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 819103285Sikob } else if (tcode == FWTCODE_PHY) { 820103285Sikob hdr_len = 12; 821103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 822103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 823103285Sikob ohcifp->mode.common.spd = 0; 824103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 825103285Sikob } else { 826103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 827103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 828103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 829103285Sikob } 830103285Sikob db = &db_tr->db[0]; 831103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 832103285Sikob db->db.desc.status = 0; 833103285Sikob/* Specify bound timer of asy. responce */ 834103285Sikob if(&sc->atrs == dbch){ 835103285Sikob db->db.desc.count 836103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 837103285Sikob } 838103285Sikob 839103285Sikob db_tr->dbcnt = 2; 840103285Sikob db = &db_tr->db[db_tr->dbcnt]; 841103285Sikob if(len > hdr_off){ 842103285Sikob if (xfer->mbuf == NULL) { 843103285Sikob db->db.desc.addr 844103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 845103285Sikob db->db.desc.cmd 846103285Sikob = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 847103285Sikob db->db.desc.status = 0; 848103285Sikob 849103285Sikob db_tr->dbcnt++; 850103285Sikob } else { 851103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 852108655Ssimokawa for (m = xfer->mbuf; m != NULL; m = m->m_next) { 853108655Ssimokawa if (m->m_len == 0) 854108655Ssimokawa /* unrecoverable error could ocurre. */ 855108655Ssimokawa continue; 856108655Ssimokawa if (db_tr->dbcnt >= dbch->ndesc) { 857108655Ssimokawa device_printf(sc->fc.dev, 858108655Ssimokawa "dbch->ndesc is too small" 859108655Ssimokawa ", trancated.\n"); 860108655Ssimokawa break; 861108655Ssimokawa } 862103285Sikob db->db.desc.addr 863103285Sikob = vtophys(mtod(m, caddr_t)); 864103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 865103285Sikob db->db.desc.status = 0; 866103285Sikob db++; 867103285Sikob db_tr->dbcnt++; 868108655Ssimokawa } 869103285Sikob } 870103285Sikob } 871108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 872108655Ssimokawa maxdesc = db_tr->dbcnt; 873108655Ssimokawa if (bootverbose) 874108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 875108655Ssimokawa } 876103285Sikob /* last db */ 877103285Sikob LAST_DB(db_tr, db); 878103285Sikob db->db.desc.cmd |= OHCI_OUTPUT_LAST 879103285Sikob | OHCI_INTERRUPT_ALWAYS 880103285Sikob | OHCI_BRANCH_ALWAYS; 881103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 882103285Sikob 883103285Sikob if(fsegment == -1 ) 884103285Sikob fsegment = db_tr->dbcnt; 885103285Sikob if (dbch->pdb_tr != NULL) { 886103285Sikob LAST_DB(dbch->pdb_tr, db); 887103285Sikob db->db.desc.depend |= db_tr->dbcnt; 888103285Sikob } 889103285Sikob dbch->pdb_tr = db_tr; 890103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 891103285Sikob if(db_tr != dbch->bottom){ 892103285Sikob goto txloop; 893103285Sikob } else { 894107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 895103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 896103285Sikob } 897103285Sikobkick: 898103285Sikob if (firewire_debug) printf("kick\n"); 899103285Sikob /* kick asy q */ 900103285Sikob 901103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 902103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 903103285Sikob } else { 904107653Ssimokawa if (bootverbose) 905107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 906103285Sikob OREAD(sc, OHCI_DMACTL(off))); 907103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 908103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 909103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 910103285Sikob } 911106790Ssimokawa 912103285Sikob dbch->top = db_tr; 913103285Sikob splx(s); 914103285Sikob return; 915103285Sikob} 916106790Ssimokawa 917106790Ssimokawastatic void 918106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 919103285Sikob{ 920103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 921103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 922103285Sikob return; 923103285Sikob} 924106790Ssimokawa 925106790Ssimokawastatic void 926106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 927103285Sikob{ 928103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 929103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 930103285Sikob return; 931103285Sikob} 932106790Ssimokawa 933106790Ssimokawastatic void 934106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 935103285Sikob{ 936103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 937103285Sikob fwohci_start( sc, &(sc->atrq)); 938103285Sikob return; 939103285Sikob} 940106790Ssimokawa 941106790Ssimokawastatic void 942106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 943103285Sikob{ 944103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 945103285Sikob fwohci_start( sc, &(sc->atrs)); 946103285Sikob return; 947103285Sikob} 948106790Ssimokawa 949106790Ssimokawavoid 950106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 951103285Sikob{ 952103285Sikob int s, err = 0; 953103285Sikob struct fwohcidb_tr *tr; 954103285Sikob volatile struct fwohcidb *db; 955103285Sikob struct fw_xfer *xfer; 956103285Sikob u_int32_t off; 957103285Sikob u_int stat; 958103285Sikob int packets; 959103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 960103285Sikob if(&sc->atrq == dbch){ 961103285Sikob off = OHCI_ATQOFF; 962103285Sikob }else if(&sc->atrs == dbch){ 963103285Sikob off = OHCI_ATSOFF; 964103285Sikob }else{ 965103285Sikob return; 966103285Sikob } 967103285Sikob s = splfw(); 968103285Sikob tr = dbch->bottom; 969103285Sikob packets = 0; 970103285Sikob while(dbch->xferq.queued > 0){ 971103285Sikob LAST_DB(tr, db); 972103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 973103285Sikob if (fc->status != FWBUSRESET) 974103285Sikob /* maybe out of order?? */ 975103285Sikob goto out; 976103285Sikob } 977103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 978103285Sikob#ifdef OHCI_DEBUG 979103285Sikob dump_dma(sc, ch); 980103285Sikob dump_db(sc, ch); 981103285Sikob#endif 982103285Sikob/* Stop DMA */ 983103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 984103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 985103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 986103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 987103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 988103285Sikob } 989103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 990103285Sikob switch(stat){ 991103285Sikob case FWOHCIEV_ACKCOMPL: 992103285Sikob case FWOHCIEV_ACKPEND: 993103285Sikob err = 0; 994103285Sikob break; 995103285Sikob case FWOHCIEV_ACKBSA: 996103285Sikob case FWOHCIEV_ACKBSB: 997103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 998103285Sikob case FWOHCIEV_ACKBSX: 999103285Sikob err = EBUSY; 1000103285Sikob break; 1001103285Sikob case FWOHCIEV_FLUSHED: 1002103285Sikob case FWOHCIEV_ACKTARD: 1003103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1004103285Sikob err = EAGAIN; 1005103285Sikob break; 1006103285Sikob case FWOHCIEV_MISSACK: 1007103285Sikob case FWOHCIEV_UNDRRUN: 1008103285Sikob case FWOHCIEV_OVRRUN: 1009103285Sikob case FWOHCIEV_DESCERR: 1010103285Sikob case FWOHCIEV_DTRDERR: 1011103285Sikob case FWOHCIEV_TIMEOUT: 1012103285Sikob case FWOHCIEV_TCODERR: 1013103285Sikob case FWOHCIEV_UNKNOWN: 1014103285Sikob case FWOHCIEV_ACKDERR: 1015103285Sikob case FWOHCIEV_ACKTERR: 1016103285Sikob default: 1017103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1018103285Sikob stat, fwohcicode[stat]); 1019103285Sikob err = EINVAL; 1020103285Sikob break; 1021103285Sikob } 1022103285Sikob if(tr->xfer != NULL){ 1023103285Sikob xfer = tr->xfer; 1024103285Sikob xfer->state = FWXF_SENT; 1025103285Sikob if(err == EBUSY && fc->status != FWBUSRESET){ 1026103285Sikob xfer->state = FWXF_BUSY; 1027103285Sikob switch(xfer->act_type){ 1028103285Sikob case FWACT_XFER: 1029103285Sikob xfer->resp = err; 1030103285Sikob if(xfer->retry_req != NULL){ 1031103285Sikob xfer->retry_req(xfer); 1032103285Sikob } 1033103285Sikob break; 1034103285Sikob default: 1035103285Sikob break; 1036103285Sikob } 1037103285Sikob } else if( stat != FWOHCIEV_ACKPEND){ 1038103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1039103285Sikob xfer->state = FWXF_SENTERR; 1040103285Sikob xfer->resp = err; 1041103285Sikob switch(xfer->act_type){ 1042103285Sikob case FWACT_XFER: 1043103285Sikob fw_xfer_done(xfer); 1044103285Sikob break; 1045103285Sikob default: 1046103285Sikob break; 1047103285Sikob } 1048103285Sikob } 1049103285Sikob dbch->xferq.queued --; 1050103285Sikob } 1051103285Sikob tr->xfer = NULL; 1052103285Sikob 1053103285Sikob packets ++; 1054103285Sikob tr = STAILQ_NEXT(tr, link); 1055103285Sikob dbch->bottom = tr; 1056103285Sikob } 1057103285Sikobout: 1058103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1059103285Sikob printf("make free slot\n"); 1060103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1061103285Sikob fwohci_start(sc, dbch); 1062103285Sikob } 1063103285Sikob splx(s); 1064103285Sikob} 1065106790Ssimokawa 1066106790Ssimokawastatic void 1067106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1068103285Sikob{ 1069103285Sikob int i, s; 1070103285Sikob struct fwohcidb_tr *tr; 1071103285Sikob 1072103285Sikob if(xfer->state != FWXF_START) return; 1073103285Sikob 1074103285Sikob s = splfw(); 1075103285Sikob tr = dbch->bottom; 1076103285Sikob for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1077103285Sikob if(tr->xfer == xfer){ 1078103285Sikob s = splfw(); 1079103285Sikob tr->xfer = NULL; 1080103285Sikob dbch->xferq.queued --; 1081103285Sikob#if 1 1082103285Sikob /* XXX */ 1083103285Sikob if (tr == dbch->bottom) 1084103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1085103285Sikob#endif 1086103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1087103285Sikob printf("fwohci_drain: make slot\n"); 1088103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1089103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1090103285Sikob } 1091103285Sikob 1092103285Sikob splx(s); 1093103285Sikob break; 1094103285Sikob } 1095103285Sikob tr = STAILQ_NEXT(tr, link); 1096103285Sikob } 1097103285Sikob splx(s); 1098103285Sikob return; 1099103285Sikob} 1100103285Sikob 1101106790Ssimokawastatic void 1102106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1103103285Sikob{ 1104103285Sikob struct fwohcidb_tr *db_tr; 1105109379Ssimokawa int idb, i; 1106103285Sikob 1107108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1108108527Ssimokawa return; 1109108527Ssimokawa 1110103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1111103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1112103285Sikob idb < dbch->ndb; 1113103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1114108527Ssimokawa if (db_tr->buf != NULL) { 1115108527Ssimokawa free(db_tr->buf, M_DEVBUF); 1116108527Ssimokawa db_tr->buf = NULL; 1117108527Ssimokawa } 1118103285Sikob } 1119103285Sikob } 1120103285Sikob dbch->ndb = 0; 1121103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1122109379Ssimokawa for (i = 0; i < dbch->npages; i++) 1123109379Ssimokawa free(dbch->pages[i], M_DEVBUF); 1124103285Sikob free(db_tr, M_DEVBUF); 1125103285Sikob STAILQ_INIT(&dbch->db_trq); 1126108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1127103285Sikob} 1128106790Ssimokawa 1129106790Ssimokawastatic void 1130106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1131103285Sikob{ 1132103285Sikob int idb; 1133103285Sikob struct fwohcidb_tr *db_tr; 1134109379Ssimokawa int ndbpp, i, j; 1135108642Ssimokawa 1136108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1137108642Ssimokawa goto out; 1138108642Ssimokawa 1139103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1140103285Sikob /* DB entry must start at 16 bytes bounary. */ 1141103285Sikob STAILQ_INIT(&dbch->db_trq); 1142103285Sikob db_tr = (struct fwohcidb_tr *) 1143103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1144108527Ssimokawa M_DEVBUF, M_DONTWAIT | M_ZERO); 1145103285Sikob if(db_tr == NULL){ 1146109379Ssimokawa printf("fwohci_db_init: malloc(1) failed\n"); 1147103285Sikob return; 1148103285Sikob } 1149109379Ssimokawa 1150109379Ssimokawa ndbpp = PAGE_SIZE / (sizeof(struct fwohcidb) * dbch->ndesc); 1151109379Ssimokawa dbch->npages = (dbch->ndb + ndbpp - 1)/ ndbpp; 1152109403Ssimokawa if (firewire_debug) 1153109403Ssimokawa printf("ndesc: %d, ndbpp: %d, ndb: %d, npages: %d\n", 1154109403Ssimokawa dbch->ndesc, ndbpp, dbch->ndb, dbch->npages); 1155109379Ssimokawa if (dbch->npages > FWOHCI_DBCH_MAX_PAGES) { 1156109379Ssimokawa printf("npages(%d) > DBCH_MAX_PAGES(%d)\n", 1157109379Ssimokawa dbch->npages, FWOHCI_DBCH_MAX_PAGES); 1158103285Sikob return; 1159103285Sikob } 1160109379Ssimokawa for (i = 0; i < dbch->npages; i++) { 1161109379Ssimokawa dbch->pages[i] = malloc(PAGE_SIZE, M_DEVBUF, 1162109379Ssimokawa M_DONTWAIT | M_ZERO); 1163109379Ssimokawa if (dbch->pages[i] == NULL) { 1164109379Ssimokawa printf("fwohci_db_init: malloc(2) failed\n"); 1165109379Ssimokawa for (j = 0; j < i; j ++) 1166109379Ssimokawa free(dbch->pages[j], M_DEVBUF); 1167109379Ssimokawa free(db_tr, M_DEVBUF); 1168109379Ssimokawa return; 1169109379Ssimokawa } 1170109379Ssimokawa } 1171103285Sikob /* Attach DB to DMA ch. */ 1172103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1173103285Sikob db_tr->dbcnt = 0; 1174109379Ssimokawa db_tr->db = (struct fwohcidb *)dbch->pages[idb/ndbpp] 1175109379Ssimokawa + dbch->ndesc * (idb % ndbpp); 1176103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1177108530Ssimokawa if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1178108530Ssimokawa dbch->xferq.bnpacket != 0) { 1179108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1180108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1181108530Ssimokawa ].start = (caddr_t)db_tr; 1182108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1183108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1184108530Ssimokawa ].end = (caddr_t)db_tr; 1185103285Sikob } 1186103285Sikob db_tr++; 1187103285Sikob } 1188103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1189103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1190108642Ssimokawaout: 1191108642Ssimokawa dbch->frag.buf = NULL; 1192108642Ssimokawa dbch->frag.len = 0; 1193108642Ssimokawa dbch->frag.plen = 0; 1194108642Ssimokawa dbch->xferq.queued = 0; 1195108642Ssimokawa dbch->pdb_tr = NULL; 1196103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1197103285Sikob dbch->bottom = dbch->top; 1198108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1199103285Sikob} 1200106790Ssimokawa 1201106790Ssimokawastatic int 1202106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1203103285Sikob{ 1204103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1205103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1206103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1207103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1208103285Sikob fwohci_db_free(&sc->it[dmach]); 1209103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1210103285Sikob return 0; 1211103285Sikob} 1212106790Ssimokawa 1213106790Ssimokawastatic int 1214106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1215103285Sikob{ 1216103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1217103285Sikob 1218103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1219103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1220103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1221103285Sikob if(sc->ir[dmach].dummy != NULL){ 1222103285Sikob free(sc->ir[dmach].dummy, M_DEVBUF); 1223103285Sikob } 1224103285Sikob sc->ir[dmach].dummy = NULL; 1225103285Sikob fwohci_db_free(&sc->ir[dmach]); 1226103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1227103285Sikob return 0; 1228103285Sikob} 1229106790Ssimokawa 1230106790Ssimokawastatic void 1231106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1232103285Sikob{ 1233103285Sikob qld[0] = ntohl(qld[0]); 1234103285Sikob return; 1235103285Sikob} 1236106790Ssimokawa 1237106790Ssimokawastatic int 1238106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1239103285Sikob{ 1240103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1241103285Sikob int err = 0; 1242103285Sikob unsigned short tag, ich; 1243103285Sikob 1244103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1245103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1246103285Sikob 1247103285Sikob#if 0 1248103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1249103285Sikob wakeup(fc->ir[dmach]); 1250103285Sikob return err; 1251103285Sikob } 1252103285Sikob#endif 1253103285Sikob 1254103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1255103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1256103285Sikob sc->ir[dmach].xferq.queued = 0; 1257103285Sikob sc->ir[dmach].ndb = NDB; 1258109379Ssimokawa sc->ir[dmach].xferq.psize = PAGE_SIZE; 1259103285Sikob sc->ir[dmach].ndesc = 1; 1260103285Sikob fwohci_db_init(&sc->ir[dmach]); 1261109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1262109179Ssimokawa return ENOMEM; 1263103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1264103285Sikob } 1265103285Sikob if(err){ 1266103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1267103285Sikob return err; 1268103285Sikob } 1269103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1270103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1271103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1272103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1273103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1274103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1275103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1276103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1277103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1278103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1279103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1280103285Sikob } 1281103285Sikob return err; 1282103285Sikob} 1283106790Ssimokawa 1284106790Ssimokawastatic int 1285106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1286103285Sikob{ 1287103285Sikob int err = 0; 1288103285Sikob int idb, z, i, dmach = 0; 1289103285Sikob u_int32_t off = NULL; 1290103285Sikob struct fwohcidb_tr *db_tr; 1291103285Sikob 1292103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1293103285Sikob err = EINVAL; 1294103285Sikob return err; 1295103285Sikob } 1296103285Sikob z = dbch->ndesc; 1297103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1298103285Sikob if( &sc->it[dmach] == dbch){ 1299103285Sikob off = OHCI_ITOFF(dmach); 1300103285Sikob break; 1301103285Sikob } 1302103285Sikob } 1303103285Sikob if(off == NULL){ 1304103285Sikob err = EINVAL; 1305103285Sikob return err; 1306103285Sikob } 1307103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1308103285Sikob return err; 1309103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1310103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1311103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1312103285Sikob } 1313103285Sikob db_tr = dbch->top; 1314103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1315103285Sikob fwohci_add_tx_buf(db_tr, 1316103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1317103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1318103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1319103285Sikob break; 1320103285Sikob } 1321103285Sikob db_tr->db[0].db.desc.depend 1322103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1323103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1324103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1325103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1326103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1327103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1328103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1329103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 1330103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1331103285Sikob ~0xf; 1332109280Ssimokawa /* OHCI 1.1 and above */ 1333109280Ssimokawa db_tr->db[0].db.desc.cmd 1334109280Ssimokawa |= OHCI_INTERRUPT_ALWAYS; 1335103285Sikob } 1336103285Sikob } 1337103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1338103285Sikob } 1339103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1340103285Sikob return err; 1341103285Sikob} 1342106790Ssimokawa 1343106790Ssimokawastatic int 1344106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1345103285Sikob{ 1346103285Sikob int err = 0; 1347103285Sikob int idb, z, i, dmach = 0; 1348103285Sikob u_int32_t off = NULL; 1349103285Sikob struct fwohcidb_tr *db_tr; 1350103285Sikob 1351103285Sikob z = dbch->ndesc; 1352103285Sikob if(&sc->arrq == dbch){ 1353103285Sikob off = OHCI_ARQOFF; 1354103285Sikob }else if(&sc->arrs == dbch){ 1355103285Sikob off = OHCI_ARSOFF; 1356103285Sikob }else{ 1357103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1358103285Sikob if( &sc->ir[dmach] == dbch){ 1359103285Sikob off = OHCI_IROFF(dmach); 1360103285Sikob break; 1361103285Sikob } 1362103285Sikob } 1363103285Sikob } 1364103285Sikob if(off == NULL){ 1365103285Sikob err = EINVAL; 1366103285Sikob return err; 1367103285Sikob } 1368103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1369103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1370103285Sikob return err; 1371103285Sikob }else{ 1372103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1373103285Sikob err = EBUSY; 1374103285Sikob return err; 1375103285Sikob } 1376103285Sikob } 1377103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1378108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1379103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1380103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1381103285Sikob } 1382103285Sikob db_tr = dbch->top; 1383103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1384103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1385103285Sikob fwohci_add_rx_buf(db_tr, 1386103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1387103285Sikob }else{ 1388103285Sikob fwohci_add_rx_buf(db_tr, 1389103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1390103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1391103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1392103285Sikob } 1393103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1394103285Sikob break; 1395103285Sikob } 1396103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1397103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1398103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1399103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1400103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1401103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1402103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1403103285Sikob ~0xf; 1404103285Sikob } 1405103285Sikob } 1406103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1407103285Sikob } 1408103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1409103285Sikob dbch->buf_offset = 0; 1410103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1411103285Sikob return err; 1412103285Sikob }else{ 1413103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1414103285Sikob } 1415103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1416103285Sikob return err; 1417103285Sikob} 1418106790Ssimokawa 1419106790Ssimokawastatic int 1420106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1421103285Sikob{ 1422103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1423103285Sikob int err = 0; 1424103285Sikob unsigned short tag, ich; 1425103285Sikob struct fwohci_dbch *dbch; 1426103285Sikob struct fw_pkt *fp; 1427103285Sikob struct fwohcidb_tr *db_tr; 1428109356Ssimokawa int cycle_now, sec, cycle, cycle_match; 1429109356Ssimokawa u_int32_t stat; 1430103285Sikob 1431103285Sikob tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1432103285Sikob ich = sc->it[dmach].xferq.flag & 0x3f; 1433103285Sikob dbch = &sc->it[dmach]; 1434109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1435103285Sikob dbch->xferq.queued = 0; 1436103285Sikob dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1437103285Sikob dbch->ndesc = 3; 1438103285Sikob fwohci_db_init(dbch); 1439109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1440109179Ssimokawa return ENOMEM; 1441103285Sikob err = fwohci_tx_enable(sc, dbch); 1442103285Sikob } 1443103285Sikob if(err) 1444103285Sikob return err; 1445109356Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1446109356Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) { 1447103285Sikob if(dbch->xferq.stdma2 != NULL){ 1448103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1449103285Sikob ((struct fwohcidb_tr *) 1450103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1451103285Sikob |= OHCI_BRANCH_ALWAYS; 1452103285Sikob ((struct fwohcidb_tr *) 1453103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1454103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1455103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1456103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1457103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1458103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1459109403Ssimokawa } else { 1460109423Ssimokawa device_printf(fc->dev, 1461109403Ssimokawa "fwohci_itxbuf_enable: queue underrun\n"); 1462103285Sikob } 1463109403Ssimokawa return err; 1464109403Ssimokawa } 1465109403Ssimokawa if (firewire_debug) 1466109403Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); 1467109403Ssimokawa fw_tbuf_update(&sc->fc, dmach, 0); 1468109403Ssimokawa if(dbch->xferq.stdma == NULL){ 1469109403Ssimokawa return err; 1470109403Ssimokawa } 1471109403Ssimokawa if(dbch->xferq.stdma2 == NULL){ 1472109403Ssimokawa /* wait until 2 chunks buffered */ 1473109403Ssimokawa return err; 1474109403Ssimokawa } 1475109403Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1476109403Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1477109403Ssimokawa OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1478109403Ssimokawa fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1479109403Ssimokawa fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1480109403Ssimokawa ((struct fwohcidb_tr *) 1481103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1482103285Sikob |= OHCI_BRANCH_ALWAYS; 1483109403Ssimokawa ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1484103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1485109403Ssimokawa ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1486103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1487109403Ssimokawa ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1488109403Ssimokawa ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1489109403Ssimokawa OWRITE(sc, OHCI_ITCMD(dmach), 1490109403Ssimokawa vtophys(((struct fwohcidb_tr *) 1491109403Ssimokawa (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1492109356Ssimokawa#define CYCLE_OFFSET 1 1493109403Ssimokawa if ((stat & OHCI_CNTL_DMA_RUN) == 0) { 1494103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1495103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1496103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1497109356Ssimokawa dbch->xferq.dvoffset = CYCLE_OFFSET; 1498109179Ssimokawa fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1499103285Sikob } 1500109356Ssimokawa /* 2bit second + 13bit cycle */ 1501109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1502109356Ssimokawa cycle = cycle_now & 0x1fff; 1503109356Ssimokawa sec = cycle_now >> 13; 1504109356Ssimokawa#define CYCLE_MOD 0x10 1505109356Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1506109356Ssimokawa cycle = cycle + CYCLE_DELAY; 1507109356Ssimokawa if (cycle >= 8000) { 1508109356Ssimokawa sec ++; 1509109356Ssimokawa cycle -= 8000; 1510109356Ssimokawa } 1511109356Ssimokawa cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1512109356Ssimokawa if (cycle >= 8000) { 1513109356Ssimokawa sec ++; 1514109356Ssimokawa if (cycle == 8000) 1515109356Ssimokawa cycle = 0; 1516109356Ssimokawa else 1517109356Ssimokawa cycle = CYCLE_MOD; 1518109356Ssimokawa } 1519109356Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1520109356Ssimokawa /* Clear cycle match counter bits */ 1521109356Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1522109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1523109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1524109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1525103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1526109403Ssimokawa if (firewire_debug) 1527109403Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1528109403Ssimokawa cycle_now, cycle_match); 1529109403Ssimokawa } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { 1530109403Ssimokawa if (firewire_debug) 1531109403Ssimokawa printf("fwohci_itxbuf_enable: restart 0x%08x\n", stat); 1532109403Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1533109403Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1534103285Sikob } 1535103285Sikob return err; 1536103285Sikob} 1537106790Ssimokawa 1538106790Ssimokawastatic int 1539106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1540103285Sikob{ 1541103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1542103285Sikob int err = 0; 1543103285Sikob unsigned short tag, ich; 1544103285Sikob 1545103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1546108995Ssimokawa tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1547108995Ssimokawa ich = sc->ir[dmach].xferq.flag & 0x3f; 1548108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1549108995Ssimokawa 1550103285Sikob sc->ir[dmach].xferq.queued = 0; 1551103285Sikob sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1552103285Sikob sc->ir[dmach].xferq.bnchunk; 1553103285Sikob sc->ir[dmach].dummy = 1554103285Sikob malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1555103285Sikob M_DEVBUF, M_DONTWAIT); 1556103285Sikob if(sc->ir[dmach].dummy == NULL){ 1557103285Sikob err = ENOMEM; 1558103285Sikob return err; 1559103285Sikob } 1560103285Sikob sc->ir[dmach].ndesc = 2; 1561103285Sikob fwohci_db_init(&sc->ir[dmach]); 1562109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1563109179Ssimokawa return ENOMEM; 1564103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1565103285Sikob } 1566103285Sikob if(err) 1567103285Sikob return err; 1568103285Sikob 1569103285Sikob if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1570103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1571103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1572103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1573103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1574103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1575103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1576103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1577103285Sikob } 1578103285Sikob }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1579103285Sikob && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1580103285Sikob fw_rbuf_update(&sc->fc, dmach, 0); 1581103285Sikob 1582103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1583103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1584103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1585103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1586103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1587103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1588103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1589103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1590103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1591103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1592103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1593103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1594103285Sikob }else{ 1595103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1596103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1597103285Sikob } 1598103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1599103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1600103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1601108995Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1602103285Sikob } 1603103285Sikob return err; 1604103285Sikob} 1605106790Ssimokawa 1606106790Ssimokawastatic int 1607106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1608103285Sikob{ 1609103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1610103285Sikob int err = 0; 1611103285Sikob 1612103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1613103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1614103285Sikob return err; 1615103285Sikob }else{ 1616103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1617103285Sikob return err; 1618103285Sikob } 1619103285Sikob} 1620106790Ssimokawa 1621106790Ssimokawaint 1622108642Ssimokawafwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1623103285Sikob{ 1624103285Sikob u_int i; 1625103285Sikob 1626103285Sikob/* Now stopping all DMA channel */ 1627103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1628103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1629103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1630103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1631103285Sikob 1632103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1633103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1634103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1635103285Sikob } 1636103285Sikob 1637103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1638103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1639103285Sikob 1640103285Sikob/* Stop interrupt */ 1641103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1642103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1643103285Sikob | OHCI_INT_PHY_INT 1644103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1645103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1646103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1647103285Sikob | OHCI_INT_PHY_BUS_R); 1648108642Ssimokawa/* XXX Link down? Bus reset? */ 1649103285Sikob return 0; 1650103285Sikob} 1651103285Sikob 1652108642Ssimokawaint 1653108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1654108642Ssimokawa{ 1655108642Ssimokawa int i; 1656108642Ssimokawa 1657108642Ssimokawa fwohci_reset(sc, dev); 1658108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1659108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1660108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1661108642Ssimokawa device_printf(sc->fc.dev, 1662108642Ssimokawa "resume iso receive ch: %d\n", i); 1663108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1664108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1665108642Ssimokawa } 1666108642Ssimokawa } 1667108642Ssimokawa 1668108642Ssimokawa bus_generic_resume(dev); 1669108642Ssimokawa sc->fc.ibr(&sc->fc); 1670108642Ssimokawa return 0; 1671108642Ssimokawa} 1672108642Ssimokawa 1673103285Sikob#define ACK_ALL 1674103285Sikobstatic void 1675106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1676103285Sikob{ 1677103285Sikob u_int32_t irstat, itstat; 1678103285Sikob u_int i; 1679103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1680103285Sikob 1681103285Sikob#ifdef OHCI_DEBUG 1682103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1683103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1684103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1685103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1686103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1687103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1688103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1689103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1690103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1691103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1692103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1693103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1694103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1695103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1696103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1697103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1698103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1699103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1700103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1701103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1702103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1703103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1704103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1705103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1706103285Sikob ); 1707103285Sikob#endif 1708103285Sikob/* Bus reset */ 1709103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1710103285Sikob device_printf(fc->dev, "BUS reset\n"); 1711103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1712103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1713103285Sikob 1714103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1715103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1716103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1717103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1718103285Sikob 1719103285Sikob#if 0 1720103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1721103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1722103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1723103285Sikob } 1724103285Sikob 1725103285Sikob#endif 1726103285Sikob fw_busreset(fc); 1727103285Sikob 1728103285Sikob /* XXX need to wait DMA to stop */ 1729103285Sikob#ifndef ACK_ALL 1730103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1731103285Sikob#endif 1732103285Sikob#if 1 1733103285Sikob /* pending all pre-bus_reset packets */ 1734103285Sikob fwohci_txd(sc, &sc->atrq); 1735103285Sikob fwohci_txd(sc, &sc->atrs); 1736106789Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1737106789Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1738103285Sikob#endif 1739103285Sikob 1740103285Sikob 1741103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1742103285Sikob /* XXX insecure ?? */ 1743103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1744103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1745103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1746103285Sikob 1747103285Sikob } 1748103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1749103285Sikob#ifndef ACK_ALL 1750103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1751103285Sikob#endif 1752103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1753109280Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 1754103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1755103285Sikob if((irstat & (1 << i)) != 0){ 1756103285Sikob if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1757106789Ssimokawa fwohci_ircv(sc, &sc->ir[i], count); 1758103285Sikob }else{ 1759103285Sikob fwohci_rbuf_update(sc, i); 1760103285Sikob } 1761103285Sikob } 1762103285Sikob } 1763103285Sikob } 1764103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1765103285Sikob#ifndef ACK_ALL 1766103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1767103285Sikob#endif 1768103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1769109280Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 1770103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1771103285Sikob if((itstat & (1 << i)) != 0){ 1772103285Sikob fwohci_tbuf_update(sc, i); 1773103285Sikob } 1774103285Sikob } 1775103285Sikob } 1776103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1777103285Sikob#ifndef ACK_ALL 1778103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1779103285Sikob#endif 1780103285Sikob#if 0 1781103285Sikob dump_dma(sc, ARRS_CH); 1782103285Sikob dump_db(sc, ARRS_CH); 1783103285Sikob#endif 1784106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1785103285Sikob } 1786103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1787103285Sikob#ifndef ACK_ALL 1788103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1789103285Sikob#endif 1790103285Sikob#if 0 1791103285Sikob dump_dma(sc, ARRQ_CH); 1792103285Sikob dump_db(sc, ARRQ_CH); 1793103285Sikob#endif 1794106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1795103285Sikob } 1796103285Sikob if(stat & OHCI_INT_PHY_SID){ 1797103285Sikob caddr_t buf; 1798103285Sikob int plen; 1799103285Sikob 1800103285Sikob#ifndef ACK_ALL 1801103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1802103285Sikob#endif 1803103285Sikob/* 1804103285Sikob** Checking whether the node is root or not. If root, turn on 1805103285Sikob** cycle master. 1806103285Sikob*/ 1807103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1808103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1809103285Sikob printf("Bus reset failure\n"); 1810103285Sikob goto sidout; 1811103285Sikob } 1812103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1813103285Sikob printf("CYCLEMASTER mode\n"); 1814103285Sikob OWRITE(sc, OHCI_LNKCTL, 1815103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1816103285Sikob }else{ 1817103285Sikob printf("non CYCLEMASTER mode\n"); 1818103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1819103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1820103285Sikob } 1821103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1822103285Sikob 1823103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1824103285Sikob plen -= 4; /* chop control info */ 1825109379Ssimokawa buf = malloc(OHCI_SIDSIZE, M_DEVBUF, M_NOWAIT); 1826103285Sikob if(buf == NULL) goto sidout; 1827108530Ssimokawa bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1828103285Sikob buf, plen); 1829103285Sikob fw_sidrcv(fc, buf, plen, 0); 1830103285Sikob } 1831103285Sikobsidout: 1832103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1833103285Sikob#ifndef ACK_ALL 1834103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1835103285Sikob#endif 1836103285Sikob fwohci_txd(sc, &(sc->atrq)); 1837103285Sikob } 1838103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1839103285Sikob#ifndef ACK_ALL 1840103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1841103285Sikob#endif 1842103285Sikob fwohci_txd(sc, &(sc->atrs)); 1843103285Sikob } 1844103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1845103285Sikob#ifndef ACK_ALL 1846103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1847103285Sikob#endif 1848103285Sikob device_printf(fc->dev, "posted write error\n"); 1849103285Sikob } 1850103285Sikob if((stat & OHCI_INT_ERR )){ 1851103285Sikob#ifndef ACK_ALL 1852103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1853103285Sikob#endif 1854103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1855103285Sikob } 1856103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1857103285Sikob#ifndef ACK_ALL 1858103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1859103285Sikob#endif 1860103285Sikob device_printf(fc->dev, "phy int\n"); 1861103285Sikob } 1862103285Sikob 1863103285Sikob return; 1864103285Sikob} 1865103285Sikob 1866103285Sikobvoid 1867103285Sikobfwohci_intr(void *arg) 1868103285Sikob{ 1869103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1870103285Sikob u_int32_t stat; 1871103285Sikob 1872103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1873103285Sikob /* polling mode */ 1874103285Sikob return; 1875103285Sikob } 1876103285Sikob 1877103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1878103285Sikob if (stat == 0xffffffff) { 1879103285Sikob device_printf(sc->fc.dev, 1880103285Sikob "device physically ejected?\n"); 1881103285Sikob return; 1882103285Sikob } 1883103285Sikob#ifdef ACK_ALL 1884103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1885103285Sikob#endif 1886106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1887103285Sikob } 1888103285Sikob} 1889103285Sikob 1890103285Sikobstatic void 1891103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1892103285Sikob{ 1893103285Sikob int s; 1894103285Sikob u_int32_t stat; 1895103285Sikob struct fwohci_softc *sc; 1896103285Sikob 1897103285Sikob 1898103285Sikob sc = (struct fwohci_softc *)fc; 1899103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1900103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1901103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1902103285Sikob#if 0 1903103285Sikob if (!quick) { 1904103285Sikob#else 1905103285Sikob if (1) { 1906103285Sikob#endif 1907103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1908103285Sikob if (stat == 0) 1909103285Sikob return; 1910103285Sikob if (stat == 0xffffffff) { 1911103285Sikob device_printf(sc->fc.dev, 1912103285Sikob "device physically ejected?\n"); 1913103285Sikob return; 1914103285Sikob } 1915103285Sikob#ifdef ACK_ALL 1916103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1917103285Sikob#endif 1918103285Sikob } 1919103285Sikob s = splfw(); 1920106789Ssimokawa fwohci_intr_body(sc, stat, count); 1921103285Sikob splx(s); 1922103285Sikob} 1923103285Sikob 1924103285Sikobstatic void 1925103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 1926103285Sikob{ 1927103285Sikob struct fwohci_softc *sc; 1928103285Sikob 1929103285Sikob sc = (struct fwohci_softc *)fc; 1930107653Ssimokawa if (bootverbose) 1931108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1932103285Sikob if (enable) { 1933103285Sikob sc->intmask |= OHCI_INT_EN; 1934103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1935103285Sikob } else { 1936103285Sikob sc->intmask &= ~OHCI_INT_EN; 1937103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1938103285Sikob } 1939103285Sikob} 1940103285Sikob 1941106790Ssimokawastatic void 1942106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1943103285Sikob{ 1944103285Sikob int stat; 1945103285Sikob struct firewire_comm *fc = &sc->fc; 1946103285Sikob struct fw_pkt *fp; 1947103285Sikob struct fwohci_dbch *dbch; 1948103285Sikob struct fwohcidb_tr *db_tr; 1949103285Sikob 1950103285Sikob dbch = &sc->it[dmach]; 1951109179Ssimokawa#if 0 /* XXX OHCI interrupt before the last packet is really on the wire */ 1952103285Sikob if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1953103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1954103285Sikob/* 1955103285Sikob * Overwrite highest significant 4 bits timestamp information 1956103285Sikob */ 1957103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1958109179Ssimokawa fp->mode.ld[2] &= htonl(0xffff0fff); 1959109179Ssimokawa fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000); 1960103285Sikob } 1961109179Ssimokawa#endif 1962109403Ssimokawa /* 1963109403Ssimokawa * XXX interrupt could be missed. 1964109403Ssimokawa * We have to check more than one buffer/chunk 1965109403Ssimokawa */ 1966109403Ssimokawa if (firewire_debug && dbch->xferq.stdma2 != NULL) { 1967109403Ssimokawa db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->end; 1968109403Ssimokawa stat = db_tr->db[2].db.desc.status; 1969109403Ssimokawa if (stat) 1970109423Ssimokawa device_printf(fc->dev, 1971109423Ssimokawa "stdma2 already done stat:0x%x\n", stat); 1972109403Ssimokawa } 1973109403Ssimokawa 1974103285Sikob stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1975103285Sikob switch(stat){ 1976103285Sikob case FWOHCIEV_ACKCOMPL: 1977109179Ssimokawa#if 1 1978109179Ssimokawa if (dbch->xferq.flag & FWXFERQ_DV) { 1979109179Ssimokawa struct ciphdr *ciph; 1980109179Ssimokawa int timer, timestamp, cycl, diff; 1981109179Ssimokawa static int last_timer=0; 1982109179Ssimokawa 1983109179Ssimokawa timer = (fc->cyctimer(fc) >> 12) & 0xffff; 1984109179Ssimokawa db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1985109179Ssimokawa fp = (struct fw_pkt *)db_tr->buf; 1986109179Ssimokawa ciph = (struct ciphdr *) &fp->mode.ld[1]; 1987109179Ssimokawa timestamp = db_tr->db[2].db.desc.count & 0xffff; 1988109179Ssimokawa cycl = ntohs(ciph->fdf.dv.cyc) >> 12; 1989109356Ssimokawa diff = cycl - (timestamp & 0xf) - CYCLE_OFFSET; 1990109179Ssimokawa if (diff < 0) 1991109179Ssimokawa diff += 16; 1992109179Ssimokawa if (diff > 8) 1993109179Ssimokawa diff -= 16; 1994109280Ssimokawa if (firewire_debug || diff != 0) 1995109179Ssimokawa printf("dbc: %3d timer: 0x%04x packet: 0x%04x" 1996109179Ssimokawa " cyc: 0x%x diff: %+1d\n", 1997109179Ssimokawa ciph->dbc, last_timer, timestamp, cycl, diff); 1998109179Ssimokawa last_timer = timer; 1999109179Ssimokawa /* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */ 2000109179Ssimokawa } 2001109179Ssimokawa#endif 2002103285Sikob fw_tbuf_update(fc, dmach, 1); 2003103285Sikob break; 2004103285Sikob default: 2005109179Ssimokawa device_printf(fc->dev, "Isochronous transmit err %02x\n", stat); 2006103285Sikob fw_tbuf_update(fc, dmach, 0); 2007103285Sikob break; 2008103285Sikob } 2009109179Ssimokawa fwohci_itxbuf_enable(fc, dmach); 2010103285Sikob} 2011106790Ssimokawa 2012106790Ssimokawastatic void 2013106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 2014103285Sikob{ 2015109179Ssimokawa struct firewire_comm *fc = &sc->fc; 2016103285Sikob int stat; 2017109179Ssimokawa 2018103285Sikob stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 2019103285Sikob switch(stat){ 2020103285Sikob case FWOHCIEV_ACKCOMPL: 2021109179Ssimokawa fw_rbuf_update(fc, dmach, 1); 2022109179Ssimokawa wakeup(fc->ir[dmach]); 2023109179Ssimokawa fwohci_irx_enable(fc, dmach); 2024103285Sikob break; 2025103285Sikob default: 2026109179Ssimokawa device_printf(fc->dev, "Isochronous receive err %02x\n", 2027109179Ssimokawa stat); 2028103285Sikob break; 2029103285Sikob } 2030103285Sikob} 2031106790Ssimokawa 2032106790Ssimokawavoid 2033106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2034106790Ssimokawa{ 2035103285Sikob u_int32_t off, cntl, stat, cmd, match; 2036103285Sikob 2037103285Sikob if(ch == 0){ 2038103285Sikob off = OHCI_ATQOFF; 2039103285Sikob }else if(ch == 1){ 2040103285Sikob off = OHCI_ATSOFF; 2041103285Sikob }else if(ch == 2){ 2042103285Sikob off = OHCI_ARQOFF; 2043103285Sikob }else if(ch == 3){ 2044103285Sikob off = OHCI_ARSOFF; 2045103285Sikob }else if(ch < IRX_CH){ 2046103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2047103285Sikob }else{ 2048103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2049103285Sikob } 2050103285Sikob cntl = stat = OREAD(sc, off); 2051103285Sikob cmd = OREAD(sc, off + 0xc); 2052103285Sikob match = OREAD(sc, off + 0x10); 2053103285Sikob 2054103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2055103285Sikob ch, 2056103285Sikob cntl, 2057103285Sikob stat, 2058103285Sikob cmd, 2059103285Sikob match); 2060103285Sikob stat &= 0xffff ; 2061103285Sikob if(stat & 0xff00){ 2062103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2063103285Sikob ch, 2064103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2065103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2066103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2067103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2068103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2069103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2070103285Sikob fwohcicode[stat & 0x1f], 2071103285Sikob stat & 0x1f 2072103285Sikob ); 2073103285Sikob }else{ 2074103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2075103285Sikob } 2076103285Sikob} 2077106790Ssimokawa 2078106790Ssimokawavoid 2079106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2080106790Ssimokawa{ 2081103285Sikob struct fwohci_dbch *dbch; 2082103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 2083103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2084103285Sikob int idb, jdb; 2085103285Sikob u_int32_t cmd, off; 2086103285Sikob if(ch == 0){ 2087103285Sikob off = OHCI_ATQOFF; 2088103285Sikob dbch = &sc->atrq; 2089103285Sikob }else if(ch == 1){ 2090103285Sikob off = OHCI_ATSOFF; 2091103285Sikob dbch = &sc->atrs; 2092103285Sikob }else if(ch == 2){ 2093103285Sikob off = OHCI_ARQOFF; 2094103285Sikob dbch = &sc->arrq; 2095103285Sikob }else if(ch == 3){ 2096103285Sikob off = OHCI_ARSOFF; 2097103285Sikob dbch = &sc->arrs; 2098103285Sikob }else if(ch < IRX_CH){ 2099103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2100103285Sikob dbch = &sc->it[ch - ITX_CH]; 2101103285Sikob }else { 2102103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2103103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2104103285Sikob } 2105103285Sikob cmd = OREAD(sc, off + 0xc); 2106103285Sikob 2107103285Sikob if( dbch->ndb == 0 ){ 2108103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2109103285Sikob return; 2110103285Sikob } 2111103285Sikob pp = dbch->top; 2112103285Sikob prev = pp->db; 2113103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2114103285Sikob if(pp == NULL){ 2115103285Sikob curr = NULL; 2116103285Sikob goto outdb; 2117103285Sikob } 2118103285Sikob cp = STAILQ_NEXT(pp, link); 2119103285Sikob if(cp == NULL){ 2120103285Sikob curr = NULL; 2121103285Sikob goto outdb; 2122103285Sikob } 2123103285Sikob np = STAILQ_NEXT(cp, link); 2124103285Sikob if(cp == NULL) break; 2125103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2126103285Sikob if((cmd & 0xfffffff0) 2127103285Sikob == vtophys(&(cp->db[jdb]))){ 2128103285Sikob curr = cp->db; 2129103285Sikob if(np != NULL){ 2130103285Sikob next = np->db; 2131103285Sikob }else{ 2132103285Sikob next = NULL; 2133103285Sikob } 2134103285Sikob goto outdb; 2135103285Sikob } 2136103285Sikob } 2137103285Sikob pp = STAILQ_NEXT(pp, link); 2138103285Sikob prev = pp->db; 2139103285Sikob } 2140103285Sikoboutdb: 2141103285Sikob if( curr != NULL){ 2142103285Sikob printf("Prev DB %d\n", ch); 2143103285Sikob print_db(prev, ch, dbch->ndesc); 2144103285Sikob printf("Current DB %d\n", ch); 2145103285Sikob print_db(curr, ch, dbch->ndesc); 2146103285Sikob printf("Next DB %d\n", ch); 2147103285Sikob print_db(next, ch, dbch->ndesc); 2148103285Sikob }else{ 2149103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2150103285Sikob } 2151103285Sikob return; 2152103285Sikob} 2153106790Ssimokawa 2154106790Ssimokawavoid 2155106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2156106790Ssimokawa{ 2157103285Sikob fwohcireg_t stat; 2158103285Sikob int i, key; 2159103285Sikob 2160103285Sikob if(db == NULL){ 2161103285Sikob printf("No Descriptor is found\n"); 2162103285Sikob return; 2163103285Sikob } 2164103285Sikob 2165103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2166103285Sikob ch, 2167103285Sikob "Current", 2168103285Sikob "OP ", 2169103285Sikob "KEY", 2170103285Sikob "INT", 2171103285Sikob "BR ", 2172103285Sikob "len", 2173103285Sikob "Addr", 2174103285Sikob "Depend", 2175103285Sikob "Stat", 2176103285Sikob "Cnt"); 2177103285Sikob for( i = 0 ; i <= max ; i ++){ 2178103285Sikob key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2179108712Ssimokawa#if __FreeBSD_version >= 500000 2180106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2181108712Ssimokawa#else 2182108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2183108712Ssimokawa#endif 2184103285Sikob vtophys(&db[i]), 2185103285Sikob dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2186103285Sikob dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2187103285Sikob dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2188103285Sikob dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2189103285Sikob db[i].db.desc.cmd & 0xffff, 2190103285Sikob db[i].db.desc.addr, 2191103285Sikob db[i].db.desc.depend, 2192103285Sikob db[i].db.desc.status, 2193103285Sikob db[i].db.desc.count); 2194103285Sikob stat = db[i].db.desc.status; 2195103285Sikob if(stat & 0xff00){ 2196103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2197103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2198103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2199103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2200103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2201103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2202103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2203103285Sikob fwohcicode[stat & 0x1f], 2204103285Sikob stat & 0x1f 2205103285Sikob ); 2206103285Sikob }else{ 2207103285Sikob printf(" Nostat\n"); 2208103285Sikob } 2209103285Sikob if(key == OHCI_KEY_ST2 ){ 2210103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2211103285Sikob db[i+1].db.immed[0], 2212103285Sikob db[i+1].db.immed[1], 2213103285Sikob db[i+1].db.immed[2], 2214103285Sikob db[i+1].db.immed[3]); 2215103285Sikob } 2216103285Sikob if(key == OHCI_KEY_DEVICE){ 2217103285Sikob return; 2218103285Sikob } 2219103285Sikob if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2220103285Sikob == OHCI_BRANCH_ALWAYS){ 2221103285Sikob return; 2222103285Sikob } 2223103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2224103285Sikob == OHCI_OUTPUT_LAST){ 2225103285Sikob return; 2226103285Sikob } 2227103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2228103285Sikob == OHCI_INPUT_LAST){ 2229103285Sikob return; 2230103285Sikob } 2231103285Sikob if(key == OHCI_KEY_ST2 ){ 2232103285Sikob i++; 2233103285Sikob } 2234103285Sikob } 2235103285Sikob return; 2236103285Sikob} 2237106790Ssimokawa 2238106790Ssimokawavoid 2239106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2240103285Sikob{ 2241103285Sikob struct fwohci_softc *sc; 2242103285Sikob u_int32_t fun; 2243103285Sikob 2244103285Sikob sc = (struct fwohci_softc *)fc; 2245108276Ssimokawa 2246108276Ssimokawa /* 2247108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2248108276Ssimokawa * shouldn't became the root node. 2249108276Ssimokawa */ 2250103285Sikob#if 1 2251103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2252109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2253103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2254109280Ssimokawa#else /* Short bus reset */ 2255103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2256109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2257103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2258103285Sikob#endif 2259103285Sikob} 2260106790Ssimokawa 2261106790Ssimokawavoid 2262106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2263103285Sikob{ 2264103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2265103285Sikob struct fwohci_dbch *dbch; 2266103285Sikob struct fw_pkt *fp; 2267103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2268103285Sikob unsigned short chtag; 2269103285Sikob int idb; 2270103285Sikob 2271103285Sikob dbch = &sc->it[dmach]; 2272103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2273103285Sikob 2274103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2275103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2276103285Sikob/* 2277103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2278103285Sikob*/ 2279103285Sikob if(bulkxfer->flag != 0){ 2280103285Sikob return; 2281103285Sikob } 2282103285Sikob bulkxfer->flag = 1; 2283103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2284103285Sikob db_tr->db[0].db.desc.cmd 2285103285Sikob = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2286103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2287103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) 2288103285Sikob db_tr->db[1].db.immed; 2289103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2290103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2291103285Sikob ohcifp->mode.stream.chtag = chtag; 2292103285Sikob ohcifp->mode.stream.tcode = 0xa; 2293103285Sikob ohcifp->mode.stream.spd = 4; 2294103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2295103285Sikob ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2296103285Sikob 2297103285Sikob db_tr->db[2].db.desc.cmd 2298103285Sikob = OHCI_OUTPUT_LAST 2299103285Sikob | OHCI_UPDATE 2300103285Sikob | OHCI_BRANCH_ALWAYS 2301103285Sikob | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2302103285Sikob db_tr->db[2].db.desc.status = 0; 2303103285Sikob db_tr->db[2].db.desc.count = 0; 2304109280Ssimokawa db_tr->db[0].db.desc.depend 2305109280Ssimokawa = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2306109280Ssimokawa db_tr->db[dbch->ndesc - 1].db.desc.depend 2307109280Ssimokawa = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2308103285Sikob bulkxfer->end = (caddr_t)db_tr; 2309103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2310103285Sikob } 2311103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2312103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2313103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2314109280Ssimokawa#if 0 2315103285Sikob/**/ 2316103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2317103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2318103285Sikob/**/ 2319109280Ssimokawa#endif 2320103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2321109280Ssimokawa /* OHCI 1.1 and above */ 2322109280Ssimokawa db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2323103285Sikob 2324103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2325103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2326103285Sikob/* 2327103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2328103285Sikob*/ 2329103285Sikob return; 2330103285Sikob} 2331106790Ssimokawa 2332106790Ssimokawastatic int 2333106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2334106790Ssimokawa int mode, void *buf) 2335103285Sikob{ 2336103285Sikob volatile struct fwohcidb *db = db_tr->db; 2337103285Sikob int err = 0; 2338103285Sikob if(buf == 0){ 2339103285Sikob err = EINVAL; 2340103285Sikob return err; 2341103285Sikob } 2342103285Sikob db_tr->buf = buf; 2343103285Sikob db_tr->dbcnt = 3; 2344103285Sikob db_tr->dummy = NULL; 2345103285Sikob 2346103285Sikob db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2347103285Sikob 2348103285Sikob db[2].db.desc.depend = 0; 2349103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2350103285Sikob db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2351103285Sikob 2352103285Sikob db[0].db.desc.status = 0; 2353103285Sikob db[0].db.desc.count = 0; 2354103285Sikob 2355103285Sikob db[2].db.desc.status = 0; 2356103285Sikob db[2].db.desc.count = 0; 2357103285Sikob if( mode & FWXFERQ_STREAM ){ 2358103285Sikob db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2359103285Sikob if(mode & FWXFERQ_PACKET ){ 2360103285Sikob db[2].db.desc.cmd 2361103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2362103285Sikob } 2363103285Sikob } 2364103285Sikob db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2365103285Sikob return 1; 2366103285Sikob} 2367106790Ssimokawa 2368106790Ssimokawaint 2369106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2370106790Ssimokawa void *buf, void *dummy) 2371103285Sikob{ 2372103285Sikob volatile struct fwohcidb *db = db_tr->db; 2373103285Sikob int i; 2374103285Sikob void *dbuf[2]; 2375103285Sikob int dsiz[2]; 2376103285Sikob 2377103285Sikob if(buf == 0){ 2378103285Sikob buf = malloc(size, M_DEVBUF, M_NOWAIT); 2379103285Sikob if(buf == NULL) return 0; 2380103285Sikob db_tr->buf = buf; 2381103285Sikob db_tr->dbcnt = 1; 2382103285Sikob db_tr->dummy = NULL; 2383103285Sikob dsiz[0] = size; 2384103285Sikob dbuf[0] = buf; 2385103285Sikob }else if(dummy == NULL){ 2386103285Sikob db_tr->buf = buf; 2387103285Sikob db_tr->dbcnt = 1; 2388103285Sikob db_tr->dummy = NULL; 2389103285Sikob dsiz[0] = size; 2390103285Sikob dbuf[0] = buf; 2391103285Sikob }else{ 2392103285Sikob db_tr->buf = buf; 2393103285Sikob db_tr->dbcnt = 2; 2394103285Sikob db_tr->dummy = dummy; 2395103285Sikob dsiz[0] = sizeof(u_int32_t); 2396103285Sikob dsiz[1] = size; 2397103285Sikob dbuf[0] = dummy; 2398103285Sikob dbuf[1] = buf; 2399103285Sikob } 2400103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2401103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2402103285Sikob db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2403103285Sikob if( mode & FWXFERQ_STREAM ){ 2404103285Sikob db[i].db.desc.cmd |= OHCI_UPDATE; 2405103285Sikob } 2406103285Sikob db[i].db.desc.status = 0; 2407103285Sikob db[i].db.desc.count = dsiz[i]; 2408103285Sikob } 2409103285Sikob if( mode & FWXFERQ_STREAM ){ 2410103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2411103285Sikob if(mode & FWXFERQ_PACKET ){ 2412103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd 2413103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2414103285Sikob } 2415103285Sikob } 2416103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2417103285Sikob return 1; 2418103285Sikob} 2419106790Ssimokawa 2420106790Ssimokawastatic void 2421106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2422103285Sikob{ 2423103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2424103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2425103285Sikob int z = 1; 2426103285Sikob struct fw_pkt *fp; 2427103285Sikob u_int8_t *ld; 2428103285Sikob u_int32_t off = NULL; 2429103285Sikob u_int32_t stat; 2430103285Sikob u_int32_t *qld; 2431103285Sikob u_int32_t reg; 2432103285Sikob u_int spd; 2433103285Sikob u_int dmach; 2434103285Sikob int len, i, plen; 2435103285Sikob caddr_t buf; 2436103285Sikob 2437103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2438103285Sikob if( &sc->ir[dmach] == dbch){ 2439103285Sikob off = OHCI_IROFF(dmach); 2440103285Sikob break; 2441103285Sikob } 2442103285Sikob } 2443103285Sikob if(off == NULL){ 2444103285Sikob return; 2445103285Sikob } 2446103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2447103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2448103285Sikob return; 2449103285Sikob } 2450103285Sikob 2451103285Sikob odb_tr = NULL; 2452103285Sikob db_tr = dbch->top; 2453103285Sikob i = 0; 2454103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2455106789Ssimokawa if (count >= 0 && count-- == 0) 2456106789Ssimokawa break; 2457103285Sikob ld = (u_int8_t *)db_tr->buf; 2458103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2459103285Sikob /* skip timeStamp */ 2460103285Sikob ld += sizeof(struct fwohci_trailer); 2461103285Sikob } 2462103285Sikob qld = (u_int32_t *)ld; 2463103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2464103285Sikob/* 2465103285Sikob{ 2466103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2467103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2468103285Sikob} 2469103285Sikob*/ 2470103285Sikob fp=(struct fw_pkt *)ld; 2471103285Sikob qld[0] = htonl(qld[0]); 2472103285Sikob plen = sizeof(struct fw_isohdr) 2473103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2474103285Sikob ld += plen; 2475103285Sikob len -= plen; 2476103285Sikob buf = db_tr->buf; 2477103285Sikob db_tr->buf = NULL; 2478103285Sikob stat = reg & 0x1f; 2479103285Sikob spd = reg & 0x3; 2480103285Sikob switch(stat){ 2481103285Sikob case FWOHCIEV_ACKCOMPL: 2482103285Sikob case FWOHCIEV_ACKPEND: 2483103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2484103285Sikob break; 2485103285Sikob default: 2486103285Sikob free(buf, M_DEVBUF); 2487103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2488103285Sikob break; 2489103285Sikob } 2490103285Sikob i++; 2491103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2492103285Sikob dbch->xferq.flag, 0, NULL); 2493103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2494103285Sikob if(dbch->pdb_tr != NULL){ 2495103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2496103285Sikob } else { 2497103285Sikob /* XXX should be rewritten in better way */ 2498103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2499103285Sikob } 2500103285Sikob dbch->pdb_tr = db_tr; 2501103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2502103285Sikob } 2503103285Sikob dbch->top = db_tr; 2504103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2505103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2506103285Sikob return; 2507103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2508103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2509103285Sikob dbch->top = db_tr; 2510103285Sikob fwohci_irx_enable(fc, dmach); 2511103285Sikob} 2512103285Sikob 2513103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2514103285Sikobstatic int 2515103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2516103285Sikob{ 2517103285Sikob int i; 2518103285Sikob 2519103285Sikob for( i = 4; i < hlen ; i+=4){ 2520103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2521103285Sikob } 2522103285Sikob 2523103285Sikob switch(fp->mode.common.tcode){ 2524103285Sikob case FWTCODE_RREQQ: 2525103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2526103285Sikob case FWTCODE_WRES: 2527103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2528103285Sikob case FWTCODE_WREQQ: 2529103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2530103285Sikob case FWTCODE_RREQB: 2531103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2532103285Sikob case FWTCODE_RRESQ: 2533103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2534103285Sikob case FWTCODE_WREQB: 2535103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2536103285Sikob + sizeof(u_int32_t); 2537103285Sikob case FWTCODE_LREQ: 2538103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2539103285Sikob + sizeof(u_int32_t); 2540103285Sikob case FWTCODE_RRESB: 2541103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2542103285Sikob + sizeof(u_int32_t); 2543103285Sikob case FWTCODE_LRES: 2544103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2545103285Sikob + sizeof(u_int32_t); 2546103285Sikob case FWOHCITCODE_PHY: 2547103285Sikob return 16; 2548103285Sikob } 2549103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2550103285Sikob return 0; 2551103285Sikob} 2552103285Sikob 2553106790Ssimokawastatic void 2554106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2555103285Sikob{ 2556103285Sikob struct fwohcidb_tr *db_tr; 2557103285Sikob int z = 1; 2558103285Sikob struct fw_pkt *fp; 2559103285Sikob u_int8_t *ld; 2560103285Sikob u_int32_t stat, off; 2561103285Sikob u_int spd; 2562103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2563103285Sikob int s; 2564103285Sikob caddr_t buf; 2565103285Sikob int resCount; 2566103285Sikob 2567103285Sikob if(&sc->arrq == dbch){ 2568103285Sikob off = OHCI_ARQOFF; 2569103285Sikob }else if(&sc->arrs == dbch){ 2570103285Sikob off = OHCI_ARSOFF; 2571103285Sikob }else{ 2572103285Sikob return; 2573103285Sikob } 2574103285Sikob 2575103285Sikob s = splfw(); 2576103285Sikob db_tr = dbch->top; 2577103285Sikob pcnt = 0; 2578103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2579103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2580103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2581103285Sikob resCount = db_tr->db[0].db.desc.count; 2582103285Sikob len = dbch->xferq.psize - resCount 2583103285Sikob - dbch->buf_offset; 2584103285Sikob while (len > 0 ) { 2585106789Ssimokawa if (count >= 0 && count-- == 0) 2586106789Ssimokawa goto out; 2587103285Sikob if(dbch->frag.buf != NULL){ 2588103285Sikob buf = dbch->frag.buf; 2589103285Sikob if (dbch->frag.plen < 0) { 2590103285Sikob /* incomplete header */ 2591103285Sikob int hlen; 2592103285Sikob 2593103285Sikob hlen = - dbch->frag.plen; 2594103285Sikob rlen = hlen - dbch->frag.len; 2595103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2596103285Sikob ld += rlen; 2597103285Sikob len -= rlen; 2598103285Sikob dbch->frag.len += rlen; 2599103285Sikob#if 0 2600103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2601103285Sikob#endif 2602103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2603103285Sikob dbch->frag.plen 2604103285Sikob = fwohci_get_plen(sc, fp, hlen); 2605103285Sikob if (dbch->frag.plen == 0) 2606103285Sikob goto out; 2607103285Sikob } 2608103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2609103285Sikob#if 0 2610103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2611103285Sikob#endif 2612103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2613103285Sikob rlen); 2614103285Sikob ld += rlen; 2615103285Sikob len -= rlen; 2616103285Sikob plen = dbch->frag.plen; 2617103285Sikob dbch->frag.buf = NULL; 2618103285Sikob dbch->frag.plen = 0; 2619103285Sikob dbch->frag.len = 0; 2620103285Sikob poff = 0; 2621103285Sikob }else{ 2622103285Sikob fp=(struct fw_pkt *)ld; 2623103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2624103285Sikob switch(fp->mode.common.tcode){ 2625103285Sikob case FWTCODE_RREQQ: 2626103285Sikob case FWTCODE_WRES: 2627103285Sikob case FWTCODE_WREQQ: 2628103285Sikob case FWTCODE_RRESQ: 2629103285Sikob case FWOHCITCODE_PHY: 2630103285Sikob hlen = 12; 2631103285Sikob break; 2632103285Sikob case FWTCODE_RREQB: 2633103285Sikob case FWTCODE_WREQB: 2634103285Sikob case FWTCODE_LREQ: 2635103285Sikob case FWTCODE_RRESB: 2636103285Sikob case FWTCODE_LRES: 2637103285Sikob hlen = 16; 2638103285Sikob break; 2639103285Sikob default: 2640103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2641103285Sikob goto out; 2642103285Sikob } 2643103285Sikob if (len >= hlen) { 2644103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2645103285Sikob if (plen == 0) 2646103285Sikob goto out; 2647103285Sikob plen = (plen + 3) & ~3; 2648103285Sikob len -= plen; 2649103285Sikob } else { 2650103285Sikob plen = -hlen; 2651103285Sikob len -= hlen; 2652103285Sikob } 2653103285Sikob if(resCount > 0 || len > 0){ 2654103285Sikob buf = malloc( dbch->xferq.psize, 2655103285Sikob M_DEVBUF, M_NOWAIT); 2656103285Sikob if(buf == NULL){ 2657103285Sikob printf("cannot malloc!\n"); 2658103285Sikob free(db_tr->buf, M_DEVBUF); 2659103285Sikob goto out; 2660103285Sikob } 2661103285Sikob bcopy(ld, buf, plen); 2662103285Sikob poff = 0; 2663103285Sikob dbch->frag.buf = NULL; 2664103285Sikob dbch->frag.plen = 0; 2665103285Sikob dbch->frag.len = 0; 2666103285Sikob }else if(len < 0){ 2667103285Sikob dbch->frag.buf = db_tr->buf; 2668103285Sikob if (plen < 0) { 2669103285Sikob#if 0 2670103285Sikob printf("plen < 0:" 2671103285Sikob "hlen: %d len: %d\n", 2672103285Sikob hlen, len); 2673103285Sikob#endif 2674103285Sikob dbch->frag.len = hlen + len; 2675103285Sikob dbch->frag.plen = -hlen; 2676103285Sikob } else { 2677103285Sikob dbch->frag.len = plen + len; 2678103285Sikob dbch->frag.plen = plen; 2679103285Sikob } 2680103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2681103285Sikob buf = NULL; 2682103285Sikob }else{ 2683103285Sikob buf = db_tr->buf; 2684103285Sikob poff = ld - (u_int8_t *)buf; 2685103285Sikob dbch->frag.buf = NULL; 2686103285Sikob dbch->frag.plen = 0; 2687103285Sikob dbch->frag.len = 0; 2688103285Sikob } 2689103285Sikob ld += plen; 2690103285Sikob } 2691103285Sikob if( buf != NULL){ 2692103285Sikob/* DMA result-code will be written at the tail of packet */ 2693103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2694103285Sikob spd = (stat >> 5) & 0x3; 2695103285Sikob stat &= 0x1f; 2696103285Sikob switch(stat){ 2697103285Sikob case FWOHCIEV_ACKPEND: 2698103285Sikob#if 0 2699103285Sikob printf("fwohci_arcv: ack pending..\n"); 2700103285Sikob#endif 2701103285Sikob /* fall through */ 2702103285Sikob case FWOHCIEV_ACKCOMPL: 2703103285Sikob if( poff != 0 ) 2704103285Sikob bcopy(buf+poff, buf, plen - 4); 2705103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2706103285Sikob break; 2707103285Sikob case FWOHCIEV_BUSRST: 2708103285Sikob free(buf, M_DEVBUF); 2709103285Sikob if (sc->fc.status != FWBUSRESET) 2710103285Sikob printf("got BUSRST packet!?\n"); 2711103285Sikob break; 2712103285Sikob default: 2713103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2714103285Sikob#if 0 /* XXX */ 2715103285Sikob goto out; 2716103285Sikob#endif 2717103285Sikob break; 2718103285Sikob } 2719103285Sikob } 2720103285Sikob pcnt ++; 2721103285Sikob }; 2722103285Sikobout: 2723103285Sikob if (resCount == 0) { 2724103285Sikob /* done on this buffer */ 2725103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2726103285Sikob dbch->xferq.flag, 0, NULL); 2727103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2728103285Sikob dbch->bottom = db_tr; 2729103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2730103285Sikob dbch->top = db_tr; 2731103285Sikob dbch->buf_offset = 0; 2732103285Sikob } else { 2733103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2734103285Sikob break; 2735103285Sikob } 2736103285Sikob /* XXX make sure DMA is not dead */ 2737103285Sikob } 2738103285Sikob#if 0 2739103285Sikob if (pcnt < 1) 2740103285Sikob printf("fwohci_arcv: no packets\n"); 2741103285Sikob#endif 2742103285Sikob splx(s); 2743103285Sikob} 2744