fwohci.c revision 109356
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 109356 2003-01-16 07:01:54Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45103285Sikob#include <sys/systm.h> 46103285Sikob#include <sys/types.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/mman.h> 49103285Sikob#include <sys/socket.h> 50103285Sikob#include <sys/socketvar.h> 51103285Sikob#include <sys/signalvar.h> 52103285Sikob#include <sys/malloc.h> 53103285Sikob#include <sys/uio.h> 54103285Sikob#include <sys/sockio.h> 55103285Sikob#include <sys/bus.h> 56103285Sikob#include <sys/kernel.h> 57103285Sikob#include <sys/conf.h> 58103285Sikob 59103285Sikob#include <machine/bus.h> 60103285Sikob#include <machine/resource.h> 61103285Sikob#include <sys/rman.h> 62103285Sikob 63103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64103285Sikob#include <machine/clock.h> 65103285Sikob#include <pci/pcivar.h> 66103285Sikob#include <pci/pcireg.h> 67103285Sikob#include <vm/vm.h> 68103285Sikob#include <vm/vm_extern.h> 69103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 70103285Sikob 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirereg.h> 73103285Sikob#include <dev/firewire/fwohcireg.h> 74103285Sikob#include <dev/firewire/fwohcivar.h> 75103285Sikob#include <dev/firewire/firewire_phy.h> 76103285Sikob 77109179Ssimokawa#include <dev/firewire/iec68113.h> 78109179Ssimokawa 79103285Sikob#undef OHCI_DEBUG 80106802Ssimokawa 81103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 82103285Sikob "STOR","LOAD","NOP ","STOP",}; 83103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 84103285Sikob "UNDEF","REG","SYS","DEV"}; 85103285Sikobchar fwohcicode[32][0x20]={ 86103285Sikob "No stat","Undef","long","miss Ack err", 87103285Sikob "underrun","overrun","desc err", "data read err", 88103285Sikob "data write err","bus reset","timeout","tcode err", 89103285Sikob "Undef","Undef","unknown event","flushed", 90103285Sikob "Undef","ack complete","ack pend","Undef", 91103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 92103285Sikob "Undef","Undef","Undef","ack tardy", 93103285Sikob "Undef","ack data_err","ack type_err",""}; 94103285Sikob#define MAX_SPEED 2 95103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 96103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 126103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 127103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 128106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 132103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 142103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 145103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 148103285Sikobstatic void fwohci_timeout __P((void *)); 149103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 150103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 151103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 154103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160103285Sikob 161103285Sikob/* 162103285Sikob * memory allocated for DMA programs 163103285Sikob */ 164103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165103285Sikob 166103285Sikob/* #define NDB 1024 */ 167103285Sikob#define NDB FWMAXQUEUE 168103285Sikob#define NDVDB (DVBUF * NDB) 169103285Sikob 170103285Sikob#define OHCI_VERSION 0x00 171103285Sikob#define OHCI_CROMHDR 0x18 172103285Sikob#define OHCI_BUS_OPT 0x20 173103285Sikob#define OHCI_BUSIRMC (1 << 31) 174103285Sikob#define OHCI_BUSCMC (1 << 30) 175103285Sikob#define OHCI_BUSISC (1 << 29) 176103285Sikob#define OHCI_BUSBMC (1 << 28) 177103285Sikob#define OHCI_BUSPMC (1 << 27) 178103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 180103285Sikob 181103285Sikob#define OHCI_EUID_HI 0x24 182103285Sikob#define OHCI_EUID_LO 0x28 183103285Sikob 184103285Sikob#define OHCI_CROMPTR 0x34 185103285Sikob#define OHCI_HCCCTL 0x50 186103285Sikob#define OHCI_HCCCTLCLR 0x54 187103285Sikob#define OHCI_AREQHI 0x100 188103285Sikob#define OHCI_AREQHICLR 0x104 189103285Sikob#define OHCI_AREQLO 0x108 190103285Sikob#define OHCI_AREQLOCLR 0x10c 191103285Sikob#define OHCI_PREQHI 0x110 192103285Sikob#define OHCI_PREQHICLR 0x114 193103285Sikob#define OHCI_PREQLO 0x118 194103285Sikob#define OHCI_PREQLOCLR 0x11c 195103285Sikob#define OHCI_PREQUPPER 0x120 196103285Sikob 197103285Sikob#define OHCI_SID_BUF 0x64 198103285Sikob#define OHCI_SID_CNT 0x68 199103285Sikob#define OHCI_SID_CNT_MASK 0xffc 200103285Sikob 201103285Sikob#define OHCI_IT_STAT 0x90 202103285Sikob#define OHCI_IT_STATCLR 0x94 203103285Sikob#define OHCI_IT_MASK 0x98 204103285Sikob#define OHCI_IT_MASKCLR 0x9c 205103285Sikob 206103285Sikob#define OHCI_IR_STAT 0xa0 207103285Sikob#define OHCI_IR_STATCLR 0xa4 208103285Sikob#define OHCI_IR_MASK 0xa8 209103285Sikob#define OHCI_IR_MASKCLR 0xac 210103285Sikob 211103285Sikob#define OHCI_LNKCTL 0xe0 212103285Sikob#define OHCI_LNKCTLCLR 0xe4 213103285Sikob 214103285Sikob#define OHCI_PHYACCESS 0xec 215103285Sikob#define OHCI_CYCLETIMER 0xf0 216103285Sikob 217103285Sikob#define OHCI_DMACTL(off) (off) 218103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 219103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 220103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 221103285Sikob 222103285Sikob#define OHCI_ATQOFF 0x180 223103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 224103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227103285Sikob 228103285Sikob#define OHCI_ATSOFF 0x1a0 229103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 230103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233103285Sikob 234103285Sikob#define OHCI_ARQOFF 0x1c0 235103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 236103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239103285Sikob 240103285Sikob#define OHCI_ARSOFF 0x1e0 241103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 242103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245103285Sikob 246103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250103285Sikob 251103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256103285Sikob 257103285Sikobd_ioctl_t fwohci_ioctl; 258103285Sikob 259103285Sikob/* 260103285Sikob * Communication with PHY device 261103285Sikob */ 262106790Ssimokawastatic u_int32_t 263106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264103285Sikob{ 265103285Sikob u_int32_t fun; 266103285Sikob 267103285Sikob addr &= 0xf; 268103285Sikob data &= 0xff; 269103285Sikob 270103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 272103285Sikob DELAY(100); 273103285Sikob 274103285Sikob return(fwphy_rddata( sc, addr)); 275103285Sikob} 276103285Sikob 277103285Sikobstatic u_int32_t 278103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279103285Sikob{ 280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281103285Sikob int i; 282103285Sikob u_int32_t bm; 283103285Sikob 284103285Sikob#define OHCI_CSR_DATA 0x0c 285103285Sikob#define OHCI_CSR_COMP 0x10 286103285Sikob#define OHCI_CSR_CONT 0x14 287103285Sikob#define OHCI_BUS_MANAGER_ID 0 288103285Sikob 289103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 290103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293109280Ssimokawa DELAY(10); 294103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 295107653Ssimokawa if((bm & 0x3f) == 0x3f) 296103285Sikob bm = node; 297107653Ssimokawa if (bootverbose) 298107653Ssimokawa device_printf(sc->fc.dev, 299107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300103285Sikob 301103285Sikob return(bm); 302103285Sikob} 303103285Sikob 304106790Ssimokawastatic u_int32_t 305106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 306103285Sikob{ 307108500Ssimokawa u_int32_t fun, stat; 308108500Ssimokawa u_int i, retry = 0; 309103285Sikob 310103285Sikob addr &= 0xf; 311108500Ssimokawa#define MAX_RETRY 100 312108500Ssimokawaagain: 313108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 316108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 318103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319103285Sikob break; 320109280Ssimokawa DELAY(100); 321103285Sikob } 322108500Ssimokawa if(i >= MAX_RETRY) { 323109280Ssimokawa if (bootverbose) 324109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 325108527Ssimokawa if (++retry < MAX_RETRY) { 326109280Ssimokawa DELAY(100); 327108527Ssimokawa goto again; 328108527Ssimokawa } 329108500Ssimokawa } 330108500Ssimokawa /* Make sure that SCLK is started */ 331108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 332108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 333108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 334109280Ssimokawa if (bootverbose) 335109280Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 336108500Ssimokawa if (++retry < MAX_RETRY) { 337109280Ssimokawa DELAY(100); 338108500Ssimokawa goto again; 339108500Ssimokawa } 340108500Ssimokawa } 341108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 342108500Ssimokawa device_printf(sc->fc.dev, 343108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 344108500Ssimokawa#undef MAX_RETRY 345103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 346103285Sikob} 347103285Sikob/* Device specific ioctl. */ 348103285Sikobint 349103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 350103285Sikob{ 351103285Sikob struct firewire_softc *sc; 352103285Sikob struct fwohci_softc *fc; 353103285Sikob int unit = DEV2UNIT(dev); 354103285Sikob int err = 0; 355103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 356103285Sikob u_int32_t *dmach = (u_int32_t *) data; 357103285Sikob 358103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 359103285Sikob if(sc == NULL){ 360103285Sikob return(EINVAL); 361103285Sikob } 362103285Sikob fc = (struct fwohci_softc *)sc->fc; 363103285Sikob 364103285Sikob if (!data) 365103285Sikob return(EINVAL); 366103285Sikob 367103285Sikob switch (cmd) { 368103285Sikob case FWOHCI_WRREG: 369103285Sikob#define OHCI_MAX_REG 0x800 370103285Sikob if(reg->addr <= OHCI_MAX_REG){ 371103285Sikob OWRITE(fc, reg->addr, reg->data); 372103285Sikob reg->data = OREAD(fc, reg->addr); 373103285Sikob }else{ 374103285Sikob err = EINVAL; 375103285Sikob } 376103285Sikob break; 377103285Sikob case FWOHCI_RDREG: 378103285Sikob if(reg->addr <= OHCI_MAX_REG){ 379103285Sikob reg->data = OREAD(fc, reg->addr); 380103285Sikob }else{ 381103285Sikob err = EINVAL; 382103285Sikob } 383103285Sikob break; 384103285Sikob/* Read DMA descriptors for debug */ 385103285Sikob case DUMPDMA: 386103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 387103285Sikob dump_dma(fc, *dmach); 388103285Sikob dump_db(fc, *dmach); 389103285Sikob }else{ 390103285Sikob err = EINVAL; 391103285Sikob } 392103285Sikob break; 393103285Sikob default: 394103285Sikob break; 395103285Sikob } 396103285Sikob return err; 397103285Sikob} 398106790Ssimokawa 399108530Ssimokawastatic int 400108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 401103285Sikob{ 402108530Ssimokawa u_int32_t reg, reg2; 403108530Ssimokawa int e1394a = 1; 404108530Ssimokawa/* 405108530Ssimokawa * probe PHY parameters 406108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 407108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 408108530Ssimokawa * number of port supported by core-logic. 409108530Ssimokawa * It is not actually available port on your PC . 410108530Ssimokawa */ 411108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 412108530Ssimokawa#if 0 413108530Ssimokawa /* XXX wait for SCLK. */ 414108530Ssimokawa DELAY(100000); 415108530Ssimokawa#endif 416108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 417108530Ssimokawa 418108530Ssimokawa if((reg >> 5) != 7 ){ 419108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 420108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 421108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 422108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 423108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 424108530Ssimokawa sc->fc.speed, MAX_SPEED); 425108530Ssimokawa sc->fc.speed = MAX_SPEED; 426108530Ssimokawa } 427108530Ssimokawa device_printf(dev, 428108701Ssimokawa "Phy 1394 only %s, %d ports.\n", 429108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 430108530Ssimokawa }else{ 431108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 432108530Ssimokawa sc->fc.mode |= FWPHYASYST; 433108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 434108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 435108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 436108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 437108530Ssimokawa sc->fc.speed, MAX_SPEED); 438108530Ssimokawa sc->fc.speed = MAX_SPEED; 439108530Ssimokawa } 440108530Ssimokawa device_printf(dev, 441108701Ssimokawa "Phy 1394a available %s, %d ports.\n", 442108701Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport); 443108530Ssimokawa 444108530Ssimokawa /* check programPhyEnable */ 445108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 446108530Ssimokawa#if 0 447108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 448108530Ssimokawa#else /* XXX force to enable 1394a */ 449108530Ssimokawa if (e1394a) { 450108530Ssimokawa#endif 451108530Ssimokawa if (bootverbose) 452108530Ssimokawa device_printf(dev, 453108530Ssimokawa "Enable 1394a Enhancements\n"); 454108530Ssimokawa /* enable EAA EMC */ 455108530Ssimokawa reg2 |= 0x03; 456108530Ssimokawa /* set aPhyEnhanceEnable */ 457108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 458108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 459108530Ssimokawa } else { 460108530Ssimokawa /* for safe */ 461108530Ssimokawa reg2 &= ~0x83; 462108530Ssimokawa } 463108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 464108530Ssimokawa } 465108530Ssimokawa 466108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 467108530Ssimokawa if((reg >> 5) == 7 ){ 468108530Ssimokawa reg = fwphy_rddata(sc, 4); 469108530Ssimokawa reg |= 1 << 6; 470108530Ssimokawa fwphy_wrdata(sc, 4, reg); 471108530Ssimokawa reg = fwphy_rddata(sc, 4); 472108530Ssimokawa } 473108530Ssimokawa return 0; 474108530Ssimokawa} 475108530Ssimokawa 476108530Ssimokawa 477108530Ssimokawavoid 478108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 479108530Ssimokawa{ 480108701Ssimokawa int i, max_rec, speed; 481103285Sikob u_int32_t reg, reg2; 482103285Sikob struct fwohcidb_tr *db_tr; 483103285Sikob 484108701Ssimokawa /* Disable interrupt */ 485108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 486108530Ssimokawa 487108701Ssimokawa /* Now stopping all DMA channel */ 488108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 489108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 490108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 491108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa 493108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 494108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 495108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 496108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 497108530Ssimokawa } 498108530Ssimokawa 499108701Ssimokawa /* FLUSH FIFO and reset Transmitter/Reciever */ 500108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 501108530Ssimokawa if (bootverbose) 502108530Ssimokawa device_printf(dev, "resetting OHCI..."); 503108530Ssimokawa i = 0; 504108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 505108530Ssimokawa if (i++ > 100) break; 506108530Ssimokawa DELAY(1000); 507108530Ssimokawa } 508108530Ssimokawa if (bootverbose) 509108530Ssimokawa printf("done (loop=%d)\n", i); 510108530Ssimokawa 511108701Ssimokawa /* Probe phy */ 512108701Ssimokawa fwohci_probe_phy(sc, dev); 513108701Ssimokawa 514108701Ssimokawa /* Probe link */ 515108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 516108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 517108701Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 518108701Ssimokawa speed = (reg & 0x00000007); 519108701Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 520108701Ssimokawa linkspeed[speed], MAXREC(max_rec)); 521108701Ssimokawa /* XXX fix max_rec */ 522108701Ssimokawa sc->fc.maxrec = sc->fc.speed + 8; 523108701Ssimokawa if (max_rec != sc->fc.maxrec) { 524108701Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); 525108701Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 526108701Ssimokawa MAXREC(max_rec), MAXREC(sc->fc.maxrec)); 527108701Ssimokawa } 528108530Ssimokawa if (bootverbose) 529108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 530108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 531108530Ssimokawa 532108701Ssimokawa /* Initialize registers */ 533108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 534108530Ssimokawa OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 535108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 536108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 537108642Ssimokawa OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 538108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 539108701Ssimokawa fw_busreset(&sc->fc); 540108530Ssimokawa 541108701Ssimokawa /* Enable link */ 542108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 543108642Ssimokawa 544108701Ssimokawa /* Force to start async RX DMA */ 545108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 546108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 547108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 548108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 549108530Ssimokawa 550108701Ssimokawa /* Initialize async TX */ 551108701Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 552108701Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 553108701Ssimokawa /* AT Retries */ 554108701Ssimokawa OWRITE(sc, FWOHCI_RETRY, 555108701Ssimokawa /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ 556108701Ssimokawa (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; 557108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 558108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 559108530Ssimokawa db_tr->xfer = NULL; 560108530Ssimokawa } 561108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 562108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 563108530Ssimokawa db_tr->xfer = NULL; 564108530Ssimokawa } 565108530Ssimokawa 566108701Ssimokawa 567108701Ssimokawa /* Enable interrupt */ 568108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 569108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 570108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 571108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 572108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 573108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 574108530Ssimokawa 575108530Ssimokawa} 576108530Ssimokawa 577108530Ssimokawaint 578108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 579108530Ssimokawa{ 580108530Ssimokawa int i; 581108530Ssimokawa u_int32_t reg; 582108530Ssimokawa 583103285Sikob reg = OREAD(sc, OHCI_VERSION); 584103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 585103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 586103285Sikob 587103285Sikob/* XXX: Available Isochrounous DMA channel probe */ 588103285Sikob for( i = 0 ; i < 0x20 ; i ++ ){ 589103285Sikob OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 590103285Sikob reg = OREAD(sc, OHCI_IRCTL(i)); 591103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 592103285Sikob OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 593103285Sikob reg = OREAD(sc, OHCI_ITCTL(i)); 594103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 595103285Sikob } 596103285Sikob sc->fc.nisodma = i; 597103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 598103285Sikob 599103285Sikob sc->fc.arq = &sc->arrq.xferq; 600103285Sikob sc->fc.ars = &sc->arrs.xferq; 601103285Sikob sc->fc.atq = &sc->atrq.xferq; 602103285Sikob sc->fc.ats = &sc->atrs.xferq; 603103285Sikob 604103285Sikob sc->arrq.xferq.start = NULL; 605103285Sikob sc->arrs.xferq.start = NULL; 606103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 607103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 608103285Sikob 609103285Sikob sc->arrq.xferq.drain = NULL; 610103285Sikob sc->arrs.xferq.drain = NULL; 611103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 612103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 613103285Sikob 614103285Sikob sc->arrq.ndesc = 1; 615103285Sikob sc->arrs.ndesc = 1; 616108655Ssimokawa sc->atrq.ndesc = 6; /* equal to maximum of mbuf chains */ 617108655Ssimokawa sc->atrs.ndesc = 6 / 2; 618103285Sikob 619103285Sikob sc->arrq.ndb = NDB; 620103285Sikob sc->arrs.ndb = NDB / 2; 621103285Sikob sc->atrq.ndb = NDB; 622103285Sikob sc->atrs.ndb = NDB / 2; 623103285Sikob 624103285Sikob sc->arrq.dummy = NULL; 625103285Sikob sc->arrs.dummy = NULL; 626103285Sikob sc->atrq.dummy = NULL; 627103285Sikob sc->atrs.dummy = NULL; 628103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 629103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 630103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 631103285Sikob sc->it[i].ndb = 0; 632103285Sikob sc->ir[i].ndb = 0; 633103285Sikob } 634103285Sikob 635103285Sikob sc->fc.tcode = tinfo; 636103285Sikob 637103285Sikob sc->cromptr = (u_int32_t *) 638103285Sikob contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 639103285Sikob 640103285Sikob if(sc->cromptr == NULL){ 641108527Ssimokawa device_printf(dev, "cromptr alloc failed."); 642103285Sikob return ENOMEM; 643103285Sikob } 644103285Sikob sc->fc.dev = dev; 645103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 646103285Sikob 647103285Sikob sc->fc.config_rom[1] = 0x31333934; 648103285Sikob sc->fc.config_rom[2] = 0xf000a002; 649103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 650103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 651103285Sikob sc->fc.config_rom[5] = 0; 652103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 653103285Sikob 654103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 655103285Sikob 656103285Sikob 657103285Sikob/* SID recieve buffer must allign 2^11 */ 658103285Sikob#define OHCI_SIDSIZE (1 << 11) 659103285Sikob sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 660103285Sikob 0x10000, 0xffffffff, OHCI_SIDSIZE); 661108527Ssimokawa if (sc->fc.sid_buf == NULL) { 662108527Ssimokawa device_printf(dev, "sid_buf alloc failed.\n"); 663108527Ssimokawa return ENOMEM; 664108527Ssimokawa } 665108527Ssimokawa 666108530Ssimokawa 667103285Sikob fwohci_db_init(&sc->arrq); 668108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 669108527Ssimokawa return ENOMEM; 670108527Ssimokawa 671103285Sikob fwohci_db_init(&sc->arrs); 672108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 673108527Ssimokawa return ENOMEM; 674103285Sikob 675103285Sikob fwohci_db_init(&sc->atrq); 676108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 677108527Ssimokawa return ENOMEM; 678108527Ssimokawa 679103285Sikob fwohci_db_init(&sc->atrs); 680108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 681108527Ssimokawa return ENOMEM; 682103285Sikob 683103285Sikob reg = OREAD(sc, FWOHCIGUID_H); 684103285Sikob for( i = 0 ; i < 4 ; i ++){ 685103285Sikob sc->fc.eui[3 - i] = reg & 0xff; 686103285Sikob reg = reg >> 8; 687103285Sikob } 688103285Sikob reg = OREAD(sc, FWOHCIGUID_L); 689103285Sikob for( i = 0 ; i < 4 ; i ++){ 690103285Sikob sc->fc.eui[7 - i] = reg & 0xff; 691103285Sikob reg = reg >> 8; 692103285Sikob } 693103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 694103285Sikob sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 695103285Sikob sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 696103285Sikob sc->fc.ioctl = fwohci_ioctl; 697103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 698103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 699103285Sikob sc->fc.ibr = fwohci_ibr; 700103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 701103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 702103285Sikob 703103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 704103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 705103285Sikob sc->fc.irx_post = fwohci_irx_post; 706103285Sikob sc->fc.itx_post = NULL; 707103285Sikob sc->fc.timeout = fwohci_timeout; 708103285Sikob sc->fc.poll = fwohci_poll; 709103285Sikob sc->fc.set_intr = fwohci_set_intr; 710106790Ssimokawa 711108530Ssimokawa fw_init(&sc->fc); 712108530Ssimokawa fwohci_reset(sc, dev); 713103285Sikob 714108530Ssimokawa return 0; 715103285Sikob} 716106790Ssimokawa 717106790Ssimokawavoid 718106790Ssimokawafwohci_timeout(void *arg) 719103285Sikob{ 720103285Sikob struct fwohci_softc *sc; 721103285Sikob 722103285Sikob sc = (struct fwohci_softc *)arg; 723103285Sikob sc->fc.timeouthandle = timeout(fwohci_timeout, 724103285Sikob (void *)sc, FW_XFERTIMEOUT * hz * 10); 725103285Sikob} 726106790Ssimokawa 727106790Ssimokawau_int32_t 728106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 729103285Sikob{ 730103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 731103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 732103285Sikob} 733103285Sikob 734108527Ssimokawaint 735108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 736108527Ssimokawa{ 737108527Ssimokawa int i; 738108527Ssimokawa 739108527Ssimokawa if (sc->fc.sid_buf != NULL) 740108527Ssimokawa contigfree((void *)(uintptr_t)sc->fc.sid_buf, 741108527Ssimokawa OHCI_SIDSIZE, M_DEVBUF); 742108527Ssimokawa if (sc->cromptr != NULL) 743108527Ssimokawa contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF); 744108527Ssimokawa 745108527Ssimokawa fwohci_db_free(&sc->arrq); 746108527Ssimokawa fwohci_db_free(&sc->arrs); 747108527Ssimokawa 748108527Ssimokawa fwohci_db_free(&sc->atrq); 749108527Ssimokawa fwohci_db_free(&sc->atrs); 750108527Ssimokawa 751108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 752108527Ssimokawa fwohci_db_free(&sc->it[i]); 753108527Ssimokawa fwohci_db_free(&sc->ir[i]); 754108527Ssimokawa } 755108527Ssimokawa 756108527Ssimokawa return 0; 757108527Ssimokawa} 758108527Ssimokawa 759108655Ssimokawa#define LAST_DB(dbtr, db) do { \ 760108655Ssimokawa struct fwohcidb_tr *_dbtr = (dbtr); \ 761108655Ssimokawa int _cnt = _dbtr->dbcnt; \ 762108655Ssimokawa db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 763108655Ssimokawa} while (0) 764108655Ssimokawa 765106790Ssimokawastatic void 766106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 767103285Sikob{ 768103285Sikob int i, s; 769103285Sikob int tcode, hdr_len, hdr_off, len; 770103285Sikob int fsegment = -1; 771103285Sikob u_int32_t off; 772103285Sikob struct fw_xfer *xfer; 773103285Sikob struct fw_pkt *fp; 774103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 775103285Sikob struct fwohcidb_tr *db_tr; 776103285Sikob volatile struct fwohcidb *db; 777103285Sikob struct mbuf *m; 778103285Sikob struct tcode_info *info; 779108655Ssimokawa static int maxdesc=0; 780103285Sikob 781103285Sikob if(&sc->atrq == dbch){ 782103285Sikob off = OHCI_ATQOFF; 783103285Sikob }else if(&sc->atrs == dbch){ 784103285Sikob off = OHCI_ATSOFF; 785103285Sikob }else{ 786103285Sikob return; 787103285Sikob } 788103285Sikob 789103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 790103285Sikob return; 791103285Sikob 792103285Sikob s = splfw(); 793103285Sikob db_tr = dbch->top; 794103285Sikobtxloop: 795103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 796103285Sikob if(xfer == NULL){ 797103285Sikob goto kick; 798103285Sikob } 799103285Sikob if(dbch->xferq.queued == 0 ){ 800103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 801103285Sikob } 802103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 803103285Sikob db_tr->xfer = xfer; 804103285Sikob xfer->state = FWXF_START; 805103285Sikob dbch->xferq.packets++; 806103285Sikob 807103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 808103285Sikob tcode = fp->mode.common.tcode; 809103285Sikob 810103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 811103285Sikob info = &tinfo[tcode]; 812103285Sikob hdr_len = hdr_off = info->hdr_len; 813103285Sikob /* fw_asyreq must pass valid send.len */ 814103285Sikob len = xfer->send.len; 815103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 816103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 817103285Sikob } 818103285Sikob ohcifp->mode.common.spd = xfer->spd; 819103285Sikob if (tcode == FWTCODE_STREAM ){ 820103285Sikob hdr_len = 8; 821103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 822103285Sikob } else if (tcode == FWTCODE_PHY) { 823103285Sikob hdr_len = 12; 824103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 825103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 826103285Sikob ohcifp->mode.common.spd = 0; 827103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 828103285Sikob } else { 829103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 830103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 831103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 832103285Sikob } 833103285Sikob db = &db_tr->db[0]; 834103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 835103285Sikob db->db.desc.status = 0; 836103285Sikob/* Specify bound timer of asy. responce */ 837103285Sikob if(&sc->atrs == dbch){ 838103285Sikob db->db.desc.count 839103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 840103285Sikob } 841103285Sikob 842103285Sikob db_tr->dbcnt = 2; 843103285Sikob db = &db_tr->db[db_tr->dbcnt]; 844103285Sikob if(len > hdr_off){ 845103285Sikob if (xfer->mbuf == NULL) { 846103285Sikob db->db.desc.addr 847103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 848103285Sikob db->db.desc.cmd 849103285Sikob = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 850103285Sikob db->db.desc.status = 0; 851103285Sikob 852103285Sikob db_tr->dbcnt++; 853103285Sikob } else { 854103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 855108655Ssimokawa for (m = xfer->mbuf; m != NULL; m = m->m_next) { 856108655Ssimokawa if (m->m_len == 0) 857108655Ssimokawa /* unrecoverable error could ocurre. */ 858108655Ssimokawa continue; 859108655Ssimokawa if (db_tr->dbcnt >= dbch->ndesc) { 860108655Ssimokawa device_printf(sc->fc.dev, 861108655Ssimokawa "dbch->ndesc is too small" 862108655Ssimokawa ", trancated.\n"); 863108655Ssimokawa break; 864108655Ssimokawa } 865103285Sikob db->db.desc.addr 866103285Sikob = vtophys(mtod(m, caddr_t)); 867103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 868103285Sikob db->db.desc.status = 0; 869103285Sikob db++; 870103285Sikob db_tr->dbcnt++; 871108655Ssimokawa } 872103285Sikob } 873103285Sikob } 874108655Ssimokawa if (maxdesc < db_tr->dbcnt) { 875108655Ssimokawa maxdesc = db_tr->dbcnt; 876108655Ssimokawa if (bootverbose) 877108655Ssimokawa device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); 878108655Ssimokawa } 879103285Sikob /* last db */ 880103285Sikob LAST_DB(db_tr, db); 881103285Sikob db->db.desc.cmd |= OHCI_OUTPUT_LAST 882103285Sikob | OHCI_INTERRUPT_ALWAYS 883103285Sikob | OHCI_BRANCH_ALWAYS; 884103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 885103285Sikob 886103285Sikob if(fsegment == -1 ) 887103285Sikob fsegment = db_tr->dbcnt; 888103285Sikob if (dbch->pdb_tr != NULL) { 889103285Sikob LAST_DB(dbch->pdb_tr, db); 890103285Sikob db->db.desc.depend |= db_tr->dbcnt; 891103285Sikob } 892103285Sikob dbch->pdb_tr = db_tr; 893103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 894103285Sikob if(db_tr != dbch->bottom){ 895103285Sikob goto txloop; 896103285Sikob } else { 897107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 898103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 899103285Sikob } 900103285Sikobkick: 901103285Sikob if (firewire_debug) printf("kick\n"); 902103285Sikob /* kick asy q */ 903103285Sikob 904103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 905103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 906103285Sikob } else { 907107653Ssimokawa if (bootverbose) 908107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 909103285Sikob OREAD(sc, OHCI_DMACTL(off))); 910103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 911103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 912103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 913103285Sikob } 914106790Ssimokawa 915103285Sikob dbch->top = db_tr; 916103285Sikob splx(s); 917103285Sikob return; 918103285Sikob} 919106790Ssimokawa 920106790Ssimokawastatic void 921106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 922103285Sikob{ 923103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 924103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 925103285Sikob return; 926103285Sikob} 927106790Ssimokawa 928106790Ssimokawastatic void 929106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 930103285Sikob{ 931103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 932103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 933103285Sikob return; 934103285Sikob} 935106790Ssimokawa 936106790Ssimokawastatic void 937106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 938103285Sikob{ 939103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 940103285Sikob fwohci_start( sc, &(sc->atrq)); 941103285Sikob return; 942103285Sikob} 943106790Ssimokawa 944106790Ssimokawastatic void 945106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 946103285Sikob{ 947103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 948103285Sikob fwohci_start( sc, &(sc->atrs)); 949103285Sikob return; 950103285Sikob} 951106790Ssimokawa 952106790Ssimokawavoid 953106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 954103285Sikob{ 955103285Sikob int s, err = 0; 956103285Sikob struct fwohcidb_tr *tr; 957103285Sikob volatile struct fwohcidb *db; 958103285Sikob struct fw_xfer *xfer; 959103285Sikob u_int32_t off; 960103285Sikob u_int stat; 961103285Sikob int packets; 962103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 963103285Sikob if(&sc->atrq == dbch){ 964103285Sikob off = OHCI_ATQOFF; 965103285Sikob }else if(&sc->atrs == dbch){ 966103285Sikob off = OHCI_ATSOFF; 967103285Sikob }else{ 968103285Sikob return; 969103285Sikob } 970103285Sikob s = splfw(); 971103285Sikob tr = dbch->bottom; 972103285Sikob packets = 0; 973103285Sikob while(dbch->xferq.queued > 0){ 974103285Sikob LAST_DB(tr, db); 975103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 976103285Sikob if (fc->status != FWBUSRESET) 977103285Sikob /* maybe out of order?? */ 978103285Sikob goto out; 979103285Sikob } 980103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 981103285Sikob#ifdef OHCI_DEBUG 982103285Sikob dump_dma(sc, ch); 983103285Sikob dump_db(sc, ch); 984103285Sikob#endif 985103285Sikob/* Stop DMA */ 986103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 987103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 988103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 989103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 990103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 991103285Sikob } 992103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 993103285Sikob switch(stat){ 994103285Sikob case FWOHCIEV_ACKCOMPL: 995103285Sikob case FWOHCIEV_ACKPEND: 996103285Sikob err = 0; 997103285Sikob break; 998103285Sikob case FWOHCIEV_ACKBSA: 999103285Sikob case FWOHCIEV_ACKBSB: 1000103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1001103285Sikob case FWOHCIEV_ACKBSX: 1002103285Sikob err = EBUSY; 1003103285Sikob break; 1004103285Sikob case FWOHCIEV_FLUSHED: 1005103285Sikob case FWOHCIEV_ACKTARD: 1006103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 1007103285Sikob err = EAGAIN; 1008103285Sikob break; 1009103285Sikob case FWOHCIEV_MISSACK: 1010103285Sikob case FWOHCIEV_UNDRRUN: 1011103285Sikob case FWOHCIEV_OVRRUN: 1012103285Sikob case FWOHCIEV_DESCERR: 1013103285Sikob case FWOHCIEV_DTRDERR: 1014103285Sikob case FWOHCIEV_TIMEOUT: 1015103285Sikob case FWOHCIEV_TCODERR: 1016103285Sikob case FWOHCIEV_UNKNOWN: 1017103285Sikob case FWOHCIEV_ACKDERR: 1018103285Sikob case FWOHCIEV_ACKTERR: 1019103285Sikob default: 1020103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 1021103285Sikob stat, fwohcicode[stat]); 1022103285Sikob err = EINVAL; 1023103285Sikob break; 1024103285Sikob } 1025103285Sikob if(tr->xfer != NULL){ 1026103285Sikob xfer = tr->xfer; 1027103285Sikob xfer->state = FWXF_SENT; 1028103285Sikob if(err == EBUSY && fc->status != FWBUSRESET){ 1029103285Sikob xfer->state = FWXF_BUSY; 1030103285Sikob switch(xfer->act_type){ 1031103285Sikob case FWACT_XFER: 1032103285Sikob xfer->resp = err; 1033103285Sikob if(xfer->retry_req != NULL){ 1034103285Sikob xfer->retry_req(xfer); 1035103285Sikob } 1036103285Sikob break; 1037103285Sikob default: 1038103285Sikob break; 1039103285Sikob } 1040103285Sikob } else if( stat != FWOHCIEV_ACKPEND){ 1041103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1042103285Sikob xfer->state = FWXF_SENTERR; 1043103285Sikob xfer->resp = err; 1044103285Sikob switch(xfer->act_type){ 1045103285Sikob case FWACT_XFER: 1046103285Sikob fw_xfer_done(xfer); 1047103285Sikob break; 1048103285Sikob default: 1049103285Sikob break; 1050103285Sikob } 1051103285Sikob } 1052103285Sikob dbch->xferq.queued --; 1053103285Sikob } 1054103285Sikob tr->xfer = NULL; 1055103285Sikob 1056103285Sikob packets ++; 1057103285Sikob tr = STAILQ_NEXT(tr, link); 1058103285Sikob dbch->bottom = tr; 1059103285Sikob } 1060103285Sikobout: 1061103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1062103285Sikob printf("make free slot\n"); 1063103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1064103285Sikob fwohci_start(sc, dbch); 1065103285Sikob } 1066103285Sikob splx(s); 1067103285Sikob} 1068106790Ssimokawa 1069106790Ssimokawastatic void 1070106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1071103285Sikob{ 1072103285Sikob int i, s; 1073103285Sikob struct fwohcidb_tr *tr; 1074103285Sikob 1075103285Sikob if(xfer->state != FWXF_START) return; 1076103285Sikob 1077103285Sikob s = splfw(); 1078103285Sikob tr = dbch->bottom; 1079103285Sikob for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1080103285Sikob if(tr->xfer == xfer){ 1081103285Sikob s = splfw(); 1082103285Sikob tr->xfer = NULL; 1083103285Sikob dbch->xferq.queued --; 1084103285Sikob#if 1 1085103285Sikob /* XXX */ 1086103285Sikob if (tr == dbch->bottom) 1087103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1088103285Sikob#endif 1089103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1090103285Sikob printf("fwohci_drain: make slot\n"); 1091103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1092103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1093103285Sikob } 1094103285Sikob 1095103285Sikob splx(s); 1096103285Sikob break; 1097103285Sikob } 1098103285Sikob tr = STAILQ_NEXT(tr, link); 1099103285Sikob } 1100103285Sikob splx(s); 1101103285Sikob return; 1102103285Sikob} 1103103285Sikob 1104106790Ssimokawastatic void 1105106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1106103285Sikob{ 1107103285Sikob struct fwohcidb_tr *db_tr; 1108103285Sikob int idb; 1109103285Sikob 1110108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1111108527Ssimokawa return; 1112108527Ssimokawa 1113103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1114103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1115103285Sikob idb < dbch->ndb; 1116103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1117108527Ssimokawa if (db_tr->buf != NULL) { 1118108527Ssimokawa free(db_tr->buf, M_DEVBUF); 1119108527Ssimokawa db_tr->buf = NULL; 1120108527Ssimokawa } 1121103285Sikob } 1122103285Sikob } 1123103285Sikob dbch->ndb = 0; 1124103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1125103285Sikob contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1126103285Sikob sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1127103285Sikob free(db_tr, M_DEVBUF); 1128103285Sikob STAILQ_INIT(&dbch->db_trq); 1129108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1130103285Sikob} 1131106790Ssimokawa 1132106790Ssimokawastatic void 1133106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1134103285Sikob{ 1135103285Sikob int idb; 1136103285Sikob struct fwohcidb *db; 1137103285Sikob struct fwohcidb_tr *db_tr; 1138108642Ssimokawa 1139108642Ssimokawa 1140108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1141108642Ssimokawa goto out; 1142108642Ssimokawa 1143103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1144103285Sikob /* DB entry must start at 16 bytes bounary. */ 1145103285Sikob STAILQ_INIT(&dbch->db_trq); 1146103285Sikob db_tr = (struct fwohcidb_tr *) 1147103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1148108527Ssimokawa M_DEVBUF, M_DONTWAIT | M_ZERO); 1149103285Sikob if(db_tr == NULL){ 1150108642Ssimokawa printf("fwohci_db_init: malloc failed\n"); 1151103285Sikob return; 1152103285Sikob } 1153103285Sikob db = (struct fwohcidb *) 1154103285Sikob contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1155103285Sikob M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1156103285Sikob if(db == NULL){ 1157108642Ssimokawa printf("fwohci_db_init: contigmalloc failed\n"); 1158108527Ssimokawa free(db_tr, M_DEVBUF); 1159103285Sikob return; 1160103285Sikob } 1161103285Sikob bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1162103285Sikob /* Attach DB to DMA ch. */ 1163103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1164103285Sikob db_tr->dbcnt = 0; 1165103285Sikob db_tr->db = &db[idb * dbch->ndesc]; 1166103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1167108530Ssimokawa if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1168108530Ssimokawa dbch->xferq.bnpacket != 0) { 1169108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1170108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1171108530Ssimokawa ].start = (caddr_t)db_tr; 1172108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1173108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1174108530Ssimokawa ].end = (caddr_t)db_tr; 1175103285Sikob } 1176103285Sikob db_tr++; 1177103285Sikob } 1178103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1179103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1180108642Ssimokawaout: 1181108642Ssimokawa dbch->frag.buf = NULL; 1182108642Ssimokawa dbch->frag.len = 0; 1183108642Ssimokawa dbch->frag.plen = 0; 1184108642Ssimokawa dbch->xferq.queued = 0; 1185108642Ssimokawa dbch->pdb_tr = NULL; 1186103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1187103285Sikob dbch->bottom = dbch->top; 1188108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1189103285Sikob} 1190106790Ssimokawa 1191106790Ssimokawastatic int 1192106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1193103285Sikob{ 1194103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1195103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1196103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1197103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1198103285Sikob fwohci_db_free(&sc->it[dmach]); 1199103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1200103285Sikob return 0; 1201103285Sikob} 1202106790Ssimokawa 1203106790Ssimokawastatic int 1204106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1205103285Sikob{ 1206103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1207103285Sikob 1208103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1209103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1210103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1211103285Sikob if(sc->ir[dmach].dummy != NULL){ 1212103285Sikob free(sc->ir[dmach].dummy, M_DEVBUF); 1213103285Sikob } 1214103285Sikob sc->ir[dmach].dummy = NULL; 1215103285Sikob fwohci_db_free(&sc->ir[dmach]); 1216103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1217103285Sikob return 0; 1218103285Sikob} 1219106790Ssimokawa 1220106790Ssimokawastatic void 1221106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1222103285Sikob{ 1223103285Sikob qld[0] = ntohl(qld[0]); 1224103285Sikob return; 1225103285Sikob} 1226106790Ssimokawa 1227106790Ssimokawastatic int 1228106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1229103285Sikob{ 1230103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1231103285Sikob int err = 0; 1232103285Sikob unsigned short tag, ich; 1233103285Sikob 1234103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1235103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1236103285Sikob 1237103285Sikob#if 0 1238103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1239103285Sikob wakeup(fc->ir[dmach]); 1240103285Sikob return err; 1241103285Sikob } 1242103285Sikob#endif 1243103285Sikob 1244103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1245103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1246103285Sikob sc->ir[dmach].xferq.queued = 0; 1247103285Sikob sc->ir[dmach].ndb = NDB; 1248103285Sikob sc->ir[dmach].xferq.psize = FWPMAX_S400; 1249103285Sikob sc->ir[dmach].ndesc = 1; 1250103285Sikob fwohci_db_init(&sc->ir[dmach]); 1251109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1252109179Ssimokawa return ENOMEM; 1253103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1254103285Sikob } 1255103285Sikob if(err){ 1256103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1257103285Sikob return err; 1258103285Sikob } 1259103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1260103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1261103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1262103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1263103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1264103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1265103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1266103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1267103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1268103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1269103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1270103285Sikob } 1271103285Sikob return err; 1272103285Sikob} 1273106790Ssimokawa 1274106790Ssimokawastatic int 1275106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1276103285Sikob{ 1277103285Sikob int err = 0; 1278103285Sikob int idb, z, i, dmach = 0; 1279103285Sikob u_int32_t off = NULL; 1280103285Sikob struct fwohcidb_tr *db_tr; 1281103285Sikob 1282103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1283103285Sikob err = EINVAL; 1284103285Sikob return err; 1285103285Sikob } 1286103285Sikob z = dbch->ndesc; 1287103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1288103285Sikob if( &sc->it[dmach] == dbch){ 1289103285Sikob off = OHCI_ITOFF(dmach); 1290103285Sikob break; 1291103285Sikob } 1292103285Sikob } 1293103285Sikob if(off == NULL){ 1294103285Sikob err = EINVAL; 1295103285Sikob return err; 1296103285Sikob } 1297103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1298103285Sikob return err; 1299103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1300103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1301103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1302103285Sikob } 1303103285Sikob db_tr = dbch->top; 1304103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1305103285Sikob fwohci_add_tx_buf(db_tr, 1306103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1307103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1308103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1309103285Sikob break; 1310103285Sikob } 1311103285Sikob db_tr->db[0].db.desc.depend 1312103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1313103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1314103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1315103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1316103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1317103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1318103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1319103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 1320103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1321103285Sikob ~0xf; 1322109280Ssimokawa /* OHCI 1.1 and above */ 1323109280Ssimokawa db_tr->db[0].db.desc.cmd 1324109280Ssimokawa |= OHCI_INTERRUPT_ALWAYS; 1325103285Sikob } 1326103285Sikob } 1327103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1328103285Sikob } 1329103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1330103285Sikob return err; 1331103285Sikob} 1332106790Ssimokawa 1333106790Ssimokawastatic int 1334106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1335103285Sikob{ 1336103285Sikob int err = 0; 1337103285Sikob int idb, z, i, dmach = 0; 1338103285Sikob u_int32_t off = NULL; 1339103285Sikob struct fwohcidb_tr *db_tr; 1340103285Sikob 1341103285Sikob z = dbch->ndesc; 1342103285Sikob if(&sc->arrq == dbch){ 1343103285Sikob off = OHCI_ARQOFF; 1344103285Sikob }else if(&sc->arrs == dbch){ 1345103285Sikob off = OHCI_ARSOFF; 1346103285Sikob }else{ 1347103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1348103285Sikob if( &sc->ir[dmach] == dbch){ 1349103285Sikob off = OHCI_IROFF(dmach); 1350103285Sikob break; 1351103285Sikob } 1352103285Sikob } 1353103285Sikob } 1354103285Sikob if(off == NULL){ 1355103285Sikob err = EINVAL; 1356103285Sikob return err; 1357103285Sikob } 1358103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1359103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1360103285Sikob return err; 1361103285Sikob }else{ 1362103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1363103285Sikob err = EBUSY; 1364103285Sikob return err; 1365103285Sikob } 1366103285Sikob } 1367103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1368108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1369103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1370103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1371103285Sikob } 1372103285Sikob db_tr = dbch->top; 1373103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1374103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1375103285Sikob fwohci_add_rx_buf(db_tr, 1376103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1377103285Sikob }else{ 1378103285Sikob fwohci_add_rx_buf(db_tr, 1379103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1380103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1381103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1382103285Sikob } 1383103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1384103285Sikob break; 1385103285Sikob } 1386103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1387103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1388103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1389103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1390103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1391103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1392103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1393103285Sikob ~0xf; 1394103285Sikob } 1395103285Sikob } 1396103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1397103285Sikob } 1398103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1399103285Sikob dbch->buf_offset = 0; 1400103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1401103285Sikob return err; 1402103285Sikob }else{ 1403103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1404103285Sikob } 1405103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1406103285Sikob return err; 1407103285Sikob} 1408106790Ssimokawa 1409106790Ssimokawastatic int 1410106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1411103285Sikob{ 1412103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1413103285Sikob int err = 0; 1414103285Sikob unsigned short tag, ich; 1415103285Sikob struct fwohci_dbch *dbch; 1416103285Sikob struct fw_pkt *fp; 1417103285Sikob struct fwohcidb_tr *db_tr; 1418109356Ssimokawa int cycle_now, sec, cycle, cycle_match; 1419109356Ssimokawa u_int32_t stat; 1420103285Sikob 1421103285Sikob tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1422103285Sikob ich = sc->it[dmach].xferq.flag & 0x3f; 1423103285Sikob dbch = &sc->it[dmach]; 1424109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { 1425103285Sikob dbch->xferq.queued = 0; 1426103285Sikob dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1427103285Sikob dbch->ndesc = 3; 1428103285Sikob fwohci_db_init(dbch); 1429109179Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1430109179Ssimokawa return ENOMEM; 1431103285Sikob err = fwohci_tx_enable(sc, dbch); 1432103285Sikob } 1433103285Sikob if(err) 1434103285Sikob return err; 1435109356Ssimokawa stat = OREAD(sc, OHCI_ITCTL(dmach)); 1436109356Ssimokawa if (stat & OHCI_CNTL_DMA_ACTIVE) { 1437103285Sikob if(dbch->xferq.stdma2 != NULL){ 1438103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1439103285Sikob ((struct fwohcidb_tr *) 1440103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1441103285Sikob |= OHCI_BRANCH_ALWAYS; 1442103285Sikob ((struct fwohcidb_tr *) 1443103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1444103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1445103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1446103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1447103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1448103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1449103285Sikob } 1450109356Ssimokawa } else if(!(stat & OHCI_CNTL_DMA_RUN)) { 1451109280Ssimokawa if (firewire_debug) 1452109280Ssimokawa printf("fwohci_itxbuf_enable: kick 0x%08x\n", 1453109280Ssimokawa OREAD(sc, OHCI_ITCTL(dmach))); 1454103285Sikob fw_tbuf_update(&sc->fc, dmach, 0); 1455103285Sikob if(dbch->xferq.stdma == NULL){ 1456103285Sikob return err; 1457103285Sikob } 1458109356Ssimokawa#if 0 1459103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1460109356Ssimokawa#endif 1461103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1462103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1463103285Sikob OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1464103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1465103285Sikob if(dbch->xferq.stdma2 != NULL){ 1466103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1467103285Sikob ((struct fwohcidb_tr *) 1468103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1469103285Sikob |= OHCI_BRANCH_ALWAYS; 1470103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1471103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1472103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1473103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1474103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1475103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1476103285Sikob }else{ 1477103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1478103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1479103285Sikob } 1480103285Sikob OWRITE(sc, OHCI_ITCMD(dmach), 1481103285Sikob vtophys(((struct fwohcidb_tr *) 1482103285Sikob (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1483109356Ssimokawa#define CYCLE_OFFSET 1 1484103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1485103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1486103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1487109356Ssimokawa dbch->xferq.dvoffset = CYCLE_OFFSET; 1488109179Ssimokawa fp->mode.ld[2] |= htonl(dbch->xferq.dvoffset << 12); 1489103285Sikob } 1490109356Ssimokawa /* 2bit second + 13bit cycle */ 1491109356Ssimokawa cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; 1492109356Ssimokawa cycle = cycle_now & 0x1fff; 1493109356Ssimokawa sec = cycle_now >> 13; 1494109356Ssimokawa#define CYCLE_MOD 0x10 1495109356Ssimokawa#define CYCLE_DELAY 8 /* min delay to start DMA */ 1496109356Ssimokawa cycle = cycle + CYCLE_DELAY; 1497109356Ssimokawa if (cycle >= 8000) { 1498109356Ssimokawa sec ++; 1499109356Ssimokawa cycle -= 8000; 1500109356Ssimokawa } 1501109356Ssimokawa cycle = ((cycle + CYCLE_MOD - 1) / CYCLE_MOD) * CYCLE_MOD; 1502109356Ssimokawa if (cycle >= 8000) { 1503109356Ssimokawa sec ++; 1504109356Ssimokawa if (cycle == 8000) 1505109356Ssimokawa cycle = 0; 1506109356Ssimokawa else 1507109356Ssimokawa cycle = CYCLE_MOD; 1508109356Ssimokawa } 1509109356Ssimokawa cycle_match = ((sec << 13) | cycle) & 0x7ffff; 1510109356Ssimokawa if (firewire_debug) 1511109356Ssimokawa printf("cycle_match: 0x%04x->0x%04x\n", 1512109356Ssimokawa cycle_now, cycle_match); 1513109356Ssimokawa /* Clear cycle match counter bits */ 1514109356Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); 1515109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), 1516109356Ssimokawa OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) 1517109356Ssimokawa | OHCI_CNTL_DMA_RUN); 1518103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1519109356Ssimokawa } else { 1520109356Ssimokawa OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); 1521103285Sikob } 1522103285Sikob return err; 1523103285Sikob} 1524106790Ssimokawa 1525106790Ssimokawastatic int 1526106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1527103285Sikob{ 1528103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1529103285Sikob int err = 0; 1530103285Sikob unsigned short tag, ich; 1531103285Sikob 1532103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1533108995Ssimokawa tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1534108995Ssimokawa ich = sc->ir[dmach].xferq.flag & 0x3f; 1535108995Ssimokawa OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1536108995Ssimokawa 1537103285Sikob sc->ir[dmach].xferq.queued = 0; 1538103285Sikob sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1539103285Sikob sc->ir[dmach].xferq.bnchunk; 1540103285Sikob sc->ir[dmach].dummy = 1541103285Sikob malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1542103285Sikob M_DEVBUF, M_DONTWAIT); 1543103285Sikob if(sc->ir[dmach].dummy == NULL){ 1544103285Sikob err = ENOMEM; 1545103285Sikob return err; 1546103285Sikob } 1547103285Sikob sc->ir[dmach].ndesc = 2; 1548103285Sikob fwohci_db_init(&sc->ir[dmach]); 1549109179Ssimokawa if ((sc->ir[dmach].flags & FWOHCI_DBCH_INIT) == 0) 1550109179Ssimokawa return ENOMEM; 1551103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1552103285Sikob } 1553103285Sikob if(err) 1554103285Sikob return err; 1555103285Sikob 1556103285Sikob if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1557103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1558103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1559103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1560103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1561103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1562103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1563103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1564103285Sikob } 1565103285Sikob }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1566103285Sikob && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1567103285Sikob fw_rbuf_update(&sc->fc, dmach, 0); 1568103285Sikob 1569103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1570103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1571103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1572103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1573103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1574103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1575103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1576103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1577103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1578103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1579103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1580103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1581103285Sikob }else{ 1582103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1583103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1584103285Sikob } 1585103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1586103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1587103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1588108995Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1589103285Sikob } 1590103285Sikob return err; 1591103285Sikob} 1592106790Ssimokawa 1593106790Ssimokawastatic int 1594106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1595103285Sikob{ 1596103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1597103285Sikob int err = 0; 1598103285Sikob 1599103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1600103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1601103285Sikob return err; 1602103285Sikob }else{ 1603103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1604103285Sikob return err; 1605103285Sikob } 1606103285Sikob} 1607106790Ssimokawa 1608106790Ssimokawaint 1609108642Ssimokawafwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1610103285Sikob{ 1611103285Sikob u_int i; 1612103285Sikob 1613103285Sikob/* Now stopping all DMA channel */ 1614103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1615103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1616103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1617103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1618103285Sikob 1619103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1620103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1621103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1622103285Sikob } 1623103285Sikob 1624103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1625103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1626103285Sikob 1627103285Sikob/* Stop interrupt */ 1628103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1629103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1630103285Sikob | OHCI_INT_PHY_INT 1631103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1632103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1633103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1634103285Sikob | OHCI_INT_PHY_BUS_R); 1635108642Ssimokawa/* XXX Link down? Bus reset? */ 1636103285Sikob return 0; 1637103285Sikob} 1638103285Sikob 1639108642Ssimokawaint 1640108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1641108642Ssimokawa{ 1642108642Ssimokawa int i; 1643108642Ssimokawa 1644108642Ssimokawa fwohci_reset(sc, dev); 1645108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1646108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1647108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1648108642Ssimokawa device_printf(sc->fc.dev, 1649108642Ssimokawa "resume iso receive ch: %d\n", i); 1650108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1651108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1652108642Ssimokawa } 1653108642Ssimokawa } 1654108642Ssimokawa 1655108642Ssimokawa bus_generic_resume(dev); 1656108642Ssimokawa sc->fc.ibr(&sc->fc); 1657108642Ssimokawa return 0; 1658108642Ssimokawa} 1659108642Ssimokawa 1660103285Sikob#define ACK_ALL 1661103285Sikobstatic void 1662106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1663103285Sikob{ 1664103285Sikob u_int32_t irstat, itstat; 1665103285Sikob u_int i; 1666103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1667103285Sikob 1668103285Sikob#ifdef OHCI_DEBUG 1669103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1670103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1671103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1672103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1673103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1674103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1675103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1676103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1677103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1678103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1679103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1680103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1681103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1682103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1683103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1684103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1685103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1686103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1687103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1688103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1689103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1690103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1691103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1692103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1693103285Sikob ); 1694103285Sikob#endif 1695103285Sikob/* Bus reset */ 1696103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1697103285Sikob device_printf(fc->dev, "BUS reset\n"); 1698103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1699103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1700103285Sikob 1701103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1702103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1703103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1704103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1705103285Sikob 1706103285Sikob#if 0 1707103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1708103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1709103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1710103285Sikob } 1711103285Sikob 1712103285Sikob#endif 1713103285Sikob fw_busreset(fc); 1714103285Sikob 1715103285Sikob /* XXX need to wait DMA to stop */ 1716103285Sikob#ifndef ACK_ALL 1717103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1718103285Sikob#endif 1719103285Sikob#if 1 1720103285Sikob /* pending all pre-bus_reset packets */ 1721103285Sikob fwohci_txd(sc, &sc->atrq); 1722103285Sikob fwohci_txd(sc, &sc->atrs); 1723106789Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1724106789Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1725103285Sikob#endif 1726103285Sikob 1727103285Sikob 1728103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1729103285Sikob /* XXX insecure ?? */ 1730103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1731103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1732103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1733103285Sikob 1734103285Sikob } 1735103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1736103285Sikob#ifndef ACK_ALL 1737103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1738103285Sikob#endif 1739103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1740109280Ssimokawa OWRITE(sc, OHCI_IR_STATCLR, irstat); 1741103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1742103285Sikob if((irstat & (1 << i)) != 0){ 1743103285Sikob if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1744106789Ssimokawa fwohci_ircv(sc, &sc->ir[i], count); 1745103285Sikob }else{ 1746103285Sikob fwohci_rbuf_update(sc, i); 1747103285Sikob } 1748103285Sikob } 1749103285Sikob } 1750103285Sikob } 1751103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1752103285Sikob#ifndef ACK_ALL 1753103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1754103285Sikob#endif 1755103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1756109280Ssimokawa OWRITE(sc, OHCI_IT_STATCLR, itstat); 1757103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1758103285Sikob if((itstat & (1 << i)) != 0){ 1759103285Sikob fwohci_tbuf_update(sc, i); 1760103285Sikob } 1761103285Sikob } 1762103285Sikob } 1763103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1764103285Sikob#ifndef ACK_ALL 1765103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1766103285Sikob#endif 1767103285Sikob#if 0 1768103285Sikob dump_dma(sc, ARRS_CH); 1769103285Sikob dump_db(sc, ARRS_CH); 1770103285Sikob#endif 1771106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1772103285Sikob } 1773103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1774103285Sikob#ifndef ACK_ALL 1775103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1776103285Sikob#endif 1777103285Sikob#if 0 1778103285Sikob dump_dma(sc, ARRQ_CH); 1779103285Sikob dump_db(sc, ARRQ_CH); 1780103285Sikob#endif 1781106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1782103285Sikob } 1783103285Sikob if(stat & OHCI_INT_PHY_SID){ 1784103285Sikob caddr_t buf; 1785103285Sikob int plen; 1786103285Sikob 1787103285Sikob#ifndef ACK_ALL 1788103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1789103285Sikob#endif 1790103285Sikob/* 1791103285Sikob** Checking whether the node is root or not. If root, turn on 1792103285Sikob** cycle master. 1793103285Sikob*/ 1794103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1795103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1796103285Sikob printf("Bus reset failure\n"); 1797103285Sikob goto sidout; 1798103285Sikob } 1799103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1800103285Sikob printf("CYCLEMASTER mode\n"); 1801103285Sikob OWRITE(sc, OHCI_LNKCTL, 1802103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1803103285Sikob }else{ 1804103285Sikob printf("non CYCLEMASTER mode\n"); 1805103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1806103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1807103285Sikob } 1808103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1809103285Sikob 1810103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1811103285Sikob plen -= 4; /* chop control info */ 1812103285Sikob buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1813103285Sikob if(buf == NULL) goto sidout; 1814108530Ssimokawa bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1815103285Sikob buf, plen); 1816103285Sikob fw_sidrcv(fc, buf, plen, 0); 1817103285Sikob } 1818103285Sikobsidout: 1819103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1820103285Sikob#ifndef ACK_ALL 1821103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1822103285Sikob#endif 1823103285Sikob fwohci_txd(sc, &(sc->atrq)); 1824103285Sikob } 1825103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1826103285Sikob#ifndef ACK_ALL 1827103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1828103285Sikob#endif 1829103285Sikob fwohci_txd(sc, &(sc->atrs)); 1830103285Sikob } 1831103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1832103285Sikob#ifndef ACK_ALL 1833103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1834103285Sikob#endif 1835103285Sikob device_printf(fc->dev, "posted write error\n"); 1836103285Sikob } 1837103285Sikob if((stat & OHCI_INT_ERR )){ 1838103285Sikob#ifndef ACK_ALL 1839103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1840103285Sikob#endif 1841103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1842103285Sikob } 1843103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1844103285Sikob#ifndef ACK_ALL 1845103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1846103285Sikob#endif 1847103285Sikob device_printf(fc->dev, "phy int\n"); 1848103285Sikob } 1849103285Sikob 1850103285Sikob return; 1851103285Sikob} 1852103285Sikob 1853103285Sikobvoid 1854103285Sikobfwohci_intr(void *arg) 1855103285Sikob{ 1856103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1857103285Sikob u_int32_t stat; 1858103285Sikob 1859103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1860103285Sikob /* polling mode */ 1861103285Sikob return; 1862103285Sikob } 1863103285Sikob 1864103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1865103285Sikob if (stat == 0xffffffff) { 1866103285Sikob device_printf(sc->fc.dev, 1867103285Sikob "device physically ejected?\n"); 1868103285Sikob return; 1869103285Sikob } 1870103285Sikob#ifdef ACK_ALL 1871103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1872103285Sikob#endif 1873106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1874103285Sikob } 1875103285Sikob} 1876103285Sikob 1877103285Sikobstatic void 1878103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1879103285Sikob{ 1880103285Sikob int s; 1881103285Sikob u_int32_t stat; 1882103285Sikob struct fwohci_softc *sc; 1883103285Sikob 1884103285Sikob 1885103285Sikob sc = (struct fwohci_softc *)fc; 1886103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1887103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1888103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1889103285Sikob#if 0 1890103285Sikob if (!quick) { 1891103285Sikob#else 1892103285Sikob if (1) { 1893103285Sikob#endif 1894103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1895103285Sikob if (stat == 0) 1896103285Sikob return; 1897103285Sikob if (stat == 0xffffffff) { 1898103285Sikob device_printf(sc->fc.dev, 1899103285Sikob "device physically ejected?\n"); 1900103285Sikob return; 1901103285Sikob } 1902103285Sikob#ifdef ACK_ALL 1903103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1904103285Sikob#endif 1905103285Sikob } 1906103285Sikob s = splfw(); 1907106789Ssimokawa fwohci_intr_body(sc, stat, count); 1908103285Sikob splx(s); 1909103285Sikob} 1910103285Sikob 1911103285Sikobstatic void 1912103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 1913103285Sikob{ 1914103285Sikob struct fwohci_softc *sc; 1915103285Sikob 1916103285Sikob sc = (struct fwohci_softc *)fc; 1917107653Ssimokawa if (bootverbose) 1918108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1919103285Sikob if (enable) { 1920103285Sikob sc->intmask |= OHCI_INT_EN; 1921103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1922103285Sikob } else { 1923103285Sikob sc->intmask &= ~OHCI_INT_EN; 1924103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1925103285Sikob } 1926103285Sikob} 1927103285Sikob 1928106790Ssimokawastatic void 1929106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1930103285Sikob{ 1931103285Sikob int stat; 1932103285Sikob struct firewire_comm *fc = &sc->fc; 1933103285Sikob struct fw_pkt *fp; 1934103285Sikob struct fwohci_dbch *dbch; 1935103285Sikob struct fwohcidb_tr *db_tr; 1936103285Sikob 1937103285Sikob dbch = &sc->it[dmach]; 1938109179Ssimokawa#if 0 /* XXX OHCI interrupt before the last packet is really on the wire */ 1939103285Sikob if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1940103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1941103285Sikob/* 1942103285Sikob * Overwrite highest significant 4 bits timestamp information 1943103285Sikob */ 1944103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1945109179Ssimokawa fp->mode.ld[2] &= htonl(0xffff0fff); 1946109179Ssimokawa fp->mode.ld[2] |= htonl((fc->cyctimer(fc) + 0x4000) & 0xf000); 1947103285Sikob } 1948109179Ssimokawa#endif 1949103285Sikob stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1950103285Sikob switch(stat){ 1951103285Sikob case FWOHCIEV_ACKCOMPL: 1952109179Ssimokawa#if 1 1953109179Ssimokawa if (dbch->xferq.flag & FWXFERQ_DV) { 1954109179Ssimokawa struct ciphdr *ciph; 1955109179Ssimokawa int timer, timestamp, cycl, diff; 1956109179Ssimokawa static int last_timer=0; 1957109179Ssimokawa 1958109179Ssimokawa timer = (fc->cyctimer(fc) >> 12) & 0xffff; 1959109179Ssimokawa db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1960109179Ssimokawa fp = (struct fw_pkt *)db_tr->buf; 1961109179Ssimokawa ciph = (struct ciphdr *) &fp->mode.ld[1]; 1962109179Ssimokawa timestamp = db_tr->db[2].db.desc.count & 0xffff; 1963109179Ssimokawa cycl = ntohs(ciph->fdf.dv.cyc) >> 12; 1964109356Ssimokawa diff = cycl - (timestamp & 0xf) - CYCLE_OFFSET; 1965109179Ssimokawa if (diff < 0) 1966109179Ssimokawa diff += 16; 1967109179Ssimokawa if (diff > 8) 1968109179Ssimokawa diff -= 16; 1969109280Ssimokawa if (firewire_debug || diff != 0) 1970109179Ssimokawa printf("dbc: %3d timer: 0x%04x packet: 0x%04x" 1971109179Ssimokawa " cyc: 0x%x diff: %+1d\n", 1972109179Ssimokawa ciph->dbc, last_timer, timestamp, cycl, diff); 1973109179Ssimokawa last_timer = timer; 1974109179Ssimokawa /* XXX adjust dbch->xferq.dvoffset if diff != 0 or 1 */ 1975109179Ssimokawa } 1976109179Ssimokawa#endif 1977103285Sikob fw_tbuf_update(fc, dmach, 1); 1978103285Sikob break; 1979103285Sikob default: 1980109179Ssimokawa device_printf(fc->dev, "Isochronous transmit err %02x\n", stat); 1981103285Sikob fw_tbuf_update(fc, dmach, 0); 1982103285Sikob break; 1983103285Sikob } 1984109179Ssimokawa fwohci_itxbuf_enable(fc, dmach); 1985103285Sikob} 1986106790Ssimokawa 1987106790Ssimokawastatic void 1988106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1989103285Sikob{ 1990109179Ssimokawa struct firewire_comm *fc = &sc->fc; 1991103285Sikob int stat; 1992109179Ssimokawa 1993103285Sikob stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1994103285Sikob switch(stat){ 1995103285Sikob case FWOHCIEV_ACKCOMPL: 1996109179Ssimokawa fw_rbuf_update(fc, dmach, 1); 1997109179Ssimokawa wakeup(fc->ir[dmach]); 1998109179Ssimokawa fwohci_irx_enable(fc, dmach); 1999103285Sikob break; 2000103285Sikob default: 2001109179Ssimokawa device_printf(fc->dev, "Isochronous receive err %02x\n", 2002109179Ssimokawa stat); 2003103285Sikob break; 2004103285Sikob } 2005103285Sikob} 2006106790Ssimokawa 2007106790Ssimokawavoid 2008106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 2009106790Ssimokawa{ 2010103285Sikob u_int32_t off, cntl, stat, cmd, match; 2011103285Sikob 2012103285Sikob if(ch == 0){ 2013103285Sikob off = OHCI_ATQOFF; 2014103285Sikob }else if(ch == 1){ 2015103285Sikob off = OHCI_ATSOFF; 2016103285Sikob }else if(ch == 2){ 2017103285Sikob off = OHCI_ARQOFF; 2018103285Sikob }else if(ch == 3){ 2019103285Sikob off = OHCI_ARSOFF; 2020103285Sikob }else if(ch < IRX_CH){ 2021103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2022103285Sikob }else{ 2023103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2024103285Sikob } 2025103285Sikob cntl = stat = OREAD(sc, off); 2026103285Sikob cmd = OREAD(sc, off + 0xc); 2027103285Sikob match = OREAD(sc, off + 0x10); 2028103285Sikob 2029103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 2030103285Sikob ch, 2031103285Sikob cntl, 2032103285Sikob stat, 2033103285Sikob cmd, 2034103285Sikob match); 2035103285Sikob stat &= 0xffff ; 2036103285Sikob if(stat & 0xff00){ 2037103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 2038103285Sikob ch, 2039103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2040103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2041103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2042103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2043103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2044103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2045103285Sikob fwohcicode[stat & 0x1f], 2046103285Sikob stat & 0x1f 2047103285Sikob ); 2048103285Sikob }else{ 2049103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 2050103285Sikob } 2051103285Sikob} 2052106790Ssimokawa 2053106790Ssimokawavoid 2054106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 2055106790Ssimokawa{ 2056103285Sikob struct fwohci_dbch *dbch; 2057103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 2058103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 2059103285Sikob int idb, jdb; 2060103285Sikob u_int32_t cmd, off; 2061103285Sikob if(ch == 0){ 2062103285Sikob off = OHCI_ATQOFF; 2063103285Sikob dbch = &sc->atrq; 2064103285Sikob }else if(ch == 1){ 2065103285Sikob off = OHCI_ATSOFF; 2066103285Sikob dbch = &sc->atrs; 2067103285Sikob }else if(ch == 2){ 2068103285Sikob off = OHCI_ARQOFF; 2069103285Sikob dbch = &sc->arrq; 2070103285Sikob }else if(ch == 3){ 2071103285Sikob off = OHCI_ARSOFF; 2072103285Sikob dbch = &sc->arrs; 2073103285Sikob }else if(ch < IRX_CH){ 2074103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 2075103285Sikob dbch = &sc->it[ch - ITX_CH]; 2076103285Sikob }else { 2077103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 2078103285Sikob dbch = &sc->ir[ch - IRX_CH]; 2079103285Sikob } 2080103285Sikob cmd = OREAD(sc, off + 0xc); 2081103285Sikob 2082103285Sikob if( dbch->ndb == 0 ){ 2083103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 2084103285Sikob return; 2085103285Sikob } 2086103285Sikob pp = dbch->top; 2087103285Sikob prev = pp->db; 2088103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 2089103285Sikob if(pp == NULL){ 2090103285Sikob curr = NULL; 2091103285Sikob goto outdb; 2092103285Sikob } 2093103285Sikob cp = STAILQ_NEXT(pp, link); 2094103285Sikob if(cp == NULL){ 2095103285Sikob curr = NULL; 2096103285Sikob goto outdb; 2097103285Sikob } 2098103285Sikob np = STAILQ_NEXT(cp, link); 2099103285Sikob if(cp == NULL) break; 2100103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 2101103285Sikob if((cmd & 0xfffffff0) 2102103285Sikob == vtophys(&(cp->db[jdb]))){ 2103103285Sikob curr = cp->db; 2104103285Sikob if(np != NULL){ 2105103285Sikob next = np->db; 2106103285Sikob }else{ 2107103285Sikob next = NULL; 2108103285Sikob } 2109103285Sikob goto outdb; 2110103285Sikob } 2111103285Sikob } 2112103285Sikob pp = STAILQ_NEXT(pp, link); 2113103285Sikob prev = pp->db; 2114103285Sikob } 2115103285Sikoboutdb: 2116103285Sikob if( curr != NULL){ 2117103285Sikob printf("Prev DB %d\n", ch); 2118103285Sikob print_db(prev, ch, dbch->ndesc); 2119103285Sikob printf("Current DB %d\n", ch); 2120103285Sikob print_db(curr, ch, dbch->ndesc); 2121103285Sikob printf("Next DB %d\n", ch); 2122103285Sikob print_db(next, ch, dbch->ndesc); 2123103285Sikob }else{ 2124103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2125103285Sikob } 2126103285Sikob return; 2127103285Sikob} 2128106790Ssimokawa 2129106790Ssimokawavoid 2130106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2131106790Ssimokawa{ 2132103285Sikob fwohcireg_t stat; 2133103285Sikob int i, key; 2134103285Sikob 2135103285Sikob if(db == NULL){ 2136103285Sikob printf("No Descriptor is found\n"); 2137103285Sikob return; 2138103285Sikob } 2139103285Sikob 2140103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2141103285Sikob ch, 2142103285Sikob "Current", 2143103285Sikob "OP ", 2144103285Sikob "KEY", 2145103285Sikob "INT", 2146103285Sikob "BR ", 2147103285Sikob "len", 2148103285Sikob "Addr", 2149103285Sikob "Depend", 2150103285Sikob "Stat", 2151103285Sikob "Cnt"); 2152103285Sikob for( i = 0 ; i <= max ; i ++){ 2153103285Sikob key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2154108712Ssimokawa#if __FreeBSD_version >= 500000 2155106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2156108712Ssimokawa#else 2157108712Ssimokawa printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2158108712Ssimokawa#endif 2159103285Sikob vtophys(&db[i]), 2160103285Sikob dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2161103285Sikob dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2162103285Sikob dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2163103285Sikob dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2164103285Sikob db[i].db.desc.cmd & 0xffff, 2165103285Sikob db[i].db.desc.addr, 2166103285Sikob db[i].db.desc.depend, 2167103285Sikob db[i].db.desc.status, 2168103285Sikob db[i].db.desc.count); 2169103285Sikob stat = db[i].db.desc.status; 2170103285Sikob if(stat & 0xff00){ 2171103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2172103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2173103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2174103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2175103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2176103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2177103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2178103285Sikob fwohcicode[stat & 0x1f], 2179103285Sikob stat & 0x1f 2180103285Sikob ); 2181103285Sikob }else{ 2182103285Sikob printf(" Nostat\n"); 2183103285Sikob } 2184103285Sikob if(key == OHCI_KEY_ST2 ){ 2185103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2186103285Sikob db[i+1].db.immed[0], 2187103285Sikob db[i+1].db.immed[1], 2188103285Sikob db[i+1].db.immed[2], 2189103285Sikob db[i+1].db.immed[3]); 2190103285Sikob } 2191103285Sikob if(key == OHCI_KEY_DEVICE){ 2192103285Sikob return; 2193103285Sikob } 2194103285Sikob if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2195103285Sikob == OHCI_BRANCH_ALWAYS){ 2196103285Sikob return; 2197103285Sikob } 2198103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2199103285Sikob == OHCI_OUTPUT_LAST){ 2200103285Sikob return; 2201103285Sikob } 2202103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2203103285Sikob == OHCI_INPUT_LAST){ 2204103285Sikob return; 2205103285Sikob } 2206103285Sikob if(key == OHCI_KEY_ST2 ){ 2207103285Sikob i++; 2208103285Sikob } 2209103285Sikob } 2210103285Sikob return; 2211103285Sikob} 2212106790Ssimokawa 2213106790Ssimokawavoid 2214106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2215103285Sikob{ 2216103285Sikob struct fwohci_softc *sc; 2217103285Sikob u_int32_t fun; 2218103285Sikob 2219103285Sikob sc = (struct fwohci_softc *)fc; 2220108276Ssimokawa 2221108276Ssimokawa /* 2222108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2223108276Ssimokawa * shouldn't became the root node. 2224108276Ssimokawa */ 2225103285Sikob#if 1 2226103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2227109280Ssimokawa fun |= FW_PHY_IBR | FW_PHY_RHB; 2228103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2229109280Ssimokawa#else /* Short bus reset */ 2230103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2231109280Ssimokawa fun |= FW_PHY_ISBR | FW_PHY_RHB; 2232103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2233103285Sikob#endif 2234103285Sikob} 2235106790Ssimokawa 2236106790Ssimokawavoid 2237106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2238103285Sikob{ 2239103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2240103285Sikob struct fwohci_dbch *dbch; 2241103285Sikob struct fw_pkt *fp; 2242103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2243103285Sikob unsigned short chtag; 2244103285Sikob int idb; 2245103285Sikob 2246103285Sikob dbch = &sc->it[dmach]; 2247103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2248103285Sikob 2249103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2250103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2251103285Sikob/* 2252103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2253103285Sikob*/ 2254103285Sikob if(bulkxfer->flag != 0){ 2255103285Sikob return; 2256103285Sikob } 2257103285Sikob bulkxfer->flag = 1; 2258103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2259103285Sikob db_tr->db[0].db.desc.cmd 2260103285Sikob = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2261103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2262103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) 2263103285Sikob db_tr->db[1].db.immed; 2264103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2265103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2266103285Sikob ohcifp->mode.stream.chtag = chtag; 2267103285Sikob ohcifp->mode.stream.tcode = 0xa; 2268103285Sikob ohcifp->mode.stream.spd = 4; 2269103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2270103285Sikob ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2271103285Sikob 2272103285Sikob db_tr->db[2].db.desc.cmd 2273103285Sikob = OHCI_OUTPUT_LAST 2274103285Sikob | OHCI_UPDATE 2275103285Sikob | OHCI_BRANCH_ALWAYS 2276103285Sikob | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2277103285Sikob db_tr->db[2].db.desc.status = 0; 2278103285Sikob db_tr->db[2].db.desc.count = 0; 2279109280Ssimokawa db_tr->db[0].db.desc.depend 2280109280Ssimokawa = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2281109280Ssimokawa db_tr->db[dbch->ndesc - 1].db.desc.depend 2282109280Ssimokawa = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2283103285Sikob bulkxfer->end = (caddr_t)db_tr; 2284103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2285103285Sikob } 2286103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2287103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2288103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2289109280Ssimokawa#if 0 2290103285Sikob/**/ 2291103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2292103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2293103285Sikob/**/ 2294109280Ssimokawa#endif 2295103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2296109280Ssimokawa /* OHCI 1.1 and above */ 2297109280Ssimokawa db_tr->db[0].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2298103285Sikob 2299103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2300103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2301103285Sikob/* 2302103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2303103285Sikob*/ 2304103285Sikob return; 2305103285Sikob} 2306106790Ssimokawa 2307106790Ssimokawastatic int 2308106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2309106790Ssimokawa int mode, void *buf) 2310103285Sikob{ 2311103285Sikob volatile struct fwohcidb *db = db_tr->db; 2312103285Sikob int err = 0; 2313103285Sikob if(buf == 0){ 2314103285Sikob err = EINVAL; 2315103285Sikob return err; 2316103285Sikob } 2317103285Sikob db_tr->buf = buf; 2318103285Sikob db_tr->dbcnt = 3; 2319103285Sikob db_tr->dummy = NULL; 2320103285Sikob 2321103285Sikob db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2322103285Sikob 2323103285Sikob db[2].db.desc.depend = 0; 2324103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2325103285Sikob db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2326103285Sikob 2327103285Sikob db[0].db.desc.status = 0; 2328103285Sikob db[0].db.desc.count = 0; 2329103285Sikob 2330103285Sikob db[2].db.desc.status = 0; 2331103285Sikob db[2].db.desc.count = 0; 2332103285Sikob if( mode & FWXFERQ_STREAM ){ 2333103285Sikob db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2334103285Sikob if(mode & FWXFERQ_PACKET ){ 2335103285Sikob db[2].db.desc.cmd 2336103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2337103285Sikob } 2338103285Sikob } 2339103285Sikob db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2340103285Sikob return 1; 2341103285Sikob} 2342106790Ssimokawa 2343106790Ssimokawaint 2344106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2345106790Ssimokawa void *buf, void *dummy) 2346103285Sikob{ 2347103285Sikob volatile struct fwohcidb *db = db_tr->db; 2348103285Sikob int i; 2349103285Sikob void *dbuf[2]; 2350103285Sikob int dsiz[2]; 2351103285Sikob 2352103285Sikob if(buf == 0){ 2353103285Sikob buf = malloc(size, M_DEVBUF, M_NOWAIT); 2354103285Sikob if(buf == NULL) return 0; 2355103285Sikob db_tr->buf = buf; 2356103285Sikob db_tr->dbcnt = 1; 2357103285Sikob db_tr->dummy = NULL; 2358103285Sikob dsiz[0] = size; 2359103285Sikob dbuf[0] = buf; 2360103285Sikob }else if(dummy == NULL){ 2361103285Sikob db_tr->buf = buf; 2362103285Sikob db_tr->dbcnt = 1; 2363103285Sikob db_tr->dummy = NULL; 2364103285Sikob dsiz[0] = size; 2365103285Sikob dbuf[0] = buf; 2366103285Sikob }else{ 2367103285Sikob db_tr->buf = buf; 2368103285Sikob db_tr->dbcnt = 2; 2369103285Sikob db_tr->dummy = dummy; 2370103285Sikob dsiz[0] = sizeof(u_int32_t); 2371103285Sikob dsiz[1] = size; 2372103285Sikob dbuf[0] = dummy; 2373103285Sikob dbuf[1] = buf; 2374103285Sikob } 2375103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2376103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2377103285Sikob db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2378103285Sikob if( mode & FWXFERQ_STREAM ){ 2379103285Sikob db[i].db.desc.cmd |= OHCI_UPDATE; 2380103285Sikob } 2381103285Sikob db[i].db.desc.status = 0; 2382103285Sikob db[i].db.desc.count = dsiz[i]; 2383103285Sikob } 2384103285Sikob if( mode & FWXFERQ_STREAM ){ 2385103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2386103285Sikob if(mode & FWXFERQ_PACKET ){ 2387103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd 2388103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2389103285Sikob } 2390103285Sikob } 2391103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2392103285Sikob return 1; 2393103285Sikob} 2394106790Ssimokawa 2395106790Ssimokawastatic void 2396106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2397103285Sikob{ 2398103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2399103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2400103285Sikob int z = 1; 2401103285Sikob struct fw_pkt *fp; 2402103285Sikob u_int8_t *ld; 2403103285Sikob u_int32_t off = NULL; 2404103285Sikob u_int32_t stat; 2405103285Sikob u_int32_t *qld; 2406103285Sikob u_int32_t reg; 2407103285Sikob u_int spd; 2408103285Sikob u_int dmach; 2409103285Sikob int len, i, plen; 2410103285Sikob caddr_t buf; 2411103285Sikob 2412103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2413103285Sikob if( &sc->ir[dmach] == dbch){ 2414103285Sikob off = OHCI_IROFF(dmach); 2415103285Sikob break; 2416103285Sikob } 2417103285Sikob } 2418103285Sikob if(off == NULL){ 2419103285Sikob return; 2420103285Sikob } 2421103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2422103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2423103285Sikob return; 2424103285Sikob } 2425103285Sikob 2426103285Sikob odb_tr = NULL; 2427103285Sikob db_tr = dbch->top; 2428103285Sikob i = 0; 2429103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2430106789Ssimokawa if (count >= 0 && count-- == 0) 2431106789Ssimokawa break; 2432103285Sikob ld = (u_int8_t *)db_tr->buf; 2433103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2434103285Sikob /* skip timeStamp */ 2435103285Sikob ld += sizeof(struct fwohci_trailer); 2436103285Sikob } 2437103285Sikob qld = (u_int32_t *)ld; 2438103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2439103285Sikob/* 2440103285Sikob{ 2441103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2442103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2443103285Sikob} 2444103285Sikob*/ 2445103285Sikob fp=(struct fw_pkt *)ld; 2446103285Sikob qld[0] = htonl(qld[0]); 2447103285Sikob plen = sizeof(struct fw_isohdr) 2448103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2449103285Sikob ld += plen; 2450103285Sikob len -= plen; 2451103285Sikob buf = db_tr->buf; 2452103285Sikob db_tr->buf = NULL; 2453103285Sikob stat = reg & 0x1f; 2454103285Sikob spd = reg & 0x3; 2455103285Sikob switch(stat){ 2456103285Sikob case FWOHCIEV_ACKCOMPL: 2457103285Sikob case FWOHCIEV_ACKPEND: 2458103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2459103285Sikob break; 2460103285Sikob default: 2461103285Sikob free(buf, M_DEVBUF); 2462103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2463103285Sikob break; 2464103285Sikob } 2465103285Sikob i++; 2466103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2467103285Sikob dbch->xferq.flag, 0, NULL); 2468103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2469103285Sikob if(dbch->pdb_tr != NULL){ 2470103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2471103285Sikob } else { 2472103285Sikob /* XXX should be rewritten in better way */ 2473103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2474103285Sikob } 2475103285Sikob dbch->pdb_tr = db_tr; 2476103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2477103285Sikob } 2478103285Sikob dbch->top = db_tr; 2479103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2480103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2481103285Sikob return; 2482103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2483103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2484103285Sikob dbch->top = db_tr; 2485103285Sikob fwohci_irx_enable(fc, dmach); 2486103285Sikob} 2487103285Sikob 2488103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2489103285Sikobstatic int 2490103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2491103285Sikob{ 2492103285Sikob int i; 2493103285Sikob 2494103285Sikob for( i = 4; i < hlen ; i+=4){ 2495103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2496103285Sikob } 2497103285Sikob 2498103285Sikob switch(fp->mode.common.tcode){ 2499103285Sikob case FWTCODE_RREQQ: 2500103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2501103285Sikob case FWTCODE_WRES: 2502103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2503103285Sikob case FWTCODE_WREQQ: 2504103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2505103285Sikob case FWTCODE_RREQB: 2506103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2507103285Sikob case FWTCODE_RRESQ: 2508103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2509103285Sikob case FWTCODE_WREQB: 2510103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2511103285Sikob + sizeof(u_int32_t); 2512103285Sikob case FWTCODE_LREQ: 2513103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2514103285Sikob + sizeof(u_int32_t); 2515103285Sikob case FWTCODE_RRESB: 2516103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2517103285Sikob + sizeof(u_int32_t); 2518103285Sikob case FWTCODE_LRES: 2519103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2520103285Sikob + sizeof(u_int32_t); 2521103285Sikob case FWOHCITCODE_PHY: 2522103285Sikob return 16; 2523103285Sikob } 2524103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2525103285Sikob return 0; 2526103285Sikob} 2527103285Sikob 2528106790Ssimokawastatic void 2529106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2530103285Sikob{ 2531103285Sikob struct fwohcidb_tr *db_tr; 2532103285Sikob int z = 1; 2533103285Sikob struct fw_pkt *fp; 2534103285Sikob u_int8_t *ld; 2535103285Sikob u_int32_t stat, off; 2536103285Sikob u_int spd; 2537103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2538103285Sikob int s; 2539103285Sikob caddr_t buf; 2540103285Sikob int resCount; 2541103285Sikob 2542103285Sikob if(&sc->arrq == dbch){ 2543103285Sikob off = OHCI_ARQOFF; 2544103285Sikob }else if(&sc->arrs == dbch){ 2545103285Sikob off = OHCI_ARSOFF; 2546103285Sikob }else{ 2547103285Sikob return; 2548103285Sikob } 2549103285Sikob 2550103285Sikob s = splfw(); 2551103285Sikob db_tr = dbch->top; 2552103285Sikob pcnt = 0; 2553103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2554103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2555103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2556103285Sikob resCount = db_tr->db[0].db.desc.count; 2557103285Sikob len = dbch->xferq.psize - resCount 2558103285Sikob - dbch->buf_offset; 2559103285Sikob while (len > 0 ) { 2560106789Ssimokawa if (count >= 0 && count-- == 0) 2561106789Ssimokawa goto out; 2562103285Sikob if(dbch->frag.buf != NULL){ 2563103285Sikob buf = dbch->frag.buf; 2564103285Sikob if (dbch->frag.plen < 0) { 2565103285Sikob /* incomplete header */ 2566103285Sikob int hlen; 2567103285Sikob 2568103285Sikob hlen = - dbch->frag.plen; 2569103285Sikob rlen = hlen - dbch->frag.len; 2570103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2571103285Sikob ld += rlen; 2572103285Sikob len -= rlen; 2573103285Sikob dbch->frag.len += rlen; 2574103285Sikob#if 0 2575103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2576103285Sikob#endif 2577103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2578103285Sikob dbch->frag.plen 2579103285Sikob = fwohci_get_plen(sc, fp, hlen); 2580103285Sikob if (dbch->frag.plen == 0) 2581103285Sikob goto out; 2582103285Sikob } 2583103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2584103285Sikob#if 0 2585103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2586103285Sikob#endif 2587103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2588103285Sikob rlen); 2589103285Sikob ld += rlen; 2590103285Sikob len -= rlen; 2591103285Sikob plen = dbch->frag.plen; 2592103285Sikob dbch->frag.buf = NULL; 2593103285Sikob dbch->frag.plen = 0; 2594103285Sikob dbch->frag.len = 0; 2595103285Sikob poff = 0; 2596103285Sikob }else{ 2597103285Sikob fp=(struct fw_pkt *)ld; 2598103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2599103285Sikob switch(fp->mode.common.tcode){ 2600103285Sikob case FWTCODE_RREQQ: 2601103285Sikob case FWTCODE_WRES: 2602103285Sikob case FWTCODE_WREQQ: 2603103285Sikob case FWTCODE_RRESQ: 2604103285Sikob case FWOHCITCODE_PHY: 2605103285Sikob hlen = 12; 2606103285Sikob break; 2607103285Sikob case FWTCODE_RREQB: 2608103285Sikob case FWTCODE_WREQB: 2609103285Sikob case FWTCODE_LREQ: 2610103285Sikob case FWTCODE_RRESB: 2611103285Sikob case FWTCODE_LRES: 2612103285Sikob hlen = 16; 2613103285Sikob break; 2614103285Sikob default: 2615103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2616103285Sikob goto out; 2617103285Sikob } 2618103285Sikob if (len >= hlen) { 2619103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2620103285Sikob if (plen == 0) 2621103285Sikob goto out; 2622103285Sikob plen = (plen + 3) & ~3; 2623103285Sikob len -= plen; 2624103285Sikob } else { 2625103285Sikob plen = -hlen; 2626103285Sikob len -= hlen; 2627103285Sikob } 2628103285Sikob if(resCount > 0 || len > 0){ 2629103285Sikob buf = malloc( dbch->xferq.psize, 2630103285Sikob M_DEVBUF, M_NOWAIT); 2631103285Sikob if(buf == NULL){ 2632103285Sikob printf("cannot malloc!\n"); 2633103285Sikob free(db_tr->buf, M_DEVBUF); 2634103285Sikob goto out; 2635103285Sikob } 2636103285Sikob bcopy(ld, buf, plen); 2637103285Sikob poff = 0; 2638103285Sikob dbch->frag.buf = NULL; 2639103285Sikob dbch->frag.plen = 0; 2640103285Sikob dbch->frag.len = 0; 2641103285Sikob }else if(len < 0){ 2642103285Sikob dbch->frag.buf = db_tr->buf; 2643103285Sikob if (plen < 0) { 2644103285Sikob#if 0 2645103285Sikob printf("plen < 0:" 2646103285Sikob "hlen: %d len: %d\n", 2647103285Sikob hlen, len); 2648103285Sikob#endif 2649103285Sikob dbch->frag.len = hlen + len; 2650103285Sikob dbch->frag.plen = -hlen; 2651103285Sikob } else { 2652103285Sikob dbch->frag.len = plen + len; 2653103285Sikob dbch->frag.plen = plen; 2654103285Sikob } 2655103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2656103285Sikob buf = NULL; 2657103285Sikob }else{ 2658103285Sikob buf = db_tr->buf; 2659103285Sikob poff = ld - (u_int8_t *)buf; 2660103285Sikob dbch->frag.buf = NULL; 2661103285Sikob dbch->frag.plen = 0; 2662103285Sikob dbch->frag.len = 0; 2663103285Sikob } 2664103285Sikob ld += plen; 2665103285Sikob } 2666103285Sikob if( buf != NULL){ 2667103285Sikob/* DMA result-code will be written at the tail of packet */ 2668103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2669103285Sikob spd = (stat >> 5) & 0x3; 2670103285Sikob stat &= 0x1f; 2671103285Sikob switch(stat){ 2672103285Sikob case FWOHCIEV_ACKPEND: 2673103285Sikob#if 0 2674103285Sikob printf("fwohci_arcv: ack pending..\n"); 2675103285Sikob#endif 2676103285Sikob /* fall through */ 2677103285Sikob case FWOHCIEV_ACKCOMPL: 2678103285Sikob if( poff != 0 ) 2679103285Sikob bcopy(buf+poff, buf, plen - 4); 2680103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2681103285Sikob break; 2682103285Sikob case FWOHCIEV_BUSRST: 2683103285Sikob free(buf, M_DEVBUF); 2684103285Sikob if (sc->fc.status != FWBUSRESET) 2685103285Sikob printf("got BUSRST packet!?\n"); 2686103285Sikob break; 2687103285Sikob default: 2688103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2689103285Sikob#if 0 /* XXX */ 2690103285Sikob goto out; 2691103285Sikob#endif 2692103285Sikob break; 2693103285Sikob } 2694103285Sikob } 2695103285Sikob pcnt ++; 2696103285Sikob }; 2697103285Sikobout: 2698103285Sikob if (resCount == 0) { 2699103285Sikob /* done on this buffer */ 2700103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2701103285Sikob dbch->xferq.flag, 0, NULL); 2702103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2703103285Sikob dbch->bottom = db_tr; 2704103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2705103285Sikob dbch->top = db_tr; 2706103285Sikob dbch->buf_offset = 0; 2707103285Sikob } else { 2708103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2709103285Sikob break; 2710103285Sikob } 2711103285Sikob /* XXX make sure DMA is not dead */ 2712103285Sikob } 2713103285Sikob#if 0 2714103285Sikob if (pcnt < 1) 2715103285Sikob printf("fwohci_arcv: no packets\n"); 2716103285Sikob#endif 2717103285Sikob splx(s); 2718103285Sikob} 2719