fwohci.c revision 108642
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 108642 2003-01-04 06:40:57Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45103285Sikob#include <sys/systm.h> 46103285Sikob#include <sys/types.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/mman.h> 49103285Sikob#include <sys/socket.h> 50103285Sikob#include <sys/socketvar.h> 51103285Sikob#include <sys/signalvar.h> 52103285Sikob#include <sys/malloc.h> 53103285Sikob#include <sys/uio.h> 54103285Sikob#include <sys/sockio.h> 55103285Sikob#include <sys/bus.h> 56103285Sikob#include <sys/kernel.h> 57103285Sikob#include <sys/conf.h> 58103285Sikob 59103285Sikob#include <machine/bus.h> 60103285Sikob#include <machine/resource.h> 61103285Sikob#include <sys/rman.h> 62103285Sikob 63103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64103285Sikob#include <machine/clock.h> 65103285Sikob#include <pci/pcivar.h> 66103285Sikob#include <pci/pcireg.h> 67103285Sikob#include <vm/vm.h> 68103285Sikob#include <vm/vm_extern.h> 69103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 70103285Sikob 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirebusreg.h> 73103285Sikob#include <dev/firewire/firewirereg.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77103285Sikob 78103285Sikob#undef OHCI_DEBUG 79106802Ssimokawa 80103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 81103285Sikob "STOR","LOAD","NOP ","STOP",}; 82103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83103285Sikob "UNDEF","REG","SYS","DEV"}; 84103285Sikobchar fwohcicode[32][0x20]={ 85103285Sikob "No stat","Undef","long","miss Ack err", 86103285Sikob "underrun","overrun","desc err", "data read err", 87103285Sikob "data write err","bus reset","timeout","tcode err", 88103285Sikob "Undef","Undef","unknown event","flushed", 89103285Sikob "Undef","ack complete","ack pend","Undef", 90103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 91103285Sikob "Undef","Undef","Undef","ack tardy", 92103285Sikob "Undef","ack data_err","ack type_err",""}; 93103285Sikob#define MAX_SPEED 2 94103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 95103285Sikobextern int maxrec[MAX_SPEED+1]; 96103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 126103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 127103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 128106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 132103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 142103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 145103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 148103285Sikobstatic void fwohci_timeout __P((void *)); 149103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 150103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 151103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 154103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160103285Sikob 161103285Sikob/* 162103285Sikob * memory allocated for DMA programs 163103285Sikob */ 164103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165103285Sikob 166103285Sikob/* #define NDB 1024 */ 167103285Sikob#define NDB FWMAXQUEUE 168103285Sikob#define NDVDB (DVBUF * NDB) 169103285Sikob 170103285Sikob#define OHCI_VERSION 0x00 171103285Sikob#define OHCI_CROMHDR 0x18 172103285Sikob#define OHCI_BUS_OPT 0x20 173103285Sikob#define OHCI_BUSIRMC (1 << 31) 174103285Sikob#define OHCI_BUSCMC (1 << 30) 175103285Sikob#define OHCI_BUSISC (1 << 29) 176103285Sikob#define OHCI_BUSBMC (1 << 28) 177103285Sikob#define OHCI_BUSPMC (1 << 27) 178103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 180103285Sikob 181103285Sikob#define OHCI_EUID_HI 0x24 182103285Sikob#define OHCI_EUID_LO 0x28 183103285Sikob 184103285Sikob#define OHCI_CROMPTR 0x34 185103285Sikob#define OHCI_HCCCTL 0x50 186103285Sikob#define OHCI_HCCCTLCLR 0x54 187103285Sikob#define OHCI_AREQHI 0x100 188103285Sikob#define OHCI_AREQHICLR 0x104 189103285Sikob#define OHCI_AREQLO 0x108 190103285Sikob#define OHCI_AREQLOCLR 0x10c 191103285Sikob#define OHCI_PREQHI 0x110 192103285Sikob#define OHCI_PREQHICLR 0x114 193103285Sikob#define OHCI_PREQLO 0x118 194103285Sikob#define OHCI_PREQLOCLR 0x11c 195103285Sikob#define OHCI_PREQUPPER 0x120 196103285Sikob 197103285Sikob#define OHCI_SID_BUF 0x64 198103285Sikob#define OHCI_SID_CNT 0x68 199103285Sikob#define OHCI_SID_CNT_MASK 0xffc 200103285Sikob 201103285Sikob#define OHCI_IT_STAT 0x90 202103285Sikob#define OHCI_IT_STATCLR 0x94 203103285Sikob#define OHCI_IT_MASK 0x98 204103285Sikob#define OHCI_IT_MASKCLR 0x9c 205103285Sikob 206103285Sikob#define OHCI_IR_STAT 0xa0 207103285Sikob#define OHCI_IR_STATCLR 0xa4 208103285Sikob#define OHCI_IR_MASK 0xa8 209103285Sikob#define OHCI_IR_MASKCLR 0xac 210103285Sikob 211103285Sikob#define OHCI_LNKCTL 0xe0 212103285Sikob#define OHCI_LNKCTLCLR 0xe4 213103285Sikob 214103285Sikob#define OHCI_PHYACCESS 0xec 215103285Sikob#define OHCI_CYCLETIMER 0xf0 216103285Sikob 217103285Sikob#define OHCI_DMACTL(off) (off) 218103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 219103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 220103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 221103285Sikob 222103285Sikob#define OHCI_ATQOFF 0x180 223103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 224103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227103285Sikob 228103285Sikob#define OHCI_ATSOFF 0x1a0 229103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 230103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233103285Sikob 234103285Sikob#define OHCI_ARQOFF 0x1c0 235103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 236103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239103285Sikob 240103285Sikob#define OHCI_ARSOFF 0x1e0 241103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 242103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245103285Sikob 246103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250103285Sikob 251103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256103285Sikob 257103285Sikobd_ioctl_t fwohci_ioctl; 258103285Sikob 259103285Sikob/* 260103285Sikob * Communication with PHY device 261103285Sikob */ 262106790Ssimokawastatic u_int32_t 263106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264103285Sikob{ 265103285Sikob u_int32_t fun; 266103285Sikob 267103285Sikob addr &= 0xf; 268103285Sikob data &= 0xff; 269103285Sikob 270103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 272103285Sikob DELAY(100); 273103285Sikob 274103285Sikob return(fwphy_rddata( sc, addr)); 275103285Sikob} 276103285Sikob 277103285Sikobstatic u_int32_t 278103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279103285Sikob{ 280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281103285Sikob int i; 282103285Sikob u_int32_t bm; 283103285Sikob 284103285Sikob#define OHCI_CSR_DATA 0x0c 285103285Sikob#define OHCI_CSR_COMP 0x10 286103285Sikob#define OHCI_CSR_CONT 0x14 287103285Sikob#define OHCI_BUS_MANAGER_ID 0 288103285Sikob 289103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 290103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293103285Sikob DELAY(100); 294103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 295107653Ssimokawa if((bm & 0x3f) == 0x3f) 296103285Sikob bm = node; 297107653Ssimokawa if (bootverbose) 298107653Ssimokawa device_printf(sc->fc.dev, 299107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300103285Sikob 301103285Sikob return(bm); 302103285Sikob} 303103285Sikob 304106790Ssimokawastatic u_int32_t 305106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 306103285Sikob{ 307108500Ssimokawa u_int32_t fun, stat; 308108500Ssimokawa u_int i, retry = 0; 309103285Sikob 310103285Sikob addr &= 0xf; 311108500Ssimokawa#define MAX_RETRY 100 312108500Ssimokawaagain: 313108500Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 316108500Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 318103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319103285Sikob break; 320103285Sikob DELAY(1000); 321103285Sikob } 322108500Ssimokawa if(i >= MAX_RETRY) { 323103285Sikob device_printf(sc->fc.dev, "cannot read phy\n"); 324108527Ssimokawa#if 0 325108500Ssimokawa return 0; /* XXX */ 326108527Ssimokawa#else 327108527Ssimokawa if (++retry < MAX_RETRY) { 328108527Ssimokawa DELAY(1000); 329108527Ssimokawa goto again; 330108527Ssimokawa } 331108527Ssimokawa#endif 332108500Ssimokawa } 333108500Ssimokawa /* Make sure that SCLK is started */ 334108500Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 335108500Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 336108500Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 337108500Ssimokawa if (++retry < MAX_RETRY) { 338108500Ssimokawa DELAY(1000); 339108500Ssimokawa goto again; 340108500Ssimokawa } 341108500Ssimokawa } 342108500Ssimokawa if (bootverbose || retry >= MAX_RETRY) 343108500Ssimokawa device_printf(sc->fc.dev, 344108500Ssimokawa "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345108500Ssimokawa#undef MAX_RETRY 346103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 347103285Sikob} 348103285Sikob/* Device specific ioctl. */ 349103285Sikobint 350103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351103285Sikob{ 352103285Sikob struct firewire_softc *sc; 353103285Sikob struct fwohci_softc *fc; 354103285Sikob int unit = DEV2UNIT(dev); 355103285Sikob int err = 0; 356103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357103285Sikob u_int32_t *dmach = (u_int32_t *) data; 358103285Sikob 359103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 360103285Sikob if(sc == NULL){ 361103285Sikob return(EINVAL); 362103285Sikob } 363103285Sikob fc = (struct fwohci_softc *)sc->fc; 364103285Sikob 365103285Sikob if (!data) 366103285Sikob return(EINVAL); 367103285Sikob 368103285Sikob switch (cmd) { 369103285Sikob case FWOHCI_WRREG: 370103285Sikob#define OHCI_MAX_REG 0x800 371103285Sikob if(reg->addr <= OHCI_MAX_REG){ 372103285Sikob OWRITE(fc, reg->addr, reg->data); 373103285Sikob reg->data = OREAD(fc, reg->addr); 374103285Sikob }else{ 375103285Sikob err = EINVAL; 376103285Sikob } 377103285Sikob break; 378103285Sikob case FWOHCI_RDREG: 379103285Sikob if(reg->addr <= OHCI_MAX_REG){ 380103285Sikob reg->data = OREAD(fc, reg->addr); 381103285Sikob }else{ 382103285Sikob err = EINVAL; 383103285Sikob } 384103285Sikob break; 385103285Sikob/* Read DMA descriptors for debug */ 386103285Sikob case DUMPDMA: 387103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 388103285Sikob dump_dma(fc, *dmach); 389103285Sikob dump_db(fc, *dmach); 390103285Sikob }else{ 391103285Sikob err = EINVAL; 392103285Sikob } 393103285Sikob break; 394103285Sikob default: 395103285Sikob break; 396103285Sikob } 397103285Sikob return err; 398103285Sikob} 399106790Ssimokawa 400108530Ssimokawastatic int 401108530Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402103285Sikob{ 403108530Ssimokawa u_int32_t reg, reg2; 404108530Ssimokawa int e1394a = 1; 405108530Ssimokawa/* 406108530Ssimokawa * probe PHY parameters 407108530Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 408108530Ssimokawa * 1. to probe maximum speed supported by the PHY and 409108530Ssimokawa * number of port supported by core-logic. 410108530Ssimokawa * It is not actually available port on your PC . 411108530Ssimokawa */ 412108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413108530Ssimokawa#if 0 414108530Ssimokawa /* XXX wait for SCLK. */ 415108530Ssimokawa DELAY(100000); 416108530Ssimokawa#endif 417108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418108530Ssimokawa 419108530Ssimokawa if((reg >> 5) != 7 ){ 420108530Ssimokawa sc->fc.mode &= ~FWPHYASYST; 421108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 422108530Ssimokawa sc->fc.speed = reg & FW_PHY_SPD >> 6; 423108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 424108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 425108530Ssimokawa sc->fc.speed, MAX_SPEED); 426108530Ssimokawa sc->fc.speed = MAX_SPEED; 427108530Ssimokawa } 428108530Ssimokawa sc->fc.maxrec = maxrec[sc->fc.speed]; 429108530Ssimokawa device_printf(dev, 430108530Ssimokawa "Link 1394 only %s, %d ports, maxrec %d bytes.\n", 431108530Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 432108530Ssimokawa }else{ 433108530Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 434108530Ssimokawa sc->fc.mode |= FWPHYASYST; 435108530Ssimokawa sc->fc.nport = reg & FW_PHY_NP; 436108530Ssimokawa sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 437108530Ssimokawa if (sc->fc.speed > MAX_SPEED) { 438108530Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 439108530Ssimokawa sc->fc.speed, MAX_SPEED); 440108530Ssimokawa sc->fc.speed = MAX_SPEED; 441108530Ssimokawa } 442108530Ssimokawa sc->fc.maxrec = maxrec[sc->fc.speed]; 443108530Ssimokawa device_printf(dev, 444108530Ssimokawa "Link 1394a available %s, %d ports, maxrec %d bytes.\n", 445108530Ssimokawa linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 446108530Ssimokawa 447108530Ssimokawa /* check programPhyEnable */ 448108530Ssimokawa reg2 = fwphy_rddata(sc, 5); 449108530Ssimokawa#if 0 450108530Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 451108530Ssimokawa#else /* XXX force to enable 1394a */ 452108530Ssimokawa if (e1394a) { 453108530Ssimokawa#endif 454108530Ssimokawa if (bootverbose) 455108530Ssimokawa device_printf(dev, 456108530Ssimokawa "Enable 1394a Enhancements\n"); 457108530Ssimokawa /* enable EAA EMC */ 458108530Ssimokawa reg2 |= 0x03; 459108530Ssimokawa /* set aPhyEnhanceEnable */ 460108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 461108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 462108530Ssimokawa } else { 463108530Ssimokawa /* for safe */ 464108530Ssimokawa reg2 &= ~0x83; 465108530Ssimokawa } 466108530Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 467108530Ssimokawa } 468108530Ssimokawa 469108530Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 470108530Ssimokawa if((reg >> 5) == 7 ){ 471108530Ssimokawa reg = fwphy_rddata(sc, 4); 472108530Ssimokawa reg |= 1 << 6; 473108530Ssimokawa fwphy_wrdata(sc, 4, reg); 474108530Ssimokawa reg = fwphy_rddata(sc, 4); 475108530Ssimokawa } 476108530Ssimokawa return 0; 477108530Ssimokawa} 478108530Ssimokawa 479108530Ssimokawa 480108530Ssimokawavoid 481108530Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 482108530Ssimokawa{ 483103285Sikob int i; 484103285Sikob u_int32_t reg, reg2; 485103285Sikob struct fwohcidb_tr *db_tr; 486103285Sikob 487108530Ssimokawa/* Disable interrupt */ 488108530Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 489108530Ssimokawa 490108530Ssimokawa/* Now stopping all DMA channel */ 491108530Ssimokawa OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 492108530Ssimokawa OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 493108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 494108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 495108530Ssimokawa 496108530Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, ~0); 497108530Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 498108530Ssimokawa OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 499108530Ssimokawa OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 500108530Ssimokawa } 501108530Ssimokawa 502108530Ssimokawa/* FLUSH FIFO and reset Transmitter/Reciever */ 503108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 504108530Ssimokawa if (bootverbose) 505108530Ssimokawa device_printf(dev, "resetting OHCI..."); 506108530Ssimokawa i = 0; 507108530Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 508108530Ssimokawa if (i++ > 100) break; 509108530Ssimokawa DELAY(1000); 510108530Ssimokawa } 511108530Ssimokawa if (bootverbose) 512108530Ssimokawa printf("done (loop=%d)\n", i); 513108530Ssimokawa 514108530Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 515108530Ssimokawa reg2 = reg | OHCI_BUSFNC; 516108530Ssimokawa /* XXX */ 517108530Ssimokawa if (((reg & 0x0000f000) >> 12) < 10) 518108530Ssimokawa reg2 = (reg2 & 0xffff0fff) | (10 << 12); 519108530Ssimokawa if (bootverbose) 520108530Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 521108530Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 522108530Ssimokawa 523108530Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 524108530Ssimokawa OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 525108530Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 526108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 527108530Ssimokawa 528108530Ssimokawa fwohci_probe_phy(sc, dev); 529108530Ssimokawa 530108642Ssimokawa OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 531108530Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 532108530Ssimokawa 533108530Ssimokawa /* enable link */ 534108530Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 535108530Ssimokawa fw_busreset(&sc->fc); 536108642Ssimokawa 537108642Ssimokawa /* force to start rx dma */ 538108642Ssimokawa sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 539108642Ssimokawa sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; 540108530Ssimokawa fwohci_rx_enable(sc, &sc->arrq); 541108530Ssimokawa fwohci_rx_enable(sc, &sc->arrs); 542108530Ssimokawa 543108530Ssimokawa for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 544108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 545108530Ssimokawa db_tr->xfer = NULL; 546108530Ssimokawa } 547108530Ssimokawa for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 548108530Ssimokawa i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 549108530Ssimokawa db_tr->xfer = NULL; 550108530Ssimokawa } 551108530Ssimokawa 552108530Ssimokawa OWRITE(sc, FWOHCI_RETRY, 553108530Ssimokawa (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ; 554108530Ssimokawa OWRITE(sc, FWOHCI_INTMASK, 555108530Ssimokawa OHCI_INT_ERR | OHCI_INT_PHY_SID 556108530Ssimokawa | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 557108530Ssimokawa | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 558108530Ssimokawa | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 559108530Ssimokawa fwohci_set_intr(&sc->fc, 1); 560108530Ssimokawa 561108530Ssimokawa OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 562108530Ssimokawa OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 563108530Ssimokawa} 564108530Ssimokawa 565108530Ssimokawaint 566108530Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 567108530Ssimokawa{ 568108530Ssimokawa int i; 569108530Ssimokawa u_int32_t reg; 570108530Ssimokawa 571103285Sikob reg = OREAD(sc, OHCI_VERSION); 572103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 573103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 574103285Sikob 575103285Sikob/* XXX: Available Isochrounous DMA channel probe */ 576103285Sikob for( i = 0 ; i < 0x20 ; i ++ ){ 577103285Sikob OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 578103285Sikob reg = OREAD(sc, OHCI_IRCTL(i)); 579103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 580103285Sikob OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 581103285Sikob reg = OREAD(sc, OHCI_ITCTL(i)); 582103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 583103285Sikob } 584103285Sikob sc->fc.nisodma = i; 585103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 586103285Sikob 587103285Sikob sc->fc.arq = &sc->arrq.xferq; 588103285Sikob sc->fc.ars = &sc->arrs.xferq; 589103285Sikob sc->fc.atq = &sc->atrq.xferq; 590103285Sikob sc->fc.ats = &sc->atrs.xferq; 591103285Sikob 592103285Sikob sc->arrq.xferq.start = NULL; 593103285Sikob sc->arrs.xferq.start = NULL; 594103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 595103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 596103285Sikob 597103285Sikob sc->arrq.xferq.drain = NULL; 598103285Sikob sc->arrs.xferq.drain = NULL; 599103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 600103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 601103285Sikob 602103285Sikob sc->arrq.ndesc = 1; 603103285Sikob sc->arrs.ndesc = 1; 604103285Sikob sc->atrq.ndesc = 10; 605103285Sikob sc->atrs.ndesc = 10 / 2; 606103285Sikob 607103285Sikob sc->arrq.ndb = NDB; 608103285Sikob sc->arrs.ndb = NDB / 2; 609103285Sikob sc->atrq.ndb = NDB; 610103285Sikob sc->atrs.ndb = NDB / 2; 611103285Sikob 612103285Sikob sc->arrq.dummy = NULL; 613103285Sikob sc->arrs.dummy = NULL; 614103285Sikob sc->atrq.dummy = NULL; 615103285Sikob sc->atrs.dummy = NULL; 616103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 617103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 618103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 619103285Sikob sc->it[i].ndb = 0; 620103285Sikob sc->ir[i].ndb = 0; 621103285Sikob } 622103285Sikob 623103285Sikob sc->fc.tcode = tinfo; 624103285Sikob 625103285Sikob sc->cromptr = (u_int32_t *) 626103285Sikob contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 627103285Sikob 628103285Sikob if(sc->cromptr == NULL){ 629108527Ssimokawa device_printf(dev, "cromptr alloc failed."); 630103285Sikob return ENOMEM; 631103285Sikob } 632103285Sikob sc->fc.dev = dev; 633103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 634103285Sikob 635103285Sikob sc->fc.config_rom[1] = 0x31333934; 636103285Sikob sc->fc.config_rom[2] = 0xf000a002; 637103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 638103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 639103285Sikob sc->fc.config_rom[5] = 0; 640103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 641103285Sikob 642103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 643103285Sikob 644103285Sikob 645103285Sikob/* SID recieve buffer must allign 2^11 */ 646103285Sikob#define OHCI_SIDSIZE (1 << 11) 647103285Sikob sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 648103285Sikob 0x10000, 0xffffffff, OHCI_SIDSIZE); 649108527Ssimokawa if (sc->fc.sid_buf == NULL) { 650108527Ssimokawa device_printf(dev, "sid_buf alloc failed.\n"); 651108527Ssimokawa return ENOMEM; 652108527Ssimokawa } 653108527Ssimokawa 654108530Ssimokawa 655103285Sikob fwohci_db_init(&sc->arrq); 656108527Ssimokawa if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 657108527Ssimokawa return ENOMEM; 658108527Ssimokawa 659103285Sikob fwohci_db_init(&sc->arrs); 660108527Ssimokawa if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 661108527Ssimokawa return ENOMEM; 662103285Sikob 663103285Sikob fwohci_db_init(&sc->atrq); 664108527Ssimokawa if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 665108527Ssimokawa return ENOMEM; 666108527Ssimokawa 667103285Sikob fwohci_db_init(&sc->atrs); 668108527Ssimokawa if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 669108527Ssimokawa return ENOMEM; 670103285Sikob 671103285Sikob reg = OREAD(sc, FWOHCIGUID_H); 672103285Sikob for( i = 0 ; i < 4 ; i ++){ 673103285Sikob sc->fc.eui[3 - i] = reg & 0xff; 674103285Sikob reg = reg >> 8; 675103285Sikob } 676103285Sikob reg = OREAD(sc, FWOHCIGUID_L); 677103285Sikob for( i = 0 ; i < 4 ; i ++){ 678103285Sikob sc->fc.eui[7 - i] = reg & 0xff; 679103285Sikob reg = reg >> 8; 680103285Sikob } 681103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 682103285Sikob sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 683103285Sikob sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 684103285Sikob sc->fc.ioctl = fwohci_ioctl; 685103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 686103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 687103285Sikob sc->fc.ibr = fwohci_ibr; 688103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 689103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 690103285Sikob 691103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 692103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 693103285Sikob sc->fc.irx_post = fwohci_irx_post; 694103285Sikob sc->fc.itx_post = NULL; 695103285Sikob sc->fc.timeout = fwohci_timeout; 696103285Sikob sc->fc.poll = fwohci_poll; 697103285Sikob sc->fc.set_intr = fwohci_set_intr; 698106790Ssimokawa 699108530Ssimokawa fw_init(&sc->fc); 700108530Ssimokawa fwohci_reset(sc, dev); 701103285Sikob 702108530Ssimokawa return 0; 703103285Sikob} 704106790Ssimokawa 705106790Ssimokawavoid 706106790Ssimokawafwohci_timeout(void *arg) 707103285Sikob{ 708103285Sikob struct fwohci_softc *sc; 709103285Sikob 710103285Sikob sc = (struct fwohci_softc *)arg; 711103285Sikob sc->fc.timeouthandle = timeout(fwohci_timeout, 712103285Sikob (void *)sc, FW_XFERTIMEOUT * hz * 10); 713103285Sikob} 714106790Ssimokawa 715106790Ssimokawau_int32_t 716106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 717103285Sikob{ 718103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 719103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 720103285Sikob} 721103285Sikob 722103285Sikob#define LAST_DB(dbtr, db) do { \ 723103285Sikob struct fwohcidb_tr *_dbtr = (dbtr); \ 724103285Sikob int _cnt = _dbtr->dbcnt; \ 725103285Sikob db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 726103285Sikob} while (0) 727103285Sikob 728108527Ssimokawaint 729108527Ssimokawafwohci_detach(struct fwohci_softc *sc, device_t dev) 730108527Ssimokawa{ 731108527Ssimokawa int i; 732108527Ssimokawa 733108527Ssimokawa if (sc->fc.sid_buf != NULL) 734108527Ssimokawa contigfree((void *)(uintptr_t)sc->fc.sid_buf, 735108527Ssimokawa OHCI_SIDSIZE, M_DEVBUF); 736108527Ssimokawa if (sc->cromptr != NULL) 737108527Ssimokawa contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF); 738108527Ssimokawa 739108527Ssimokawa fwohci_db_free(&sc->arrq); 740108527Ssimokawa fwohci_db_free(&sc->arrs); 741108527Ssimokawa 742108527Ssimokawa fwohci_db_free(&sc->atrq); 743108527Ssimokawa fwohci_db_free(&sc->atrs); 744108527Ssimokawa 745108527Ssimokawa for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 746108527Ssimokawa fwohci_db_free(&sc->it[i]); 747108527Ssimokawa fwohci_db_free(&sc->ir[i]); 748108527Ssimokawa } 749108527Ssimokawa 750108527Ssimokawa return 0; 751108527Ssimokawa} 752108527Ssimokawa 753106790Ssimokawastatic void 754106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 755103285Sikob{ 756103285Sikob int i, s; 757103285Sikob int tcode, hdr_len, hdr_off, len; 758103285Sikob int fsegment = -1; 759103285Sikob u_int32_t off; 760103285Sikob struct fw_xfer *xfer; 761103285Sikob struct fw_pkt *fp; 762103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 763103285Sikob struct fwohcidb_tr *db_tr; 764103285Sikob volatile struct fwohcidb *db; 765103285Sikob struct mbuf *m; 766103285Sikob struct tcode_info *info; 767103285Sikob 768103285Sikob if(&sc->atrq == dbch){ 769103285Sikob off = OHCI_ATQOFF; 770103285Sikob }else if(&sc->atrs == dbch){ 771103285Sikob off = OHCI_ATSOFF; 772103285Sikob }else{ 773103285Sikob return; 774103285Sikob } 775103285Sikob 776103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 777103285Sikob return; 778103285Sikob 779103285Sikob s = splfw(); 780103285Sikob db_tr = dbch->top; 781103285Sikobtxloop: 782103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 783103285Sikob if(xfer == NULL){ 784103285Sikob goto kick; 785103285Sikob } 786103285Sikob if(dbch->xferq.queued == 0 ){ 787103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 788103285Sikob } 789103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 790103285Sikob db_tr->xfer = xfer; 791103285Sikob xfer->state = FWXF_START; 792103285Sikob dbch->xferq.packets++; 793103285Sikob 794103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 795103285Sikob tcode = fp->mode.common.tcode; 796103285Sikob 797103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 798103285Sikob info = &tinfo[tcode]; 799103285Sikob hdr_len = hdr_off = info->hdr_len; 800103285Sikob /* fw_asyreq must pass valid send.len */ 801103285Sikob len = xfer->send.len; 802103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 803103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 804103285Sikob } 805103285Sikob ohcifp->mode.common.spd = xfer->spd; 806103285Sikob if (tcode == FWTCODE_STREAM ){ 807103285Sikob hdr_len = 8; 808103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 809103285Sikob } else if (tcode == FWTCODE_PHY) { 810103285Sikob hdr_len = 12; 811103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 812103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 813103285Sikob ohcifp->mode.common.spd = 0; 814103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 815103285Sikob } else { 816103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 817103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 818103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 819103285Sikob } 820103285Sikob db = &db_tr->db[0]; 821103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 822103285Sikob db->db.desc.status = 0; 823103285Sikob/* Specify bound timer of asy. responce */ 824103285Sikob if(&sc->atrs == dbch){ 825103285Sikob db->db.desc.count 826103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 827103285Sikob } 828103285Sikob 829103285Sikob db_tr->dbcnt = 2; 830103285Sikob db = &db_tr->db[db_tr->dbcnt]; 831103285Sikob if(len > hdr_off){ 832103285Sikob if (xfer->mbuf == NULL) { 833103285Sikob db->db.desc.addr 834103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 835103285Sikob db->db.desc.cmd 836103285Sikob = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 837103285Sikob db->db.desc.status = 0; 838103285Sikob 839103285Sikob db_tr->dbcnt++; 840103285Sikob } else { 841103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 842103285Sikob m = xfer->mbuf; 843103285Sikob do { 844103285Sikob db->db.desc.addr 845103285Sikob = vtophys(mtod(m, caddr_t)); 846103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 847103285Sikob db->db.desc.status = 0; 848103285Sikob db++; 849103285Sikob db_tr->dbcnt++; 850103285Sikob m = m->m_next; 851103285Sikob } while (m != NULL); 852103285Sikob } 853103285Sikob } 854103285Sikob /* last db */ 855103285Sikob LAST_DB(db_tr, db); 856103285Sikob db->db.desc.cmd |= OHCI_OUTPUT_LAST 857103285Sikob | OHCI_INTERRUPT_ALWAYS 858103285Sikob | OHCI_BRANCH_ALWAYS; 859103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 860103285Sikob 861103285Sikob if(fsegment == -1 ) 862103285Sikob fsegment = db_tr->dbcnt; 863103285Sikob if (dbch->pdb_tr != NULL) { 864103285Sikob LAST_DB(dbch->pdb_tr, db); 865103285Sikob db->db.desc.depend |= db_tr->dbcnt; 866103285Sikob } 867103285Sikob dbch->pdb_tr = db_tr; 868103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 869103285Sikob if(db_tr != dbch->bottom){ 870103285Sikob goto txloop; 871103285Sikob } else { 872107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 873103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 874103285Sikob } 875103285Sikobkick: 876103285Sikob if (firewire_debug) printf("kick\n"); 877103285Sikob /* kick asy q */ 878103285Sikob 879103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 880103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 881103285Sikob } else { 882107653Ssimokawa if (bootverbose) 883107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 884103285Sikob OREAD(sc, OHCI_DMACTL(off))); 885103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 886103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 887103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 888103285Sikob } 889106790Ssimokawa 890103285Sikob dbch->top = db_tr; 891103285Sikob splx(s); 892103285Sikob return; 893103285Sikob} 894106790Ssimokawa 895106790Ssimokawastatic void 896106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 897103285Sikob{ 898103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 899103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 900103285Sikob return; 901103285Sikob} 902106790Ssimokawa 903106790Ssimokawastatic void 904106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 905103285Sikob{ 906103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 907103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 908103285Sikob return; 909103285Sikob} 910106790Ssimokawa 911106790Ssimokawastatic void 912106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 913103285Sikob{ 914103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 915103285Sikob fwohci_start( sc, &(sc->atrq)); 916103285Sikob return; 917103285Sikob} 918106790Ssimokawa 919106790Ssimokawastatic void 920106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 921103285Sikob{ 922103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 923103285Sikob fwohci_start( sc, &(sc->atrs)); 924103285Sikob return; 925103285Sikob} 926106790Ssimokawa 927106790Ssimokawavoid 928106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 929103285Sikob{ 930103285Sikob int s, err = 0; 931103285Sikob struct fwohcidb_tr *tr; 932103285Sikob volatile struct fwohcidb *db; 933103285Sikob struct fw_xfer *xfer; 934103285Sikob u_int32_t off; 935103285Sikob u_int stat; 936103285Sikob int packets; 937103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 938103285Sikob if(&sc->atrq == dbch){ 939103285Sikob off = OHCI_ATQOFF; 940103285Sikob }else if(&sc->atrs == dbch){ 941103285Sikob off = OHCI_ATSOFF; 942103285Sikob }else{ 943103285Sikob return; 944103285Sikob } 945103285Sikob s = splfw(); 946103285Sikob tr = dbch->bottom; 947103285Sikob packets = 0; 948103285Sikob while(dbch->xferq.queued > 0){ 949103285Sikob LAST_DB(tr, db); 950103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 951103285Sikob if (fc->status != FWBUSRESET) 952103285Sikob /* maybe out of order?? */ 953103285Sikob goto out; 954103285Sikob } 955103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 956103285Sikob#ifdef OHCI_DEBUG 957103285Sikob dump_dma(sc, ch); 958103285Sikob dump_db(sc, ch); 959103285Sikob#endif 960103285Sikob/* Stop DMA */ 961103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 962103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 963103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 964103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 965103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 966103285Sikob } 967103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 968103285Sikob switch(stat){ 969103285Sikob case FWOHCIEV_ACKCOMPL: 970103285Sikob case FWOHCIEV_ACKPEND: 971103285Sikob err = 0; 972103285Sikob break; 973103285Sikob case FWOHCIEV_ACKBSA: 974103285Sikob case FWOHCIEV_ACKBSB: 975103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 976103285Sikob case FWOHCIEV_ACKBSX: 977103285Sikob err = EBUSY; 978103285Sikob break; 979103285Sikob case FWOHCIEV_FLUSHED: 980103285Sikob case FWOHCIEV_ACKTARD: 981103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 982103285Sikob err = EAGAIN; 983103285Sikob break; 984103285Sikob case FWOHCIEV_MISSACK: 985103285Sikob case FWOHCIEV_UNDRRUN: 986103285Sikob case FWOHCIEV_OVRRUN: 987103285Sikob case FWOHCIEV_DESCERR: 988103285Sikob case FWOHCIEV_DTRDERR: 989103285Sikob case FWOHCIEV_TIMEOUT: 990103285Sikob case FWOHCIEV_TCODERR: 991103285Sikob case FWOHCIEV_UNKNOWN: 992103285Sikob case FWOHCIEV_ACKDERR: 993103285Sikob case FWOHCIEV_ACKTERR: 994103285Sikob default: 995103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 996103285Sikob stat, fwohcicode[stat]); 997103285Sikob err = EINVAL; 998103285Sikob break; 999103285Sikob } 1000103285Sikob if(tr->xfer != NULL){ 1001103285Sikob xfer = tr->xfer; 1002103285Sikob xfer->state = FWXF_SENT; 1003103285Sikob if(err == EBUSY && fc->status != FWBUSRESET){ 1004103285Sikob xfer->state = FWXF_BUSY; 1005103285Sikob switch(xfer->act_type){ 1006103285Sikob case FWACT_XFER: 1007103285Sikob xfer->resp = err; 1008103285Sikob if(xfer->retry_req != NULL){ 1009103285Sikob xfer->retry_req(xfer); 1010103285Sikob } 1011103285Sikob break; 1012103285Sikob default: 1013103285Sikob break; 1014103285Sikob } 1015103285Sikob } else if( stat != FWOHCIEV_ACKPEND){ 1016103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1017103285Sikob xfer->state = FWXF_SENTERR; 1018103285Sikob xfer->resp = err; 1019103285Sikob switch(xfer->act_type){ 1020103285Sikob case FWACT_XFER: 1021103285Sikob fw_xfer_done(xfer); 1022103285Sikob break; 1023103285Sikob default: 1024103285Sikob break; 1025103285Sikob } 1026103285Sikob } 1027103285Sikob dbch->xferq.queued --; 1028103285Sikob } 1029103285Sikob tr->xfer = NULL; 1030103285Sikob 1031103285Sikob packets ++; 1032103285Sikob tr = STAILQ_NEXT(tr, link); 1033103285Sikob dbch->bottom = tr; 1034103285Sikob } 1035103285Sikobout: 1036103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1037103285Sikob printf("make free slot\n"); 1038103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1039103285Sikob fwohci_start(sc, dbch); 1040103285Sikob } 1041103285Sikob splx(s); 1042103285Sikob} 1043106790Ssimokawa 1044106790Ssimokawastatic void 1045106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1046103285Sikob{ 1047103285Sikob int i, s; 1048103285Sikob struct fwohcidb_tr *tr; 1049103285Sikob 1050103285Sikob if(xfer->state != FWXF_START) return; 1051103285Sikob 1052103285Sikob s = splfw(); 1053103285Sikob tr = dbch->bottom; 1054103285Sikob for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1055103285Sikob if(tr->xfer == xfer){ 1056103285Sikob s = splfw(); 1057103285Sikob tr->xfer = NULL; 1058103285Sikob dbch->xferq.queued --; 1059103285Sikob#if 1 1060103285Sikob /* XXX */ 1061103285Sikob if (tr == dbch->bottom) 1062103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1063103285Sikob#endif 1064103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1065103285Sikob printf("fwohci_drain: make slot\n"); 1066103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1067103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1068103285Sikob } 1069103285Sikob 1070103285Sikob splx(s); 1071103285Sikob break; 1072103285Sikob } 1073103285Sikob tr = STAILQ_NEXT(tr, link); 1074103285Sikob } 1075103285Sikob splx(s); 1076103285Sikob return; 1077103285Sikob} 1078103285Sikob 1079106790Ssimokawastatic void 1080106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1081103285Sikob{ 1082103285Sikob struct fwohcidb_tr *db_tr; 1083103285Sikob int idb; 1084103285Sikob 1085108527Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1086108527Ssimokawa return; 1087108527Ssimokawa 1088103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1089103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1090103285Sikob idb < dbch->ndb; 1091103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1092108527Ssimokawa if (db_tr->buf != NULL) { 1093108527Ssimokawa free(db_tr->buf, M_DEVBUF); 1094108527Ssimokawa db_tr->buf = NULL; 1095108527Ssimokawa } 1096103285Sikob } 1097103285Sikob } 1098103285Sikob dbch->ndb = 0; 1099103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1100103285Sikob contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1101103285Sikob sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1102103285Sikob free(db_tr, M_DEVBUF); 1103103285Sikob STAILQ_INIT(&dbch->db_trq); 1104108527Ssimokawa dbch->flags &= ~FWOHCI_DBCH_INIT; 1105103285Sikob} 1106106790Ssimokawa 1107106790Ssimokawastatic void 1108106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1109103285Sikob{ 1110103285Sikob int idb; 1111103285Sikob struct fwohcidb *db; 1112103285Sikob struct fwohcidb_tr *db_tr; 1113108642Ssimokawa 1114108642Ssimokawa 1115108642Ssimokawa if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1116108642Ssimokawa goto out; 1117108642Ssimokawa 1118103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1119103285Sikob /* DB entry must start at 16 bytes bounary. */ 1120103285Sikob STAILQ_INIT(&dbch->db_trq); 1121103285Sikob db_tr = (struct fwohcidb_tr *) 1122103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1123108527Ssimokawa M_DEVBUF, M_DONTWAIT | M_ZERO); 1124103285Sikob if(db_tr == NULL){ 1125108642Ssimokawa printf("fwohci_db_init: malloc failed\n"); 1126103285Sikob return; 1127103285Sikob } 1128103285Sikob db = (struct fwohcidb *) 1129103285Sikob contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1130103285Sikob M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1131103285Sikob if(db == NULL){ 1132108642Ssimokawa printf("fwohci_db_init: contigmalloc failed\n"); 1133108527Ssimokawa free(db_tr, M_DEVBUF); 1134103285Sikob return; 1135103285Sikob } 1136103285Sikob bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1137103285Sikob /* Attach DB to DMA ch. */ 1138103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1139103285Sikob db_tr->dbcnt = 0; 1140103285Sikob db_tr->db = &db[idb * dbch->ndesc]; 1141103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1142108530Ssimokawa if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1143108530Ssimokawa dbch->xferq.bnpacket != 0) { 1144108530Ssimokawa /* XXX what thoes for? */ 1145108530Ssimokawa if (idb % dbch->xferq.bnpacket == 0) 1146108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1147108530Ssimokawa ].start = (caddr_t)db_tr; 1148108530Ssimokawa if ((idb + 1) % dbch->xferq.bnpacket == 0) 1149108530Ssimokawa dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1150108530Ssimokawa ].end = (caddr_t)db_tr; 1151103285Sikob } 1152103285Sikob db_tr++; 1153103285Sikob } 1154103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1155103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1156108642Ssimokawaout: 1157108642Ssimokawa dbch->frag.buf = NULL; 1158108642Ssimokawa dbch->frag.len = 0; 1159108642Ssimokawa dbch->frag.plen = 0; 1160108642Ssimokawa dbch->xferq.queued = 0; 1161108642Ssimokawa dbch->pdb_tr = NULL; 1162103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1163103285Sikob dbch->bottom = dbch->top; 1164108527Ssimokawa dbch->flags = FWOHCI_DBCH_INIT; 1165103285Sikob} 1166106790Ssimokawa 1167106790Ssimokawastatic int 1168106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1169103285Sikob{ 1170103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1171103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1172103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1173103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1174103285Sikob fwohci_db_free(&sc->it[dmach]); 1175103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1176103285Sikob return 0; 1177103285Sikob} 1178106790Ssimokawa 1179106790Ssimokawastatic int 1180106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1181103285Sikob{ 1182103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1183103285Sikob 1184103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1185103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1186103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1187103285Sikob if(sc->ir[dmach].dummy != NULL){ 1188103285Sikob free(sc->ir[dmach].dummy, M_DEVBUF); 1189103285Sikob } 1190103285Sikob sc->ir[dmach].dummy = NULL; 1191103285Sikob fwohci_db_free(&sc->ir[dmach]); 1192103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1193103285Sikob return 0; 1194103285Sikob} 1195106790Ssimokawa 1196106790Ssimokawastatic void 1197106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1198103285Sikob{ 1199103285Sikob qld[0] = ntohl(qld[0]); 1200103285Sikob return; 1201103285Sikob} 1202106790Ssimokawa 1203106790Ssimokawastatic int 1204106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1205103285Sikob{ 1206103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1207103285Sikob int err = 0; 1208103285Sikob unsigned short tag, ich; 1209103285Sikob 1210103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1211103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1212103285Sikob 1213103285Sikob#if 0 1214103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1215103285Sikob wakeup(fc->ir[dmach]); 1216103285Sikob return err; 1217103285Sikob } 1218103285Sikob#endif 1219103285Sikob 1220103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1221103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1222103285Sikob sc->ir[dmach].xferq.queued = 0; 1223103285Sikob sc->ir[dmach].ndb = NDB; 1224103285Sikob sc->ir[dmach].xferq.psize = FWPMAX_S400; 1225103285Sikob sc->ir[dmach].ndesc = 1; 1226103285Sikob fwohci_db_init(&sc->ir[dmach]); 1227103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1228103285Sikob } 1229103285Sikob if(err){ 1230103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1231103285Sikob return err; 1232103285Sikob } 1233103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1234103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1235103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1236103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1237103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1238103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1239103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1240103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1241103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1242103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1243103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1244103285Sikob } 1245103285Sikob return err; 1246103285Sikob} 1247106790Ssimokawa 1248106790Ssimokawastatic int 1249106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1250103285Sikob{ 1251103285Sikob int err = 0; 1252103285Sikob int idb, z, i, dmach = 0; 1253103285Sikob u_int32_t off = NULL; 1254103285Sikob struct fwohcidb_tr *db_tr; 1255103285Sikob 1256103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1257103285Sikob err = EINVAL; 1258103285Sikob return err; 1259103285Sikob } 1260103285Sikob z = dbch->ndesc; 1261103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1262103285Sikob if( &sc->it[dmach] == dbch){ 1263103285Sikob off = OHCI_ITOFF(dmach); 1264103285Sikob break; 1265103285Sikob } 1266103285Sikob } 1267103285Sikob if(off == NULL){ 1268103285Sikob err = EINVAL; 1269103285Sikob return err; 1270103285Sikob } 1271103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1272103285Sikob return err; 1273103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1274103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1275103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1276103285Sikob } 1277103285Sikob db_tr = dbch->top; 1278103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1279103285Sikob fwohci_add_tx_buf(db_tr, 1280103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1281103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1282103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1283103285Sikob break; 1284103285Sikob } 1285103285Sikob db_tr->db[0].db.desc.depend 1286103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1287103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1288103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1289103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1290103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1291103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1292103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1293103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 1294103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1295103285Sikob ~0xf; 1296103285Sikob } 1297103285Sikob } 1298103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1299103285Sikob } 1300103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1301103285Sikob return err; 1302103285Sikob} 1303106790Ssimokawa 1304106790Ssimokawastatic int 1305106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1306103285Sikob{ 1307103285Sikob int err = 0; 1308103285Sikob int idb, z, i, dmach = 0; 1309103285Sikob u_int32_t off = NULL; 1310103285Sikob struct fwohcidb_tr *db_tr; 1311103285Sikob 1312103285Sikob z = dbch->ndesc; 1313103285Sikob if(&sc->arrq == dbch){ 1314103285Sikob off = OHCI_ARQOFF; 1315103285Sikob }else if(&sc->arrs == dbch){ 1316103285Sikob off = OHCI_ARSOFF; 1317103285Sikob }else{ 1318103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1319103285Sikob if( &sc->ir[dmach] == dbch){ 1320103285Sikob off = OHCI_IROFF(dmach); 1321103285Sikob break; 1322103285Sikob } 1323103285Sikob } 1324103285Sikob } 1325103285Sikob if(off == NULL){ 1326103285Sikob err = EINVAL; 1327103285Sikob return err; 1328103285Sikob } 1329103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1330103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1331103285Sikob return err; 1332103285Sikob }else{ 1333103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1334103285Sikob err = EBUSY; 1335103285Sikob return err; 1336103285Sikob } 1337103285Sikob } 1338103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1339108642Ssimokawa dbch->top = STAILQ_FIRST(&dbch->db_trq); 1340103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1341103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1342103285Sikob } 1343103285Sikob db_tr = dbch->top; 1344103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1345103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1346103285Sikob fwohci_add_rx_buf(db_tr, 1347103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1348103285Sikob }else{ 1349103285Sikob fwohci_add_rx_buf(db_tr, 1350103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1351103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1352103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1353103285Sikob } 1354103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1355103285Sikob break; 1356103285Sikob } 1357103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1358103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1359103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1360103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1361103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1362103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1363103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1364103285Sikob ~0xf; 1365103285Sikob } 1366103285Sikob } 1367103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1368103285Sikob } 1369103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1370103285Sikob dbch->buf_offset = 0; 1371103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1372103285Sikob return err; 1373103285Sikob }else{ 1374103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1375103285Sikob } 1376103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1377103285Sikob return err; 1378103285Sikob} 1379106790Ssimokawa 1380106790Ssimokawastatic int 1381106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1382103285Sikob{ 1383103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1384103285Sikob int err = 0; 1385103285Sikob unsigned short tag, ich; 1386103285Sikob struct fwohci_dbch *dbch; 1387103285Sikob struct fw_pkt *fp; 1388103285Sikob struct fwohcidb_tr *db_tr; 1389103285Sikob 1390103285Sikob tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1391103285Sikob ich = sc->it[dmach].xferq.flag & 0x3f; 1392103285Sikob dbch = &sc->it[dmach]; 1393103285Sikob if(dbch->ndb == 0){ 1394103285Sikob dbch->xferq.queued = 0; 1395103285Sikob dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1396103285Sikob dbch->ndesc = 3; 1397103285Sikob fwohci_db_init(dbch); 1398103285Sikob err = fwohci_tx_enable(sc, dbch); 1399103285Sikob } 1400103285Sikob if(err) 1401103285Sikob return err; 1402103285Sikob if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1403103285Sikob if(dbch->xferq.stdma2 != NULL){ 1404103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1405103285Sikob ((struct fwohcidb_tr *) 1406103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1407103285Sikob |= OHCI_BRANCH_ALWAYS; 1408103285Sikob ((struct fwohcidb_tr *) 1409103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1410103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1411103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1412103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1413103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1414103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1415103285Sikob } 1416103285Sikob }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1417103285Sikob fw_tbuf_update(&sc->fc, dmach, 0); 1418103285Sikob if(dbch->xferq.stdma == NULL){ 1419103285Sikob return err; 1420103285Sikob } 1421103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1422103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1423103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1424103285Sikob OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1425103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1426103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1427103285Sikob if(dbch->xferq.stdma2 != NULL){ 1428103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1429103285Sikob ((struct fwohcidb_tr *) 1430103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1431103285Sikob |= OHCI_BRANCH_ALWAYS; 1432103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1433103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1434103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1435103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1436103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1437103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1438103285Sikob }else{ 1439103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1440103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1441103285Sikob } 1442103285Sikob OWRITE(sc, OHCI_ITCMD(dmach), 1443103285Sikob vtophys(((struct fwohcidb_tr *) 1444103285Sikob (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1445103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1446103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1447103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1448103285Sikob fp->mode.ld[2] = htonl(0x80000000 + 1449103285Sikob ((fc->cyctimer(fc) + 0x3000) & 0xf000)); 1450103285Sikob } 1451103285Sikob 1452103285Sikob OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1453103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1454103285Sikob } 1455103285Sikob return err; 1456103285Sikob} 1457106790Ssimokawa 1458106790Ssimokawastatic int 1459106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1460103285Sikob{ 1461103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1462103285Sikob int err = 0; 1463103285Sikob unsigned short tag, ich; 1464103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1465103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1466103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1467103285Sikob 1468103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1469103285Sikob sc->ir[dmach].xferq.queued = 0; 1470103285Sikob sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1471103285Sikob sc->ir[dmach].xferq.bnchunk; 1472103285Sikob sc->ir[dmach].dummy = 1473103285Sikob malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1474103285Sikob M_DEVBUF, M_DONTWAIT); 1475103285Sikob if(sc->ir[dmach].dummy == NULL){ 1476103285Sikob err = ENOMEM; 1477103285Sikob return err; 1478103285Sikob } 1479103285Sikob sc->ir[dmach].ndesc = 2; 1480103285Sikob fwohci_db_init(&sc->ir[dmach]); 1481103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1482103285Sikob } 1483103285Sikob if(err) 1484103285Sikob return err; 1485103285Sikob 1486103285Sikob if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1487103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1488103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1489103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1490103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1491103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1492103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1493103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1494103285Sikob } 1495103285Sikob }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1496103285Sikob && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1497103285Sikob fw_rbuf_update(&sc->fc, dmach, 0); 1498103285Sikob 1499103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1500103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1501103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1502103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1503103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1504103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1505103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1506103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1507103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1508103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1509103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1510103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1511103285Sikob }else{ 1512103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1513103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1514103285Sikob } 1515103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1516103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1517103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1518103285Sikob } 1519103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1520103285Sikob return err; 1521103285Sikob} 1522106790Ssimokawa 1523106790Ssimokawastatic int 1524106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1525103285Sikob{ 1526103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1527103285Sikob int err = 0; 1528103285Sikob 1529103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1530103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1531103285Sikob return err; 1532103285Sikob }else{ 1533103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1534103285Sikob return err; 1535103285Sikob } 1536103285Sikob} 1537106790Ssimokawa 1538106790Ssimokawaint 1539108642Ssimokawafwohci_shutdown(struct fwohci_softc *sc, device_t dev) 1540103285Sikob{ 1541103285Sikob u_int i; 1542103285Sikob 1543103285Sikob/* Now stopping all DMA channel */ 1544103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1545103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1546103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1547103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1548103285Sikob 1549103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1550103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1551103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1552103285Sikob } 1553103285Sikob 1554103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1555103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1556103285Sikob 1557103285Sikob/* Stop interrupt */ 1558103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1559103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1560103285Sikob | OHCI_INT_PHY_INT 1561103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1562103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1563103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1564103285Sikob | OHCI_INT_PHY_BUS_R); 1565108642Ssimokawa/* XXX Link down? Bus reset? */ 1566103285Sikob return 0; 1567103285Sikob} 1568103285Sikob 1569108642Ssimokawaint 1570108642Ssimokawafwohci_resume(struct fwohci_softc *sc, device_t dev) 1571108642Ssimokawa{ 1572108642Ssimokawa int i; 1573108642Ssimokawa 1574108642Ssimokawa fwohci_reset(sc, dev); 1575108642Ssimokawa /* XXX resume isochronus receive automatically. (how about TX?) */ 1576108642Ssimokawa for(i = 0; i < sc->fc.nisodma; i ++) { 1577108642Ssimokawa if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1578108642Ssimokawa device_printf(sc->fc.dev, 1579108642Ssimokawa "resume iso receive ch: %d\n", i); 1580108642Ssimokawa sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1581108642Ssimokawa sc->fc.irx_enable(&sc->fc, i); 1582108642Ssimokawa } 1583108642Ssimokawa } 1584108642Ssimokawa 1585108642Ssimokawa bus_generic_resume(dev); 1586108642Ssimokawa sc->fc.ibr(&sc->fc); 1587108642Ssimokawa return 0; 1588108642Ssimokawa} 1589108642Ssimokawa 1590103285Sikob#define ACK_ALL 1591103285Sikobstatic void 1592106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1593103285Sikob{ 1594103285Sikob u_int32_t irstat, itstat; 1595103285Sikob u_int i; 1596103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1597103285Sikob 1598103285Sikob#ifdef OHCI_DEBUG 1599103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1600103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1601103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1602103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1603103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1604103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1605103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1606103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1607103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1608103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1609103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1610103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1611103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1612103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1613103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1614103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1615103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1616103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1617103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1618103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1619103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1620103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1621103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1622103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1623103285Sikob ); 1624103285Sikob#endif 1625103285Sikob/* Bus reset */ 1626103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1627103285Sikob device_printf(fc->dev, "BUS reset\n"); 1628103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1629103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1630103285Sikob 1631103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1632103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1633103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1634103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1635103285Sikob 1636103285Sikob#if 0 1637103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1638103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1639103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1640103285Sikob } 1641103285Sikob 1642103285Sikob#endif 1643103285Sikob fw_busreset(fc); 1644103285Sikob 1645103285Sikob /* XXX need to wait DMA to stop */ 1646103285Sikob#ifndef ACK_ALL 1647103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1648103285Sikob#endif 1649103285Sikob#if 1 1650103285Sikob /* pending all pre-bus_reset packets */ 1651103285Sikob fwohci_txd(sc, &sc->atrq); 1652103285Sikob fwohci_txd(sc, &sc->atrs); 1653106789Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1654106789Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1655103285Sikob#endif 1656103285Sikob 1657103285Sikob 1658103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1659103285Sikob /* XXX insecure ?? */ 1660103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1661103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1662103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1663103285Sikob 1664103285Sikob } 1665103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1666103285Sikob#ifndef ACK_ALL 1667103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1668103285Sikob#endif 1669103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1670103285Sikob OWRITE(sc, OHCI_IR_STATCLR, ~0); 1671103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1672103285Sikob if((irstat & (1 << i)) != 0){ 1673103285Sikob if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1674106789Ssimokawa fwohci_ircv(sc, &sc->ir[i], count); 1675103285Sikob }else{ 1676103285Sikob fwohci_rbuf_update(sc, i); 1677103285Sikob } 1678103285Sikob } 1679103285Sikob } 1680103285Sikob } 1681103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1682103285Sikob#ifndef ACK_ALL 1683103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1684103285Sikob#endif 1685103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1686103285Sikob OWRITE(sc, OHCI_IT_STATCLR, ~0); 1687103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1688103285Sikob if((itstat & (1 << i)) != 0){ 1689103285Sikob fwohci_tbuf_update(sc, i); 1690103285Sikob } 1691103285Sikob } 1692103285Sikob } 1693103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1694103285Sikob#ifndef ACK_ALL 1695103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1696103285Sikob#endif 1697103285Sikob#if 0 1698103285Sikob dump_dma(sc, ARRS_CH); 1699103285Sikob dump_db(sc, ARRS_CH); 1700103285Sikob#endif 1701106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1702103285Sikob } 1703103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1704103285Sikob#ifndef ACK_ALL 1705103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1706103285Sikob#endif 1707103285Sikob#if 0 1708103285Sikob dump_dma(sc, ARRQ_CH); 1709103285Sikob dump_db(sc, ARRQ_CH); 1710103285Sikob#endif 1711106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1712103285Sikob } 1713103285Sikob if(stat & OHCI_INT_PHY_SID){ 1714103285Sikob caddr_t buf; 1715103285Sikob int plen; 1716103285Sikob 1717103285Sikob#ifndef ACK_ALL 1718103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1719103285Sikob#endif 1720103285Sikob/* 1721103285Sikob** Checking whether the node is root or not. If root, turn on 1722103285Sikob** cycle master. 1723103285Sikob*/ 1724103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1725103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1726103285Sikob printf("Bus reset failure\n"); 1727103285Sikob goto sidout; 1728103285Sikob } 1729103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1730103285Sikob printf("CYCLEMASTER mode\n"); 1731103285Sikob OWRITE(sc, OHCI_LNKCTL, 1732103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1733103285Sikob }else{ 1734103285Sikob printf("non CYCLEMASTER mode\n"); 1735103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1736103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1737103285Sikob } 1738103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1739103285Sikob 1740103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1741103285Sikob plen -= 4; /* chop control info */ 1742103285Sikob buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1743103285Sikob if(buf == NULL) goto sidout; 1744108530Ssimokawa bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1745103285Sikob buf, plen); 1746103285Sikob fw_sidrcv(fc, buf, plen, 0); 1747103285Sikob } 1748103285Sikobsidout: 1749103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1750103285Sikob#ifndef ACK_ALL 1751103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1752103285Sikob#endif 1753103285Sikob fwohci_txd(sc, &(sc->atrq)); 1754103285Sikob } 1755103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1756103285Sikob#ifndef ACK_ALL 1757103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1758103285Sikob#endif 1759103285Sikob fwohci_txd(sc, &(sc->atrs)); 1760103285Sikob } 1761103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1762103285Sikob#ifndef ACK_ALL 1763103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1764103285Sikob#endif 1765103285Sikob device_printf(fc->dev, "posted write error\n"); 1766103285Sikob } 1767103285Sikob if((stat & OHCI_INT_ERR )){ 1768103285Sikob#ifndef ACK_ALL 1769103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1770103285Sikob#endif 1771103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1772103285Sikob } 1773103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1774103285Sikob#ifndef ACK_ALL 1775103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1776103285Sikob#endif 1777103285Sikob device_printf(fc->dev, "phy int\n"); 1778103285Sikob } 1779103285Sikob 1780103285Sikob return; 1781103285Sikob} 1782103285Sikob 1783103285Sikobvoid 1784103285Sikobfwohci_intr(void *arg) 1785103285Sikob{ 1786103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1787103285Sikob u_int32_t stat; 1788103285Sikob 1789103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1790103285Sikob /* polling mode */ 1791103285Sikob return; 1792103285Sikob } 1793103285Sikob 1794103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1795103285Sikob if (stat == 0xffffffff) { 1796103285Sikob device_printf(sc->fc.dev, 1797103285Sikob "device physically ejected?\n"); 1798103285Sikob return; 1799103285Sikob } 1800103285Sikob#ifdef ACK_ALL 1801103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1802103285Sikob#endif 1803106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1804103285Sikob } 1805103285Sikob} 1806103285Sikob 1807103285Sikobstatic void 1808103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1809103285Sikob{ 1810103285Sikob int s; 1811103285Sikob u_int32_t stat; 1812103285Sikob struct fwohci_softc *sc; 1813103285Sikob 1814103285Sikob 1815103285Sikob sc = (struct fwohci_softc *)fc; 1816103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1817103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1818103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1819103285Sikob#if 0 1820103285Sikob if (!quick) { 1821103285Sikob#else 1822103285Sikob if (1) { 1823103285Sikob#endif 1824103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1825103285Sikob if (stat == 0) 1826103285Sikob return; 1827103285Sikob if (stat == 0xffffffff) { 1828103285Sikob device_printf(sc->fc.dev, 1829103285Sikob "device physically ejected?\n"); 1830103285Sikob return; 1831103285Sikob } 1832103285Sikob#ifdef ACK_ALL 1833103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1834103285Sikob#endif 1835103285Sikob } 1836103285Sikob s = splfw(); 1837106789Ssimokawa fwohci_intr_body(sc, stat, count); 1838103285Sikob splx(s); 1839103285Sikob} 1840103285Sikob 1841103285Sikobstatic void 1842103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 1843103285Sikob{ 1844103285Sikob struct fwohci_softc *sc; 1845103285Sikob 1846103285Sikob sc = (struct fwohci_softc *)fc; 1847107653Ssimokawa if (bootverbose) 1848108642Ssimokawa device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); 1849103285Sikob if (enable) { 1850103285Sikob sc->intmask |= OHCI_INT_EN; 1851103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1852103285Sikob } else { 1853103285Sikob sc->intmask &= ~OHCI_INT_EN; 1854103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1855103285Sikob } 1856103285Sikob} 1857103285Sikob 1858106790Ssimokawastatic void 1859106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1860103285Sikob{ 1861103285Sikob int stat; 1862103285Sikob struct firewire_comm *fc = &sc->fc; 1863103285Sikob struct fw_pkt *fp; 1864103285Sikob struct fwohci_dbch *dbch; 1865103285Sikob struct fwohcidb_tr *db_tr; 1866103285Sikob 1867103285Sikob dbch = &sc->it[dmach]; 1868103285Sikob if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1869103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1870103285Sikob/* 1871103285Sikob * Overwrite highest significant 4 bits timestamp information 1872103285Sikob */ 1873103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1874103285Sikob fp->mode.ld[2] |= htonl(0x80000000 | 1875103285Sikob ((fc->cyctimer(fc) + 0x4000) & 0xf000)); 1876103285Sikob } 1877103285Sikob stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1878103285Sikob switch(stat){ 1879103285Sikob case FWOHCIEV_ACKCOMPL: 1880103285Sikob fw_tbuf_update(fc, dmach, 1); 1881103285Sikob break; 1882103285Sikob default: 1883103285Sikob fw_tbuf_update(fc, dmach, 0); 1884103285Sikob break; 1885103285Sikob } 1886103285Sikob fwohci_itxbuf_enable(&sc->fc, dmach); 1887103285Sikob} 1888106790Ssimokawa 1889106790Ssimokawastatic void 1890106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1891103285Sikob{ 1892103285Sikob int stat; 1893103285Sikob stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1894103285Sikob switch(stat){ 1895103285Sikob case FWOHCIEV_ACKCOMPL: 1896103285Sikob fw_rbuf_update(&sc->fc, dmach, 1); 1897103285Sikob wakeup(sc->fc.ir[dmach]); 1898103285Sikob fwohci_irx_enable(&sc->fc, dmach); 1899103285Sikob break; 1900103285Sikob default: 1901103285Sikob break; 1902103285Sikob } 1903103285Sikob} 1904106790Ssimokawa 1905106790Ssimokawavoid 1906106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 1907106790Ssimokawa{ 1908103285Sikob u_int32_t off, cntl, stat, cmd, match; 1909103285Sikob 1910103285Sikob if(ch == 0){ 1911103285Sikob off = OHCI_ATQOFF; 1912103285Sikob }else if(ch == 1){ 1913103285Sikob off = OHCI_ATSOFF; 1914103285Sikob }else if(ch == 2){ 1915103285Sikob off = OHCI_ARQOFF; 1916103285Sikob }else if(ch == 3){ 1917103285Sikob off = OHCI_ARSOFF; 1918103285Sikob }else if(ch < IRX_CH){ 1919103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1920103285Sikob }else{ 1921103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1922103285Sikob } 1923103285Sikob cntl = stat = OREAD(sc, off); 1924103285Sikob cmd = OREAD(sc, off + 0xc); 1925103285Sikob match = OREAD(sc, off + 0x10); 1926103285Sikob 1927103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1928103285Sikob ch, 1929103285Sikob cntl, 1930103285Sikob stat, 1931103285Sikob cmd, 1932103285Sikob match); 1933103285Sikob stat &= 0xffff ; 1934103285Sikob if(stat & 0xff00){ 1935103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 1936103285Sikob ch, 1937103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1938103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1939103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1940103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1941103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1942103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1943103285Sikob fwohcicode[stat & 0x1f], 1944103285Sikob stat & 0x1f 1945103285Sikob ); 1946103285Sikob }else{ 1947103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 1948103285Sikob } 1949103285Sikob} 1950106790Ssimokawa 1951106790Ssimokawavoid 1952106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 1953106790Ssimokawa{ 1954103285Sikob struct fwohci_dbch *dbch; 1955103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 1956103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 1957103285Sikob int idb, jdb; 1958103285Sikob u_int32_t cmd, off; 1959103285Sikob if(ch == 0){ 1960103285Sikob off = OHCI_ATQOFF; 1961103285Sikob dbch = &sc->atrq; 1962103285Sikob }else if(ch == 1){ 1963103285Sikob off = OHCI_ATSOFF; 1964103285Sikob dbch = &sc->atrs; 1965103285Sikob }else if(ch == 2){ 1966103285Sikob off = OHCI_ARQOFF; 1967103285Sikob dbch = &sc->arrq; 1968103285Sikob }else if(ch == 3){ 1969103285Sikob off = OHCI_ARSOFF; 1970103285Sikob dbch = &sc->arrs; 1971103285Sikob }else if(ch < IRX_CH){ 1972103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1973103285Sikob dbch = &sc->it[ch - ITX_CH]; 1974103285Sikob }else { 1975103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1976103285Sikob dbch = &sc->ir[ch - IRX_CH]; 1977103285Sikob } 1978103285Sikob cmd = OREAD(sc, off + 0xc); 1979103285Sikob 1980103285Sikob if( dbch->ndb == 0 ){ 1981103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 1982103285Sikob return; 1983103285Sikob } 1984103285Sikob pp = dbch->top; 1985103285Sikob prev = pp->db; 1986103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 1987103285Sikob if(pp == NULL){ 1988103285Sikob curr = NULL; 1989103285Sikob goto outdb; 1990103285Sikob } 1991103285Sikob cp = STAILQ_NEXT(pp, link); 1992103285Sikob if(cp == NULL){ 1993103285Sikob curr = NULL; 1994103285Sikob goto outdb; 1995103285Sikob } 1996103285Sikob np = STAILQ_NEXT(cp, link); 1997103285Sikob if(cp == NULL) break; 1998103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 1999103285Sikob if((cmd & 0xfffffff0) 2000103285Sikob == vtophys(&(cp->db[jdb]))){ 2001103285Sikob curr = cp->db; 2002103285Sikob if(np != NULL){ 2003103285Sikob next = np->db; 2004103285Sikob }else{ 2005103285Sikob next = NULL; 2006103285Sikob } 2007103285Sikob goto outdb; 2008103285Sikob } 2009103285Sikob } 2010103285Sikob pp = STAILQ_NEXT(pp, link); 2011103285Sikob prev = pp->db; 2012103285Sikob } 2013103285Sikoboutdb: 2014103285Sikob if( curr != NULL){ 2015103285Sikob printf("Prev DB %d\n", ch); 2016103285Sikob print_db(prev, ch, dbch->ndesc); 2017103285Sikob printf("Current DB %d\n", ch); 2018103285Sikob print_db(curr, ch, dbch->ndesc); 2019103285Sikob printf("Next DB %d\n", ch); 2020103285Sikob print_db(next, ch, dbch->ndesc); 2021103285Sikob }else{ 2022103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2023103285Sikob } 2024103285Sikob return; 2025103285Sikob} 2026106790Ssimokawa 2027106790Ssimokawavoid 2028106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2029106790Ssimokawa{ 2030103285Sikob fwohcireg_t stat; 2031103285Sikob int i, key; 2032103285Sikob 2033103285Sikob if(db == NULL){ 2034103285Sikob printf("No Descriptor is found\n"); 2035103285Sikob return; 2036103285Sikob } 2037103285Sikob 2038103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2039103285Sikob ch, 2040103285Sikob "Current", 2041103285Sikob "OP ", 2042103285Sikob "KEY", 2043103285Sikob "INT", 2044103285Sikob "BR ", 2045103285Sikob "len", 2046103285Sikob "Addr", 2047103285Sikob "Depend", 2048103285Sikob "Stat", 2049103285Sikob "Cnt"); 2050103285Sikob for( i = 0 ; i <= max ; i ++){ 2051103285Sikob key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2052106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2053103285Sikob vtophys(&db[i]), 2054103285Sikob dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2055103285Sikob dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2056103285Sikob dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2057103285Sikob dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2058103285Sikob db[i].db.desc.cmd & 0xffff, 2059103285Sikob db[i].db.desc.addr, 2060103285Sikob db[i].db.desc.depend, 2061103285Sikob db[i].db.desc.status, 2062103285Sikob db[i].db.desc.count); 2063103285Sikob stat = db[i].db.desc.status; 2064103285Sikob if(stat & 0xff00){ 2065103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2066103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2067103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2068103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2069103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2070103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2071103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2072103285Sikob fwohcicode[stat & 0x1f], 2073103285Sikob stat & 0x1f 2074103285Sikob ); 2075103285Sikob }else{ 2076103285Sikob printf(" Nostat\n"); 2077103285Sikob } 2078103285Sikob if(key == OHCI_KEY_ST2 ){ 2079103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2080103285Sikob db[i+1].db.immed[0], 2081103285Sikob db[i+1].db.immed[1], 2082103285Sikob db[i+1].db.immed[2], 2083103285Sikob db[i+1].db.immed[3]); 2084103285Sikob } 2085103285Sikob if(key == OHCI_KEY_DEVICE){ 2086103285Sikob return; 2087103285Sikob } 2088103285Sikob if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2089103285Sikob == OHCI_BRANCH_ALWAYS){ 2090103285Sikob return; 2091103285Sikob } 2092103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2093103285Sikob == OHCI_OUTPUT_LAST){ 2094103285Sikob return; 2095103285Sikob } 2096103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2097103285Sikob == OHCI_INPUT_LAST){ 2098103285Sikob return; 2099103285Sikob } 2100103285Sikob if(key == OHCI_KEY_ST2 ){ 2101103285Sikob i++; 2102103285Sikob } 2103103285Sikob } 2104103285Sikob return; 2105103285Sikob} 2106106790Ssimokawa 2107106790Ssimokawavoid 2108106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2109103285Sikob{ 2110103285Sikob struct fwohci_softc *sc; 2111103285Sikob u_int32_t fun; 2112103285Sikob 2113103285Sikob sc = (struct fwohci_softc *)fc; 2114108276Ssimokawa 2115108276Ssimokawa /* 2116108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2117108276Ssimokawa * shouldn't became the root node. 2118108276Ssimokawa */ 2119108276Ssimokawa fun = fwphy_rddata(sc, FW_PHY_RHB_REG); 2120108276Ssimokawa fun |= FW_PHY_RHB; 2121108276Ssimokawa fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun); 2122103285Sikob#if 1 2123103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2124103285Sikob fun |= FW_PHY_IBR; 2125103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2126103285Sikob#else 2127103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2128103285Sikob fun |= FW_PHY_ISBR; 2129103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2130103285Sikob#endif 2131103285Sikob} 2132106790Ssimokawa 2133106790Ssimokawavoid 2134106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2135103285Sikob{ 2136103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2137103285Sikob struct fwohci_dbch *dbch; 2138103285Sikob struct fw_pkt *fp; 2139103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2140103285Sikob unsigned short chtag; 2141103285Sikob int idb; 2142103285Sikob 2143103285Sikob dbch = &sc->it[dmach]; 2144103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2145103285Sikob 2146103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2147103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2148103285Sikob/* 2149103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2150103285Sikob*/ 2151103285Sikob if(bulkxfer->flag != 0){ 2152103285Sikob return; 2153103285Sikob } 2154103285Sikob bulkxfer->flag = 1; 2155103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2156103285Sikob db_tr->db[0].db.desc.cmd 2157103285Sikob = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2158103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2159103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) 2160103285Sikob db_tr->db[1].db.immed; 2161103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2162103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2163103285Sikob ohcifp->mode.stream.chtag = chtag; 2164103285Sikob ohcifp->mode.stream.tcode = 0xa; 2165103285Sikob ohcifp->mode.stream.spd = 4; 2166103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2167103285Sikob ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2168103285Sikob 2169103285Sikob db_tr->db[2].db.desc.cmd 2170103285Sikob = OHCI_OUTPUT_LAST 2171103285Sikob | OHCI_UPDATE 2172103285Sikob | OHCI_BRANCH_ALWAYS 2173103285Sikob | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2174103285Sikob db_tr->db[2].db.desc.status = 0; 2175103285Sikob db_tr->db[2].db.desc.count = 0; 2176103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 2177103285Sikob db_tr->db[0].db.desc.depend 2178103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2179103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2180103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2181103285Sikob }else{ 2182103285Sikob db_tr->db[0].db.desc.depend 2183103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2184103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2185103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2186103285Sikob } 2187103285Sikob bulkxfer->end = (caddr_t)db_tr; 2188103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2189103285Sikob } 2190103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2191103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2192103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2193103285Sikob/**/ 2194103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2195103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2196103285Sikob/**/ 2197103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2198103285Sikob 2199103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2200103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2201103285Sikob/* 2202103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2203103285Sikob*/ 2204103285Sikob return; 2205103285Sikob} 2206106790Ssimokawa 2207106790Ssimokawastatic int 2208106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2209106790Ssimokawa int mode, void *buf) 2210103285Sikob{ 2211103285Sikob volatile struct fwohcidb *db = db_tr->db; 2212103285Sikob int err = 0; 2213103285Sikob if(buf == 0){ 2214103285Sikob err = EINVAL; 2215103285Sikob return err; 2216103285Sikob } 2217103285Sikob db_tr->buf = buf; 2218103285Sikob db_tr->dbcnt = 3; 2219103285Sikob db_tr->dummy = NULL; 2220103285Sikob 2221103285Sikob db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2222103285Sikob 2223103285Sikob db[2].db.desc.depend = 0; 2224103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2225103285Sikob db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2226103285Sikob 2227103285Sikob db[0].db.desc.status = 0; 2228103285Sikob db[0].db.desc.count = 0; 2229103285Sikob 2230103285Sikob db[2].db.desc.status = 0; 2231103285Sikob db[2].db.desc.count = 0; 2232103285Sikob if( mode & FWXFERQ_STREAM ){ 2233103285Sikob db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2234103285Sikob if(mode & FWXFERQ_PACKET ){ 2235103285Sikob db[2].db.desc.cmd 2236103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2237103285Sikob } 2238103285Sikob } 2239103285Sikob db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2240103285Sikob return 1; 2241103285Sikob} 2242106790Ssimokawa 2243106790Ssimokawaint 2244106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2245106790Ssimokawa void *buf, void *dummy) 2246103285Sikob{ 2247103285Sikob volatile struct fwohcidb *db = db_tr->db; 2248103285Sikob int i; 2249103285Sikob void *dbuf[2]; 2250103285Sikob int dsiz[2]; 2251103285Sikob 2252103285Sikob if(buf == 0){ 2253103285Sikob buf = malloc(size, M_DEVBUF, M_NOWAIT); 2254103285Sikob if(buf == NULL) return 0; 2255103285Sikob db_tr->buf = buf; 2256103285Sikob db_tr->dbcnt = 1; 2257103285Sikob db_tr->dummy = NULL; 2258103285Sikob dsiz[0] = size; 2259103285Sikob dbuf[0] = buf; 2260103285Sikob }else if(dummy == NULL){ 2261103285Sikob db_tr->buf = buf; 2262103285Sikob db_tr->dbcnt = 1; 2263103285Sikob db_tr->dummy = NULL; 2264103285Sikob dsiz[0] = size; 2265103285Sikob dbuf[0] = buf; 2266103285Sikob }else{ 2267103285Sikob db_tr->buf = buf; 2268103285Sikob db_tr->dbcnt = 2; 2269103285Sikob db_tr->dummy = dummy; 2270103285Sikob dsiz[0] = sizeof(u_int32_t); 2271103285Sikob dsiz[1] = size; 2272103285Sikob dbuf[0] = dummy; 2273103285Sikob dbuf[1] = buf; 2274103285Sikob } 2275103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2276103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2277103285Sikob db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2278103285Sikob if( mode & FWXFERQ_STREAM ){ 2279103285Sikob db[i].db.desc.cmd |= OHCI_UPDATE; 2280103285Sikob } 2281103285Sikob db[i].db.desc.status = 0; 2282103285Sikob db[i].db.desc.count = dsiz[i]; 2283103285Sikob } 2284103285Sikob if( mode & FWXFERQ_STREAM ){ 2285103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2286103285Sikob if(mode & FWXFERQ_PACKET ){ 2287103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd 2288103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2289103285Sikob } 2290103285Sikob } 2291103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2292103285Sikob return 1; 2293103285Sikob} 2294106790Ssimokawa 2295106790Ssimokawastatic void 2296106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2297103285Sikob{ 2298103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2299103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2300103285Sikob int z = 1; 2301103285Sikob struct fw_pkt *fp; 2302103285Sikob u_int8_t *ld; 2303103285Sikob u_int32_t off = NULL; 2304103285Sikob u_int32_t stat; 2305103285Sikob u_int32_t *qld; 2306103285Sikob u_int32_t reg; 2307103285Sikob u_int spd; 2308103285Sikob u_int dmach; 2309103285Sikob int len, i, plen; 2310103285Sikob caddr_t buf; 2311103285Sikob 2312103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2313103285Sikob if( &sc->ir[dmach] == dbch){ 2314103285Sikob off = OHCI_IROFF(dmach); 2315103285Sikob break; 2316103285Sikob } 2317103285Sikob } 2318103285Sikob if(off == NULL){ 2319103285Sikob return; 2320103285Sikob } 2321103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2322103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2323103285Sikob return; 2324103285Sikob } 2325103285Sikob 2326103285Sikob odb_tr = NULL; 2327103285Sikob db_tr = dbch->top; 2328103285Sikob i = 0; 2329103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2330106789Ssimokawa if (count >= 0 && count-- == 0) 2331106789Ssimokawa break; 2332103285Sikob ld = (u_int8_t *)db_tr->buf; 2333103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2334103285Sikob /* skip timeStamp */ 2335103285Sikob ld += sizeof(struct fwohci_trailer); 2336103285Sikob } 2337103285Sikob qld = (u_int32_t *)ld; 2338103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2339103285Sikob/* 2340103285Sikob{ 2341103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2342103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2343103285Sikob} 2344103285Sikob*/ 2345103285Sikob fp=(struct fw_pkt *)ld; 2346103285Sikob qld[0] = htonl(qld[0]); 2347103285Sikob plen = sizeof(struct fw_isohdr) 2348103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2349103285Sikob ld += plen; 2350103285Sikob len -= plen; 2351103285Sikob buf = db_tr->buf; 2352103285Sikob db_tr->buf = NULL; 2353103285Sikob stat = reg & 0x1f; 2354103285Sikob spd = reg & 0x3; 2355103285Sikob switch(stat){ 2356103285Sikob case FWOHCIEV_ACKCOMPL: 2357103285Sikob case FWOHCIEV_ACKPEND: 2358103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2359103285Sikob break; 2360103285Sikob default: 2361103285Sikob free(buf, M_DEVBUF); 2362103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2363103285Sikob break; 2364103285Sikob } 2365103285Sikob i++; 2366103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2367103285Sikob dbch->xferq.flag, 0, NULL); 2368103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2369103285Sikob if(dbch->pdb_tr != NULL){ 2370103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2371103285Sikob } else { 2372103285Sikob /* XXX should be rewritten in better way */ 2373103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2374103285Sikob } 2375103285Sikob dbch->pdb_tr = db_tr; 2376103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2377103285Sikob } 2378103285Sikob dbch->top = db_tr; 2379103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2380103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2381103285Sikob return; 2382103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2383103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2384103285Sikob dbch->top = db_tr; 2385103285Sikob fwohci_irx_enable(fc, dmach); 2386103285Sikob} 2387103285Sikob 2388103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2389103285Sikobstatic int 2390103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2391103285Sikob{ 2392103285Sikob int i; 2393103285Sikob 2394103285Sikob for( i = 4; i < hlen ; i+=4){ 2395103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2396103285Sikob } 2397103285Sikob 2398103285Sikob switch(fp->mode.common.tcode){ 2399103285Sikob case FWTCODE_RREQQ: 2400103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2401103285Sikob case FWTCODE_WRES: 2402103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2403103285Sikob case FWTCODE_WREQQ: 2404103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2405103285Sikob case FWTCODE_RREQB: 2406103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2407103285Sikob case FWTCODE_RRESQ: 2408103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2409103285Sikob case FWTCODE_WREQB: 2410103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2411103285Sikob + sizeof(u_int32_t); 2412103285Sikob case FWTCODE_LREQ: 2413103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2414103285Sikob + sizeof(u_int32_t); 2415103285Sikob case FWTCODE_RRESB: 2416103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2417103285Sikob + sizeof(u_int32_t); 2418103285Sikob case FWTCODE_LRES: 2419103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2420103285Sikob + sizeof(u_int32_t); 2421103285Sikob case FWOHCITCODE_PHY: 2422103285Sikob return 16; 2423103285Sikob } 2424103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2425103285Sikob return 0; 2426103285Sikob} 2427103285Sikob 2428106790Ssimokawastatic void 2429106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2430103285Sikob{ 2431103285Sikob struct fwohcidb_tr *db_tr; 2432103285Sikob int z = 1; 2433103285Sikob struct fw_pkt *fp; 2434103285Sikob u_int8_t *ld; 2435103285Sikob u_int32_t stat, off; 2436103285Sikob u_int spd; 2437103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2438103285Sikob int s; 2439103285Sikob caddr_t buf; 2440103285Sikob int resCount; 2441103285Sikob 2442103285Sikob if(&sc->arrq == dbch){ 2443103285Sikob off = OHCI_ARQOFF; 2444103285Sikob }else if(&sc->arrs == dbch){ 2445103285Sikob off = OHCI_ARSOFF; 2446103285Sikob }else{ 2447103285Sikob return; 2448103285Sikob } 2449103285Sikob 2450103285Sikob s = splfw(); 2451103285Sikob db_tr = dbch->top; 2452103285Sikob pcnt = 0; 2453103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2454103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2455103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2456103285Sikob resCount = db_tr->db[0].db.desc.count; 2457103285Sikob len = dbch->xferq.psize - resCount 2458103285Sikob - dbch->buf_offset; 2459103285Sikob while (len > 0 ) { 2460106789Ssimokawa if (count >= 0 && count-- == 0) 2461106789Ssimokawa goto out; 2462103285Sikob if(dbch->frag.buf != NULL){ 2463103285Sikob buf = dbch->frag.buf; 2464103285Sikob if (dbch->frag.plen < 0) { 2465103285Sikob /* incomplete header */ 2466103285Sikob int hlen; 2467103285Sikob 2468103285Sikob hlen = - dbch->frag.plen; 2469103285Sikob rlen = hlen - dbch->frag.len; 2470103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2471103285Sikob ld += rlen; 2472103285Sikob len -= rlen; 2473103285Sikob dbch->frag.len += rlen; 2474103285Sikob#if 0 2475103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2476103285Sikob#endif 2477103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2478103285Sikob dbch->frag.plen 2479103285Sikob = fwohci_get_plen(sc, fp, hlen); 2480103285Sikob if (dbch->frag.plen == 0) 2481103285Sikob goto out; 2482103285Sikob } 2483103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2484103285Sikob#if 0 2485103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2486103285Sikob#endif 2487103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2488103285Sikob rlen); 2489103285Sikob ld += rlen; 2490103285Sikob len -= rlen; 2491103285Sikob plen = dbch->frag.plen; 2492103285Sikob dbch->frag.buf = NULL; 2493103285Sikob dbch->frag.plen = 0; 2494103285Sikob dbch->frag.len = 0; 2495103285Sikob poff = 0; 2496103285Sikob }else{ 2497103285Sikob fp=(struct fw_pkt *)ld; 2498103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2499103285Sikob switch(fp->mode.common.tcode){ 2500103285Sikob case FWTCODE_RREQQ: 2501103285Sikob case FWTCODE_WRES: 2502103285Sikob case FWTCODE_WREQQ: 2503103285Sikob case FWTCODE_RRESQ: 2504103285Sikob case FWOHCITCODE_PHY: 2505103285Sikob hlen = 12; 2506103285Sikob break; 2507103285Sikob case FWTCODE_RREQB: 2508103285Sikob case FWTCODE_WREQB: 2509103285Sikob case FWTCODE_LREQ: 2510103285Sikob case FWTCODE_RRESB: 2511103285Sikob case FWTCODE_LRES: 2512103285Sikob hlen = 16; 2513103285Sikob break; 2514103285Sikob default: 2515103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2516103285Sikob goto out; 2517103285Sikob } 2518103285Sikob if (len >= hlen) { 2519103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2520103285Sikob if (plen == 0) 2521103285Sikob goto out; 2522103285Sikob plen = (plen + 3) & ~3; 2523103285Sikob len -= plen; 2524103285Sikob } else { 2525103285Sikob plen = -hlen; 2526103285Sikob len -= hlen; 2527103285Sikob } 2528103285Sikob if(resCount > 0 || len > 0){ 2529103285Sikob buf = malloc( dbch->xferq.psize, 2530103285Sikob M_DEVBUF, M_NOWAIT); 2531103285Sikob if(buf == NULL){ 2532103285Sikob printf("cannot malloc!\n"); 2533103285Sikob free(db_tr->buf, M_DEVBUF); 2534103285Sikob goto out; 2535103285Sikob } 2536103285Sikob bcopy(ld, buf, plen); 2537103285Sikob poff = 0; 2538103285Sikob dbch->frag.buf = NULL; 2539103285Sikob dbch->frag.plen = 0; 2540103285Sikob dbch->frag.len = 0; 2541103285Sikob }else if(len < 0){ 2542103285Sikob dbch->frag.buf = db_tr->buf; 2543103285Sikob if (plen < 0) { 2544103285Sikob#if 0 2545103285Sikob printf("plen < 0:" 2546103285Sikob "hlen: %d len: %d\n", 2547103285Sikob hlen, len); 2548103285Sikob#endif 2549103285Sikob dbch->frag.len = hlen + len; 2550103285Sikob dbch->frag.plen = -hlen; 2551103285Sikob } else { 2552103285Sikob dbch->frag.len = plen + len; 2553103285Sikob dbch->frag.plen = plen; 2554103285Sikob } 2555103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2556103285Sikob buf = NULL; 2557103285Sikob }else{ 2558103285Sikob buf = db_tr->buf; 2559103285Sikob poff = ld - (u_int8_t *)buf; 2560103285Sikob dbch->frag.buf = NULL; 2561103285Sikob dbch->frag.plen = 0; 2562103285Sikob dbch->frag.len = 0; 2563103285Sikob } 2564103285Sikob ld += plen; 2565103285Sikob } 2566103285Sikob if( buf != NULL){ 2567103285Sikob/* DMA result-code will be written at the tail of packet */ 2568103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2569103285Sikob spd = (stat >> 5) & 0x3; 2570103285Sikob stat &= 0x1f; 2571103285Sikob switch(stat){ 2572103285Sikob case FWOHCIEV_ACKPEND: 2573103285Sikob#if 0 2574103285Sikob printf("fwohci_arcv: ack pending..\n"); 2575103285Sikob#endif 2576103285Sikob /* fall through */ 2577103285Sikob case FWOHCIEV_ACKCOMPL: 2578103285Sikob if( poff != 0 ) 2579103285Sikob bcopy(buf+poff, buf, plen - 4); 2580103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2581103285Sikob break; 2582103285Sikob case FWOHCIEV_BUSRST: 2583103285Sikob free(buf, M_DEVBUF); 2584103285Sikob if (sc->fc.status != FWBUSRESET) 2585103285Sikob printf("got BUSRST packet!?\n"); 2586103285Sikob break; 2587103285Sikob default: 2588103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2589103285Sikob#if 0 /* XXX */ 2590103285Sikob goto out; 2591103285Sikob#endif 2592103285Sikob break; 2593103285Sikob } 2594103285Sikob } 2595103285Sikob pcnt ++; 2596103285Sikob }; 2597103285Sikobout: 2598103285Sikob if (resCount == 0) { 2599103285Sikob /* done on this buffer */ 2600103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2601103285Sikob dbch->xferq.flag, 0, NULL); 2602103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2603103285Sikob dbch->bottom = db_tr; 2604103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2605103285Sikob dbch->top = db_tr; 2606103285Sikob dbch->buf_offset = 0; 2607103285Sikob } else { 2608103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2609103285Sikob break; 2610103285Sikob } 2611103285Sikob /* XXX make sure DMA is not dead */ 2612103285Sikob } 2613103285Sikob#if 0 2614103285Sikob if (pcnt < 1) 2615103285Sikob printf("fwohci_arcv: no packets\n"); 2616103285Sikob#endif 2617103285Sikob splx(s); 2618103285Sikob} 2619