fwohci.c revision 108276
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 108276 2002-12-26 03:17:59Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45103285Sikob#include <sys/systm.h> 46103285Sikob#include <sys/types.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/mman.h> 49103285Sikob#include <sys/socket.h> 50103285Sikob#include <sys/socketvar.h> 51103285Sikob#include <sys/signalvar.h> 52103285Sikob#include <sys/malloc.h> 53103285Sikob#include <sys/uio.h> 54103285Sikob#include <sys/sockio.h> 55103285Sikob#include <sys/bus.h> 56103285Sikob#include <sys/kernel.h> 57103285Sikob#include <sys/conf.h> 58103285Sikob 59103285Sikob#include <machine/bus.h> 60103285Sikob#include <machine/resource.h> 61103285Sikob#include <sys/rman.h> 62103285Sikob 63103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64103285Sikob#include <machine/clock.h> 65103285Sikob#include <pci/pcivar.h> 66103285Sikob#include <pci/pcireg.h> 67103285Sikob#include <vm/vm.h> 68103285Sikob#include <vm/vm_extern.h> 69103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 70103285Sikob 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirebusreg.h> 73103285Sikob#include <dev/firewire/firewirereg.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77103285Sikob 78103285Sikob#undef OHCI_DEBUG 79106802Ssimokawa 80103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 81103285Sikob "STOR","LOAD","NOP ","STOP",}; 82103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83103285Sikob "UNDEF","REG","SYS","DEV"}; 84103285Sikobchar fwohcicode[32][0x20]={ 85103285Sikob "No stat","Undef","long","miss Ack err", 86103285Sikob "underrun","overrun","desc err", "data read err", 87103285Sikob "data write err","bus reset","timeout","tcode err", 88103285Sikob "Undef","Undef","unknown event","flushed", 89103285Sikob "Undef","ack complete","ack pend","Undef", 90103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 91103285Sikob "Undef","Undef","Undef","ack tardy", 92103285Sikob "Undef","ack data_err","ack type_err",""}; 93103285Sikob#define MAX_SPEED 2 94103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 95103285Sikobextern int maxrec[MAX_SPEED+1]; 96103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 126103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 127103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 128106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 132103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 142103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 145103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 148103285Sikobstatic void fwohci_timeout __P((void *)); 149103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 150103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 151103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 154103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160103285Sikob 161103285Sikob/* 162103285Sikob * memory allocated for DMA programs 163103285Sikob */ 164103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165103285Sikob 166103285Sikob/* #define NDB 1024 */ 167103285Sikob#define NDB FWMAXQUEUE 168103285Sikob#define NDVDB (DVBUF * NDB) 169103285Sikob 170103285Sikob#define OHCI_VERSION 0x00 171103285Sikob#define OHCI_CROMHDR 0x18 172103285Sikob#define OHCI_BUS_OPT 0x20 173103285Sikob#define OHCI_BUSIRMC (1 << 31) 174103285Sikob#define OHCI_BUSCMC (1 << 30) 175103285Sikob#define OHCI_BUSISC (1 << 29) 176103285Sikob#define OHCI_BUSBMC (1 << 28) 177103285Sikob#define OHCI_BUSPMC (1 << 27) 178103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 180103285Sikob 181103285Sikob#define OHCI_EUID_HI 0x24 182103285Sikob#define OHCI_EUID_LO 0x28 183103285Sikob 184103285Sikob#define OHCI_CROMPTR 0x34 185103285Sikob#define OHCI_HCCCTL 0x50 186103285Sikob#define OHCI_HCCCTLCLR 0x54 187103285Sikob#define OHCI_AREQHI 0x100 188103285Sikob#define OHCI_AREQHICLR 0x104 189103285Sikob#define OHCI_AREQLO 0x108 190103285Sikob#define OHCI_AREQLOCLR 0x10c 191103285Sikob#define OHCI_PREQHI 0x110 192103285Sikob#define OHCI_PREQHICLR 0x114 193103285Sikob#define OHCI_PREQLO 0x118 194103285Sikob#define OHCI_PREQLOCLR 0x11c 195103285Sikob#define OHCI_PREQUPPER 0x120 196103285Sikob 197103285Sikob#define OHCI_SID_BUF 0x64 198103285Sikob#define OHCI_SID_CNT 0x68 199103285Sikob#define OHCI_SID_CNT_MASK 0xffc 200103285Sikob 201103285Sikob#define OHCI_IT_STAT 0x90 202103285Sikob#define OHCI_IT_STATCLR 0x94 203103285Sikob#define OHCI_IT_MASK 0x98 204103285Sikob#define OHCI_IT_MASKCLR 0x9c 205103285Sikob 206103285Sikob#define OHCI_IR_STAT 0xa0 207103285Sikob#define OHCI_IR_STATCLR 0xa4 208103285Sikob#define OHCI_IR_MASK 0xa8 209103285Sikob#define OHCI_IR_MASKCLR 0xac 210103285Sikob 211103285Sikob#define OHCI_LNKCTL 0xe0 212103285Sikob#define OHCI_LNKCTLCLR 0xe4 213103285Sikob 214103285Sikob#define OHCI_PHYACCESS 0xec 215103285Sikob#define OHCI_CYCLETIMER 0xf0 216103285Sikob 217103285Sikob#define OHCI_DMACTL(off) (off) 218103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 219103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 220103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 221103285Sikob 222103285Sikob#define OHCI_ATQOFF 0x180 223103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 224103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227103285Sikob 228103285Sikob#define OHCI_ATSOFF 0x1a0 229103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 230103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233103285Sikob 234103285Sikob#define OHCI_ARQOFF 0x1c0 235103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 236103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239103285Sikob 240103285Sikob#define OHCI_ARSOFF 0x1e0 241103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 242103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245103285Sikob 246103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250103285Sikob 251103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256103285Sikob 257103285Sikobd_ioctl_t fwohci_ioctl; 258103285Sikob 259103285Sikob/* 260103285Sikob * Communication with PHY device 261103285Sikob */ 262106790Ssimokawastatic u_int32_t 263106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264103285Sikob{ 265103285Sikob u_int32_t fun; 266103285Sikob 267103285Sikob addr &= 0xf; 268103285Sikob data &= 0xff; 269103285Sikob 270103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 272103285Sikob DELAY(100); 273103285Sikob 274103285Sikob return(fwphy_rddata( sc, addr)); 275103285Sikob} 276103285Sikob 277103285Sikobstatic u_int32_t 278103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279103285Sikob{ 280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281103285Sikob int i; 282103285Sikob u_int32_t bm; 283103285Sikob 284103285Sikob#define OHCI_CSR_DATA 0x0c 285103285Sikob#define OHCI_CSR_COMP 0x10 286103285Sikob#define OHCI_CSR_CONT 0x14 287103285Sikob#define OHCI_BUS_MANAGER_ID 0 288103285Sikob 289103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 290103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293103285Sikob DELAY(100); 294103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 295107653Ssimokawa if((bm & 0x3f) == 0x3f) 296103285Sikob bm = node; 297107653Ssimokawa if (bootverbose) 298107653Ssimokawa device_printf(sc->fc.dev, 299107653Ssimokawa "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300103285Sikob 301103285Sikob return(bm); 302103285Sikob} 303103285Sikob 304106790Ssimokawastatic u_int32_t 305106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 306103285Sikob{ 307103285Sikob u_int32_t fun; 308103285Sikob u_int i; 309103285Sikob 310103285Sikob addr &= 0xf; 311103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 312103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 313108276Ssimokawa#if 1 314108276Ssimokawa /* Make sure that SCLK is started */ 315108276Ssimokawa for(i = 0; i < 1000; i++) { 316108276Ssimokawa if ((OREAD(sc, FWOHCI_INTSTAT) & OHCI_INT_REG_FAIL) == 0) 317108276Ssimokawa break; 318108276Ssimokawa DELAY(100); 319108276Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 320108276Ssimokawa OWRITE(sc, OHCI_PHYACCESS, fun); 321108276Ssimokawa } 322108276Ssimokawa if (bootverbose) 323108276Ssimokawa device_printf(sc->fc.dev, "fwphy_rddata: write loop=%d\n", i); 324108276Ssimokawa#endif 325103285Sikob for ( i = 0 ; i < 1000 ; i ++ ){ 326103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 327103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 328103285Sikob break; 329103285Sikob DELAY(1000); 330103285Sikob } 331103285Sikob if( i >= 1000) 332103285Sikob device_printf(sc->fc.dev, "cannot read phy\n"); 333103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 334103285Sikob} 335103285Sikob/* Device specific ioctl. */ 336103285Sikobint 337103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 338103285Sikob{ 339103285Sikob struct firewire_softc *sc; 340103285Sikob struct fwohci_softc *fc; 341103285Sikob int unit = DEV2UNIT(dev); 342103285Sikob int err = 0; 343103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 344103285Sikob u_int32_t *dmach = (u_int32_t *) data; 345103285Sikob 346103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 347103285Sikob if(sc == NULL){ 348103285Sikob return(EINVAL); 349103285Sikob } 350103285Sikob fc = (struct fwohci_softc *)sc->fc; 351103285Sikob 352103285Sikob if (!data) 353103285Sikob return(EINVAL); 354103285Sikob 355103285Sikob switch (cmd) { 356103285Sikob case FWOHCI_WRREG: 357103285Sikob#define OHCI_MAX_REG 0x800 358103285Sikob if(reg->addr <= OHCI_MAX_REG){ 359103285Sikob OWRITE(fc, reg->addr, reg->data); 360103285Sikob reg->data = OREAD(fc, reg->addr); 361103285Sikob }else{ 362103285Sikob err = EINVAL; 363103285Sikob } 364103285Sikob break; 365103285Sikob case FWOHCI_RDREG: 366103285Sikob if(reg->addr <= OHCI_MAX_REG){ 367103285Sikob reg->data = OREAD(fc, reg->addr); 368103285Sikob }else{ 369103285Sikob err = EINVAL; 370103285Sikob } 371103285Sikob break; 372103285Sikob/* Read DMA descriptors for debug */ 373103285Sikob case DUMPDMA: 374103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 375103285Sikob dump_dma(fc, *dmach); 376103285Sikob dump_db(fc, *dmach); 377103285Sikob }else{ 378103285Sikob err = EINVAL; 379103285Sikob } 380103285Sikob break; 381103285Sikob default: 382103285Sikob break; 383103285Sikob } 384103285Sikob return err; 385103285Sikob} 386106790Ssimokawa 387106790Ssimokawaint 388106790Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 389103285Sikob{ 390103285Sikob int err = 0; 391103285Sikob int i; 392103285Sikob u_int32_t reg, reg2; 393103285Sikob struct fwohcidb_tr *db_tr; 394103285Sikob int e1394a = 1; 395103285Sikob 396103285Sikob reg = OREAD(sc, OHCI_VERSION); 397103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 398103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 399103285Sikob 400103285Sikob/* XXX: Available Isochrounous DMA channel probe */ 401103285Sikob for( i = 0 ; i < 0x20 ; i ++ ){ 402103285Sikob OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 403103285Sikob reg = OREAD(sc, OHCI_IRCTL(i)); 404103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 405103285Sikob OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 406103285Sikob reg = OREAD(sc, OHCI_ITCTL(i)); 407103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 408103285Sikob } 409103285Sikob sc->fc.nisodma = i; 410103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 411103285Sikob 412103285Sikob sc->fc.arq = &sc->arrq.xferq; 413103285Sikob sc->fc.ars = &sc->arrs.xferq; 414103285Sikob sc->fc.atq = &sc->atrq.xferq; 415103285Sikob sc->fc.ats = &sc->atrs.xferq; 416103285Sikob 417103285Sikob sc->arrq.xferq.start = NULL; 418103285Sikob sc->arrs.xferq.start = NULL; 419103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 420103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 421103285Sikob 422103285Sikob sc->arrq.xferq.drain = NULL; 423103285Sikob sc->arrs.xferq.drain = NULL; 424103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 425103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 426103285Sikob 427103285Sikob sc->arrq.ndesc = 1; 428103285Sikob sc->arrs.ndesc = 1; 429103285Sikob sc->atrq.ndesc = 10; 430103285Sikob sc->atrs.ndesc = 10 / 2; 431103285Sikob 432103285Sikob sc->arrq.ndb = NDB; 433103285Sikob sc->arrs.ndb = NDB / 2; 434103285Sikob sc->atrq.ndb = NDB; 435103285Sikob sc->atrs.ndb = NDB / 2; 436103285Sikob 437103285Sikob sc->arrq.dummy = NULL; 438103285Sikob sc->arrs.dummy = NULL; 439103285Sikob sc->atrq.dummy = NULL; 440103285Sikob sc->atrs.dummy = NULL; 441103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 442103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 443103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 444103285Sikob sc->it[i].ndb = 0; 445103285Sikob sc->ir[i].ndb = 0; 446103285Sikob } 447103285Sikob 448103285Sikob sc->fc.tcode = tinfo; 449103285Sikob 450103285Sikob sc->cromptr = (u_int32_t *) 451103285Sikob contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 452103285Sikob 453103285Sikob if(sc->cromptr == NULL){ 454103285Sikob return ENOMEM; 455103285Sikob } 456103285Sikob sc->fc.dev = dev; 457103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 458103285Sikob 459103285Sikob sc->fc.config_rom[1] = 0x31333934; 460103285Sikob sc->fc.config_rom[2] = 0xf000a002; 461103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 462103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 463103285Sikob sc->fc.config_rom[5] = 0; 464103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 465103285Sikob 466103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 467103285Sikob 468103285Sikob 469103285Sikob fw_init(&sc->fc); 470103285Sikob 471108276Ssimokawa/* Disable interrupt */ 472108276Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 473108276Ssimokawa 474103285Sikob/* Now stopping all DMA channel */ 475103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 476103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 477103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 478103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 479103285Sikob 480103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, ~0); 481103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 482103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 483103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 484103285Sikob } 485103285Sikob 486103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 487103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 488107653Ssimokawa if (bootverbose) 489107653Ssimokawa device_printf(dev, "resetting OHCI..."); 490103285Sikob i = 0; 491103285Sikob while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 492103285Sikob if (i++ > 100) break; 493103285Sikob DELAY(1000); 494103285Sikob } 495107653Ssimokawa if (bootverbose) 496108276Ssimokawa printf("done (loop=%d)\n", i); 497103285Sikob 498103285Sikob reg = OREAD(sc, OHCI_BUS_OPT); 499103285Sikob reg2 = reg | OHCI_BUSFNC; 500103285Sikob /* XXX */ 501103285Sikob if (((reg & 0x0000f000) >> 12) < 10) 502103285Sikob reg2 = (reg2 & 0xffff0fff) | (10 << 12); 503107653Ssimokawa if (bootverbose) 504107653Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 505103285Sikob OWRITE(sc, OHCI_BUS_OPT, reg2); 506103285Sikob 507103285Sikob OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 508103285Sikob OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 509103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 510103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 511103285Sikob 512103285Sikob/* 513103285Sikob * probe PHY parameters 514103285Sikob * 0. to prove PHY version, whether compliance of 1394a. 515103285Sikob * 1. to probe maximum speed supported by the PHY and 516103285Sikob * number of port supported by core-logic. 517103285Sikob * It is not actually available port on your PC . 518103285Sikob */ 519108276Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 520103285Sikob#if 0 521108276Ssimokawa /* XXX wait for SCLK. */ 522108276Ssimokawa DELAY(100000); 523108276Ssimokawa#endif 524103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 525108276Ssimokawa 526103285Sikob if((reg >> 5) != 7 ){ 527103285Sikob sc->fc.mode &= ~FWPHYASYST; 528103285Sikob sc->fc.nport = reg & FW_PHY_NP; 529103285Sikob sc->fc.speed = reg & FW_PHY_SPD >> 6; 530103285Sikob if (sc->fc.speed > MAX_SPEED) { 531103285Sikob device_printf(dev, "invalid speed %d (fixed to %d).\n", 532103285Sikob sc->fc.speed, MAX_SPEED); 533103285Sikob sc->fc.speed = MAX_SPEED; 534103285Sikob } 535103285Sikob sc->fc.maxrec = maxrec[sc->fc.speed]; 536103285Sikob device_printf(dev, 537103285Sikob "Link 1394 only %s, %d ports, maxrec %d bytes.\n", 538103285Sikob linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 539103285Sikob }else{ 540103285Sikob reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 541103285Sikob sc->fc.mode |= FWPHYASYST; 542103285Sikob sc->fc.nport = reg & FW_PHY_NP; 543103285Sikob sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 544103285Sikob if (sc->fc.speed > MAX_SPEED) { 545103285Sikob device_printf(dev, "invalid speed %d (fixed to %d).\n", 546103285Sikob sc->fc.speed, MAX_SPEED); 547103285Sikob sc->fc.speed = MAX_SPEED; 548103285Sikob } 549103285Sikob sc->fc.maxrec = maxrec[sc->fc.speed]; 550103285Sikob device_printf(dev, 551103285Sikob "Link 1394a available %s, %d ports, maxrec %d bytes.\n", 552103285Sikob linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 553103285Sikob 554103285Sikob /* check programPhyEnable */ 555103285Sikob reg2 = fwphy_rddata(sc, 5); 556103285Sikob#if 0 557103285Sikob if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 558106790Ssimokawa#else /* XXX force to enable 1394a */ 559103285Sikob if (e1394a) { 560103285Sikob#endif 561107653Ssimokawa if (bootverbose) 562107653Ssimokawa device_printf(dev, 563107653Ssimokawa "Enable 1394a Enhancements\n"); 564103285Sikob /* enable EAA EMC */ 565103285Sikob reg2 |= 0x03; 566103285Sikob /* set aPhyEnhanceEnable */ 567103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 568103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 569103285Sikob } else { 570103285Sikob /* for safe */ 571103285Sikob reg2 &= ~0x83; 572103285Sikob } 573103285Sikob reg2 = fwphy_wrdata(sc, 5, reg2); 574103285Sikob } 575103285Sikob 576103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 577103285Sikob if((reg >> 5) == 7 ){ 578103285Sikob reg = fwphy_rddata(sc, 4); 579103285Sikob reg |= 1 << 6; 580103285Sikob fwphy_wrdata(sc, 4, reg); 581103285Sikob reg = fwphy_rddata(sc, 4); 582103285Sikob } 583103285Sikob 584103285Sikob/* SID recieve buffer must allign 2^11 */ 585103285Sikob#define OHCI_SIDSIZE (1 << 11) 586103285Sikob sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 587103285Sikob 0x10000, 0xffffffff, OHCI_SIDSIZE); 588103285Sikob OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 589103285Sikob sc->fc.sid_buf++; 590103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 591103285Sikob 592103285Sikob fwohci_db_init(&sc->arrq); 593103285Sikob fwohci_db_init(&sc->arrs); 594103285Sikob 595103285Sikob fwohci_db_init(&sc->atrq); 596103285Sikob fwohci_db_init(&sc->atrs); 597103285Sikob 598103285Sikob reg = OREAD(sc, FWOHCIGUID_H); 599103285Sikob for( i = 0 ; i < 4 ; i ++){ 600103285Sikob sc->fc.eui[3 - i] = reg & 0xff; 601103285Sikob reg = reg >> 8; 602103285Sikob } 603103285Sikob reg = OREAD(sc, FWOHCIGUID_L); 604103285Sikob for( i = 0 ; i < 4 ; i ++){ 605103285Sikob sc->fc.eui[7 - i] = reg & 0xff; 606103285Sikob reg = reg >> 8; 607103285Sikob } 608103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 609103285Sikob sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 610103285Sikob sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 611103285Sikob sc->fc.ioctl = fwohci_ioctl; 612103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 613103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 614103285Sikob sc->fc.ibr = fwohci_ibr; 615103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 616103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 617103285Sikob 618103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 619103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 620103285Sikob sc->fc.irx_post = fwohci_irx_post; 621103285Sikob sc->fc.itx_post = NULL; 622103285Sikob sc->fc.timeout = fwohci_timeout; 623103285Sikob sc->fc.poll = fwohci_poll; 624103285Sikob sc->fc.set_intr = fwohci_set_intr; 625106790Ssimokawa 626103285Sikob /* enable link */ 627103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 628103285Sikob fw_busreset(&sc->fc); 629103285Sikob fwohci_rx_enable(sc, &sc->arrq); 630103285Sikob fwohci_rx_enable(sc, &sc->arrs); 631103285Sikob 632103285Sikob for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 633103285Sikob i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 634103285Sikob db_tr->xfer = NULL; 635103285Sikob } 636103285Sikob for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 637103285Sikob i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 638103285Sikob db_tr->xfer = NULL; 639103285Sikob } 640103285Sikob sc->atrq.flags = sc->atrs.flags = 0; 641103285Sikob 642103285Sikob OWRITE(sc, FWOHCI_RETRY, 643103285Sikob (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ; 644103285Sikob OWRITE(sc, FWOHCI_INTMASK, 645103285Sikob OHCI_INT_ERR | OHCI_INT_PHY_SID 646103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 647103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 648103285Sikob | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 649103285Sikob fwohci_set_intr(&sc->fc, 1); 650103285Sikob 651103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 652103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 653103285Sikob 654103285Sikob return err; 655103285Sikob} 656106790Ssimokawa 657106790Ssimokawavoid 658106790Ssimokawafwohci_timeout(void *arg) 659103285Sikob{ 660103285Sikob struct fwohci_softc *sc; 661103285Sikob 662103285Sikob sc = (struct fwohci_softc *)arg; 663103285Sikob sc->fc.timeouthandle = timeout(fwohci_timeout, 664103285Sikob (void *)sc, FW_XFERTIMEOUT * hz * 10); 665103285Sikob} 666106790Ssimokawa 667106790Ssimokawau_int32_t 668106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 669103285Sikob{ 670103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 671103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 672103285Sikob} 673103285Sikob 674103285Sikob#define LAST_DB(dbtr, db) do { \ 675103285Sikob struct fwohcidb_tr *_dbtr = (dbtr); \ 676103285Sikob int _cnt = _dbtr->dbcnt; \ 677103285Sikob db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 678103285Sikob} while (0) 679103285Sikob 680106790Ssimokawastatic void 681106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 682103285Sikob{ 683103285Sikob int i, s; 684103285Sikob int tcode, hdr_len, hdr_off, len; 685103285Sikob int fsegment = -1; 686103285Sikob u_int32_t off; 687103285Sikob struct fw_xfer *xfer; 688103285Sikob struct fw_pkt *fp; 689103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 690103285Sikob struct fwohcidb_tr *db_tr; 691103285Sikob volatile struct fwohcidb *db; 692103285Sikob struct mbuf *m; 693103285Sikob struct tcode_info *info; 694103285Sikob 695103285Sikob if(&sc->atrq == dbch){ 696103285Sikob off = OHCI_ATQOFF; 697103285Sikob }else if(&sc->atrs == dbch){ 698103285Sikob off = OHCI_ATSOFF; 699103285Sikob }else{ 700103285Sikob return; 701103285Sikob } 702103285Sikob 703103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 704103285Sikob return; 705103285Sikob 706103285Sikob s = splfw(); 707103285Sikob db_tr = dbch->top; 708103285Sikobtxloop: 709103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 710103285Sikob if(xfer == NULL){ 711103285Sikob goto kick; 712103285Sikob } 713103285Sikob if(dbch->xferq.queued == 0 ){ 714103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 715103285Sikob } 716103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 717103285Sikob db_tr->xfer = xfer; 718103285Sikob xfer->state = FWXF_START; 719103285Sikob dbch->xferq.packets++; 720103285Sikob 721103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 722103285Sikob tcode = fp->mode.common.tcode; 723103285Sikob 724103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 725103285Sikob info = &tinfo[tcode]; 726103285Sikob hdr_len = hdr_off = info->hdr_len; 727103285Sikob /* fw_asyreq must pass valid send.len */ 728103285Sikob len = xfer->send.len; 729103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 730103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 731103285Sikob } 732103285Sikob ohcifp->mode.common.spd = xfer->spd; 733103285Sikob if (tcode == FWTCODE_STREAM ){ 734103285Sikob hdr_len = 8; 735103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 736103285Sikob } else if (tcode == FWTCODE_PHY) { 737103285Sikob hdr_len = 12; 738103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 739103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 740103285Sikob ohcifp->mode.common.spd = 0; 741103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 742103285Sikob } else { 743103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 744103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 745103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 746103285Sikob } 747103285Sikob db = &db_tr->db[0]; 748103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 749103285Sikob db->db.desc.status = 0; 750103285Sikob/* Specify bound timer of asy. responce */ 751103285Sikob if(&sc->atrs == dbch){ 752103285Sikob db->db.desc.count 753103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 754103285Sikob } 755103285Sikob 756103285Sikob db_tr->dbcnt = 2; 757103285Sikob db = &db_tr->db[db_tr->dbcnt]; 758103285Sikob if(len > hdr_off){ 759103285Sikob if (xfer->mbuf == NULL) { 760103285Sikob db->db.desc.addr 761103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 762103285Sikob db->db.desc.cmd 763103285Sikob = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 764103285Sikob db->db.desc.status = 0; 765103285Sikob 766103285Sikob db_tr->dbcnt++; 767103285Sikob } else { 768103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 769103285Sikob m = xfer->mbuf; 770103285Sikob do { 771103285Sikob db->db.desc.addr 772103285Sikob = vtophys(mtod(m, caddr_t)); 773103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 774103285Sikob db->db.desc.status = 0; 775103285Sikob db++; 776103285Sikob db_tr->dbcnt++; 777103285Sikob m = m->m_next; 778103285Sikob } while (m != NULL); 779103285Sikob } 780103285Sikob } 781103285Sikob /* last db */ 782103285Sikob LAST_DB(db_tr, db); 783103285Sikob db->db.desc.cmd |= OHCI_OUTPUT_LAST 784103285Sikob | OHCI_INTERRUPT_ALWAYS 785103285Sikob | OHCI_BRANCH_ALWAYS; 786103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 787103285Sikob 788103285Sikob if(fsegment == -1 ) 789103285Sikob fsegment = db_tr->dbcnt; 790103285Sikob if (dbch->pdb_tr != NULL) { 791103285Sikob LAST_DB(dbch->pdb_tr, db); 792103285Sikob db->db.desc.depend |= db_tr->dbcnt; 793103285Sikob } 794103285Sikob dbch->pdb_tr = db_tr; 795103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 796103285Sikob if(db_tr != dbch->bottom){ 797103285Sikob goto txloop; 798103285Sikob } else { 799107653Ssimokawa device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 800103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 801103285Sikob } 802103285Sikobkick: 803103285Sikob if (firewire_debug) printf("kick\n"); 804103285Sikob /* kick asy q */ 805103285Sikob 806103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 807103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 808103285Sikob } else { 809107653Ssimokawa if (bootverbose) 810107653Ssimokawa device_printf(sc->fc.dev, "start AT DMA status=%x\n", 811103285Sikob OREAD(sc, OHCI_DMACTL(off))); 812103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 813103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 814103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 815103285Sikob } 816106790Ssimokawa 817103285Sikob dbch->top = db_tr; 818103285Sikob splx(s); 819103285Sikob return; 820103285Sikob} 821106790Ssimokawa 822106790Ssimokawastatic void 823106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 824103285Sikob{ 825103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 826103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 827103285Sikob return; 828103285Sikob} 829106790Ssimokawa 830106790Ssimokawastatic void 831106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 832103285Sikob{ 833103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 834103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 835103285Sikob return; 836103285Sikob} 837106790Ssimokawa 838106790Ssimokawastatic void 839106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 840103285Sikob{ 841103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 842103285Sikob fwohci_start( sc, &(sc->atrq)); 843103285Sikob return; 844103285Sikob} 845106790Ssimokawa 846106790Ssimokawastatic void 847106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 848103285Sikob{ 849103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 850103285Sikob fwohci_start( sc, &(sc->atrs)); 851103285Sikob return; 852103285Sikob} 853106790Ssimokawa 854106790Ssimokawavoid 855106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 856103285Sikob{ 857103285Sikob int s, err = 0; 858103285Sikob struct fwohcidb_tr *tr; 859103285Sikob volatile struct fwohcidb *db; 860103285Sikob struct fw_xfer *xfer; 861103285Sikob u_int32_t off; 862103285Sikob u_int stat; 863103285Sikob int packets; 864103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 865103285Sikob if(&sc->atrq == dbch){ 866103285Sikob off = OHCI_ATQOFF; 867103285Sikob }else if(&sc->atrs == dbch){ 868103285Sikob off = OHCI_ATSOFF; 869103285Sikob }else{ 870103285Sikob return; 871103285Sikob } 872103285Sikob s = splfw(); 873103285Sikob tr = dbch->bottom; 874103285Sikob packets = 0; 875103285Sikob while(dbch->xferq.queued > 0){ 876103285Sikob LAST_DB(tr, db); 877103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 878103285Sikob if (fc->status != FWBUSRESET) 879103285Sikob /* maybe out of order?? */ 880103285Sikob goto out; 881103285Sikob } 882103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 883103285Sikob#ifdef OHCI_DEBUG 884103285Sikob dump_dma(sc, ch); 885103285Sikob dump_db(sc, ch); 886103285Sikob#endif 887103285Sikob/* Stop DMA */ 888103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 889103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 890103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 891103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 892103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 893103285Sikob } 894103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 895103285Sikob switch(stat){ 896103285Sikob case FWOHCIEV_ACKCOMPL: 897103285Sikob case FWOHCIEV_ACKPEND: 898103285Sikob err = 0; 899103285Sikob break; 900103285Sikob case FWOHCIEV_ACKBSA: 901103285Sikob case FWOHCIEV_ACKBSB: 902103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 903103285Sikob case FWOHCIEV_ACKBSX: 904103285Sikob err = EBUSY; 905103285Sikob break; 906103285Sikob case FWOHCIEV_FLUSHED: 907103285Sikob case FWOHCIEV_ACKTARD: 908103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 909103285Sikob err = EAGAIN; 910103285Sikob break; 911103285Sikob case FWOHCIEV_MISSACK: 912103285Sikob case FWOHCIEV_UNDRRUN: 913103285Sikob case FWOHCIEV_OVRRUN: 914103285Sikob case FWOHCIEV_DESCERR: 915103285Sikob case FWOHCIEV_DTRDERR: 916103285Sikob case FWOHCIEV_TIMEOUT: 917103285Sikob case FWOHCIEV_TCODERR: 918103285Sikob case FWOHCIEV_UNKNOWN: 919103285Sikob case FWOHCIEV_ACKDERR: 920103285Sikob case FWOHCIEV_ACKTERR: 921103285Sikob default: 922103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 923103285Sikob stat, fwohcicode[stat]); 924103285Sikob err = EINVAL; 925103285Sikob break; 926103285Sikob } 927103285Sikob if(tr->xfer != NULL){ 928103285Sikob xfer = tr->xfer; 929103285Sikob xfer->state = FWXF_SENT; 930103285Sikob if(err == EBUSY && fc->status != FWBUSRESET){ 931103285Sikob xfer->state = FWXF_BUSY; 932103285Sikob switch(xfer->act_type){ 933103285Sikob case FWACT_XFER: 934103285Sikob xfer->resp = err; 935103285Sikob if(xfer->retry_req != NULL){ 936103285Sikob xfer->retry_req(xfer); 937103285Sikob } 938103285Sikob break; 939103285Sikob default: 940103285Sikob break; 941103285Sikob } 942103285Sikob } else if( stat != FWOHCIEV_ACKPEND){ 943103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 944103285Sikob xfer->state = FWXF_SENTERR; 945103285Sikob xfer->resp = err; 946103285Sikob switch(xfer->act_type){ 947103285Sikob case FWACT_XFER: 948103285Sikob fw_xfer_done(xfer); 949103285Sikob break; 950103285Sikob default: 951103285Sikob break; 952103285Sikob } 953103285Sikob } 954103285Sikob dbch->xferq.queued --; 955103285Sikob } 956103285Sikob tr->xfer = NULL; 957103285Sikob 958103285Sikob packets ++; 959103285Sikob tr = STAILQ_NEXT(tr, link); 960103285Sikob dbch->bottom = tr; 961103285Sikob } 962103285Sikobout: 963103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 964103285Sikob printf("make free slot\n"); 965103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 966103285Sikob fwohci_start(sc, dbch); 967103285Sikob } 968103285Sikob splx(s); 969103285Sikob} 970106790Ssimokawa 971106790Ssimokawastatic void 972106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 973103285Sikob{ 974103285Sikob int i, s; 975103285Sikob struct fwohcidb_tr *tr; 976103285Sikob 977103285Sikob if(xfer->state != FWXF_START) return; 978103285Sikob 979103285Sikob s = splfw(); 980103285Sikob tr = dbch->bottom; 981103285Sikob for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 982103285Sikob if(tr->xfer == xfer){ 983103285Sikob s = splfw(); 984103285Sikob tr->xfer = NULL; 985103285Sikob dbch->xferq.queued --; 986103285Sikob#if 1 987103285Sikob /* XXX */ 988103285Sikob if (tr == dbch->bottom) 989103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 990103285Sikob#endif 991103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 992103285Sikob printf("fwohci_drain: make slot\n"); 993103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 994103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 995103285Sikob } 996103285Sikob 997103285Sikob splx(s); 998103285Sikob break; 999103285Sikob } 1000103285Sikob tr = STAILQ_NEXT(tr, link); 1001103285Sikob } 1002103285Sikob splx(s); 1003103285Sikob return; 1004103285Sikob} 1005103285Sikob 1006106790Ssimokawastatic void 1007106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 1008103285Sikob{ 1009103285Sikob struct fwohcidb_tr *db_tr; 1010103285Sikob int idb; 1011103285Sikob 1012103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1013103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1014103285Sikob idb < dbch->ndb; 1015103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1016103285Sikob free(db_tr->buf, M_DEVBUF); 1017103285Sikob db_tr->buf = NULL; 1018103285Sikob } 1019103285Sikob } 1020103285Sikob dbch->ndb = 0; 1021103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1022103285Sikob contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1023103285Sikob sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1024103285Sikob /* Attach DB to DMA ch. */ 1025103285Sikob free(db_tr, M_DEVBUF); 1026103285Sikob STAILQ_INIT(&dbch->db_trq); 1027103285Sikob} 1028106790Ssimokawa 1029106790Ssimokawastatic void 1030106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1031103285Sikob{ 1032103285Sikob int idb; 1033103285Sikob struct fwohcidb *db; 1034103285Sikob struct fwohcidb_tr *db_tr; 1035103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1036103285Sikob /* DB entry must start at 16 bytes bounary. */ 1037103285Sikob dbch->frag.buf = NULL; 1038103285Sikob dbch->frag.len = 0; 1039103285Sikob dbch->frag.plen = 0; 1040103285Sikob dbch->xferq.queued = 0; 1041103285Sikob dbch->pdb_tr = NULL; 1042103285Sikob 1043103285Sikob STAILQ_INIT(&dbch->db_trq); 1044103285Sikob db_tr = (struct fwohcidb_tr *) 1045103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1046103285Sikob M_DEVBUF, M_DONTWAIT); 1047103285Sikob if(db_tr == NULL){ 1048103285Sikob return; 1049103285Sikob } 1050103285Sikob db = (struct fwohcidb *) 1051103285Sikob contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1052103285Sikob M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1053103285Sikob if(db == NULL){ 1054103285Sikob printf("fwochi_db_init: contigmalloc failed\n"); 1055103285Sikob return; 1056103285Sikob } 1057103285Sikob bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1058103285Sikob /* Attach DB to DMA ch. */ 1059103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1060103285Sikob db_tr->dbcnt = 0; 1061103285Sikob db_tr->db = &db[idb * dbch->ndesc]; 1062103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1063103285Sikob if(!(dbch->xferq.flag & FWXFERQ_PACKET) && 1064103285Sikob (idb % dbch->xferq.bnpacket == 0)){ 1065103285Sikob dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].start 1066103285Sikob = (caddr_t)db_tr; 1067103285Sikob } 1068103285Sikob if((!(dbch->xferq.flag & FWXFERQ_PACKET)) && 1069103285Sikob ((idb + 1)% dbch->xferq.bnpacket == 0)){ 1070103285Sikob dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].end 1071103285Sikob = (caddr_t)db_tr; 1072103285Sikob } 1073103285Sikob db_tr++; 1074103285Sikob } 1075103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1076103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1077103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1078103285Sikob dbch->bottom = dbch->top; 1079103285Sikob} 1080106790Ssimokawa 1081106790Ssimokawastatic int 1082106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1083103285Sikob{ 1084103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1085103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1086103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1087103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1088103285Sikob fwohci_db_free(&sc->it[dmach]); 1089103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1090103285Sikob return 0; 1091103285Sikob} 1092106790Ssimokawa 1093106790Ssimokawastatic int 1094106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1095103285Sikob{ 1096103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1097103285Sikob 1098103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1099103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1100103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1101103285Sikob if(sc->ir[dmach].dummy != NULL){ 1102103285Sikob free(sc->ir[dmach].dummy, M_DEVBUF); 1103103285Sikob } 1104103285Sikob sc->ir[dmach].dummy = NULL; 1105103285Sikob fwohci_db_free(&sc->ir[dmach]); 1106103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1107103285Sikob return 0; 1108103285Sikob} 1109106790Ssimokawa 1110106790Ssimokawastatic void 1111106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1112103285Sikob{ 1113103285Sikob qld[0] = ntohl(qld[0]); 1114103285Sikob return; 1115103285Sikob} 1116106790Ssimokawa 1117106790Ssimokawastatic int 1118106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1119103285Sikob{ 1120103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1121103285Sikob int err = 0; 1122103285Sikob unsigned short tag, ich; 1123103285Sikob 1124103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1125103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1126103285Sikob 1127103285Sikob#if 0 1128103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1129103285Sikob wakeup(fc->ir[dmach]); 1130103285Sikob return err; 1131103285Sikob } 1132103285Sikob#endif 1133103285Sikob 1134103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1135103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1136103285Sikob sc->ir[dmach].xferq.queued = 0; 1137103285Sikob sc->ir[dmach].ndb = NDB; 1138103285Sikob sc->ir[dmach].xferq.psize = FWPMAX_S400; 1139103285Sikob sc->ir[dmach].ndesc = 1; 1140103285Sikob fwohci_db_init(&sc->ir[dmach]); 1141103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1142103285Sikob } 1143103285Sikob if(err){ 1144103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1145103285Sikob return err; 1146103285Sikob } 1147103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1148103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1149103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1150103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1151103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1152103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1153103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1154103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1155103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1156103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1157103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1158103285Sikob } 1159103285Sikob return err; 1160103285Sikob} 1161106790Ssimokawa 1162106790Ssimokawastatic int 1163106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1164103285Sikob{ 1165103285Sikob int err = 0; 1166103285Sikob int idb, z, i, dmach = 0; 1167103285Sikob u_int32_t off = NULL; 1168103285Sikob struct fwohcidb_tr *db_tr; 1169103285Sikob 1170103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1171103285Sikob err = EINVAL; 1172103285Sikob return err; 1173103285Sikob } 1174103285Sikob z = dbch->ndesc; 1175103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1176103285Sikob if( &sc->it[dmach] == dbch){ 1177103285Sikob off = OHCI_ITOFF(dmach); 1178103285Sikob break; 1179103285Sikob } 1180103285Sikob } 1181103285Sikob if(off == NULL){ 1182103285Sikob err = EINVAL; 1183103285Sikob return err; 1184103285Sikob } 1185103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1186103285Sikob return err; 1187103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1188103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1189103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1190103285Sikob } 1191103285Sikob db_tr = dbch->top; 1192103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1193103285Sikob fwohci_add_tx_buf(db_tr, 1194103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1195103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1196103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1197103285Sikob break; 1198103285Sikob } 1199103285Sikob db_tr->db[0].db.desc.depend 1200103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1201103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1202103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1203103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1204103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1205103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1206103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1207103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 1208103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1209103285Sikob ~0xf; 1210103285Sikob } 1211103285Sikob } 1212103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1213103285Sikob } 1214103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1215103285Sikob return err; 1216103285Sikob} 1217106790Ssimokawa 1218106790Ssimokawastatic int 1219106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1220103285Sikob{ 1221103285Sikob int err = 0; 1222103285Sikob int idb, z, i, dmach = 0; 1223103285Sikob u_int32_t off = NULL; 1224103285Sikob struct fwohcidb_tr *db_tr; 1225103285Sikob 1226103285Sikob z = dbch->ndesc; 1227103285Sikob if(&sc->arrq == dbch){ 1228103285Sikob off = OHCI_ARQOFF; 1229103285Sikob }else if(&sc->arrs == dbch){ 1230103285Sikob off = OHCI_ARSOFF; 1231103285Sikob }else{ 1232103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1233103285Sikob if( &sc->ir[dmach] == dbch){ 1234103285Sikob off = OHCI_IROFF(dmach); 1235103285Sikob break; 1236103285Sikob } 1237103285Sikob } 1238103285Sikob } 1239103285Sikob if(off == NULL){ 1240103285Sikob err = EINVAL; 1241103285Sikob return err; 1242103285Sikob } 1243103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1244103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1245103285Sikob return err; 1246103285Sikob }else{ 1247103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1248103285Sikob err = EBUSY; 1249103285Sikob return err; 1250103285Sikob } 1251103285Sikob } 1252103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1253103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1254103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1255103285Sikob } 1256103285Sikob db_tr = dbch->top; 1257103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1258103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1259103285Sikob fwohci_add_rx_buf(db_tr, 1260103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1261103285Sikob }else{ 1262103285Sikob fwohci_add_rx_buf(db_tr, 1263103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1264103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1265103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1266103285Sikob } 1267103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1268103285Sikob break; 1269103285Sikob } 1270103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1271103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1272103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1273103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1274103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1275103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1276103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1277103285Sikob ~0xf; 1278103285Sikob } 1279103285Sikob } 1280103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1281103285Sikob } 1282103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1283103285Sikob dbch->buf_offset = 0; 1284103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1285103285Sikob return err; 1286103285Sikob }else{ 1287103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1288103285Sikob } 1289103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1290103285Sikob return err; 1291103285Sikob} 1292106790Ssimokawa 1293106790Ssimokawastatic int 1294106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1295103285Sikob{ 1296103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1297103285Sikob int err = 0; 1298103285Sikob unsigned short tag, ich; 1299103285Sikob struct fwohci_dbch *dbch; 1300103285Sikob struct fw_pkt *fp; 1301103285Sikob struct fwohcidb_tr *db_tr; 1302103285Sikob 1303103285Sikob tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1304103285Sikob ich = sc->it[dmach].xferq.flag & 0x3f; 1305103285Sikob dbch = &sc->it[dmach]; 1306103285Sikob if(dbch->ndb == 0){ 1307103285Sikob dbch->xferq.queued = 0; 1308103285Sikob dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1309103285Sikob dbch->ndesc = 3; 1310103285Sikob fwohci_db_init(dbch); 1311103285Sikob err = fwohci_tx_enable(sc, dbch); 1312103285Sikob } 1313103285Sikob if(err) 1314103285Sikob return err; 1315103285Sikob if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1316103285Sikob if(dbch->xferq.stdma2 != NULL){ 1317103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1318103285Sikob ((struct fwohcidb_tr *) 1319103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1320103285Sikob |= OHCI_BRANCH_ALWAYS; 1321103285Sikob ((struct fwohcidb_tr *) 1322103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1323103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1324103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1325103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1326103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1327103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1328103285Sikob } 1329103285Sikob }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1330103285Sikob fw_tbuf_update(&sc->fc, dmach, 0); 1331103285Sikob if(dbch->xferq.stdma == NULL){ 1332103285Sikob return err; 1333103285Sikob } 1334103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1335103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1336103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1337103285Sikob OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1338103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1339103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1340103285Sikob if(dbch->xferq.stdma2 != NULL){ 1341103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1342103285Sikob ((struct fwohcidb_tr *) 1343103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1344103285Sikob |= OHCI_BRANCH_ALWAYS; 1345103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1346103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1347103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1348103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1349103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1350103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1351103285Sikob }else{ 1352103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1353103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1354103285Sikob } 1355103285Sikob OWRITE(sc, OHCI_ITCMD(dmach), 1356103285Sikob vtophys(((struct fwohcidb_tr *) 1357103285Sikob (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1358103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1359103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1360103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1361103285Sikob fp->mode.ld[2] = htonl(0x80000000 + 1362103285Sikob ((fc->cyctimer(fc) + 0x3000) & 0xf000)); 1363103285Sikob } 1364103285Sikob 1365103285Sikob OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1366103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1367103285Sikob } 1368103285Sikob return err; 1369103285Sikob} 1370106790Ssimokawa 1371106790Ssimokawastatic int 1372106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1373103285Sikob{ 1374103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1375103285Sikob int err = 0; 1376103285Sikob unsigned short tag, ich; 1377103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1378103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1379103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1380103285Sikob 1381103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1382103285Sikob sc->ir[dmach].xferq.queued = 0; 1383103285Sikob sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1384103285Sikob sc->ir[dmach].xferq.bnchunk; 1385103285Sikob sc->ir[dmach].dummy = 1386103285Sikob malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1387103285Sikob M_DEVBUF, M_DONTWAIT); 1388103285Sikob if(sc->ir[dmach].dummy == NULL){ 1389103285Sikob err = ENOMEM; 1390103285Sikob return err; 1391103285Sikob } 1392103285Sikob sc->ir[dmach].ndesc = 2; 1393103285Sikob fwohci_db_init(&sc->ir[dmach]); 1394103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1395103285Sikob } 1396103285Sikob if(err) 1397103285Sikob return err; 1398103285Sikob 1399103285Sikob if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1400103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1401103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1402103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1403103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1404103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1405103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1406103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1407103285Sikob } 1408103285Sikob }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1409103285Sikob && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1410103285Sikob fw_rbuf_update(&sc->fc, dmach, 0); 1411103285Sikob 1412103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1413103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1414103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1415103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1416103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1417103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1418103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1419103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1420103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1421103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1422103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1423103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1424103285Sikob }else{ 1425103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1426103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1427103285Sikob } 1428103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1429103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1430103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1431103285Sikob } 1432103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1433103285Sikob return err; 1434103285Sikob} 1435106790Ssimokawa 1436106790Ssimokawastatic int 1437106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1438103285Sikob{ 1439103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1440103285Sikob int err = 0; 1441103285Sikob 1442103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1443103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1444103285Sikob return err; 1445103285Sikob }else{ 1446103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1447103285Sikob return err; 1448103285Sikob } 1449103285Sikob} 1450106790Ssimokawa 1451106790Ssimokawaint 1452106790Ssimokawafwohci_shutdown(device_t dev) 1453103285Sikob{ 1454103285Sikob u_int i; 1455103285Sikob struct fwohci_softc *sc = device_get_softc(dev); 1456103285Sikob 1457103285Sikob/* Now stopping all DMA channel */ 1458103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1459103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1460103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1461103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1462103285Sikob 1463103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1464103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1465103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1466103285Sikob } 1467103285Sikob 1468103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1469103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1470103285Sikob 1471103285Sikob/* Stop interrupt */ 1472103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1473103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1474103285Sikob | OHCI_INT_PHY_INT 1475103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1476103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1477103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1478103285Sikob | OHCI_INT_PHY_BUS_R); 1479103285Sikob return 0; 1480103285Sikob} 1481103285Sikob 1482103285Sikob#define ACK_ALL 1483103285Sikobstatic void 1484106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1485103285Sikob{ 1486103285Sikob u_int32_t irstat, itstat; 1487103285Sikob u_int i; 1488103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1489103285Sikob 1490103285Sikob#ifdef OHCI_DEBUG 1491103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1492103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1493103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1494103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1495103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1496103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1497103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1498103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1499103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1500103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1501103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1502103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1503103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1504103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1505103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1506103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1507103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1508103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1509103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1510103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1511103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1512103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1513103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1514103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1515103285Sikob ); 1516103285Sikob#endif 1517103285Sikob/* Bus reset */ 1518103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1519103285Sikob device_printf(fc->dev, "BUS reset\n"); 1520103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1521103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1522103285Sikob 1523103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1524103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1525103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1526103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1527103285Sikob 1528103285Sikob#if 0 1529103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1530103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1531103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1532103285Sikob } 1533103285Sikob 1534103285Sikob#endif 1535103285Sikob fw_busreset(fc); 1536103285Sikob 1537103285Sikob /* XXX need to wait DMA to stop */ 1538103285Sikob#ifndef ACK_ALL 1539103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1540103285Sikob#endif 1541103285Sikob#if 1 1542103285Sikob /* pending all pre-bus_reset packets */ 1543103285Sikob fwohci_txd(sc, &sc->atrq); 1544103285Sikob fwohci_txd(sc, &sc->atrs); 1545106789Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1546106789Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1547103285Sikob#endif 1548103285Sikob 1549103285Sikob 1550103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1551103285Sikob /* XXX insecure ?? */ 1552103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1553103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1554103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1555103285Sikob 1556103285Sikob } 1557103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1558103285Sikob#ifndef ACK_ALL 1559103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1560103285Sikob#endif 1561103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1562103285Sikob OWRITE(sc, OHCI_IR_STATCLR, ~0); 1563103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1564103285Sikob if((irstat & (1 << i)) != 0){ 1565103285Sikob if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1566106789Ssimokawa fwohci_ircv(sc, &sc->ir[i], count); 1567103285Sikob }else{ 1568103285Sikob fwohci_rbuf_update(sc, i); 1569103285Sikob } 1570103285Sikob } 1571103285Sikob } 1572103285Sikob } 1573103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1574103285Sikob#ifndef ACK_ALL 1575103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1576103285Sikob#endif 1577103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1578103285Sikob OWRITE(sc, OHCI_IT_STATCLR, ~0); 1579103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1580103285Sikob if((itstat & (1 << i)) != 0){ 1581103285Sikob fwohci_tbuf_update(sc, i); 1582103285Sikob } 1583103285Sikob } 1584103285Sikob } 1585103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1586103285Sikob#ifndef ACK_ALL 1587103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1588103285Sikob#endif 1589103285Sikob#if 0 1590103285Sikob dump_dma(sc, ARRS_CH); 1591103285Sikob dump_db(sc, ARRS_CH); 1592103285Sikob#endif 1593106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1594103285Sikob } 1595103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1596103285Sikob#ifndef ACK_ALL 1597103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1598103285Sikob#endif 1599103285Sikob#if 0 1600103285Sikob dump_dma(sc, ARRQ_CH); 1601103285Sikob dump_db(sc, ARRQ_CH); 1602103285Sikob#endif 1603106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1604103285Sikob } 1605103285Sikob if(stat & OHCI_INT_PHY_SID){ 1606103285Sikob caddr_t buf; 1607103285Sikob int plen; 1608103285Sikob 1609103285Sikob#ifndef ACK_ALL 1610103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1611103285Sikob#endif 1612103285Sikob/* 1613103285Sikob** Checking whether the node is root or not. If root, turn on 1614103285Sikob** cycle master. 1615103285Sikob*/ 1616103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1617103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1618103285Sikob printf("Bus reset failure\n"); 1619103285Sikob goto sidout; 1620103285Sikob } 1621103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1622103285Sikob printf("CYCLEMASTER mode\n"); 1623103285Sikob OWRITE(sc, OHCI_LNKCTL, 1624103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1625103285Sikob }else{ 1626103285Sikob printf("non CYCLEMASTER mode\n"); 1627103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1628103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1629103285Sikob } 1630103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1631103285Sikob 1632103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1633103285Sikob plen -= 4; /* chop control info */ 1634103285Sikob buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1635103285Sikob if(buf == NULL) goto sidout; 1636103285Sikob bcopy((void *)(uintptr_t)(volatile void *)fc->sid_buf, 1637103285Sikob buf, plen); 1638103285Sikob fw_sidrcv(fc, buf, plen, 0); 1639103285Sikob } 1640103285Sikobsidout: 1641103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1642103285Sikob#ifndef ACK_ALL 1643103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1644103285Sikob#endif 1645103285Sikob fwohci_txd(sc, &(sc->atrq)); 1646103285Sikob } 1647103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1648103285Sikob#ifndef ACK_ALL 1649103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1650103285Sikob#endif 1651103285Sikob fwohci_txd(sc, &(sc->atrs)); 1652103285Sikob } 1653103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1654103285Sikob#ifndef ACK_ALL 1655103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1656103285Sikob#endif 1657103285Sikob device_printf(fc->dev, "posted write error\n"); 1658103285Sikob } 1659103285Sikob if((stat & OHCI_INT_ERR )){ 1660103285Sikob#ifndef ACK_ALL 1661103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1662103285Sikob#endif 1663103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1664103285Sikob } 1665103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1666103285Sikob#ifndef ACK_ALL 1667103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1668103285Sikob#endif 1669103285Sikob device_printf(fc->dev, "phy int\n"); 1670103285Sikob } 1671103285Sikob 1672103285Sikob return; 1673103285Sikob} 1674103285Sikob 1675103285Sikobvoid 1676103285Sikobfwohci_intr(void *arg) 1677103285Sikob{ 1678103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1679103285Sikob u_int32_t stat; 1680103285Sikob 1681103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1682103285Sikob /* polling mode */ 1683103285Sikob return; 1684103285Sikob } 1685103285Sikob 1686103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1687103285Sikob if (stat == 0xffffffff) { 1688103285Sikob device_printf(sc->fc.dev, 1689103285Sikob "device physically ejected?\n"); 1690103285Sikob return; 1691103285Sikob } 1692103285Sikob#ifdef ACK_ALL 1693103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1694103285Sikob#endif 1695106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1696103285Sikob } 1697103285Sikob} 1698103285Sikob 1699103285Sikobstatic void 1700103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1701103285Sikob{ 1702103285Sikob int s; 1703103285Sikob u_int32_t stat; 1704103285Sikob struct fwohci_softc *sc; 1705103285Sikob 1706103285Sikob 1707103285Sikob sc = (struct fwohci_softc *)fc; 1708103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1709103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1710103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1711103285Sikob#if 0 1712103285Sikob if (!quick) { 1713103285Sikob#else 1714103285Sikob if (1) { 1715103285Sikob#endif 1716103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1717103285Sikob if (stat == 0) 1718103285Sikob return; 1719103285Sikob if (stat == 0xffffffff) { 1720103285Sikob device_printf(sc->fc.dev, 1721103285Sikob "device physically ejected?\n"); 1722103285Sikob return; 1723103285Sikob } 1724103285Sikob#ifdef ACK_ALL 1725103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1726103285Sikob#endif 1727103285Sikob } 1728103285Sikob s = splfw(); 1729106789Ssimokawa fwohci_intr_body(sc, stat, count); 1730103285Sikob splx(s); 1731103285Sikob} 1732103285Sikob 1733103285Sikobstatic void 1734103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 1735103285Sikob{ 1736103285Sikob struct fwohci_softc *sc; 1737103285Sikob 1738103285Sikob sc = (struct fwohci_softc *)fc; 1739107653Ssimokawa if (bootverbose) 1740107653Ssimokawa device_printf(sc->fc.dev, "fwochi_set_intr: %d\n", enable); 1741103285Sikob if (enable) { 1742103285Sikob sc->intmask |= OHCI_INT_EN; 1743103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1744103285Sikob } else { 1745103285Sikob sc->intmask &= ~OHCI_INT_EN; 1746103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1747103285Sikob } 1748103285Sikob} 1749103285Sikob 1750106790Ssimokawastatic void 1751106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1752103285Sikob{ 1753103285Sikob int stat; 1754103285Sikob struct firewire_comm *fc = &sc->fc; 1755103285Sikob struct fw_pkt *fp; 1756103285Sikob struct fwohci_dbch *dbch; 1757103285Sikob struct fwohcidb_tr *db_tr; 1758103285Sikob 1759103285Sikob dbch = &sc->it[dmach]; 1760103285Sikob if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1761103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1762103285Sikob/* 1763103285Sikob * Overwrite highest significant 4 bits timestamp information 1764103285Sikob */ 1765103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1766103285Sikob fp->mode.ld[2] |= htonl(0x80000000 | 1767103285Sikob ((fc->cyctimer(fc) + 0x4000) & 0xf000)); 1768103285Sikob } 1769103285Sikob stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1770103285Sikob switch(stat){ 1771103285Sikob case FWOHCIEV_ACKCOMPL: 1772103285Sikob fw_tbuf_update(fc, dmach, 1); 1773103285Sikob break; 1774103285Sikob default: 1775103285Sikob fw_tbuf_update(fc, dmach, 0); 1776103285Sikob break; 1777103285Sikob } 1778103285Sikob fwohci_itxbuf_enable(&sc->fc, dmach); 1779103285Sikob} 1780106790Ssimokawa 1781106790Ssimokawastatic void 1782106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1783103285Sikob{ 1784103285Sikob int stat; 1785103285Sikob stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1786103285Sikob switch(stat){ 1787103285Sikob case FWOHCIEV_ACKCOMPL: 1788103285Sikob fw_rbuf_update(&sc->fc, dmach, 1); 1789103285Sikob wakeup(sc->fc.ir[dmach]); 1790103285Sikob fwohci_irx_enable(&sc->fc, dmach); 1791103285Sikob break; 1792103285Sikob default: 1793103285Sikob break; 1794103285Sikob } 1795103285Sikob} 1796106790Ssimokawa 1797106790Ssimokawavoid 1798106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 1799106790Ssimokawa{ 1800103285Sikob u_int32_t off, cntl, stat, cmd, match; 1801103285Sikob 1802103285Sikob if(ch == 0){ 1803103285Sikob off = OHCI_ATQOFF; 1804103285Sikob }else if(ch == 1){ 1805103285Sikob off = OHCI_ATSOFF; 1806103285Sikob }else if(ch == 2){ 1807103285Sikob off = OHCI_ARQOFF; 1808103285Sikob }else if(ch == 3){ 1809103285Sikob off = OHCI_ARSOFF; 1810103285Sikob }else if(ch < IRX_CH){ 1811103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1812103285Sikob }else{ 1813103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1814103285Sikob } 1815103285Sikob cntl = stat = OREAD(sc, off); 1816103285Sikob cmd = OREAD(sc, off + 0xc); 1817103285Sikob match = OREAD(sc, off + 0x10); 1818103285Sikob 1819103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1820103285Sikob ch, 1821103285Sikob cntl, 1822103285Sikob stat, 1823103285Sikob cmd, 1824103285Sikob match); 1825103285Sikob stat &= 0xffff ; 1826103285Sikob if(stat & 0xff00){ 1827103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 1828103285Sikob ch, 1829103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1830103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1831103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1832103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1833103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1834103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1835103285Sikob fwohcicode[stat & 0x1f], 1836103285Sikob stat & 0x1f 1837103285Sikob ); 1838103285Sikob }else{ 1839103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 1840103285Sikob } 1841103285Sikob} 1842106790Ssimokawa 1843106790Ssimokawavoid 1844106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 1845106790Ssimokawa{ 1846103285Sikob struct fwohci_dbch *dbch; 1847103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 1848103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 1849103285Sikob int idb, jdb; 1850103285Sikob u_int32_t cmd, off; 1851103285Sikob if(ch == 0){ 1852103285Sikob off = OHCI_ATQOFF; 1853103285Sikob dbch = &sc->atrq; 1854103285Sikob }else if(ch == 1){ 1855103285Sikob off = OHCI_ATSOFF; 1856103285Sikob dbch = &sc->atrs; 1857103285Sikob }else if(ch == 2){ 1858103285Sikob off = OHCI_ARQOFF; 1859103285Sikob dbch = &sc->arrq; 1860103285Sikob }else if(ch == 3){ 1861103285Sikob off = OHCI_ARSOFF; 1862103285Sikob dbch = &sc->arrs; 1863103285Sikob }else if(ch < IRX_CH){ 1864103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1865103285Sikob dbch = &sc->it[ch - ITX_CH]; 1866103285Sikob }else { 1867103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1868103285Sikob dbch = &sc->ir[ch - IRX_CH]; 1869103285Sikob } 1870103285Sikob cmd = OREAD(sc, off + 0xc); 1871103285Sikob 1872103285Sikob if( dbch->ndb == 0 ){ 1873103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 1874103285Sikob return; 1875103285Sikob } 1876103285Sikob pp = dbch->top; 1877103285Sikob prev = pp->db; 1878103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 1879103285Sikob if(pp == NULL){ 1880103285Sikob curr = NULL; 1881103285Sikob goto outdb; 1882103285Sikob } 1883103285Sikob cp = STAILQ_NEXT(pp, link); 1884103285Sikob if(cp == NULL){ 1885103285Sikob curr = NULL; 1886103285Sikob goto outdb; 1887103285Sikob } 1888103285Sikob np = STAILQ_NEXT(cp, link); 1889103285Sikob if(cp == NULL) break; 1890103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 1891103285Sikob if((cmd & 0xfffffff0) 1892103285Sikob == vtophys(&(cp->db[jdb]))){ 1893103285Sikob curr = cp->db; 1894103285Sikob if(np != NULL){ 1895103285Sikob next = np->db; 1896103285Sikob }else{ 1897103285Sikob next = NULL; 1898103285Sikob } 1899103285Sikob goto outdb; 1900103285Sikob } 1901103285Sikob } 1902103285Sikob pp = STAILQ_NEXT(pp, link); 1903103285Sikob prev = pp->db; 1904103285Sikob } 1905103285Sikoboutdb: 1906103285Sikob if( curr != NULL){ 1907103285Sikob printf("Prev DB %d\n", ch); 1908103285Sikob print_db(prev, ch, dbch->ndesc); 1909103285Sikob printf("Current DB %d\n", ch); 1910103285Sikob print_db(curr, ch, dbch->ndesc); 1911103285Sikob printf("Next DB %d\n", ch); 1912103285Sikob print_db(next, ch, dbch->ndesc); 1913103285Sikob }else{ 1914103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 1915103285Sikob } 1916103285Sikob return; 1917103285Sikob} 1918106790Ssimokawa 1919106790Ssimokawavoid 1920106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 1921106790Ssimokawa{ 1922103285Sikob fwohcireg_t stat; 1923103285Sikob int i, key; 1924103285Sikob 1925103285Sikob if(db == NULL){ 1926103285Sikob printf("No Descriptor is found\n"); 1927103285Sikob return; 1928103285Sikob } 1929103285Sikob 1930103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 1931103285Sikob ch, 1932103285Sikob "Current", 1933103285Sikob "OP ", 1934103285Sikob "KEY", 1935103285Sikob "INT", 1936103285Sikob "BR ", 1937103285Sikob "len", 1938103285Sikob "Addr", 1939103285Sikob "Depend", 1940103285Sikob "Stat", 1941103285Sikob "Cnt"); 1942103285Sikob for( i = 0 ; i <= max ; i ++){ 1943103285Sikob key = db[i].db.desc.cmd & OHCI_KEY_MASK; 1944106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 1945103285Sikob vtophys(&db[i]), 1946103285Sikob dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 1947103285Sikob dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 1948103285Sikob dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 1949103285Sikob dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 1950103285Sikob db[i].db.desc.cmd & 0xffff, 1951103285Sikob db[i].db.desc.addr, 1952103285Sikob db[i].db.desc.depend, 1953103285Sikob db[i].db.desc.status, 1954103285Sikob db[i].db.desc.count); 1955103285Sikob stat = db[i].db.desc.status; 1956103285Sikob if(stat & 0xff00){ 1957103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 1958103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1959103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1960103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1961103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1962103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1963103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1964103285Sikob fwohcicode[stat & 0x1f], 1965103285Sikob stat & 0x1f 1966103285Sikob ); 1967103285Sikob }else{ 1968103285Sikob printf(" Nostat\n"); 1969103285Sikob } 1970103285Sikob if(key == OHCI_KEY_ST2 ){ 1971103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 1972103285Sikob db[i+1].db.immed[0], 1973103285Sikob db[i+1].db.immed[1], 1974103285Sikob db[i+1].db.immed[2], 1975103285Sikob db[i+1].db.immed[3]); 1976103285Sikob } 1977103285Sikob if(key == OHCI_KEY_DEVICE){ 1978103285Sikob return; 1979103285Sikob } 1980103285Sikob if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 1981103285Sikob == OHCI_BRANCH_ALWAYS){ 1982103285Sikob return; 1983103285Sikob } 1984103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 1985103285Sikob == OHCI_OUTPUT_LAST){ 1986103285Sikob return; 1987103285Sikob } 1988103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 1989103285Sikob == OHCI_INPUT_LAST){ 1990103285Sikob return; 1991103285Sikob } 1992103285Sikob if(key == OHCI_KEY_ST2 ){ 1993103285Sikob i++; 1994103285Sikob } 1995103285Sikob } 1996103285Sikob return; 1997103285Sikob} 1998106790Ssimokawa 1999106790Ssimokawavoid 2000106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 2001103285Sikob{ 2002103285Sikob struct fwohci_softc *sc; 2003103285Sikob u_int32_t fun; 2004103285Sikob 2005103285Sikob sc = (struct fwohci_softc *)fc; 2006108276Ssimokawa 2007108276Ssimokawa /* 2008108276Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 2009108276Ssimokawa * shouldn't became the root node. 2010108276Ssimokawa */ 2011108276Ssimokawa fun = fwphy_rddata(sc, FW_PHY_RHB_REG); 2012108276Ssimokawa fun |= FW_PHY_RHB; 2013108276Ssimokawa fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun); 2014103285Sikob#if 1 2015103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2016103285Sikob fun |= FW_PHY_IBR; 2017103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2018103285Sikob#else 2019103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2020103285Sikob fun |= FW_PHY_ISBR; 2021103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2022103285Sikob#endif 2023103285Sikob} 2024106790Ssimokawa 2025106790Ssimokawavoid 2026106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2027103285Sikob{ 2028103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2029103285Sikob struct fwohci_dbch *dbch; 2030103285Sikob struct fw_pkt *fp; 2031103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2032103285Sikob unsigned short chtag; 2033103285Sikob int idb; 2034103285Sikob 2035103285Sikob dbch = &sc->it[dmach]; 2036103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2037103285Sikob 2038103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2039103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2040103285Sikob/* 2041103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2042103285Sikob*/ 2043103285Sikob if(bulkxfer->flag != 0){ 2044103285Sikob return; 2045103285Sikob } 2046103285Sikob bulkxfer->flag = 1; 2047103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2048103285Sikob db_tr->db[0].db.desc.cmd 2049103285Sikob = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2050103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2051103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) 2052103285Sikob db_tr->db[1].db.immed; 2053103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2054103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2055103285Sikob ohcifp->mode.stream.chtag = chtag; 2056103285Sikob ohcifp->mode.stream.tcode = 0xa; 2057103285Sikob ohcifp->mode.stream.spd = 4; 2058103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2059103285Sikob ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2060103285Sikob 2061103285Sikob db_tr->db[2].db.desc.cmd 2062103285Sikob = OHCI_OUTPUT_LAST 2063103285Sikob | OHCI_UPDATE 2064103285Sikob | OHCI_BRANCH_ALWAYS 2065103285Sikob | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2066103285Sikob db_tr->db[2].db.desc.status = 0; 2067103285Sikob db_tr->db[2].db.desc.count = 0; 2068103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 2069103285Sikob db_tr->db[0].db.desc.depend 2070103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2071103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2072103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2073103285Sikob }else{ 2074103285Sikob db_tr->db[0].db.desc.depend 2075103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2076103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2077103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2078103285Sikob } 2079103285Sikob bulkxfer->end = (caddr_t)db_tr; 2080103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2081103285Sikob } 2082103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2083103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2084103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2085103285Sikob/**/ 2086103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2087103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2088103285Sikob/**/ 2089103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2090103285Sikob 2091103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2092103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2093103285Sikob/* 2094103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2095103285Sikob*/ 2096103285Sikob return; 2097103285Sikob} 2098106790Ssimokawa 2099106790Ssimokawastatic int 2100106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2101106790Ssimokawa int mode, void *buf) 2102103285Sikob{ 2103103285Sikob volatile struct fwohcidb *db = db_tr->db; 2104103285Sikob int err = 0; 2105103285Sikob if(buf == 0){ 2106103285Sikob err = EINVAL; 2107103285Sikob return err; 2108103285Sikob } 2109103285Sikob db_tr->buf = buf; 2110103285Sikob db_tr->dbcnt = 3; 2111103285Sikob db_tr->dummy = NULL; 2112103285Sikob 2113103285Sikob db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2114103285Sikob 2115103285Sikob db[2].db.desc.depend = 0; 2116103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2117103285Sikob db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2118103285Sikob 2119103285Sikob db[0].db.desc.status = 0; 2120103285Sikob db[0].db.desc.count = 0; 2121103285Sikob 2122103285Sikob db[2].db.desc.status = 0; 2123103285Sikob db[2].db.desc.count = 0; 2124103285Sikob if( mode & FWXFERQ_STREAM ){ 2125103285Sikob db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2126103285Sikob if(mode & FWXFERQ_PACKET ){ 2127103285Sikob db[2].db.desc.cmd 2128103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2129103285Sikob } 2130103285Sikob } 2131103285Sikob db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2132103285Sikob return 1; 2133103285Sikob} 2134106790Ssimokawa 2135106790Ssimokawaint 2136106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2137106790Ssimokawa void *buf, void *dummy) 2138103285Sikob{ 2139103285Sikob volatile struct fwohcidb *db = db_tr->db; 2140103285Sikob int i; 2141103285Sikob void *dbuf[2]; 2142103285Sikob int dsiz[2]; 2143103285Sikob 2144103285Sikob if(buf == 0){ 2145103285Sikob buf = malloc(size, M_DEVBUF, M_NOWAIT); 2146103285Sikob if(buf == NULL) return 0; 2147103285Sikob db_tr->buf = buf; 2148103285Sikob db_tr->dbcnt = 1; 2149103285Sikob db_tr->dummy = NULL; 2150103285Sikob dsiz[0] = size; 2151103285Sikob dbuf[0] = buf; 2152103285Sikob }else if(dummy == NULL){ 2153103285Sikob db_tr->buf = buf; 2154103285Sikob db_tr->dbcnt = 1; 2155103285Sikob db_tr->dummy = NULL; 2156103285Sikob dsiz[0] = size; 2157103285Sikob dbuf[0] = buf; 2158103285Sikob }else{ 2159103285Sikob db_tr->buf = buf; 2160103285Sikob db_tr->dbcnt = 2; 2161103285Sikob db_tr->dummy = dummy; 2162103285Sikob dsiz[0] = sizeof(u_int32_t); 2163103285Sikob dsiz[1] = size; 2164103285Sikob dbuf[0] = dummy; 2165103285Sikob dbuf[1] = buf; 2166103285Sikob } 2167103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2168103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2169103285Sikob db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2170103285Sikob if( mode & FWXFERQ_STREAM ){ 2171103285Sikob db[i].db.desc.cmd |= OHCI_UPDATE; 2172103285Sikob } 2173103285Sikob db[i].db.desc.status = 0; 2174103285Sikob db[i].db.desc.count = dsiz[i]; 2175103285Sikob } 2176103285Sikob if( mode & FWXFERQ_STREAM ){ 2177103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2178103285Sikob if(mode & FWXFERQ_PACKET ){ 2179103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd 2180103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2181103285Sikob } 2182103285Sikob } 2183103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2184103285Sikob return 1; 2185103285Sikob} 2186106790Ssimokawa 2187106790Ssimokawastatic void 2188106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2189103285Sikob{ 2190103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2191103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2192103285Sikob int z = 1; 2193103285Sikob struct fw_pkt *fp; 2194103285Sikob u_int8_t *ld; 2195103285Sikob u_int32_t off = NULL; 2196103285Sikob u_int32_t stat; 2197103285Sikob u_int32_t *qld; 2198103285Sikob u_int32_t reg; 2199103285Sikob u_int spd; 2200103285Sikob u_int dmach; 2201103285Sikob int len, i, plen; 2202103285Sikob caddr_t buf; 2203103285Sikob 2204103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2205103285Sikob if( &sc->ir[dmach] == dbch){ 2206103285Sikob off = OHCI_IROFF(dmach); 2207103285Sikob break; 2208103285Sikob } 2209103285Sikob } 2210103285Sikob if(off == NULL){ 2211103285Sikob return; 2212103285Sikob } 2213103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2214103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2215103285Sikob return; 2216103285Sikob } 2217103285Sikob 2218103285Sikob odb_tr = NULL; 2219103285Sikob db_tr = dbch->top; 2220103285Sikob i = 0; 2221103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2222106789Ssimokawa if (count >= 0 && count-- == 0) 2223106789Ssimokawa break; 2224103285Sikob ld = (u_int8_t *)db_tr->buf; 2225103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2226103285Sikob /* skip timeStamp */ 2227103285Sikob ld += sizeof(struct fwohci_trailer); 2228103285Sikob } 2229103285Sikob qld = (u_int32_t *)ld; 2230103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2231103285Sikob/* 2232103285Sikob{ 2233103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2234103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2235103285Sikob} 2236103285Sikob*/ 2237103285Sikob fp=(struct fw_pkt *)ld; 2238103285Sikob qld[0] = htonl(qld[0]); 2239103285Sikob plen = sizeof(struct fw_isohdr) 2240103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2241103285Sikob ld += plen; 2242103285Sikob len -= plen; 2243103285Sikob buf = db_tr->buf; 2244103285Sikob db_tr->buf = NULL; 2245103285Sikob stat = reg & 0x1f; 2246103285Sikob spd = reg & 0x3; 2247103285Sikob switch(stat){ 2248103285Sikob case FWOHCIEV_ACKCOMPL: 2249103285Sikob case FWOHCIEV_ACKPEND: 2250103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2251103285Sikob break; 2252103285Sikob default: 2253103285Sikob free(buf, M_DEVBUF); 2254103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2255103285Sikob break; 2256103285Sikob } 2257103285Sikob i++; 2258103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2259103285Sikob dbch->xferq.flag, 0, NULL); 2260103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2261103285Sikob if(dbch->pdb_tr != NULL){ 2262103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2263103285Sikob } else { 2264103285Sikob /* XXX should be rewritten in better way */ 2265103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2266103285Sikob } 2267103285Sikob dbch->pdb_tr = db_tr; 2268103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2269103285Sikob } 2270103285Sikob dbch->top = db_tr; 2271103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2272103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2273103285Sikob return; 2274103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2275103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2276103285Sikob dbch->top = db_tr; 2277103285Sikob fwohci_irx_enable(fc, dmach); 2278103285Sikob} 2279103285Sikob 2280103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2281103285Sikobstatic int 2282103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2283103285Sikob{ 2284103285Sikob int i; 2285103285Sikob 2286103285Sikob for( i = 4; i < hlen ; i+=4){ 2287103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2288103285Sikob } 2289103285Sikob 2290103285Sikob switch(fp->mode.common.tcode){ 2291103285Sikob case FWTCODE_RREQQ: 2292103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2293103285Sikob case FWTCODE_WRES: 2294103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2295103285Sikob case FWTCODE_WREQQ: 2296103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2297103285Sikob case FWTCODE_RREQB: 2298103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2299103285Sikob case FWTCODE_RRESQ: 2300103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2301103285Sikob case FWTCODE_WREQB: 2302103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2303103285Sikob + sizeof(u_int32_t); 2304103285Sikob case FWTCODE_LREQ: 2305103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2306103285Sikob + sizeof(u_int32_t); 2307103285Sikob case FWTCODE_RRESB: 2308103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2309103285Sikob + sizeof(u_int32_t); 2310103285Sikob case FWTCODE_LRES: 2311103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2312103285Sikob + sizeof(u_int32_t); 2313103285Sikob case FWOHCITCODE_PHY: 2314103285Sikob return 16; 2315103285Sikob } 2316103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2317103285Sikob return 0; 2318103285Sikob} 2319103285Sikob 2320106790Ssimokawastatic void 2321106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2322103285Sikob{ 2323103285Sikob struct fwohcidb_tr *db_tr; 2324103285Sikob int z = 1; 2325103285Sikob struct fw_pkt *fp; 2326103285Sikob u_int8_t *ld; 2327103285Sikob u_int32_t stat, off; 2328103285Sikob u_int spd; 2329103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2330103285Sikob int s; 2331103285Sikob caddr_t buf; 2332103285Sikob int resCount; 2333103285Sikob 2334103285Sikob if(&sc->arrq == dbch){ 2335103285Sikob off = OHCI_ARQOFF; 2336103285Sikob }else if(&sc->arrs == dbch){ 2337103285Sikob off = OHCI_ARSOFF; 2338103285Sikob }else{ 2339103285Sikob return; 2340103285Sikob } 2341103285Sikob 2342103285Sikob s = splfw(); 2343103285Sikob db_tr = dbch->top; 2344103285Sikob pcnt = 0; 2345103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2346103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2347103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2348103285Sikob resCount = db_tr->db[0].db.desc.count; 2349103285Sikob len = dbch->xferq.psize - resCount 2350103285Sikob - dbch->buf_offset; 2351103285Sikob while (len > 0 ) { 2352106789Ssimokawa if (count >= 0 && count-- == 0) 2353106789Ssimokawa goto out; 2354103285Sikob if(dbch->frag.buf != NULL){ 2355103285Sikob buf = dbch->frag.buf; 2356103285Sikob if (dbch->frag.plen < 0) { 2357103285Sikob /* incomplete header */ 2358103285Sikob int hlen; 2359103285Sikob 2360103285Sikob hlen = - dbch->frag.plen; 2361103285Sikob rlen = hlen - dbch->frag.len; 2362103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2363103285Sikob ld += rlen; 2364103285Sikob len -= rlen; 2365103285Sikob dbch->frag.len += rlen; 2366103285Sikob#if 0 2367103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2368103285Sikob#endif 2369103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2370103285Sikob dbch->frag.plen 2371103285Sikob = fwohci_get_plen(sc, fp, hlen); 2372103285Sikob if (dbch->frag.plen == 0) 2373103285Sikob goto out; 2374103285Sikob } 2375103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2376103285Sikob#if 0 2377103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2378103285Sikob#endif 2379103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2380103285Sikob rlen); 2381103285Sikob ld += rlen; 2382103285Sikob len -= rlen; 2383103285Sikob plen = dbch->frag.plen; 2384103285Sikob dbch->frag.buf = NULL; 2385103285Sikob dbch->frag.plen = 0; 2386103285Sikob dbch->frag.len = 0; 2387103285Sikob poff = 0; 2388103285Sikob }else{ 2389103285Sikob fp=(struct fw_pkt *)ld; 2390103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2391103285Sikob switch(fp->mode.common.tcode){ 2392103285Sikob case FWTCODE_RREQQ: 2393103285Sikob case FWTCODE_WRES: 2394103285Sikob case FWTCODE_WREQQ: 2395103285Sikob case FWTCODE_RRESQ: 2396103285Sikob case FWOHCITCODE_PHY: 2397103285Sikob hlen = 12; 2398103285Sikob break; 2399103285Sikob case FWTCODE_RREQB: 2400103285Sikob case FWTCODE_WREQB: 2401103285Sikob case FWTCODE_LREQ: 2402103285Sikob case FWTCODE_RRESB: 2403103285Sikob case FWTCODE_LRES: 2404103285Sikob hlen = 16; 2405103285Sikob break; 2406103285Sikob default: 2407103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2408103285Sikob goto out; 2409103285Sikob } 2410103285Sikob if (len >= hlen) { 2411103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2412103285Sikob if (plen == 0) 2413103285Sikob goto out; 2414103285Sikob plen = (plen + 3) & ~3; 2415103285Sikob len -= plen; 2416103285Sikob } else { 2417103285Sikob plen = -hlen; 2418103285Sikob len -= hlen; 2419103285Sikob } 2420103285Sikob if(resCount > 0 || len > 0){ 2421103285Sikob buf = malloc( dbch->xferq.psize, 2422103285Sikob M_DEVBUF, M_NOWAIT); 2423103285Sikob if(buf == NULL){ 2424103285Sikob printf("cannot malloc!\n"); 2425103285Sikob free(db_tr->buf, M_DEVBUF); 2426103285Sikob goto out; 2427103285Sikob } 2428103285Sikob bcopy(ld, buf, plen); 2429103285Sikob poff = 0; 2430103285Sikob dbch->frag.buf = NULL; 2431103285Sikob dbch->frag.plen = 0; 2432103285Sikob dbch->frag.len = 0; 2433103285Sikob }else if(len < 0){ 2434103285Sikob dbch->frag.buf = db_tr->buf; 2435103285Sikob if (plen < 0) { 2436103285Sikob#if 0 2437103285Sikob printf("plen < 0:" 2438103285Sikob "hlen: %d len: %d\n", 2439103285Sikob hlen, len); 2440103285Sikob#endif 2441103285Sikob dbch->frag.len = hlen + len; 2442103285Sikob dbch->frag.plen = -hlen; 2443103285Sikob } else { 2444103285Sikob dbch->frag.len = plen + len; 2445103285Sikob dbch->frag.plen = plen; 2446103285Sikob } 2447103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2448103285Sikob buf = NULL; 2449103285Sikob }else{ 2450103285Sikob buf = db_tr->buf; 2451103285Sikob poff = ld - (u_int8_t *)buf; 2452103285Sikob dbch->frag.buf = NULL; 2453103285Sikob dbch->frag.plen = 0; 2454103285Sikob dbch->frag.len = 0; 2455103285Sikob } 2456103285Sikob ld += plen; 2457103285Sikob } 2458103285Sikob if( buf != NULL){ 2459103285Sikob/* DMA result-code will be written at the tail of packet */ 2460103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2461103285Sikob spd = (stat >> 5) & 0x3; 2462103285Sikob stat &= 0x1f; 2463103285Sikob switch(stat){ 2464103285Sikob case FWOHCIEV_ACKPEND: 2465103285Sikob#if 0 2466103285Sikob printf("fwohci_arcv: ack pending..\n"); 2467103285Sikob#endif 2468103285Sikob /* fall through */ 2469103285Sikob case FWOHCIEV_ACKCOMPL: 2470103285Sikob if( poff != 0 ) 2471103285Sikob bcopy(buf+poff, buf, plen - 4); 2472103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2473103285Sikob break; 2474103285Sikob case FWOHCIEV_BUSRST: 2475103285Sikob free(buf, M_DEVBUF); 2476103285Sikob if (sc->fc.status != FWBUSRESET) 2477103285Sikob printf("got BUSRST packet!?\n"); 2478103285Sikob break; 2479103285Sikob default: 2480103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2481103285Sikob#if 0 /* XXX */ 2482103285Sikob goto out; 2483103285Sikob#endif 2484103285Sikob break; 2485103285Sikob } 2486103285Sikob } 2487103285Sikob pcnt ++; 2488103285Sikob }; 2489103285Sikobout: 2490103285Sikob if (resCount == 0) { 2491103285Sikob /* done on this buffer */ 2492103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2493103285Sikob dbch->xferq.flag, 0, NULL); 2494103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2495103285Sikob dbch->bottom = db_tr; 2496103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2497103285Sikob dbch->top = db_tr; 2498103285Sikob dbch->buf_offset = 0; 2499103285Sikob } else { 2500103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2501103285Sikob break; 2502103285Sikob } 2503103285Sikob /* XXX make sure DMA is not dead */ 2504103285Sikob } 2505103285Sikob#if 0 2506103285Sikob if (pcnt < 1) 2507103285Sikob printf("fwohci_arcv: no packets\n"); 2508103285Sikob#endif 2509103285Sikob splx(s); 2510103285Sikob} 2511