fwohci.c revision 106802
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16106802Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 106802 2002-11-12 10:02:50Z simokawa $ 34103285Sikob * 35103285Sikob */ 36106802Ssimokawa 37103285Sikob#define ATRQ_CH 0 38103285Sikob#define ATRS_CH 1 39103285Sikob#define ARRQ_CH 2 40103285Sikob#define ARRS_CH 3 41103285Sikob#define ITX_CH 4 42103285Sikob#define IRX_CH 0x24 43103285Sikob 44103285Sikob#include <sys/param.h> 45103285Sikob#include <sys/systm.h> 46103285Sikob#include <sys/types.h> 47103285Sikob#include <sys/mbuf.h> 48103285Sikob#include <sys/mman.h> 49103285Sikob#include <sys/socket.h> 50103285Sikob#include <sys/socketvar.h> 51103285Sikob#include <sys/signalvar.h> 52103285Sikob#include <sys/malloc.h> 53103285Sikob#include <sys/uio.h> 54103285Sikob#include <sys/sockio.h> 55103285Sikob#include <sys/bus.h> 56103285Sikob#include <sys/kernel.h> 57103285Sikob#include <sys/conf.h> 58103285Sikob 59103285Sikob#include <machine/bus.h> 60103285Sikob#include <machine/resource.h> 61103285Sikob#include <sys/rman.h> 62103285Sikob 63103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64103285Sikob#include <machine/clock.h> 65103285Sikob#include <pci/pcivar.h> 66103285Sikob#include <pci/pcireg.h> 67103285Sikob#include <vm/vm.h> 68103285Sikob#include <vm/vm_extern.h> 69103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 70103285Sikob 71103285Sikob#include <dev/firewire/firewire.h> 72103285Sikob#include <dev/firewire/firewirebusreg.h> 73103285Sikob#include <dev/firewire/firewirereg.h> 74103285Sikob#include <dev/firewire/fwohcireg.h> 75103285Sikob#include <dev/firewire/fwohcivar.h> 76103285Sikob#include <dev/firewire/firewire_phy.h> 77103285Sikob 78103285Sikob#undef OHCI_DEBUG 79106802Ssimokawa 80103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 81103285Sikob "STOR","LOAD","NOP ","STOP",}; 82103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83103285Sikob "UNDEF","REG","SYS","DEV"}; 84103285Sikobchar fwohcicode[32][0x20]={ 85103285Sikob "No stat","Undef","long","miss Ack err", 86103285Sikob "underrun","overrun","desc err", "data read err", 87103285Sikob "data write err","bus reset","timeout","tcode err", 88103285Sikob "Undef","Undef","unknown event","flushed", 89103285Sikob "Undef","ack complete","ack pend","Undef", 90103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 91103285Sikob "Undef","Undef","Undef","ack tardy", 92103285Sikob "Undef","ack data_err","ack type_err",""}; 93103285Sikob#define MAX_SPEED 2 94103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 95103285Sikobextern int maxrec[MAX_SPEED+1]; 96103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98103285Sikob 99103285Sikobstatic struct tcode_info tinfo[] = { 100103285Sikob/* hdr_len block flag*/ 101103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103103285Sikob/* 2 WRES */ {12, FWTI_RES}, 104103285Sikob/* 3 XXX */ { 0, 0}, 105103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 108103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109103285Sikob/* 8 CYCS */ { 0, 0}, 110103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113103285Sikob/* c XXX */ { 0, 0}, 114103285Sikob/* d XXX */ { 0, 0}, 115103285Sikob/* e PHY */ {12, FWTI_REQ}, 116103285Sikob/* f XXX */ { 0, 0} 117103285Sikob}; 118103285Sikob 119103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 120103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 121103285Sikob 122103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124103285Sikob 125103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 126103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 127103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 128106789Ssimokawastatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129106789Ssimokawastatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 132103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 133103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 142103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 145103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 148103285Sikobstatic void fwohci_timeout __P((void *)); 149103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 150103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 151103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 154103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160103285Sikob 161103285Sikob/* 162103285Sikob * memory allocated for DMA programs 163103285Sikob */ 164103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165103285Sikob 166103285Sikob/* #define NDB 1024 */ 167103285Sikob#define NDB FWMAXQUEUE 168103285Sikob#define NDVDB (DVBUF * NDB) 169103285Sikob 170103285Sikob#define OHCI_VERSION 0x00 171103285Sikob#define OHCI_CROMHDR 0x18 172103285Sikob#define OHCI_BUS_OPT 0x20 173103285Sikob#define OHCI_BUSIRMC (1 << 31) 174103285Sikob#define OHCI_BUSCMC (1 << 30) 175103285Sikob#define OHCI_BUSISC (1 << 29) 176103285Sikob#define OHCI_BUSBMC (1 << 28) 177103285Sikob#define OHCI_BUSPMC (1 << 27) 178103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 180103285Sikob 181103285Sikob#define OHCI_EUID_HI 0x24 182103285Sikob#define OHCI_EUID_LO 0x28 183103285Sikob 184103285Sikob#define OHCI_CROMPTR 0x34 185103285Sikob#define OHCI_HCCCTL 0x50 186103285Sikob#define OHCI_HCCCTLCLR 0x54 187103285Sikob#define OHCI_AREQHI 0x100 188103285Sikob#define OHCI_AREQHICLR 0x104 189103285Sikob#define OHCI_AREQLO 0x108 190103285Sikob#define OHCI_AREQLOCLR 0x10c 191103285Sikob#define OHCI_PREQHI 0x110 192103285Sikob#define OHCI_PREQHICLR 0x114 193103285Sikob#define OHCI_PREQLO 0x118 194103285Sikob#define OHCI_PREQLOCLR 0x11c 195103285Sikob#define OHCI_PREQUPPER 0x120 196103285Sikob 197103285Sikob#define OHCI_SID_BUF 0x64 198103285Sikob#define OHCI_SID_CNT 0x68 199103285Sikob#define OHCI_SID_CNT_MASK 0xffc 200103285Sikob 201103285Sikob#define OHCI_IT_STAT 0x90 202103285Sikob#define OHCI_IT_STATCLR 0x94 203103285Sikob#define OHCI_IT_MASK 0x98 204103285Sikob#define OHCI_IT_MASKCLR 0x9c 205103285Sikob 206103285Sikob#define OHCI_IR_STAT 0xa0 207103285Sikob#define OHCI_IR_STATCLR 0xa4 208103285Sikob#define OHCI_IR_MASK 0xa8 209103285Sikob#define OHCI_IR_MASKCLR 0xac 210103285Sikob 211103285Sikob#define OHCI_LNKCTL 0xe0 212103285Sikob#define OHCI_LNKCTLCLR 0xe4 213103285Sikob 214103285Sikob#define OHCI_PHYACCESS 0xec 215103285Sikob#define OHCI_CYCLETIMER 0xf0 216103285Sikob 217103285Sikob#define OHCI_DMACTL(off) (off) 218103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 219103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 220103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 221103285Sikob 222103285Sikob#define OHCI_ATQOFF 0x180 223103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 224103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227103285Sikob 228103285Sikob#define OHCI_ATSOFF 0x1a0 229103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 230103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233103285Sikob 234103285Sikob#define OHCI_ARQOFF 0x1c0 235103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 236103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239103285Sikob 240103285Sikob#define OHCI_ARSOFF 0x1e0 241103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 242103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245103285Sikob 246103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250103285Sikob 251103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256103285Sikob 257103285Sikobd_ioctl_t fwohci_ioctl; 258103285Sikob 259103285Sikob/* 260103285Sikob * Communication with PHY device 261103285Sikob */ 262106790Ssimokawastatic u_int32_t 263106790Ssimokawafwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264103285Sikob{ 265103285Sikob u_int32_t fun; 266103285Sikob 267103285Sikob addr &= 0xf; 268103285Sikob data &= 0xff; 269103285Sikob 270103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 272103285Sikob DELAY(100); 273103285Sikob 274103285Sikob return(fwphy_rddata( sc, addr)); 275103285Sikob} 276103285Sikob 277103285Sikobstatic u_int32_t 278103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279103285Sikob{ 280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281103285Sikob int i; 282103285Sikob u_int32_t bm; 283103285Sikob 284103285Sikob#define OHCI_CSR_DATA 0x0c 285103285Sikob#define OHCI_CSR_COMP 0x10 286103285Sikob#define OHCI_CSR_CONT 0x14 287103285Sikob#define OHCI_BUS_MANAGER_ID 0 288103285Sikob 289103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 290103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293103285Sikob DELAY(100); 294103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 295103285Sikob if((bm & 0x3f) == 0x3f){ 296103285Sikob printf("fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 297103285Sikob bm = node; 298103285Sikob }else{ 299103285Sikob printf("fw_set_bus_manager: %d-X%d (loop=%d)\n", bm, node, i); 300103285Sikob } 301103285Sikob 302103285Sikob return(bm); 303103285Sikob} 304103285Sikob 305106790Ssimokawastatic u_int32_t 306106790Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 307103285Sikob{ 308103285Sikob u_int32_t fun; 309103285Sikob u_int i; 310103285Sikob 311103285Sikob addr &= 0xf; 312103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 313103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 314103285Sikob for ( i = 0 ; i < 1000 ; i ++ ){ 315103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 316103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 317103285Sikob break; 318103285Sikob DELAY(1000); 319103285Sikob } 320103285Sikob if( i >= 1000) 321103285Sikob device_printf(sc->fc.dev, "cannot read phy\n"); 322103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 323103285Sikob} 324103285Sikob/* Device specific ioctl. */ 325103285Sikobint 326103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 327103285Sikob{ 328103285Sikob struct firewire_softc *sc; 329103285Sikob struct fwohci_softc *fc; 330103285Sikob int unit = DEV2UNIT(dev); 331103285Sikob int err = 0; 332103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 333103285Sikob u_int32_t *dmach = (u_int32_t *) data; 334103285Sikob 335103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 336103285Sikob if(sc == NULL){ 337103285Sikob return(EINVAL); 338103285Sikob } 339103285Sikob fc = (struct fwohci_softc *)sc->fc; 340103285Sikob 341103285Sikob if (!data) 342103285Sikob return(EINVAL); 343103285Sikob 344103285Sikob switch (cmd) { 345103285Sikob case FWOHCI_WRREG: 346103285Sikob#define OHCI_MAX_REG 0x800 347103285Sikob if(reg->addr <= OHCI_MAX_REG){ 348103285Sikob OWRITE(fc, reg->addr, reg->data); 349103285Sikob reg->data = OREAD(fc, reg->addr); 350103285Sikob }else{ 351103285Sikob err = EINVAL; 352103285Sikob } 353103285Sikob break; 354103285Sikob case FWOHCI_RDREG: 355103285Sikob if(reg->addr <= OHCI_MAX_REG){ 356103285Sikob reg->data = OREAD(fc, reg->addr); 357103285Sikob }else{ 358103285Sikob err = EINVAL; 359103285Sikob } 360103285Sikob break; 361103285Sikob/* Read DMA descriptors for debug */ 362103285Sikob case DUMPDMA: 363103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 364103285Sikob dump_dma(fc, *dmach); 365103285Sikob dump_db(fc, *dmach); 366103285Sikob }else{ 367103285Sikob err = EINVAL; 368103285Sikob } 369103285Sikob break; 370103285Sikob default: 371103285Sikob break; 372103285Sikob } 373103285Sikob return err; 374103285Sikob} 375106790Ssimokawa 376106790Ssimokawaint 377106790Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 378103285Sikob{ 379103285Sikob int err = 0; 380103285Sikob int i; 381103285Sikob u_int32_t reg, reg2; 382103285Sikob struct fwohcidb_tr *db_tr; 383103285Sikob int e1394a = 1; 384103285Sikob 385103285Sikob reg = OREAD(sc, OHCI_VERSION); 386103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 387103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 388103285Sikob 389103285Sikob/* XXX: Available Isochrounous DMA channel probe */ 390103285Sikob for( i = 0 ; i < 0x20 ; i ++ ){ 391103285Sikob OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 392103285Sikob reg = OREAD(sc, OHCI_IRCTL(i)); 393103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 394103285Sikob OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 395103285Sikob reg = OREAD(sc, OHCI_ITCTL(i)); 396103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 397103285Sikob } 398103285Sikob sc->fc.nisodma = i; 399103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 400103285Sikob 401103285Sikob sc->fc.arq = &sc->arrq.xferq; 402103285Sikob sc->fc.ars = &sc->arrs.xferq; 403103285Sikob sc->fc.atq = &sc->atrq.xferq; 404103285Sikob sc->fc.ats = &sc->atrs.xferq; 405103285Sikob 406103285Sikob sc->arrq.xferq.start = NULL; 407103285Sikob sc->arrs.xferq.start = NULL; 408103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 409103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 410103285Sikob 411103285Sikob sc->arrq.xferq.drain = NULL; 412103285Sikob sc->arrs.xferq.drain = NULL; 413103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 414103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 415103285Sikob 416103285Sikob sc->arrq.ndesc = 1; 417103285Sikob sc->arrs.ndesc = 1; 418103285Sikob sc->atrq.ndesc = 10; 419103285Sikob sc->atrs.ndesc = 10 / 2; 420103285Sikob 421103285Sikob sc->arrq.ndb = NDB; 422103285Sikob sc->arrs.ndb = NDB / 2; 423103285Sikob sc->atrq.ndb = NDB; 424103285Sikob sc->atrs.ndb = NDB / 2; 425103285Sikob 426103285Sikob sc->arrq.dummy = NULL; 427103285Sikob sc->arrs.dummy = NULL; 428103285Sikob sc->atrq.dummy = NULL; 429103285Sikob sc->atrs.dummy = NULL; 430103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 431103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 432103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 433103285Sikob sc->it[i].ndb = 0; 434103285Sikob sc->ir[i].ndb = 0; 435103285Sikob } 436103285Sikob 437103285Sikob sc->fc.tcode = tinfo; 438103285Sikob 439103285Sikob sc->cromptr = (u_int32_t *) 440103285Sikob contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 441103285Sikob 442103285Sikob if(sc->cromptr == NULL){ 443103285Sikob return ENOMEM; 444103285Sikob } 445103285Sikob sc->fc.dev = dev; 446103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 447103285Sikob 448103285Sikob sc->fc.config_rom[1] = 0x31333934; 449103285Sikob sc->fc.config_rom[2] = 0xf000a002; 450103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 451103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 452103285Sikob sc->fc.config_rom[5] = 0; 453103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 454103285Sikob 455103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 456103285Sikob 457103285Sikob 458103285Sikob fw_init(&sc->fc); 459103285Sikob 460103285Sikob/* Now stopping all DMA channel */ 461103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 462103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 463103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 464103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 465103285Sikob 466103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, ~0); 467103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 468103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 469103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 470103285Sikob } 471103285Sikob 472103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 473103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 474103285Sikob device_printf(dev, "resetting OHCI..."); 475103285Sikob i = 0; 476103285Sikob while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 477103285Sikob if (i++ > 100) break; 478103285Sikob DELAY(1000); 479103285Sikob } 480103285Sikob printf("done (%d)\n", i); 481103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 482103285Sikob /* XXX wait for SCLK. */ 483106439Ssimokawa DELAY(100000); 484103285Sikob 485103285Sikob reg = OREAD(sc, OHCI_BUS_OPT); 486103285Sikob reg2 = reg | OHCI_BUSFNC; 487103285Sikob /* XXX */ 488103285Sikob if (((reg & 0x0000f000) >> 12) < 10) 489103285Sikob reg2 = (reg2 & 0xffff0fff) | (10 << 12); 490103285Sikob device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 491103285Sikob OWRITE(sc, OHCI_BUS_OPT, reg2); 492103285Sikob 493103285Sikob OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 494103285Sikob OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 495103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 496103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 497103285Sikob 498103285Sikob/* 499103285Sikob * probe PHY parameters 500103285Sikob * 0. to prove PHY version, whether compliance of 1394a. 501103285Sikob * 1. to probe maximum speed supported by the PHY and 502103285Sikob * number of port supported by core-logic. 503103285Sikob * It is not actually available port on your PC . 504103285Sikob */ 505103285Sikob /* Wait a while */ 506103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 507103285Sikob#if 0 508103285Sikob /* try again */ 509103285Sikob DELAY(1000); 510103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 511103285Sikob#endif 512103285Sikob if((reg >> 5) != 7 ){ 513103285Sikob sc->fc.mode &= ~FWPHYASYST; 514103285Sikob sc->fc.nport = reg & FW_PHY_NP; 515103285Sikob sc->fc.speed = reg & FW_PHY_SPD >> 6; 516103285Sikob if (sc->fc.speed > MAX_SPEED) { 517103285Sikob device_printf(dev, "invalid speed %d (fixed to %d).\n", 518103285Sikob sc->fc.speed, MAX_SPEED); 519103285Sikob sc->fc.speed = MAX_SPEED; 520103285Sikob } 521103285Sikob sc->fc.maxrec = maxrec[sc->fc.speed]; 522103285Sikob device_printf(dev, 523103285Sikob "Link 1394 only %s, %d ports, maxrec %d bytes.\n", 524103285Sikob linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 525103285Sikob }else{ 526103285Sikob reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 527103285Sikob sc->fc.mode |= FWPHYASYST; 528103285Sikob sc->fc.nport = reg & FW_PHY_NP; 529103285Sikob sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 530103285Sikob if (sc->fc.speed > MAX_SPEED) { 531103285Sikob device_printf(dev, "invalid speed %d (fixed to %d).\n", 532103285Sikob sc->fc.speed, MAX_SPEED); 533103285Sikob sc->fc.speed = MAX_SPEED; 534103285Sikob } 535103285Sikob sc->fc.maxrec = maxrec[sc->fc.speed]; 536103285Sikob device_printf(dev, 537103285Sikob "Link 1394a available %s, %d ports, maxrec %d bytes.\n", 538103285Sikob linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 539103285Sikob 540103285Sikob /* check programPhyEnable */ 541103285Sikob reg2 = fwphy_rddata(sc, 5); 542103285Sikob#if 0 543103285Sikob if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 544106790Ssimokawa#else /* XXX force to enable 1394a */ 545103285Sikob if (e1394a) { 546103285Sikob#endif 547103285Sikob device_printf(dev, "Enable 1394a Enhancements\n"); 548103285Sikob /* enable EAA EMC */ 549103285Sikob reg2 |= 0x03; 550103285Sikob /* set aPhyEnhanceEnable */ 551103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 552103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 553103285Sikob } else { 554103285Sikob /* for safe */ 555103285Sikob reg2 &= ~0x83; 556103285Sikob } 557103285Sikob reg2 = fwphy_wrdata(sc, 5, reg2); 558103285Sikob } 559103285Sikob 560103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 561103285Sikob if((reg >> 5) == 7 ){ 562103285Sikob reg = fwphy_rddata(sc, 4); 563103285Sikob reg |= 1 << 6; 564103285Sikob fwphy_wrdata(sc, 4, reg); 565103285Sikob reg = fwphy_rddata(sc, 4); 566103285Sikob } 567103285Sikob 568103285Sikob/* SID recieve buffer must allign 2^11 */ 569103285Sikob#define OHCI_SIDSIZE (1 << 11) 570103285Sikob sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 571103285Sikob 0x10000, 0xffffffff, OHCI_SIDSIZE); 572103285Sikob OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 573103285Sikob sc->fc.sid_buf++; 574103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 575103285Sikob 576103285Sikob fwohci_db_init(&sc->arrq); 577103285Sikob fwohci_db_init(&sc->arrs); 578103285Sikob 579103285Sikob fwohci_db_init(&sc->atrq); 580103285Sikob fwohci_db_init(&sc->atrs); 581103285Sikob 582103285Sikob reg = OREAD(sc, FWOHCIGUID_H); 583103285Sikob for( i = 0 ; i < 4 ; i ++){ 584103285Sikob sc->fc.eui[3 - i] = reg & 0xff; 585103285Sikob reg = reg >> 8; 586103285Sikob } 587103285Sikob reg = OREAD(sc, FWOHCIGUID_L); 588103285Sikob for( i = 0 ; i < 4 ; i ++){ 589103285Sikob sc->fc.eui[7 - i] = reg & 0xff; 590103285Sikob reg = reg >> 8; 591103285Sikob } 592103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 593103285Sikob sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 594103285Sikob sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 595103285Sikob sc->fc.ioctl = fwohci_ioctl; 596103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 597103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 598103285Sikob sc->fc.ibr = fwohci_ibr; 599103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 600103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 601103285Sikob 602103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 603103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 604103285Sikob sc->fc.irx_post = fwohci_irx_post; 605103285Sikob sc->fc.itx_post = NULL; 606103285Sikob sc->fc.timeout = fwohci_timeout; 607103285Sikob sc->fc.poll = fwohci_poll; 608103285Sikob sc->fc.set_intr = fwohci_set_intr; 609106790Ssimokawa 610103285Sikob /* enable link */ 611103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 612103285Sikob fw_busreset(&sc->fc); 613103285Sikob fwohci_rx_enable(sc, &sc->arrq); 614103285Sikob fwohci_rx_enable(sc, &sc->arrs); 615103285Sikob 616103285Sikob for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 617103285Sikob i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 618103285Sikob db_tr->xfer = NULL; 619103285Sikob } 620103285Sikob for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 621103285Sikob i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 622103285Sikob db_tr->xfer = NULL; 623103285Sikob } 624103285Sikob sc->atrq.flags = sc->atrs.flags = 0; 625103285Sikob 626103285Sikob OWRITE(sc, FWOHCI_RETRY, 627103285Sikob (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ; 628103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 629103285Sikob OWRITE(sc, FWOHCI_INTMASK, 630103285Sikob OHCI_INT_ERR | OHCI_INT_PHY_SID 631103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 632103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 633103285Sikob | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 634103285Sikob fwohci_set_intr(&sc->fc, 1); 635103285Sikob 636103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 637103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 638103285Sikob 639103285Sikob return err; 640103285Sikob} 641106790Ssimokawa 642106790Ssimokawavoid 643106790Ssimokawafwohci_timeout(void *arg) 644103285Sikob{ 645103285Sikob struct fwohci_softc *sc; 646103285Sikob 647103285Sikob sc = (struct fwohci_softc *)arg; 648103285Sikob sc->fc.timeouthandle = timeout(fwohci_timeout, 649103285Sikob (void *)sc, FW_XFERTIMEOUT * hz * 10); 650103285Sikob} 651106790Ssimokawa 652106790Ssimokawau_int32_t 653106790Ssimokawafwohci_cyctimer(struct firewire_comm *fc) 654103285Sikob{ 655103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 656103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 657103285Sikob} 658103285Sikob 659103285Sikob#define LAST_DB(dbtr, db) do { \ 660103285Sikob struct fwohcidb_tr *_dbtr = (dbtr); \ 661103285Sikob int _cnt = _dbtr->dbcnt; \ 662103285Sikob db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 663103285Sikob} while (0) 664103285Sikob 665106790Ssimokawastatic void 666106790Ssimokawafwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 667103285Sikob{ 668103285Sikob int i, s; 669103285Sikob int tcode, hdr_len, hdr_off, len; 670103285Sikob int fsegment = -1; 671103285Sikob u_int32_t off; 672103285Sikob struct fw_xfer *xfer; 673103285Sikob struct fw_pkt *fp; 674103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 675103285Sikob struct fwohcidb_tr *db_tr; 676103285Sikob volatile struct fwohcidb *db; 677103285Sikob struct mbuf *m; 678103285Sikob struct tcode_info *info; 679103285Sikob 680103285Sikob if(&sc->atrq == dbch){ 681103285Sikob off = OHCI_ATQOFF; 682103285Sikob }else if(&sc->atrs == dbch){ 683103285Sikob off = OHCI_ATSOFF; 684103285Sikob }else{ 685103285Sikob return; 686103285Sikob } 687103285Sikob 688103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 689103285Sikob return; 690103285Sikob 691103285Sikob s = splfw(); 692103285Sikob db_tr = dbch->top; 693103285Sikobtxloop: 694103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 695103285Sikob if(xfer == NULL){ 696103285Sikob goto kick; 697103285Sikob } 698103285Sikob if(dbch->xferq.queued == 0 ){ 699103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 700103285Sikob } 701103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 702103285Sikob db_tr->xfer = xfer; 703103285Sikob xfer->state = FWXF_START; 704103285Sikob dbch->xferq.packets++; 705103285Sikob 706103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 707103285Sikob tcode = fp->mode.common.tcode; 708103285Sikob 709103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 710103285Sikob info = &tinfo[tcode]; 711103285Sikob hdr_len = hdr_off = info->hdr_len; 712103285Sikob /* fw_asyreq must pass valid send.len */ 713103285Sikob len = xfer->send.len; 714103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 715103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 716103285Sikob } 717103285Sikob ohcifp->mode.common.spd = xfer->spd; 718103285Sikob if (tcode == FWTCODE_STREAM ){ 719103285Sikob hdr_len = 8; 720103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 721103285Sikob } else if (tcode == FWTCODE_PHY) { 722103285Sikob hdr_len = 12; 723103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 724103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 725103285Sikob ohcifp->mode.common.spd = 0; 726103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 727103285Sikob } else { 728103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 729103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 730103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 731103285Sikob } 732103285Sikob db = &db_tr->db[0]; 733103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 734103285Sikob db->db.desc.status = 0; 735103285Sikob/* Specify bound timer of asy. responce */ 736103285Sikob if(&sc->atrs == dbch){ 737103285Sikob db->db.desc.count 738103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 739103285Sikob } 740103285Sikob 741103285Sikob db_tr->dbcnt = 2; 742103285Sikob db = &db_tr->db[db_tr->dbcnt]; 743103285Sikob if(len > hdr_off){ 744103285Sikob if (xfer->mbuf == NULL) { 745103285Sikob db->db.desc.addr 746103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 747103285Sikob db->db.desc.cmd 748103285Sikob = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 749103285Sikob db->db.desc.status = 0; 750103285Sikob 751103285Sikob db_tr->dbcnt++; 752103285Sikob } else { 753103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 754103285Sikob m = xfer->mbuf; 755103285Sikob do { 756103285Sikob db->db.desc.addr 757103285Sikob = vtophys(mtod(m, caddr_t)); 758103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 759103285Sikob db->db.desc.status = 0; 760103285Sikob db++; 761103285Sikob db_tr->dbcnt++; 762103285Sikob m = m->m_next; 763103285Sikob } while (m != NULL); 764103285Sikob } 765103285Sikob } 766103285Sikob /* last db */ 767103285Sikob LAST_DB(db_tr, db); 768103285Sikob db->db.desc.cmd |= OHCI_OUTPUT_LAST 769103285Sikob | OHCI_INTERRUPT_ALWAYS 770103285Sikob | OHCI_BRANCH_ALWAYS; 771103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 772103285Sikob 773103285Sikob if(fsegment == -1 ) 774103285Sikob fsegment = db_tr->dbcnt; 775103285Sikob if (dbch->pdb_tr != NULL) { 776103285Sikob LAST_DB(dbch->pdb_tr, db); 777103285Sikob db->db.desc.depend |= db_tr->dbcnt; 778103285Sikob } 779103285Sikob dbch->pdb_tr = db_tr; 780103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 781103285Sikob if(db_tr != dbch->bottom){ 782103285Sikob goto txloop; 783103285Sikob } else { 784103285Sikob printf("fwohci_start: lack of db_trq\n"); 785103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 786103285Sikob } 787103285Sikobkick: 788103285Sikob if (firewire_debug) printf("kick\n"); 789103285Sikob /* kick asy q */ 790103285Sikob 791103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 792103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 793103285Sikob } else { 794103285Sikob printf("start AT DMA status=%x\n", 795103285Sikob OREAD(sc, OHCI_DMACTL(off))); 796103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 797103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 798103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 799103285Sikob } 800106790Ssimokawa 801103285Sikob dbch->top = db_tr; 802103285Sikob splx(s); 803103285Sikob return; 804103285Sikob} 805106790Ssimokawa 806106790Ssimokawastatic void 807106790Ssimokawafwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 808103285Sikob{ 809103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 810103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 811103285Sikob return; 812103285Sikob} 813106790Ssimokawa 814106790Ssimokawastatic void 815106790Ssimokawafwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 816103285Sikob{ 817103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 818103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 819103285Sikob return; 820103285Sikob} 821106790Ssimokawa 822106790Ssimokawastatic void 823106790Ssimokawafwohci_start_atq(struct firewire_comm *fc) 824103285Sikob{ 825103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 826103285Sikob fwohci_start( sc, &(sc->atrq)); 827103285Sikob return; 828103285Sikob} 829106790Ssimokawa 830106790Ssimokawastatic void 831106790Ssimokawafwohci_start_ats(struct firewire_comm *fc) 832103285Sikob{ 833103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 834103285Sikob fwohci_start( sc, &(sc->atrs)); 835103285Sikob return; 836103285Sikob} 837106790Ssimokawa 838106790Ssimokawavoid 839106790Ssimokawafwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 840103285Sikob{ 841103285Sikob int s, err = 0; 842103285Sikob struct fwohcidb_tr *tr; 843103285Sikob volatile struct fwohcidb *db; 844103285Sikob struct fw_xfer *xfer; 845103285Sikob u_int32_t off; 846103285Sikob u_int stat; 847103285Sikob int packets; 848103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 849103285Sikob if(&sc->atrq == dbch){ 850103285Sikob off = OHCI_ATQOFF; 851103285Sikob }else if(&sc->atrs == dbch){ 852103285Sikob off = OHCI_ATSOFF; 853103285Sikob }else{ 854103285Sikob return; 855103285Sikob } 856103285Sikob s = splfw(); 857103285Sikob tr = dbch->bottom; 858103285Sikob packets = 0; 859103285Sikob while(dbch->xferq.queued > 0){ 860103285Sikob LAST_DB(tr, db); 861103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 862103285Sikob if (fc->status != FWBUSRESET) 863103285Sikob /* maybe out of order?? */ 864103285Sikob goto out; 865103285Sikob } 866103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 867103285Sikob#ifdef OHCI_DEBUG 868103285Sikob dump_dma(sc, ch); 869103285Sikob dump_db(sc, ch); 870103285Sikob#endif 871103285Sikob/* Stop DMA */ 872103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 873103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 874103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 875103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 876103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 877103285Sikob } 878103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 879103285Sikob switch(stat){ 880103285Sikob case FWOHCIEV_ACKCOMPL: 881103285Sikob case FWOHCIEV_ACKPEND: 882103285Sikob err = 0; 883103285Sikob break; 884103285Sikob case FWOHCIEV_ACKBSA: 885103285Sikob case FWOHCIEV_ACKBSB: 886103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 887103285Sikob case FWOHCIEV_ACKBSX: 888103285Sikob err = EBUSY; 889103285Sikob break; 890103285Sikob case FWOHCIEV_FLUSHED: 891103285Sikob case FWOHCIEV_ACKTARD: 892103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 893103285Sikob err = EAGAIN; 894103285Sikob break; 895103285Sikob case FWOHCIEV_MISSACK: 896103285Sikob case FWOHCIEV_UNDRRUN: 897103285Sikob case FWOHCIEV_OVRRUN: 898103285Sikob case FWOHCIEV_DESCERR: 899103285Sikob case FWOHCIEV_DTRDERR: 900103285Sikob case FWOHCIEV_TIMEOUT: 901103285Sikob case FWOHCIEV_TCODERR: 902103285Sikob case FWOHCIEV_UNKNOWN: 903103285Sikob case FWOHCIEV_ACKDERR: 904103285Sikob case FWOHCIEV_ACKTERR: 905103285Sikob default: 906103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 907103285Sikob stat, fwohcicode[stat]); 908103285Sikob err = EINVAL; 909103285Sikob break; 910103285Sikob } 911103285Sikob if(tr->xfer != NULL){ 912103285Sikob xfer = tr->xfer; 913103285Sikob xfer->state = FWXF_SENT; 914103285Sikob if(err == EBUSY && fc->status != FWBUSRESET){ 915103285Sikob xfer->state = FWXF_BUSY; 916103285Sikob switch(xfer->act_type){ 917103285Sikob case FWACT_XFER: 918103285Sikob xfer->resp = err; 919103285Sikob if(xfer->retry_req != NULL){ 920103285Sikob xfer->retry_req(xfer); 921103285Sikob } 922103285Sikob break; 923103285Sikob default: 924103285Sikob break; 925103285Sikob } 926103285Sikob } else if( stat != FWOHCIEV_ACKPEND){ 927103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 928103285Sikob xfer->state = FWXF_SENTERR; 929103285Sikob xfer->resp = err; 930103285Sikob switch(xfer->act_type){ 931103285Sikob case FWACT_XFER: 932103285Sikob fw_xfer_done(xfer); 933103285Sikob break; 934103285Sikob default: 935103285Sikob break; 936103285Sikob } 937103285Sikob } 938103285Sikob dbch->xferq.queued --; 939103285Sikob } 940103285Sikob tr->xfer = NULL; 941103285Sikob 942103285Sikob packets ++; 943103285Sikob tr = STAILQ_NEXT(tr, link); 944103285Sikob dbch->bottom = tr; 945103285Sikob } 946103285Sikobout: 947103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 948103285Sikob printf("make free slot\n"); 949103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 950103285Sikob fwohci_start(sc, dbch); 951103285Sikob } 952103285Sikob splx(s); 953103285Sikob} 954106790Ssimokawa 955106790Ssimokawastatic void 956106790Ssimokawafwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 957103285Sikob{ 958103285Sikob int i, s; 959103285Sikob struct fwohcidb_tr *tr; 960103285Sikob 961103285Sikob if(xfer->state != FWXF_START) return; 962103285Sikob 963103285Sikob s = splfw(); 964103285Sikob tr = dbch->bottom; 965103285Sikob for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 966103285Sikob if(tr->xfer == xfer){ 967103285Sikob s = splfw(); 968103285Sikob tr->xfer = NULL; 969103285Sikob dbch->xferq.queued --; 970103285Sikob#if 1 971103285Sikob /* XXX */ 972103285Sikob if (tr == dbch->bottom) 973103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 974103285Sikob#endif 975103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 976103285Sikob printf("fwohci_drain: make slot\n"); 977103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 978103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 979103285Sikob } 980103285Sikob 981103285Sikob splx(s); 982103285Sikob break; 983103285Sikob } 984103285Sikob tr = STAILQ_NEXT(tr, link); 985103285Sikob } 986103285Sikob splx(s); 987103285Sikob return; 988103285Sikob} 989103285Sikob 990106790Ssimokawastatic void 991106790Ssimokawafwohci_db_free(struct fwohci_dbch *dbch) 992103285Sikob{ 993103285Sikob struct fwohcidb_tr *db_tr; 994103285Sikob int idb; 995103285Sikob 996103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 997103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 998103285Sikob idb < dbch->ndb; 999103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1000103285Sikob free(db_tr->buf, M_DEVBUF); 1001103285Sikob db_tr->buf = NULL; 1002103285Sikob } 1003103285Sikob } 1004103285Sikob dbch->ndb = 0; 1005103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1006103285Sikob contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1007103285Sikob sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1008103285Sikob /* Attach DB to DMA ch. */ 1009103285Sikob free(db_tr, M_DEVBUF); 1010103285Sikob STAILQ_INIT(&dbch->db_trq); 1011103285Sikob} 1012106790Ssimokawa 1013106790Ssimokawastatic void 1014106790Ssimokawafwohci_db_init(struct fwohci_dbch *dbch) 1015103285Sikob{ 1016103285Sikob int idb; 1017103285Sikob struct fwohcidb *db; 1018103285Sikob struct fwohcidb_tr *db_tr; 1019103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1020103285Sikob /* DB entry must start at 16 bytes bounary. */ 1021103285Sikob dbch->frag.buf = NULL; 1022103285Sikob dbch->frag.len = 0; 1023103285Sikob dbch->frag.plen = 0; 1024103285Sikob dbch->xferq.queued = 0; 1025103285Sikob dbch->pdb_tr = NULL; 1026103285Sikob 1027103285Sikob STAILQ_INIT(&dbch->db_trq); 1028103285Sikob db_tr = (struct fwohcidb_tr *) 1029103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1030103285Sikob M_DEVBUF, M_DONTWAIT); 1031103285Sikob if(db_tr == NULL){ 1032103285Sikob return; 1033103285Sikob } 1034103285Sikob db = (struct fwohcidb *) 1035103285Sikob contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1036103285Sikob M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1037103285Sikob if(db == NULL){ 1038103285Sikob printf("fwochi_db_init: contigmalloc failed\n"); 1039103285Sikob return; 1040103285Sikob } 1041103285Sikob bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1042103285Sikob /* Attach DB to DMA ch. */ 1043103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1044103285Sikob db_tr->dbcnt = 0; 1045103285Sikob db_tr->db = &db[idb * dbch->ndesc]; 1046103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1047103285Sikob if(!(dbch->xferq.flag & FWXFERQ_PACKET) && 1048103285Sikob (idb % dbch->xferq.bnpacket == 0)){ 1049103285Sikob dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].start 1050103285Sikob = (caddr_t)db_tr; 1051103285Sikob } 1052103285Sikob if((!(dbch->xferq.flag & FWXFERQ_PACKET)) && 1053103285Sikob ((idb + 1)% dbch->xferq.bnpacket == 0)){ 1054103285Sikob dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].end 1055103285Sikob = (caddr_t)db_tr; 1056103285Sikob } 1057103285Sikob db_tr++; 1058103285Sikob } 1059103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1060103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1061103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1062103285Sikob dbch->bottom = dbch->top; 1063103285Sikob} 1064106790Ssimokawa 1065106790Ssimokawastatic int 1066106790Ssimokawafwohci_itx_disable(struct firewire_comm *fc, int dmach) 1067103285Sikob{ 1068103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1069103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1070103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1071103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1072103285Sikob fwohci_db_free(&sc->it[dmach]); 1073103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1074103285Sikob return 0; 1075103285Sikob} 1076106790Ssimokawa 1077106790Ssimokawastatic int 1078106790Ssimokawafwohci_irx_disable(struct firewire_comm *fc, int dmach) 1079103285Sikob{ 1080103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1081103285Sikob 1082103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1083103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1084103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1085103285Sikob if(sc->ir[dmach].dummy != NULL){ 1086103285Sikob free(sc->ir[dmach].dummy, M_DEVBUF); 1087103285Sikob } 1088103285Sikob sc->ir[dmach].dummy = NULL; 1089103285Sikob fwohci_db_free(&sc->ir[dmach]); 1090103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1091103285Sikob return 0; 1092103285Sikob} 1093106790Ssimokawa 1094106790Ssimokawastatic void 1095106790Ssimokawafwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1096103285Sikob{ 1097103285Sikob qld[0] = ntohl(qld[0]); 1098103285Sikob return; 1099103285Sikob} 1100106790Ssimokawa 1101106790Ssimokawastatic int 1102106790Ssimokawafwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1103103285Sikob{ 1104103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1105103285Sikob int err = 0; 1106103285Sikob unsigned short tag, ich; 1107103285Sikob 1108103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1109103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1110103285Sikob 1111103285Sikob#if 0 1112103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1113103285Sikob wakeup(fc->ir[dmach]); 1114103285Sikob return err; 1115103285Sikob } 1116103285Sikob#endif 1117103285Sikob 1118103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1119103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1120103285Sikob sc->ir[dmach].xferq.queued = 0; 1121103285Sikob sc->ir[dmach].ndb = NDB; 1122103285Sikob sc->ir[dmach].xferq.psize = FWPMAX_S400; 1123103285Sikob sc->ir[dmach].ndesc = 1; 1124103285Sikob fwohci_db_init(&sc->ir[dmach]); 1125103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1126103285Sikob } 1127103285Sikob if(err){ 1128103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1129103285Sikob return err; 1130103285Sikob } 1131103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1132103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1133103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1134103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1135103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1136103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1137103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1138103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1139103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1140103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1141103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1142103285Sikob } 1143103285Sikob return err; 1144103285Sikob} 1145106790Ssimokawa 1146106790Ssimokawastatic int 1147106790Ssimokawafwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1148103285Sikob{ 1149103285Sikob int err = 0; 1150103285Sikob int idb, z, i, dmach = 0; 1151103285Sikob u_int32_t off = NULL; 1152103285Sikob struct fwohcidb_tr *db_tr; 1153103285Sikob 1154103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1155103285Sikob err = EINVAL; 1156103285Sikob return err; 1157103285Sikob } 1158103285Sikob z = dbch->ndesc; 1159103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1160103285Sikob if( &sc->it[dmach] == dbch){ 1161103285Sikob off = OHCI_ITOFF(dmach); 1162103285Sikob break; 1163103285Sikob } 1164103285Sikob } 1165103285Sikob if(off == NULL){ 1166103285Sikob err = EINVAL; 1167103285Sikob return err; 1168103285Sikob } 1169103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1170103285Sikob return err; 1171103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1172103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1173103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1174103285Sikob } 1175103285Sikob db_tr = dbch->top; 1176103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1177103285Sikob fwohci_add_tx_buf(db_tr, 1178103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1179103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1180103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1181103285Sikob break; 1182103285Sikob } 1183103285Sikob db_tr->db[0].db.desc.depend 1184103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1185103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1186103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1187103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1188103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1189103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1190103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1191103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 1192103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1193103285Sikob ~0xf; 1194103285Sikob } 1195103285Sikob } 1196103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1197103285Sikob } 1198103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1199103285Sikob return err; 1200103285Sikob} 1201106790Ssimokawa 1202106790Ssimokawastatic int 1203106790Ssimokawafwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1204103285Sikob{ 1205103285Sikob int err = 0; 1206103285Sikob int idb, z, i, dmach = 0; 1207103285Sikob u_int32_t off = NULL; 1208103285Sikob struct fwohcidb_tr *db_tr; 1209103285Sikob 1210103285Sikob z = dbch->ndesc; 1211103285Sikob if(&sc->arrq == dbch){ 1212103285Sikob off = OHCI_ARQOFF; 1213103285Sikob }else if(&sc->arrs == dbch){ 1214103285Sikob off = OHCI_ARSOFF; 1215103285Sikob }else{ 1216103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1217103285Sikob if( &sc->ir[dmach] == dbch){ 1218103285Sikob off = OHCI_IROFF(dmach); 1219103285Sikob break; 1220103285Sikob } 1221103285Sikob } 1222103285Sikob } 1223103285Sikob if(off == NULL){ 1224103285Sikob err = EINVAL; 1225103285Sikob return err; 1226103285Sikob } 1227103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1228103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1229103285Sikob return err; 1230103285Sikob }else{ 1231103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1232103285Sikob err = EBUSY; 1233103285Sikob return err; 1234103285Sikob } 1235103285Sikob } 1236103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1237103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1238103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1239103285Sikob } 1240103285Sikob db_tr = dbch->top; 1241103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1242103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1243103285Sikob fwohci_add_rx_buf(db_tr, 1244103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1245103285Sikob }else{ 1246103285Sikob fwohci_add_rx_buf(db_tr, 1247103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1248103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1249103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1250103285Sikob } 1251103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1252103285Sikob break; 1253103285Sikob } 1254103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1255103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1256103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1257103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1258103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1259103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1260103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1261103285Sikob ~0xf; 1262103285Sikob } 1263103285Sikob } 1264103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1265103285Sikob } 1266103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1267103285Sikob dbch->buf_offset = 0; 1268103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1269103285Sikob return err; 1270103285Sikob }else{ 1271103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1272103285Sikob } 1273103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1274103285Sikob return err; 1275103285Sikob} 1276106790Ssimokawa 1277106790Ssimokawastatic int 1278106790Ssimokawafwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1279103285Sikob{ 1280103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1281103285Sikob int err = 0; 1282103285Sikob unsigned short tag, ich; 1283103285Sikob struct fwohci_dbch *dbch; 1284103285Sikob struct fw_pkt *fp; 1285103285Sikob struct fwohcidb_tr *db_tr; 1286103285Sikob 1287103285Sikob tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1288103285Sikob ich = sc->it[dmach].xferq.flag & 0x3f; 1289103285Sikob dbch = &sc->it[dmach]; 1290103285Sikob if(dbch->ndb == 0){ 1291103285Sikob dbch->xferq.queued = 0; 1292103285Sikob dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1293103285Sikob dbch->ndesc = 3; 1294103285Sikob fwohci_db_init(dbch); 1295103285Sikob err = fwohci_tx_enable(sc, dbch); 1296103285Sikob } 1297103285Sikob if(err) 1298103285Sikob return err; 1299103285Sikob if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1300103285Sikob if(dbch->xferq.stdma2 != NULL){ 1301103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1302103285Sikob ((struct fwohcidb_tr *) 1303103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1304103285Sikob |= OHCI_BRANCH_ALWAYS; 1305103285Sikob ((struct fwohcidb_tr *) 1306103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1307103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1308103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1309103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1310103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1311103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1312103285Sikob } 1313103285Sikob }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1314103285Sikob fw_tbuf_update(&sc->fc, dmach, 0); 1315103285Sikob if(dbch->xferq.stdma == NULL){ 1316103285Sikob return err; 1317103285Sikob } 1318103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1319103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1320103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1321103285Sikob OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1322103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1323103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1324103285Sikob if(dbch->xferq.stdma2 != NULL){ 1325103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1326103285Sikob ((struct fwohcidb_tr *) 1327103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1328103285Sikob |= OHCI_BRANCH_ALWAYS; 1329103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1330103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1331103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1332103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1333103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1334103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1335103285Sikob }else{ 1336103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1337103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1338103285Sikob } 1339103285Sikob OWRITE(sc, OHCI_ITCMD(dmach), 1340103285Sikob vtophys(((struct fwohcidb_tr *) 1341103285Sikob (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1342103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1343103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1344103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1345103285Sikob fp->mode.ld[2] = htonl(0x80000000 + 1346103285Sikob ((fc->cyctimer(fc) + 0x3000) & 0xf000)); 1347103285Sikob } 1348103285Sikob 1349103285Sikob OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1350103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1351103285Sikob } 1352103285Sikob return err; 1353103285Sikob} 1354106790Ssimokawa 1355106790Ssimokawastatic int 1356106790Ssimokawafwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1357103285Sikob{ 1358103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1359103285Sikob int err = 0; 1360103285Sikob unsigned short tag, ich; 1361103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1362103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1363103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1364103285Sikob 1365103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1366103285Sikob sc->ir[dmach].xferq.queued = 0; 1367103285Sikob sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1368103285Sikob sc->ir[dmach].xferq.bnchunk; 1369103285Sikob sc->ir[dmach].dummy = 1370103285Sikob malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1371103285Sikob M_DEVBUF, M_DONTWAIT); 1372103285Sikob if(sc->ir[dmach].dummy == NULL){ 1373103285Sikob err = ENOMEM; 1374103285Sikob return err; 1375103285Sikob } 1376103285Sikob sc->ir[dmach].ndesc = 2; 1377103285Sikob fwohci_db_init(&sc->ir[dmach]); 1378103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1379103285Sikob } 1380103285Sikob if(err) 1381103285Sikob return err; 1382103285Sikob 1383103285Sikob if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1384103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1385103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1386103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1387103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1388103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1389103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1390103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1391103285Sikob } 1392103285Sikob }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1393103285Sikob && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1394103285Sikob fw_rbuf_update(&sc->fc, dmach, 0); 1395103285Sikob 1396103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1397103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1398103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1399103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1400103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1401103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1402103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1403103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1404103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1405103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1406103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1407103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1408103285Sikob }else{ 1409103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1410103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1411103285Sikob } 1412103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1413103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1414103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1415103285Sikob } 1416103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1417103285Sikob return err; 1418103285Sikob} 1419106790Ssimokawa 1420106790Ssimokawastatic int 1421106790Ssimokawafwohci_irx_enable(struct firewire_comm *fc, int dmach) 1422103285Sikob{ 1423103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1424103285Sikob int err = 0; 1425103285Sikob 1426103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1427103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1428103285Sikob return err; 1429103285Sikob }else{ 1430103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1431103285Sikob return err; 1432103285Sikob } 1433103285Sikob} 1434106790Ssimokawa 1435106790Ssimokawaint 1436106790Ssimokawafwohci_shutdown(device_t dev) 1437103285Sikob{ 1438103285Sikob u_int i; 1439103285Sikob struct fwohci_softc *sc = device_get_softc(dev); 1440103285Sikob 1441103285Sikob/* Now stopping all DMA channel */ 1442103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1443103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1444103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1445103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1446103285Sikob 1447103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1448103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1449103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1450103285Sikob } 1451103285Sikob 1452103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1453103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1454103285Sikob 1455103285Sikob/* Stop interrupt */ 1456103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1457103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1458103285Sikob | OHCI_INT_PHY_INT 1459103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1460103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1461103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1462103285Sikob | OHCI_INT_PHY_BUS_R); 1463103285Sikob return 0; 1464103285Sikob} 1465103285Sikob 1466103285Sikob#define ACK_ALL 1467103285Sikobstatic void 1468106789Ssimokawafwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1469103285Sikob{ 1470103285Sikob u_int32_t irstat, itstat; 1471103285Sikob u_int i; 1472103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1473103285Sikob 1474103285Sikob#ifdef OHCI_DEBUG 1475103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1476103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1477103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1478103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1479103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1480103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1481103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1482103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1483103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1484103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1485103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1486103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1487103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1488103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1489103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1490103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1491103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1492103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1493103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1494103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1495103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1496103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1497103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1498103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1499103285Sikob ); 1500103285Sikob#endif 1501103285Sikob/* Bus reset */ 1502103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1503103285Sikob device_printf(fc->dev, "BUS reset\n"); 1504103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1505103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1506103285Sikob 1507103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1508103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1509103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1510103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1511103285Sikob 1512103285Sikob#if 0 1513103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1514103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1515103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1516103285Sikob } 1517103285Sikob 1518103285Sikob#endif 1519103285Sikob fw_busreset(fc); 1520103285Sikob 1521103285Sikob /* XXX need to wait DMA to stop */ 1522103285Sikob#ifndef ACK_ALL 1523103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1524103285Sikob#endif 1525103285Sikob#if 1 1526103285Sikob /* pending all pre-bus_reset packets */ 1527103285Sikob fwohci_txd(sc, &sc->atrq); 1528103285Sikob fwohci_txd(sc, &sc->atrs); 1529106789Ssimokawa fwohci_arcv(sc, &sc->arrs, -1); 1530106789Ssimokawa fwohci_arcv(sc, &sc->arrq, -1); 1531103285Sikob#endif 1532103285Sikob 1533103285Sikob 1534103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1535103285Sikob /* XXX insecure ?? */ 1536103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1537103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1538103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1539103285Sikob 1540103285Sikob } 1541103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1542103285Sikob#ifndef ACK_ALL 1543103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1544103285Sikob#endif 1545103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1546103285Sikob OWRITE(sc, OHCI_IR_STATCLR, ~0); 1547103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1548103285Sikob if((irstat & (1 << i)) != 0){ 1549103285Sikob if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1550106789Ssimokawa fwohci_ircv(sc, &sc->ir[i], count); 1551103285Sikob }else{ 1552103285Sikob fwohci_rbuf_update(sc, i); 1553103285Sikob } 1554103285Sikob } 1555103285Sikob } 1556103285Sikob } 1557103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1558103285Sikob#ifndef ACK_ALL 1559103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1560103285Sikob#endif 1561103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1562103285Sikob OWRITE(sc, OHCI_IT_STATCLR, ~0); 1563103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1564103285Sikob if((itstat & (1 << i)) != 0){ 1565103285Sikob fwohci_tbuf_update(sc, i); 1566103285Sikob } 1567103285Sikob } 1568103285Sikob } 1569103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1570103285Sikob#ifndef ACK_ALL 1571103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1572103285Sikob#endif 1573103285Sikob#if 0 1574103285Sikob dump_dma(sc, ARRS_CH); 1575103285Sikob dump_db(sc, ARRS_CH); 1576103285Sikob#endif 1577106789Ssimokawa fwohci_arcv(sc, &sc->arrs, count); 1578103285Sikob } 1579103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1580103285Sikob#ifndef ACK_ALL 1581103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1582103285Sikob#endif 1583103285Sikob#if 0 1584103285Sikob dump_dma(sc, ARRQ_CH); 1585103285Sikob dump_db(sc, ARRQ_CH); 1586103285Sikob#endif 1587106789Ssimokawa fwohci_arcv(sc, &sc->arrq, count); 1588103285Sikob } 1589103285Sikob if(stat & OHCI_INT_PHY_SID){ 1590103285Sikob caddr_t buf; 1591103285Sikob int plen; 1592103285Sikob 1593103285Sikob#ifndef ACK_ALL 1594103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1595103285Sikob#endif 1596103285Sikob/* 1597103285Sikob** Checking whether the node is root or not. If root, turn on 1598103285Sikob** cycle master. 1599103285Sikob*/ 1600103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1601103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1602103285Sikob printf("Bus reset failure\n"); 1603103285Sikob goto sidout; 1604103285Sikob } 1605103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1606103285Sikob printf("CYCLEMASTER mode\n"); 1607103285Sikob OWRITE(sc, OHCI_LNKCTL, 1608103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1609103285Sikob }else{ 1610103285Sikob printf("non CYCLEMASTER mode\n"); 1611103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1612103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1613103285Sikob } 1614103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1615103285Sikob 1616103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1617103285Sikob plen -= 4; /* chop control info */ 1618103285Sikob buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1619103285Sikob if(buf == NULL) goto sidout; 1620103285Sikob bcopy((void *)(uintptr_t)(volatile void *)fc->sid_buf, 1621103285Sikob buf, plen); 1622103285Sikob fw_sidrcv(fc, buf, plen, 0); 1623103285Sikob } 1624103285Sikobsidout: 1625103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1626103285Sikob#ifndef ACK_ALL 1627103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1628103285Sikob#endif 1629103285Sikob fwohci_txd(sc, &(sc->atrq)); 1630103285Sikob } 1631103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1632103285Sikob#ifndef ACK_ALL 1633103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1634103285Sikob#endif 1635103285Sikob fwohci_txd(sc, &(sc->atrs)); 1636103285Sikob } 1637103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1638103285Sikob#ifndef ACK_ALL 1639103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1640103285Sikob#endif 1641103285Sikob device_printf(fc->dev, "posted write error\n"); 1642103285Sikob } 1643103285Sikob if((stat & OHCI_INT_ERR )){ 1644103285Sikob#ifndef ACK_ALL 1645103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1646103285Sikob#endif 1647103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1648103285Sikob } 1649103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1650103285Sikob#ifndef ACK_ALL 1651103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1652103285Sikob#endif 1653103285Sikob device_printf(fc->dev, "phy int\n"); 1654103285Sikob } 1655103285Sikob 1656103285Sikob return; 1657103285Sikob} 1658103285Sikob 1659103285Sikobvoid 1660103285Sikobfwohci_intr(void *arg) 1661103285Sikob{ 1662103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1663103285Sikob u_int32_t stat; 1664103285Sikob 1665103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1666103285Sikob /* polling mode */ 1667103285Sikob return; 1668103285Sikob } 1669103285Sikob 1670103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1671103285Sikob if (stat == 0xffffffff) { 1672103285Sikob device_printf(sc->fc.dev, 1673103285Sikob "device physically ejected?\n"); 1674103285Sikob return; 1675103285Sikob } 1676103285Sikob#ifdef ACK_ALL 1677103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1678103285Sikob#endif 1679106789Ssimokawa fwohci_intr_body(sc, stat, -1); 1680103285Sikob } 1681103285Sikob} 1682103285Sikob 1683103285Sikobstatic void 1684103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1685103285Sikob{ 1686103285Sikob int s; 1687103285Sikob u_int32_t stat; 1688103285Sikob struct fwohci_softc *sc; 1689103285Sikob 1690103285Sikob 1691103285Sikob sc = (struct fwohci_softc *)fc; 1692103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1693103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1694103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1695103285Sikob#if 0 1696103285Sikob if (!quick) { 1697103285Sikob#else 1698103285Sikob if (1) { 1699103285Sikob#endif 1700103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1701103285Sikob if (stat == 0) 1702103285Sikob return; 1703103285Sikob if (stat == 0xffffffff) { 1704103285Sikob device_printf(sc->fc.dev, 1705103285Sikob "device physically ejected?\n"); 1706103285Sikob return; 1707103285Sikob } 1708103285Sikob#ifdef ACK_ALL 1709103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1710103285Sikob#endif 1711103285Sikob } 1712103285Sikob s = splfw(); 1713106789Ssimokawa fwohci_intr_body(sc, stat, count); 1714103285Sikob splx(s); 1715103285Sikob} 1716103285Sikob 1717103285Sikobstatic void 1718103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 1719103285Sikob{ 1720103285Sikob struct fwohci_softc *sc; 1721103285Sikob 1722103285Sikob sc = (struct fwohci_softc *)fc; 1723103285Sikob printf("fwochi_set_intr: %d\n", enable); 1724103285Sikob if (enable) { 1725103285Sikob sc->intmask |= OHCI_INT_EN; 1726103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1727103285Sikob } else { 1728103285Sikob sc->intmask &= ~OHCI_INT_EN; 1729103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1730103285Sikob } 1731103285Sikob} 1732103285Sikob 1733106790Ssimokawastatic void 1734106790Ssimokawafwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1735103285Sikob{ 1736103285Sikob int stat; 1737103285Sikob struct firewire_comm *fc = &sc->fc; 1738103285Sikob struct fw_pkt *fp; 1739103285Sikob struct fwohci_dbch *dbch; 1740103285Sikob struct fwohcidb_tr *db_tr; 1741103285Sikob 1742103285Sikob dbch = &sc->it[dmach]; 1743103285Sikob if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1744103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1745103285Sikob/* 1746103285Sikob * Overwrite highest significant 4 bits timestamp information 1747103285Sikob */ 1748103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1749103285Sikob fp->mode.ld[2] |= htonl(0x80000000 | 1750103285Sikob ((fc->cyctimer(fc) + 0x4000) & 0xf000)); 1751103285Sikob } 1752103285Sikob stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1753103285Sikob switch(stat){ 1754103285Sikob case FWOHCIEV_ACKCOMPL: 1755103285Sikob fw_tbuf_update(fc, dmach, 1); 1756103285Sikob break; 1757103285Sikob default: 1758103285Sikob fw_tbuf_update(fc, dmach, 0); 1759103285Sikob break; 1760103285Sikob } 1761103285Sikob fwohci_itxbuf_enable(&sc->fc, dmach); 1762103285Sikob} 1763106790Ssimokawa 1764106790Ssimokawastatic void 1765106790Ssimokawafwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1766103285Sikob{ 1767103285Sikob int stat; 1768103285Sikob stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1769103285Sikob switch(stat){ 1770103285Sikob case FWOHCIEV_ACKCOMPL: 1771103285Sikob fw_rbuf_update(&sc->fc, dmach, 1); 1772103285Sikob wakeup(sc->fc.ir[dmach]); 1773103285Sikob fwohci_irx_enable(&sc->fc, dmach); 1774103285Sikob break; 1775103285Sikob default: 1776103285Sikob break; 1777103285Sikob } 1778103285Sikob} 1779106790Ssimokawa 1780106790Ssimokawavoid 1781106790Ssimokawadump_dma(struct fwohci_softc *sc, u_int32_t ch) 1782106790Ssimokawa{ 1783103285Sikob u_int32_t off, cntl, stat, cmd, match; 1784103285Sikob 1785103285Sikob if(ch == 0){ 1786103285Sikob off = OHCI_ATQOFF; 1787103285Sikob }else if(ch == 1){ 1788103285Sikob off = OHCI_ATSOFF; 1789103285Sikob }else if(ch == 2){ 1790103285Sikob off = OHCI_ARQOFF; 1791103285Sikob }else if(ch == 3){ 1792103285Sikob off = OHCI_ARSOFF; 1793103285Sikob }else if(ch < IRX_CH){ 1794103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1795103285Sikob }else{ 1796103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1797103285Sikob } 1798103285Sikob cntl = stat = OREAD(sc, off); 1799103285Sikob cmd = OREAD(sc, off + 0xc); 1800103285Sikob match = OREAD(sc, off + 0x10); 1801103285Sikob 1802103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1803103285Sikob ch, 1804103285Sikob cntl, 1805103285Sikob stat, 1806103285Sikob cmd, 1807103285Sikob match); 1808103285Sikob stat &= 0xffff ; 1809103285Sikob if(stat & 0xff00){ 1810103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 1811103285Sikob ch, 1812103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1813103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1814103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1815103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1816103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1817103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1818103285Sikob fwohcicode[stat & 0x1f], 1819103285Sikob stat & 0x1f 1820103285Sikob ); 1821103285Sikob }else{ 1822103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 1823103285Sikob } 1824103285Sikob} 1825106790Ssimokawa 1826106790Ssimokawavoid 1827106790Ssimokawadump_db(struct fwohci_softc *sc, u_int32_t ch) 1828106790Ssimokawa{ 1829103285Sikob struct fwohci_dbch *dbch; 1830103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 1831103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 1832103285Sikob int idb, jdb; 1833103285Sikob u_int32_t cmd, off; 1834103285Sikob if(ch == 0){ 1835103285Sikob off = OHCI_ATQOFF; 1836103285Sikob dbch = &sc->atrq; 1837103285Sikob }else if(ch == 1){ 1838103285Sikob off = OHCI_ATSOFF; 1839103285Sikob dbch = &sc->atrs; 1840103285Sikob }else if(ch == 2){ 1841103285Sikob off = OHCI_ARQOFF; 1842103285Sikob dbch = &sc->arrq; 1843103285Sikob }else if(ch == 3){ 1844103285Sikob off = OHCI_ARSOFF; 1845103285Sikob dbch = &sc->arrs; 1846103285Sikob }else if(ch < IRX_CH){ 1847103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1848103285Sikob dbch = &sc->it[ch - ITX_CH]; 1849103285Sikob }else { 1850103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1851103285Sikob dbch = &sc->ir[ch - IRX_CH]; 1852103285Sikob } 1853103285Sikob cmd = OREAD(sc, off + 0xc); 1854103285Sikob 1855103285Sikob if( dbch->ndb == 0 ){ 1856103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 1857103285Sikob return; 1858103285Sikob } 1859103285Sikob pp = dbch->top; 1860103285Sikob prev = pp->db; 1861103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 1862103285Sikob if(pp == NULL){ 1863103285Sikob curr = NULL; 1864103285Sikob goto outdb; 1865103285Sikob } 1866103285Sikob cp = STAILQ_NEXT(pp, link); 1867103285Sikob if(cp == NULL){ 1868103285Sikob curr = NULL; 1869103285Sikob goto outdb; 1870103285Sikob } 1871103285Sikob np = STAILQ_NEXT(cp, link); 1872103285Sikob if(cp == NULL) break; 1873103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 1874103285Sikob if((cmd & 0xfffffff0) 1875103285Sikob == vtophys(&(cp->db[jdb]))){ 1876103285Sikob curr = cp->db; 1877103285Sikob if(np != NULL){ 1878103285Sikob next = np->db; 1879103285Sikob }else{ 1880103285Sikob next = NULL; 1881103285Sikob } 1882103285Sikob goto outdb; 1883103285Sikob } 1884103285Sikob } 1885103285Sikob pp = STAILQ_NEXT(pp, link); 1886103285Sikob prev = pp->db; 1887103285Sikob } 1888103285Sikoboutdb: 1889103285Sikob if( curr != NULL){ 1890103285Sikob printf("Prev DB %d\n", ch); 1891103285Sikob print_db(prev, ch, dbch->ndesc); 1892103285Sikob printf("Current DB %d\n", ch); 1893103285Sikob print_db(curr, ch, dbch->ndesc); 1894103285Sikob printf("Next DB %d\n", ch); 1895103285Sikob print_db(next, ch, dbch->ndesc); 1896103285Sikob }else{ 1897103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 1898103285Sikob } 1899103285Sikob return; 1900103285Sikob} 1901106790Ssimokawa 1902106790Ssimokawavoid 1903106790Ssimokawaprint_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 1904106790Ssimokawa{ 1905103285Sikob fwohcireg_t stat; 1906103285Sikob int i, key; 1907103285Sikob 1908103285Sikob if(db == NULL){ 1909103285Sikob printf("No Descriptor is found\n"); 1910103285Sikob return; 1911103285Sikob } 1912103285Sikob 1913103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 1914103285Sikob ch, 1915103285Sikob "Current", 1916103285Sikob "OP ", 1917103285Sikob "KEY", 1918103285Sikob "INT", 1919103285Sikob "BR ", 1920103285Sikob "len", 1921103285Sikob "Addr", 1922103285Sikob "Depend", 1923103285Sikob "Stat", 1924103285Sikob "Cnt"); 1925103285Sikob for( i = 0 ; i <= max ; i ++){ 1926103285Sikob key = db[i].db.desc.cmd & OHCI_KEY_MASK; 1927106543Ssimokawa printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 1928103285Sikob vtophys(&db[i]), 1929103285Sikob dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 1930103285Sikob dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 1931103285Sikob dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 1932103285Sikob dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 1933103285Sikob db[i].db.desc.cmd & 0xffff, 1934103285Sikob db[i].db.desc.addr, 1935103285Sikob db[i].db.desc.depend, 1936103285Sikob db[i].db.desc.status, 1937103285Sikob db[i].db.desc.count); 1938103285Sikob stat = db[i].db.desc.status; 1939103285Sikob if(stat & 0xff00){ 1940103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 1941103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1942103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1943103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1944103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1945103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1946103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1947103285Sikob fwohcicode[stat & 0x1f], 1948103285Sikob stat & 0x1f 1949103285Sikob ); 1950103285Sikob }else{ 1951103285Sikob printf(" Nostat\n"); 1952103285Sikob } 1953103285Sikob if(key == OHCI_KEY_ST2 ){ 1954103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 1955103285Sikob db[i+1].db.immed[0], 1956103285Sikob db[i+1].db.immed[1], 1957103285Sikob db[i+1].db.immed[2], 1958103285Sikob db[i+1].db.immed[3]); 1959103285Sikob } 1960103285Sikob if(key == OHCI_KEY_DEVICE){ 1961103285Sikob return; 1962103285Sikob } 1963103285Sikob if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 1964103285Sikob == OHCI_BRANCH_ALWAYS){ 1965103285Sikob return; 1966103285Sikob } 1967103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 1968103285Sikob == OHCI_OUTPUT_LAST){ 1969103285Sikob return; 1970103285Sikob } 1971103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 1972103285Sikob == OHCI_INPUT_LAST){ 1973103285Sikob return; 1974103285Sikob } 1975103285Sikob if(key == OHCI_KEY_ST2 ){ 1976103285Sikob i++; 1977103285Sikob } 1978103285Sikob } 1979103285Sikob return; 1980103285Sikob} 1981106790Ssimokawa 1982106790Ssimokawavoid 1983106790Ssimokawafwohci_ibr(struct firewire_comm *fc) 1984103285Sikob{ 1985103285Sikob struct fwohci_softc *sc; 1986103285Sikob u_int32_t fun; 1987103285Sikob 1988103285Sikob sc = (struct fwohci_softc *)fc; 1989103285Sikob#if 1 1990103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 1991103285Sikob fun |= FW_PHY_IBR; 1992103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 1993103285Sikob#else 1994103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 1995103285Sikob fun |= FW_PHY_ISBR; 1996103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 1997103285Sikob#endif 1998103285Sikob} 1999106790Ssimokawa 2000106790Ssimokawavoid 2001106790Ssimokawafwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2002103285Sikob{ 2003103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2004103285Sikob struct fwohci_dbch *dbch; 2005103285Sikob struct fw_pkt *fp; 2006103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2007103285Sikob unsigned short chtag; 2008103285Sikob int idb; 2009103285Sikob 2010103285Sikob dbch = &sc->it[dmach]; 2011103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2012103285Sikob 2013103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2014103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2015103285Sikob/* 2016103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2017103285Sikob*/ 2018103285Sikob if(bulkxfer->flag != 0){ 2019103285Sikob return; 2020103285Sikob } 2021103285Sikob bulkxfer->flag = 1; 2022103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2023103285Sikob db_tr->db[0].db.desc.cmd 2024103285Sikob = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2025103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2026103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) 2027103285Sikob db_tr->db[1].db.immed; 2028103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2029103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2030103285Sikob ohcifp->mode.stream.chtag = chtag; 2031103285Sikob ohcifp->mode.stream.tcode = 0xa; 2032103285Sikob ohcifp->mode.stream.spd = 4; 2033103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2034103285Sikob ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2035103285Sikob 2036103285Sikob db_tr->db[2].db.desc.cmd 2037103285Sikob = OHCI_OUTPUT_LAST 2038103285Sikob | OHCI_UPDATE 2039103285Sikob | OHCI_BRANCH_ALWAYS 2040103285Sikob | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2041103285Sikob db_tr->db[2].db.desc.status = 0; 2042103285Sikob db_tr->db[2].db.desc.count = 0; 2043103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 2044103285Sikob db_tr->db[0].db.desc.depend 2045103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2046103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2047103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2048103285Sikob }else{ 2049103285Sikob db_tr->db[0].db.desc.depend 2050103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2051103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2052103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2053103285Sikob } 2054103285Sikob bulkxfer->end = (caddr_t)db_tr; 2055103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2056103285Sikob } 2057103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2058103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2059103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2060103285Sikob/**/ 2061103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2062103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2063103285Sikob/**/ 2064103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2065103285Sikob 2066103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2067103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2068103285Sikob/* 2069103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2070103285Sikob*/ 2071103285Sikob return; 2072103285Sikob} 2073106790Ssimokawa 2074106790Ssimokawastatic int 2075106790Ssimokawafwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2076106790Ssimokawa int mode, void *buf) 2077103285Sikob{ 2078103285Sikob volatile struct fwohcidb *db = db_tr->db; 2079103285Sikob int err = 0; 2080103285Sikob if(buf == 0){ 2081103285Sikob err = EINVAL; 2082103285Sikob return err; 2083103285Sikob } 2084103285Sikob db_tr->buf = buf; 2085103285Sikob db_tr->dbcnt = 3; 2086103285Sikob db_tr->dummy = NULL; 2087103285Sikob 2088103285Sikob db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2089103285Sikob 2090103285Sikob db[2].db.desc.depend = 0; 2091103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2092103285Sikob db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2093103285Sikob 2094103285Sikob db[0].db.desc.status = 0; 2095103285Sikob db[0].db.desc.count = 0; 2096103285Sikob 2097103285Sikob db[2].db.desc.status = 0; 2098103285Sikob db[2].db.desc.count = 0; 2099103285Sikob if( mode & FWXFERQ_STREAM ){ 2100103285Sikob db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2101103285Sikob if(mode & FWXFERQ_PACKET ){ 2102103285Sikob db[2].db.desc.cmd 2103103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2104103285Sikob } 2105103285Sikob } 2106103285Sikob db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2107103285Sikob return 1; 2108103285Sikob} 2109106790Ssimokawa 2110106790Ssimokawaint 2111106790Ssimokawafwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2112106790Ssimokawa void *buf, void *dummy) 2113103285Sikob{ 2114103285Sikob volatile struct fwohcidb *db = db_tr->db; 2115103285Sikob int i; 2116103285Sikob void *dbuf[2]; 2117103285Sikob int dsiz[2]; 2118103285Sikob 2119103285Sikob if(buf == 0){ 2120103285Sikob buf = malloc(size, M_DEVBUF, M_NOWAIT); 2121103285Sikob if(buf == NULL) return 0; 2122103285Sikob db_tr->buf = buf; 2123103285Sikob db_tr->dbcnt = 1; 2124103285Sikob db_tr->dummy = NULL; 2125103285Sikob dsiz[0] = size; 2126103285Sikob dbuf[0] = buf; 2127103285Sikob }else if(dummy == NULL){ 2128103285Sikob db_tr->buf = buf; 2129103285Sikob db_tr->dbcnt = 1; 2130103285Sikob db_tr->dummy = NULL; 2131103285Sikob dsiz[0] = size; 2132103285Sikob dbuf[0] = buf; 2133103285Sikob }else{ 2134103285Sikob db_tr->buf = buf; 2135103285Sikob db_tr->dbcnt = 2; 2136103285Sikob db_tr->dummy = dummy; 2137103285Sikob dsiz[0] = sizeof(u_int32_t); 2138103285Sikob dsiz[1] = size; 2139103285Sikob dbuf[0] = dummy; 2140103285Sikob dbuf[1] = buf; 2141103285Sikob } 2142103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2143103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2144103285Sikob db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2145103285Sikob if( mode & FWXFERQ_STREAM ){ 2146103285Sikob db[i].db.desc.cmd |= OHCI_UPDATE; 2147103285Sikob } 2148103285Sikob db[i].db.desc.status = 0; 2149103285Sikob db[i].db.desc.count = dsiz[i]; 2150103285Sikob } 2151103285Sikob if( mode & FWXFERQ_STREAM ){ 2152103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2153103285Sikob if(mode & FWXFERQ_PACKET ){ 2154103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd 2155103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2156103285Sikob } 2157103285Sikob } 2158103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2159103285Sikob return 1; 2160103285Sikob} 2161106790Ssimokawa 2162106790Ssimokawastatic void 2163106790Ssimokawafwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2164103285Sikob{ 2165103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2166103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2167103285Sikob int z = 1; 2168103285Sikob struct fw_pkt *fp; 2169103285Sikob u_int8_t *ld; 2170103285Sikob u_int32_t off = NULL; 2171103285Sikob u_int32_t stat; 2172103285Sikob u_int32_t *qld; 2173103285Sikob u_int32_t reg; 2174103285Sikob u_int spd; 2175103285Sikob u_int dmach; 2176103285Sikob int len, i, plen; 2177103285Sikob caddr_t buf; 2178103285Sikob 2179103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2180103285Sikob if( &sc->ir[dmach] == dbch){ 2181103285Sikob off = OHCI_IROFF(dmach); 2182103285Sikob break; 2183103285Sikob } 2184103285Sikob } 2185103285Sikob if(off == NULL){ 2186103285Sikob return; 2187103285Sikob } 2188103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2189103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2190103285Sikob return; 2191103285Sikob } 2192103285Sikob 2193103285Sikob odb_tr = NULL; 2194103285Sikob db_tr = dbch->top; 2195103285Sikob i = 0; 2196103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2197106789Ssimokawa if (count >= 0 && count-- == 0) 2198106789Ssimokawa break; 2199103285Sikob ld = (u_int8_t *)db_tr->buf; 2200103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2201103285Sikob /* skip timeStamp */ 2202103285Sikob ld += sizeof(struct fwohci_trailer); 2203103285Sikob } 2204103285Sikob qld = (u_int32_t *)ld; 2205103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2206103285Sikob/* 2207103285Sikob{ 2208103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2209103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2210103285Sikob} 2211103285Sikob*/ 2212103285Sikob fp=(struct fw_pkt *)ld; 2213103285Sikob qld[0] = htonl(qld[0]); 2214103285Sikob plen = sizeof(struct fw_isohdr) 2215103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2216103285Sikob ld += plen; 2217103285Sikob len -= plen; 2218103285Sikob buf = db_tr->buf; 2219103285Sikob db_tr->buf = NULL; 2220103285Sikob stat = reg & 0x1f; 2221103285Sikob spd = reg & 0x3; 2222103285Sikob switch(stat){ 2223103285Sikob case FWOHCIEV_ACKCOMPL: 2224103285Sikob case FWOHCIEV_ACKPEND: 2225103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2226103285Sikob break; 2227103285Sikob default: 2228103285Sikob free(buf, M_DEVBUF); 2229103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2230103285Sikob break; 2231103285Sikob } 2232103285Sikob i++; 2233103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2234103285Sikob dbch->xferq.flag, 0, NULL); 2235103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2236103285Sikob if(dbch->pdb_tr != NULL){ 2237103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2238103285Sikob } else { 2239103285Sikob /* XXX should be rewritten in better way */ 2240103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2241103285Sikob } 2242103285Sikob dbch->pdb_tr = db_tr; 2243103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2244103285Sikob } 2245103285Sikob dbch->top = db_tr; 2246103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2247103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2248103285Sikob return; 2249103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2250103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2251103285Sikob dbch->top = db_tr; 2252103285Sikob fwohci_irx_enable(fc, dmach); 2253103285Sikob} 2254103285Sikob 2255103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2256103285Sikobstatic int 2257103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2258103285Sikob{ 2259103285Sikob int i; 2260103285Sikob 2261103285Sikob for( i = 4; i < hlen ; i+=4){ 2262103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2263103285Sikob } 2264103285Sikob 2265103285Sikob switch(fp->mode.common.tcode){ 2266103285Sikob case FWTCODE_RREQQ: 2267103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2268103285Sikob case FWTCODE_WRES: 2269103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2270103285Sikob case FWTCODE_WREQQ: 2271103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2272103285Sikob case FWTCODE_RREQB: 2273103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2274103285Sikob case FWTCODE_RRESQ: 2275103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2276103285Sikob case FWTCODE_WREQB: 2277103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2278103285Sikob + sizeof(u_int32_t); 2279103285Sikob case FWTCODE_LREQ: 2280103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2281103285Sikob + sizeof(u_int32_t); 2282103285Sikob case FWTCODE_RRESB: 2283103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2284103285Sikob + sizeof(u_int32_t); 2285103285Sikob case FWTCODE_LRES: 2286103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2287103285Sikob + sizeof(u_int32_t); 2288103285Sikob case FWOHCITCODE_PHY: 2289103285Sikob return 16; 2290103285Sikob } 2291103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2292103285Sikob return 0; 2293103285Sikob} 2294103285Sikob 2295106790Ssimokawastatic void 2296106790Ssimokawafwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2297103285Sikob{ 2298103285Sikob struct fwohcidb_tr *db_tr; 2299103285Sikob int z = 1; 2300103285Sikob struct fw_pkt *fp; 2301103285Sikob u_int8_t *ld; 2302103285Sikob u_int32_t stat, off; 2303103285Sikob u_int spd; 2304103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2305103285Sikob int s; 2306103285Sikob caddr_t buf; 2307103285Sikob int resCount; 2308103285Sikob 2309103285Sikob if(&sc->arrq == dbch){ 2310103285Sikob off = OHCI_ARQOFF; 2311103285Sikob }else if(&sc->arrs == dbch){ 2312103285Sikob off = OHCI_ARSOFF; 2313103285Sikob }else{ 2314103285Sikob return; 2315103285Sikob } 2316103285Sikob 2317103285Sikob s = splfw(); 2318103285Sikob db_tr = dbch->top; 2319103285Sikob pcnt = 0; 2320103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2321103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2322103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2323103285Sikob resCount = db_tr->db[0].db.desc.count; 2324103285Sikob len = dbch->xferq.psize - resCount 2325103285Sikob - dbch->buf_offset; 2326103285Sikob while (len > 0 ) { 2327106789Ssimokawa if (count >= 0 && count-- == 0) 2328106789Ssimokawa goto out; 2329103285Sikob if(dbch->frag.buf != NULL){ 2330103285Sikob buf = dbch->frag.buf; 2331103285Sikob if (dbch->frag.plen < 0) { 2332103285Sikob /* incomplete header */ 2333103285Sikob int hlen; 2334103285Sikob 2335103285Sikob hlen = - dbch->frag.plen; 2336103285Sikob rlen = hlen - dbch->frag.len; 2337103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2338103285Sikob ld += rlen; 2339103285Sikob len -= rlen; 2340103285Sikob dbch->frag.len += rlen; 2341103285Sikob#if 0 2342103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2343103285Sikob#endif 2344103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2345103285Sikob dbch->frag.plen 2346103285Sikob = fwohci_get_plen(sc, fp, hlen); 2347103285Sikob if (dbch->frag.plen == 0) 2348103285Sikob goto out; 2349103285Sikob } 2350103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2351103285Sikob#if 0 2352103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2353103285Sikob#endif 2354103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2355103285Sikob rlen); 2356103285Sikob ld += rlen; 2357103285Sikob len -= rlen; 2358103285Sikob plen = dbch->frag.plen; 2359103285Sikob dbch->frag.buf = NULL; 2360103285Sikob dbch->frag.plen = 0; 2361103285Sikob dbch->frag.len = 0; 2362103285Sikob poff = 0; 2363103285Sikob }else{ 2364103285Sikob fp=(struct fw_pkt *)ld; 2365103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2366103285Sikob switch(fp->mode.common.tcode){ 2367103285Sikob case FWTCODE_RREQQ: 2368103285Sikob case FWTCODE_WRES: 2369103285Sikob case FWTCODE_WREQQ: 2370103285Sikob case FWTCODE_RRESQ: 2371103285Sikob case FWOHCITCODE_PHY: 2372103285Sikob hlen = 12; 2373103285Sikob break; 2374103285Sikob case FWTCODE_RREQB: 2375103285Sikob case FWTCODE_WREQB: 2376103285Sikob case FWTCODE_LREQ: 2377103285Sikob case FWTCODE_RRESB: 2378103285Sikob case FWTCODE_LRES: 2379103285Sikob hlen = 16; 2380103285Sikob break; 2381103285Sikob default: 2382103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2383103285Sikob goto out; 2384103285Sikob } 2385103285Sikob if (len >= hlen) { 2386103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2387103285Sikob if (plen == 0) 2388103285Sikob goto out; 2389103285Sikob plen = (plen + 3) & ~3; 2390103285Sikob len -= plen; 2391103285Sikob } else { 2392103285Sikob plen = -hlen; 2393103285Sikob len -= hlen; 2394103285Sikob } 2395103285Sikob if(resCount > 0 || len > 0){ 2396103285Sikob buf = malloc( dbch->xferq.psize, 2397103285Sikob M_DEVBUF, M_NOWAIT); 2398103285Sikob if(buf == NULL){ 2399103285Sikob printf("cannot malloc!\n"); 2400103285Sikob free(db_tr->buf, M_DEVBUF); 2401103285Sikob goto out; 2402103285Sikob } 2403103285Sikob bcopy(ld, buf, plen); 2404103285Sikob poff = 0; 2405103285Sikob dbch->frag.buf = NULL; 2406103285Sikob dbch->frag.plen = 0; 2407103285Sikob dbch->frag.len = 0; 2408103285Sikob }else if(len < 0){ 2409103285Sikob dbch->frag.buf = db_tr->buf; 2410103285Sikob if (plen < 0) { 2411103285Sikob#if 0 2412103285Sikob printf("plen < 0:" 2413103285Sikob "hlen: %d len: %d\n", 2414103285Sikob hlen, len); 2415103285Sikob#endif 2416103285Sikob dbch->frag.len = hlen + len; 2417103285Sikob dbch->frag.plen = -hlen; 2418103285Sikob } else { 2419103285Sikob dbch->frag.len = plen + len; 2420103285Sikob dbch->frag.plen = plen; 2421103285Sikob } 2422103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2423103285Sikob buf = NULL; 2424103285Sikob }else{ 2425103285Sikob buf = db_tr->buf; 2426103285Sikob poff = ld - (u_int8_t *)buf; 2427103285Sikob dbch->frag.buf = NULL; 2428103285Sikob dbch->frag.plen = 0; 2429103285Sikob dbch->frag.len = 0; 2430103285Sikob } 2431103285Sikob ld += plen; 2432103285Sikob } 2433103285Sikob if( buf != NULL){ 2434103285Sikob/* DMA result-code will be written at the tail of packet */ 2435103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2436103285Sikob spd = (stat >> 5) & 0x3; 2437103285Sikob stat &= 0x1f; 2438103285Sikob switch(stat){ 2439103285Sikob case FWOHCIEV_ACKPEND: 2440103285Sikob#if 0 2441103285Sikob printf("fwohci_arcv: ack pending..\n"); 2442103285Sikob#endif 2443103285Sikob /* fall through */ 2444103285Sikob case FWOHCIEV_ACKCOMPL: 2445103285Sikob if( poff != 0 ) 2446103285Sikob bcopy(buf+poff, buf, plen - 4); 2447103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2448103285Sikob break; 2449103285Sikob case FWOHCIEV_BUSRST: 2450103285Sikob free(buf, M_DEVBUF); 2451103285Sikob if (sc->fc.status != FWBUSRESET) 2452103285Sikob printf("got BUSRST packet!?\n"); 2453103285Sikob break; 2454103285Sikob default: 2455103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2456103285Sikob#if 0 /* XXX */ 2457103285Sikob goto out; 2458103285Sikob#endif 2459103285Sikob break; 2460103285Sikob } 2461103285Sikob } 2462103285Sikob pcnt ++; 2463103285Sikob }; 2464103285Sikobout: 2465103285Sikob if (resCount == 0) { 2466103285Sikob /* done on this buffer */ 2467103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2468103285Sikob dbch->xferq.flag, 0, NULL); 2469103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2470103285Sikob dbch->bottom = db_tr; 2471103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2472103285Sikob dbch->top = db_tr; 2473103285Sikob dbch->buf_offset = 0; 2474103285Sikob } else { 2475103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2476103285Sikob break; 2477103285Sikob } 2478103285Sikob /* XXX make sure DMA is not dead */ 2479103285Sikob } 2480103285Sikob#if 0 2481103285Sikob if (pcnt < 1) 2482103285Sikob printf("fwohci_arcv: no packets\n"); 2483103285Sikob#endif 2484103285Sikob splx(s); 2485103285Sikob} 2486