fwohci.c revision 103285
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16103285Sikob * This product includes software developed by K. Kobayashi and H. SHimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohci.c 103285 2002-09-13 12:31:56Z ikob $ 34103285Sikob * 35103285Sikob */ 36103285Sikobextern int nxfer; 37103285Sikob#define DEBUG_PACKET 38103285Sikob#undef DEBUG_PACKET 39103285Sikob#define ATRQ_CH 0 40103285Sikob#define ATRS_CH 1 41103285Sikob#define ARRQ_CH 2 42103285Sikob#define ARRS_CH 3 43103285Sikob#define ITX_CH 4 44103285Sikob#define IRX_CH 0x24 45103285Sikob 46103285Sikob#include <sys/param.h> 47103285Sikob#include <sys/systm.h> 48103285Sikob#include <sys/types.h> 49103285Sikob#include <sys/mbuf.h> 50103285Sikob#include <sys/mman.h> 51103285Sikob#include <sys/socket.h> 52103285Sikob#include <sys/socketvar.h> 53103285Sikob#include <sys/signalvar.h> 54103285Sikob#include <sys/malloc.h> 55103285Sikob#include <sys/uio.h> 56103285Sikob#include <sys/sockio.h> 57103285Sikob#include <sys/bus.h> 58103285Sikob#include <sys/kernel.h> 59103285Sikob#include <sys/conf.h> 60103285Sikob 61103285Sikob#include <machine/bus.h> 62103285Sikob#include <machine/resource.h> 63103285Sikob#include <sys/rman.h> 64103285Sikob 65103285Sikob#ifdef __FreeBSD__ 66103285Sikob#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 67103285Sikob#include <machine/clock.h> 68103285Sikob#include <pci/pcivar.h> 69103285Sikob#include <pci/pcireg.h> 70103285Sikob#include <vm/vm.h> 71103285Sikob#include <vm/vm_extern.h> 72103285Sikob#include <vm/pmap.h> /* for vtophys proto */ 73103285Sikob 74103285Sikob#include <dev/firewire/firewire.h> 75103285Sikob#include <dev/firewire/firewirebusreg.h> 76103285Sikob#include <dev/firewire/firewirereg.h> 77103285Sikob#include <dev/firewire/fwohcireg.h> 78103285Sikob#include <dev/firewire/fwohcivar.h> 79103285Sikob#include <dev/firewire/firewire_phy.h> 80103285Sikob 81103285Sikob#define OHCI_DEBUG 82103285Sikob#undef OHCI_DEBUG 83103285Sikob/* 84103285Sikob#define OHCI_DEBUG 85103285Sikob*/ 86103285Sikobstatic char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 87103285Sikob "STOR","LOAD","NOP ","STOP",}; 88103285Sikobstatic char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 89103285Sikob "UNDEF","REG","SYS","DEV"}; 90103285Sikobchar fwohcicode[32][0x20]={ 91103285Sikob "No stat","Undef","long","miss Ack err", 92103285Sikob "underrun","overrun","desc err", "data read err", 93103285Sikob "data write err","bus reset","timeout","tcode err", 94103285Sikob "Undef","Undef","unknown event","flushed", 95103285Sikob "Undef","ack complete","ack pend","Undef", 96103285Sikob "ack busy_X","ack busy_A","ack busy_B","Undef", 97103285Sikob "Undef","Undef","Undef","ack tardy", 98103285Sikob "Undef","ack data_err","ack type_err",""}; 99103285Sikob#define MAX_SPEED 2 100103285Sikobextern char linkspeed[MAX_SPEED+1][0x10]; 101103285Sikobextern int maxrec[MAX_SPEED+1]; 102103285Sikobstatic char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 103103285Sikobu_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 104103285Sikob 105103285Sikobstatic struct tcode_info tinfo[] = { 106103285Sikob/* hdr_len block flag*/ 107103285Sikob/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 108103285Sikob/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 109103285Sikob/* 2 WRES */ {12, FWTI_RES}, 110103285Sikob/* 3 XXX */ { 0, 0}, 111103285Sikob/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 112103285Sikob/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 113103285Sikob/* 6 RRESQ */ {16, FWTI_RES}, 114103285Sikob/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 115103285Sikob/* 8 CYCS */ { 0, 0}, 116103285Sikob/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 117103285Sikob/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 118103285Sikob/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 119103285Sikob/* c XXX */ { 0, 0}, 120103285Sikob/* d XXX */ { 0, 0}, 121103285Sikob/* e PHY */ {12, FWTI_REQ}, 122103285Sikob/* f XXX */ { 0, 0} 123103285Sikob}; 124103285Sikob 125103285Sikob#define OHCI_WRITE_SIGMASK 0xffff0000 126103285Sikob#define OHCI_READ_SIGMASK 0xffff0000 127103285Sikob 128103285Sikob#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 129103285Sikob#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 130103285Sikob 131103285Sikob#endif /* __FreeBSD__ */ 132103285Sikob 133103285Sikob#define senderr(e) { error = (e); goto bad;} 134103285Sikob 135103285Sikobstatic void fwohci_ibr __P((struct firewire_comm *)); 136103285Sikobstatic void fwohci_db_init __P((struct fwohci_dbch *)); 137103285Sikobstatic void fwohci_db_free __P((struct fwohci_dbch *)); 138103285Sikobstatic void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *)); 139103285Sikobstatic void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *)); 140103285Sikobstatic void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 141103285Sikobstatic void fwohci_start_atq __P((struct firewire_comm *)); 142103285Sikobstatic void fwohci_start_ats __P((struct firewire_comm *)); 143103285Sikobstatic void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 144103285Sikobstatic void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 145103285Sikobstatic void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 146103285Sikobstatic void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 147103285Sikobstatic u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 148103285Sikobstatic u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 149103285Sikobstatic int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 150103285Sikobstatic int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 151103285Sikobstatic int fwohci_irx_enable __P((struct firewire_comm *, int)); 152103285Sikobstatic int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 153103285Sikobstatic int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 154103285Sikobstatic int fwohci_irx_disable __P((struct firewire_comm *, int)); 155103285Sikobstatic void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 156103285Sikobstatic int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 157103285Sikobstatic int fwohci_itx_disable __P((struct firewire_comm *, int)); 158103285Sikobstatic void fwohci_timeout __P((void *)); 159103285Sikobstatic void fwohci_poll __P((struct firewire_comm *, int, int)); 160103285Sikobstatic void fwohci_set_intr __P((struct firewire_comm *, int)); 161103285Sikobstatic int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 162103285Sikobstatic int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 163103285Sikobstatic void dump_db __P((struct fwohci_softc *, u_int32_t)); 164103285Sikobstatic void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 165103285Sikobstatic void dump_dma __P((struct fwohci_softc *, u_int32_t)); 166103285Sikobstatic u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 167103285Sikobstatic void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 168103285Sikobstatic void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 169103285Sikobvoid fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 170103285Sikob 171103285Sikob/* 172103285Sikob * memory allocated for DMA programs 173103285Sikob */ 174103285Sikob#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 175103285Sikob 176103285Sikob/* #define NDB 1024 */ 177103285Sikob#define NDB FWMAXQUEUE 178103285Sikob#define NDVDB (DVBUF * NDB) 179103285Sikob 180103285Sikob#define OHCI_VERSION 0x00 181103285Sikob#define OHCI_CROMHDR 0x18 182103285Sikob#define OHCI_BUS_OPT 0x20 183103285Sikob#define OHCI_BUSIRMC (1 << 31) 184103285Sikob#define OHCI_BUSCMC (1 << 30) 185103285Sikob#define OHCI_BUSISC (1 << 29) 186103285Sikob#define OHCI_BUSBMC (1 << 28) 187103285Sikob#define OHCI_BUSPMC (1 << 27) 188103285Sikob#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 189103285Sikob OHCI_BUSBMC | OHCI_BUSPMC 190103285Sikob 191103285Sikob#define OHCI_EUID_HI 0x24 192103285Sikob#define OHCI_EUID_LO 0x28 193103285Sikob 194103285Sikob#define OHCI_CROMPTR 0x34 195103285Sikob#define OHCI_HCCCTL 0x50 196103285Sikob#define OHCI_HCCCTLCLR 0x54 197103285Sikob#define OHCI_AREQHI 0x100 198103285Sikob#define OHCI_AREQHICLR 0x104 199103285Sikob#define OHCI_AREQLO 0x108 200103285Sikob#define OHCI_AREQLOCLR 0x10c 201103285Sikob#define OHCI_PREQHI 0x110 202103285Sikob#define OHCI_PREQHICLR 0x114 203103285Sikob#define OHCI_PREQLO 0x118 204103285Sikob#define OHCI_PREQLOCLR 0x11c 205103285Sikob#define OHCI_PREQUPPER 0x120 206103285Sikob 207103285Sikob#define OHCI_SID_BUF 0x64 208103285Sikob#define OHCI_SID_CNT 0x68 209103285Sikob#define OHCI_SID_CNT_MASK 0xffc 210103285Sikob 211103285Sikob#define OHCI_IT_STAT 0x90 212103285Sikob#define OHCI_IT_STATCLR 0x94 213103285Sikob#define OHCI_IT_MASK 0x98 214103285Sikob#define OHCI_IT_MASKCLR 0x9c 215103285Sikob 216103285Sikob#define OHCI_IR_STAT 0xa0 217103285Sikob#define OHCI_IR_STATCLR 0xa4 218103285Sikob#define OHCI_IR_MASK 0xa8 219103285Sikob#define OHCI_IR_MASKCLR 0xac 220103285Sikob 221103285Sikob#define OHCI_LNKCTL 0xe0 222103285Sikob#define OHCI_LNKCTLCLR 0xe4 223103285Sikob 224103285Sikob#define OHCI_PHYACCESS 0xec 225103285Sikob#define OHCI_CYCLETIMER 0xf0 226103285Sikob 227103285Sikob#define OHCI_DMACTL(off) (off) 228103285Sikob#define OHCI_DMACTLCLR(off) (off + 4) 229103285Sikob#define OHCI_DMACMD(off) (off + 0xc) 230103285Sikob#define OHCI_DMAMATCH(off) (off + 0x10) 231103285Sikob 232103285Sikob#define OHCI_ATQOFF 0x180 233103285Sikob#define OHCI_ATQCTL OHCI_ATQOFF 234103285Sikob#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 235103285Sikob#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 236103285Sikob#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 237103285Sikob 238103285Sikob#define OHCI_ATSOFF 0x1a0 239103285Sikob#define OHCI_ATSCTL OHCI_ATSOFF 240103285Sikob#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 241103285Sikob#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 242103285Sikob#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 243103285Sikob 244103285Sikob#define OHCI_ARQOFF 0x1c0 245103285Sikob#define OHCI_ARQCTL OHCI_ARQOFF 246103285Sikob#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 247103285Sikob#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 248103285Sikob#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 249103285Sikob 250103285Sikob#define OHCI_ARSOFF 0x1e0 251103285Sikob#define OHCI_ARSCTL OHCI_ARSOFF 252103285Sikob#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 253103285Sikob#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 254103285Sikob#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 255103285Sikob 256103285Sikob#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 257103285Sikob#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 258103285Sikob#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 259103285Sikob#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 260103285Sikob 261103285Sikob#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 262103285Sikob#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 263103285Sikob#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 264103285Sikob#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 265103285Sikob#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 266103285Sikob 267103285Sikobd_ioctl_t fwohci_ioctl; 268103285Sikob 269103285Sikob/* 270103285Sikob * Communication with PHY device 271103285Sikob */ 272103285Sikobstatic u_int32_t fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 273103285Sikob{ 274103285Sikob u_int32_t fun; 275103285Sikob 276103285Sikob addr &= 0xf; 277103285Sikob data &= 0xff; 278103285Sikob 279103285Sikob fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 280103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 281103285Sikob DELAY(100); 282103285Sikob 283103285Sikob return(fwphy_rddata( sc, addr)); 284103285Sikob} 285103285Sikob 286103285Sikobstatic u_int32_t 287103285Sikobfwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 288103285Sikob{ 289103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 290103285Sikob int i; 291103285Sikob u_int32_t bm; 292103285Sikob 293103285Sikob#define OHCI_CSR_DATA 0x0c 294103285Sikob#define OHCI_CSR_COMP 0x10 295103285Sikob#define OHCI_CSR_CONT 0x14 296103285Sikob#define OHCI_BUS_MANAGER_ID 0 297103285Sikob 298103285Sikob OWRITE(sc, OHCI_CSR_DATA, node); 299103285Sikob OWRITE(sc, OHCI_CSR_COMP, 0x3f); 300103285Sikob OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 301103285Sikob for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 302103285Sikob DELAY(100); 303103285Sikob bm = OREAD(sc, OHCI_CSR_DATA); 304103285Sikob if((bm & 0x3f) == 0x3f){ 305103285Sikob printf("fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 306103285Sikob bm = node; 307103285Sikob }else{ 308103285Sikob printf("fw_set_bus_manager: %d-X%d (loop=%d)\n", bm, node, i); 309103285Sikob } 310103285Sikob 311103285Sikob return(bm); 312103285Sikob} 313103285Sikob 314103285Sikobstatic u_int32_t fwphy_rddata(struct fwohci_softc *sc, u_int addr) 315103285Sikob{ 316103285Sikob u_int32_t fun; 317103285Sikob u_int i; 318103285Sikob 319103285Sikob addr &= 0xf; 320103285Sikob fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 321103285Sikob OWRITE(sc, OHCI_PHYACCESS, fun); 322103285Sikob for ( i = 0 ; i < 1000 ; i ++ ){ 323103285Sikob fun = OREAD(sc, OHCI_PHYACCESS); 324103285Sikob if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 325103285Sikob break; 326103285Sikob DELAY(1000); 327103285Sikob } 328103285Sikob if( i >= 1000) 329103285Sikob device_printf(sc->fc.dev, "cannot read phy\n"); 330103285Sikob return((fun >> PHYDEV_RDDATA )& 0xff); 331103285Sikob} 332103285Sikob/* Device specific ioctl. */ 333103285Sikobint 334103285Sikobfwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 335103285Sikob{ 336103285Sikob struct firewire_softc *sc; 337103285Sikob struct fwohci_softc *fc; 338103285Sikob int unit = DEV2UNIT(dev); 339103285Sikob int err = 0; 340103285Sikob struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 341103285Sikob u_int32_t *dmach = (u_int32_t *) data; 342103285Sikob 343103285Sikob sc = devclass_get_softc(firewire_devclass, unit); 344103285Sikob if(sc == NULL){ 345103285Sikob return(EINVAL); 346103285Sikob } 347103285Sikob fc = (struct fwohci_softc *)sc->fc; 348103285Sikob 349103285Sikob if (!data) 350103285Sikob return(EINVAL); 351103285Sikob 352103285Sikob switch (cmd) { 353103285Sikob case FWOHCI_WRREG: 354103285Sikob#define OHCI_MAX_REG 0x800 355103285Sikob if(reg->addr <= OHCI_MAX_REG){ 356103285Sikob OWRITE(fc, reg->addr, reg->data); 357103285Sikob reg->data = OREAD(fc, reg->addr); 358103285Sikob }else{ 359103285Sikob err = EINVAL; 360103285Sikob } 361103285Sikob break; 362103285Sikob case FWOHCI_RDREG: 363103285Sikob if(reg->addr <= OHCI_MAX_REG){ 364103285Sikob reg->data = OREAD(fc, reg->addr); 365103285Sikob }else{ 366103285Sikob err = EINVAL; 367103285Sikob } 368103285Sikob break; 369103285Sikob/* Read DMA descriptors for debug */ 370103285Sikob case DUMPDMA: 371103285Sikob if(*dmach <= OHCI_MAX_DMA_CH ){ 372103285Sikob dump_dma(fc, *dmach); 373103285Sikob dump_db(fc, *dmach); 374103285Sikob }else{ 375103285Sikob err = EINVAL; 376103285Sikob } 377103285Sikob break; 378103285Sikob default: 379103285Sikob break; 380103285Sikob } 381103285Sikob return err; 382103285Sikob} 383103285Sikobint fwohci_init(struct fwohci_softc *sc, device_t dev) 384103285Sikob{ 385103285Sikob int err = 0; 386103285Sikob int i; 387103285Sikob u_int32_t reg, reg2; 388103285Sikob struct fwohcidb_tr *db_tr; 389103285Sikob int e1394a = 1; 390103285Sikob 391103285Sikob reg = OREAD(sc, OHCI_VERSION); 392103285Sikob device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 393103285Sikob (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 394103285Sikob 395103285Sikob#if 0 396103285Sikob/* XXX: Not support bridge function yet, then clear bus ID */ 397103285Sikob OWRITE(sc, FWOHCI_NODEID, (OREAD(sc, FWOHCI_NODEID)) & 0xffff003f); 398103285Sikob#endif 399103285Sikob 400103285Sikob/* XXX: Available Isochrounous DMA channel probe */ 401103285Sikob for( i = 0 ; i < 0x20 ; i ++ ){ 402103285Sikob OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 403103285Sikob reg = OREAD(sc, OHCI_IRCTL(i)); 404103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 405103285Sikob OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 406103285Sikob reg = OREAD(sc, OHCI_ITCTL(i)); 407103285Sikob if(!(reg & OHCI_CNTL_DMA_RUN)) break; 408103285Sikob } 409103285Sikob sc->fc.nisodma = i; 410103285Sikob device_printf(dev, "No. of Isochronous channel is %d.\n", i); 411103285Sikob 412103285Sikob sc->fc.arq = &sc->arrq.xferq; 413103285Sikob sc->fc.ars = &sc->arrs.xferq; 414103285Sikob sc->fc.atq = &sc->atrq.xferq; 415103285Sikob sc->fc.ats = &sc->atrs.xferq; 416103285Sikob 417103285Sikob sc->arrq.xferq.start = NULL; 418103285Sikob sc->arrs.xferq.start = NULL; 419103285Sikob sc->atrq.xferq.start = fwohci_start_atq; 420103285Sikob sc->atrs.xferq.start = fwohci_start_ats; 421103285Sikob 422103285Sikob sc->arrq.xferq.drain = NULL; 423103285Sikob sc->arrs.xferq.drain = NULL; 424103285Sikob sc->atrq.xferq.drain = fwohci_drain_atq; 425103285Sikob sc->atrs.xferq.drain = fwohci_drain_ats; 426103285Sikob 427103285Sikob sc->arrq.ndesc = 1; 428103285Sikob sc->arrs.ndesc = 1; 429103285Sikob sc->atrq.ndesc = 10; 430103285Sikob sc->atrs.ndesc = 10 / 2; 431103285Sikob 432103285Sikob sc->arrq.ndb = NDB; 433103285Sikob sc->arrs.ndb = NDB / 2; 434103285Sikob sc->atrq.ndb = NDB; 435103285Sikob sc->atrs.ndb = NDB / 2; 436103285Sikob 437103285Sikob sc->arrq.dummy = NULL; 438103285Sikob sc->arrs.dummy = NULL; 439103285Sikob sc->atrq.dummy = NULL; 440103285Sikob sc->atrs.dummy = NULL; 441103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 442103285Sikob sc->fc.it[i] = &sc->it[i].xferq; 443103285Sikob sc->fc.ir[i] = &sc->ir[i].xferq; 444103285Sikob sc->it[i].ndb = 0; 445103285Sikob sc->ir[i].ndb = 0; 446103285Sikob } 447103285Sikob 448103285Sikob sc->fc.tcode = tinfo; 449103285Sikob 450103285Sikob sc->cromptr = (u_int32_t *) 451103285Sikob contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 452103285Sikob 453103285Sikob if(sc->cromptr == NULL){ 454103285Sikob return ENOMEM; 455103285Sikob } 456103285Sikob sc->fc.dev = dev; 457103285Sikob sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 458103285Sikob 459103285Sikob sc->fc.config_rom[1] = 0x31333934; 460103285Sikob sc->fc.config_rom[2] = 0xf000a002; 461103285Sikob sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 462103285Sikob sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 463103285Sikob sc->fc.config_rom[5] = 0; 464103285Sikob sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 465103285Sikob 466103285Sikob sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 467103285Sikob 468103285Sikob 469103285Sikob fw_init(&sc->fc); 470103285Sikob 471103285Sikob/* Now stopping all DMA channel */ 472103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 473103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 474103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 475103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 476103285Sikob 477103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, ~0); 478103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 479103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 480103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 481103285Sikob } 482103285Sikob 483103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 484103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 485103285Sikob device_printf(dev, "resetting OHCI..."); 486103285Sikob i = 0; 487103285Sikob while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 488103285Sikob if (i++ > 100) break; 489103285Sikob DELAY(1000); 490103285Sikob } 491103285Sikob printf("done (%d)\n", i); 492103285Sikob#if 0 493103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN | OHCI_HCC_LPS); 494103285Sikob#endif 495103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 496103285Sikob /* XXX wait for SCLK. */ 497103285Sikob DELAY(10000); 498103285Sikob 499103285Sikob reg = OREAD(sc, OHCI_BUS_OPT); 500103285Sikob reg2 = reg | OHCI_BUSFNC; 501103285Sikob /* XXX */ 502103285Sikob if (((reg & 0x0000f000) >> 12) < 10) 503103285Sikob reg2 = (reg2 & 0xffff0fff) | (10 << 12); 504103285Sikob device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 505103285Sikob OWRITE(sc, OHCI_BUS_OPT, reg2); 506103285Sikob 507103285Sikob OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 508103285Sikob OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 509103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 510103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 511103285Sikob 512103285Sikob/* 513103285Sikob * probe PHY parameters 514103285Sikob * 0. to prove PHY version, whether compliance of 1394a. 515103285Sikob * 1. to probe maximum speed supported by the PHY and 516103285Sikob * number of port supported by core-logic. 517103285Sikob * It is not actually available port on your PC . 518103285Sikob */ 519103285Sikob /* Wait a while */ 520103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 521103285Sikob#if 0 522103285Sikob /* try again */ 523103285Sikob DELAY(1000); 524103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 525103285Sikob#endif 526103285Sikob if((reg >> 5) != 7 ){ 527103285Sikob sc->fc.mode &= ~FWPHYASYST; 528103285Sikob sc->fc.nport = reg & FW_PHY_NP; 529103285Sikob sc->fc.speed = reg & FW_PHY_SPD >> 6; 530103285Sikob if (sc->fc.speed > MAX_SPEED) { 531103285Sikob device_printf(dev, "invalid speed %d (fixed to %d).\n", 532103285Sikob sc->fc.speed, MAX_SPEED); 533103285Sikob sc->fc.speed = MAX_SPEED; 534103285Sikob } 535103285Sikob sc->fc.maxrec = maxrec[sc->fc.speed]; 536103285Sikob device_printf(dev, 537103285Sikob "Link 1394 only %s, %d ports, maxrec %d bytes.\n", 538103285Sikob linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 539103285Sikob }else{ 540103285Sikob reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 541103285Sikob sc->fc.mode |= FWPHYASYST; 542103285Sikob sc->fc.nport = reg & FW_PHY_NP; 543103285Sikob sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 544103285Sikob if (sc->fc.speed > MAX_SPEED) { 545103285Sikob device_printf(dev, "invalid speed %d (fixed to %d).\n", 546103285Sikob sc->fc.speed, MAX_SPEED); 547103285Sikob sc->fc.speed = MAX_SPEED; 548103285Sikob } 549103285Sikob sc->fc.maxrec = maxrec[sc->fc.speed]; 550103285Sikob device_printf(dev, 551103285Sikob "Link 1394a available %s, %d ports, maxrec %d bytes.\n", 552103285Sikob linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 553103285Sikob 554103285Sikob /* check programPhyEnable */ 555103285Sikob reg2 = fwphy_rddata(sc, 5); 556103285Sikob#if 0 557103285Sikob if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 558103285Sikob#else /* XXX f�force to enable 1394a */ 559103285Sikob if (e1394a) { 560103285Sikob#endif 561103285Sikob device_printf(dev, "Enable 1394a Enhancements\n"); 562103285Sikob /* enable EAA EMC */ 563103285Sikob reg2 |= 0x03; 564103285Sikob /* set aPhyEnhanceEnable */ 565103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 566103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 567103285Sikob } else { 568103285Sikob /* for safe */ 569103285Sikob reg2 &= ~0x83; 570103285Sikob } 571103285Sikob reg2 = fwphy_wrdata(sc, 5, reg2); 572103285Sikob } 573103285Sikob 574103285Sikob reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 575103285Sikob if((reg >> 5) == 7 ){ 576103285Sikob reg = fwphy_rddata(sc, 4); 577103285Sikob reg |= 1 << 6; 578103285Sikob fwphy_wrdata(sc, 4, reg); 579103285Sikob reg = fwphy_rddata(sc, 4); 580103285Sikob } 581103285Sikob 582103285Sikob/* SID recieve buffer must allign 2^11 */ 583103285Sikob#define OHCI_SIDSIZE (1 << 11) 584103285Sikob sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 585103285Sikob 0x10000, 0xffffffff, OHCI_SIDSIZE); 586103285Sikob OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); 587103285Sikob sc->fc.sid_buf++; 588103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 589103285Sikob 590103285Sikob fwohci_db_init(&sc->arrq); 591103285Sikob fwohci_db_init(&sc->arrs); 592103285Sikob 593103285Sikob fwohci_db_init(&sc->atrq); 594103285Sikob fwohci_db_init(&sc->atrs); 595103285Sikob 596103285Sikob reg = OREAD(sc, FWOHCIGUID_H); 597103285Sikob for( i = 0 ; i < 4 ; i ++){ 598103285Sikob sc->fc.eui[3 - i] = reg & 0xff; 599103285Sikob reg = reg >> 8; 600103285Sikob } 601103285Sikob reg = OREAD(sc, FWOHCIGUID_L); 602103285Sikob for( i = 0 ; i < 4 ; i ++){ 603103285Sikob sc->fc.eui[7 - i] = reg & 0xff; 604103285Sikob reg = reg >> 8; 605103285Sikob } 606103285Sikob device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 607103285Sikob sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 608103285Sikob sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 609103285Sikob sc->fc.ioctl = fwohci_ioctl; 610103285Sikob sc->fc.cyctimer = fwohci_cyctimer; 611103285Sikob sc->fc.set_bmr = fwohci_set_bus_manager; 612103285Sikob sc->fc.ibr = fwohci_ibr; 613103285Sikob sc->fc.irx_enable = fwohci_irx_enable; 614103285Sikob sc->fc.irx_disable = fwohci_irx_disable; 615103285Sikob 616103285Sikob sc->fc.itx_enable = fwohci_itxbuf_enable; 617103285Sikob sc->fc.itx_disable = fwohci_itx_disable; 618103285Sikob sc->fc.irx_post = fwohci_irx_post; 619103285Sikob sc->fc.itx_post = NULL; 620103285Sikob sc->fc.timeout = fwohci_timeout; 621103285Sikob sc->fc.poll = fwohci_poll; 622103285Sikob sc->fc.set_intr = fwohci_set_intr; 623103285Sikob#if 0 624103285Sikob /* why this need twice? */ 625103285Sikob fwohci_db_init(&sc->arrq); 626103285Sikob#endif 627103285Sikob /* enable link */ 628103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 629103285Sikob fw_busreset(&sc->fc); 630103285Sikob fwohci_rx_enable(sc, &sc->arrq); 631103285Sikob fwohci_rx_enable(sc, &sc->arrs); 632103285Sikob 633103285Sikob for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 634103285Sikob i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 635103285Sikob db_tr->xfer = NULL; 636103285Sikob } 637103285Sikob for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 638103285Sikob i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 639103285Sikob db_tr->xfer = NULL; 640103285Sikob } 641103285Sikob sc->atrq.flags = sc->atrs.flags = 0; 642103285Sikob 643103285Sikob OWRITE(sc, FWOHCI_RETRY, 644103285Sikob (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ; 645103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 646103285Sikob OWRITE(sc, FWOHCI_INTMASK, 647103285Sikob OHCI_INT_ERR | OHCI_INT_PHY_SID 648103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 649103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 650103285Sikob | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 651103285Sikob fwohci_set_intr(&sc->fc, 1); 652103285Sikob 653103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 654103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 655103285Sikob 656103285Sikob#if 0 657103285Sikob fwohci_ibr(sc); 658103285Sikob#endif 659103285Sikob 660103285Sikob return err; 661103285Sikob} 662103285Sikobvoid fwohci_timeout(void *arg) 663103285Sikob{ 664103285Sikob/* 665103285Sikob fwohci_txd(sc, &(sc->atrq)); 666103285Sikob fwohci_txd(sc, &(sc->atrs)); 667103285Sikob fw_expire_tlabel(&sc->fc); 668103285Sikob*/ 669103285Sikob struct fwohci_softc *sc; 670103285Sikob 671103285Sikob sc = (struct fwohci_softc *)arg; 672103285Sikob sc->fc.timeouthandle = timeout(fwohci_timeout, 673103285Sikob (void *)sc, FW_XFERTIMEOUT * hz * 10); 674103285Sikob} 675103285Sikobu_int32_t fwohci_cyctimer(struct firewire_comm *fc) 676103285Sikob{ 677103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 678103285Sikob return(OREAD(sc, OHCI_CYCLETIMER)); 679103285Sikob} 680103285Sikob 681103285Sikob#define LAST_DB(dbtr, db) do { \ 682103285Sikob struct fwohcidb_tr *_dbtr = (dbtr); \ 683103285Sikob int _cnt = _dbtr->dbcnt; \ 684103285Sikob db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 685103285Sikob} while (0) 686103285Sikob 687103285Sikobstatic void fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 688103285Sikob{ 689103285Sikob int i, s; 690103285Sikob int tcode, hdr_len, hdr_off, len; 691103285Sikob int fsegment = -1; 692103285Sikob u_int32_t off; 693103285Sikob#if 0 694103285Sikob u_int32_t reg; 695103285Sikob#endif 696103285Sikob struct fw_xfer *xfer; 697103285Sikob struct fw_pkt *fp; 698103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 699103285Sikob struct fwohcidb_tr *db_tr; 700103285Sikob volatile struct fwohcidb *db; 701103285Sikob struct mbuf *m; 702103285Sikob struct tcode_info *info; 703103285Sikob 704103285Sikob if(&sc->atrq == dbch){ 705103285Sikob off = OHCI_ATQOFF; 706103285Sikob }else if(&sc->atrs == dbch){ 707103285Sikob off = OHCI_ATSOFF; 708103285Sikob }else{ 709103285Sikob return; 710103285Sikob } 711103285Sikob 712103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) 713103285Sikob return; 714103285Sikob 715103285Sikob s = splfw(); 716103285Sikob db_tr = dbch->top; 717103285Sikobtxloop: 718103285Sikob xfer = STAILQ_FIRST(&dbch->xferq.q); 719103285Sikob if(xfer == NULL){ 720103285Sikob goto kick; 721103285Sikob } 722103285Sikob if(dbch->xferq.queued == 0 ){ 723103285Sikob device_printf(sc->fc.dev, "TX queue empty\n"); 724103285Sikob } 725103285Sikob STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 726103285Sikob db_tr->xfer = xfer; 727103285Sikob xfer->state = FWXF_START; 728103285Sikob dbch->xferq.packets++; 729103285Sikob 730103285Sikob fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 731103285Sikob tcode = fp->mode.common.tcode; 732103285Sikob 733103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 734103285Sikob#if 0 735103285Sikob switch(tcode){ 736103285Sikob case FWTCODE_STREAM: 737103285Sikob hdr_off = 4; 738103285Sikob hdr_len = 8; 739103285Sikob len = ntohs(fp->mode.stream.len) + 4; 740103285Sikob break; 741103285Sikob case FWTCODE_RREQQ: 742103285Sikob case FWTCODE_WRES: 743103285Sikob hdr_off = 12; 744103285Sikob hdr_len = 12; 745103285Sikob len = 12; 746103285Sikob break; 747103285Sikob case FWTCODE_WREQQ: 748103285Sikob case FWTCODE_RRESQ: 749103285Sikob case FWTCODE_RREQB: 750103285Sikob hdr_off = 16; 751103285Sikob hdr_len = 16; 752103285Sikob len = 16; 753103285Sikob break; 754103285Sikob case FWTCODE_PHY: 755103285Sikob hdr_off = 12; 756103285Sikob hdr_len = 12; 757103285Sikob len = 12; 758103285Sikob break; 759103285Sikob default: 760103285Sikob hdr_off = 16; 761103285Sikob hdr_len = 16; 762103285Sikob /* presume block request len */ 763103285Sikob len = ntohs(fp->mode.rresb.len) + 16; 764103285Sikob break; 765103285Sikob } 766103285Sikob#else 767103285Sikob info = &tinfo[tcode]; 768103285Sikob hdr_len = hdr_off = info->hdr_len; 769103285Sikob /* fw_asyreq must pass valid send.len */ 770103285Sikob len = xfer->send.len; 771103285Sikob#endif 772103285Sikob for( i = 0 ; i < hdr_off ; i+= 4){ 773103285Sikob ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 774103285Sikob } 775103285Sikob ohcifp->mode.common.spd = xfer->spd; 776103285Sikob if (tcode == FWTCODE_STREAM ){ 777103285Sikob hdr_len = 8; 778103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 779103285Sikob } else if (tcode == FWTCODE_PHY) { 780103285Sikob hdr_len = 12; 781103285Sikob ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 782103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 783103285Sikob ohcifp->mode.common.spd = 0; 784103285Sikob ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 785103285Sikob } else { 786103285Sikob ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 787103285Sikob ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 788103285Sikob ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 789103285Sikob } 790103285Sikob db = &db_tr->db[0]; 791103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 792103285Sikob db->db.desc.status = 0; 793103285Sikob/* Specify bound timer of asy. responce */ 794103285Sikob if(&sc->atrs == dbch){ 795103285Sikob db->db.desc.count 796103285Sikob = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 797103285Sikob } 798103285Sikob 799103285Sikob db_tr->dbcnt = 2; 800103285Sikob db = &db_tr->db[db_tr->dbcnt]; 801103285Sikob if(len > hdr_off){ 802103285Sikob if (xfer->mbuf == NULL) { 803103285Sikob db->db.desc.addr 804103285Sikob = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 805103285Sikob db->db.desc.cmd 806103285Sikob = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 807103285Sikob db->db.desc.status = 0; 808103285Sikob 809103285Sikob db_tr->dbcnt++; 810103285Sikob } else { 811103285Sikob /* XXX we assume mbuf chain is shorter than ndesc */ 812103285Sikob m = xfer->mbuf; 813103285Sikob#if 0 814103285Sikob m_adj(m, hdr_off); 815103285Sikob#endif 816103285Sikob do { 817103285Sikob db->db.desc.addr 818103285Sikob = vtophys(mtod(m, caddr_t)); 819103285Sikob db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 820103285Sikob db->db.desc.status = 0; 821103285Sikob db++; 822103285Sikob db_tr->dbcnt++; 823103285Sikob m = m->m_next; 824103285Sikob } while (m != NULL); 825103285Sikob } 826103285Sikob } 827103285Sikob /* last db */ 828103285Sikob LAST_DB(db_tr, db); 829103285Sikob db->db.desc.cmd |= OHCI_OUTPUT_LAST 830103285Sikob | OHCI_INTERRUPT_ALWAYS 831103285Sikob | OHCI_BRANCH_ALWAYS; 832103285Sikob db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 833103285Sikob 834103285Sikob if(fsegment == -1 ) 835103285Sikob fsegment = db_tr->dbcnt; 836103285Sikob if (dbch->pdb_tr != NULL) { 837103285Sikob LAST_DB(dbch->pdb_tr, db); 838103285Sikob db->db.desc.depend |= db_tr->dbcnt; 839103285Sikob } 840103285Sikob dbch->pdb_tr = db_tr; 841103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 842103285Sikob if(db_tr != dbch->bottom){ 843103285Sikob goto txloop; 844103285Sikob } else { 845103285Sikob printf("fwohci_start: lack of db_trq\n"); 846103285Sikob dbch->flags |= FWOHCI_DBCH_FULL; 847103285Sikob } 848103285Sikobkick: 849103285Sikob if (firewire_debug) printf("kick\n"); 850103285Sikob /* kick asy q */ 851103285Sikob#if 0 852103285Sikob if(!(OREAD(sc, OHCI_DMACTL(off)) & OHCI_CNTL_DMA_ACTIVE) 853103285Sikob && fsegment != -1){ 854103285Sikob if (OREAD(sc, OHCI_DMACTL(off)) & OHCI_CNTL_DMA_RUN) { 855103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 856103285Sikob } else if (dbch->top != db_tr) { 857103285Sikob /* db_tr contains next unfilled db */ 858103285Sikob#if 0 859103285Sikob printf("start DMA\n"); 860103285Sikob print_db(dbch->top->db, 0, 2); 861103285Sikob#endif 862103285Sikob OWRITE(sc, OHCI_DMACMD(off), 863103285Sikob vtophys(dbch->top->db) | fsegment); 864103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 865103285Sikob } else 866103285Sikob printf("fwohci_start: nothing to kick\n"); 867103285Sikob } 868103285Sikob#else 869103285Sikob 870103285Sikob#if 1 871103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) { 872103285Sikob#else 873103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 874103285Sikob if ((reg & OHCI_CNTL_DMA_RUN) && !(reg & OHCI_CNTL_DMA_DEAD)) { 875103285Sikob#endif 876103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 877103285Sikob } else { 878103285Sikob printf("start AT DMA status=%x\n", 879103285Sikob OREAD(sc, OHCI_DMACTL(off))); 880103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 881103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 882103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 883103285Sikob } 884103285Sikob#endif 885103285Sikob dbch->top = db_tr; 886103285Sikob splx(s); 887103285Sikob return; 888103285Sikob} 889103285Sikobstatic void fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 890103285Sikob{ 891103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 892103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 893103285Sikob return; 894103285Sikob} 895103285Sikobstatic void fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 896103285Sikob{ 897103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 898103285Sikob fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 899103285Sikob return; 900103285Sikob} 901103285Sikobstatic void fwohci_start_atq(struct firewire_comm *fc) 902103285Sikob{ 903103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 904103285Sikob fwohci_start( sc, &(sc->atrq)); 905103285Sikob return; 906103285Sikob} 907103285Sikobstatic void fwohci_start_ats(struct firewire_comm *fc) 908103285Sikob{ 909103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 910103285Sikob fwohci_start( sc, &(sc->atrs)); 911103285Sikob return; 912103285Sikob} 913103285Sikobvoid fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 914103285Sikob{ 915103285Sikob int s, err = 0; 916103285Sikob struct fwohcidb_tr *tr; 917103285Sikob volatile struct fwohcidb *db; 918103285Sikob struct fw_xfer *xfer; 919103285Sikob u_int32_t off; 920103285Sikob u_int stat; 921103285Sikob int packets; 922103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 923103285Sikob if(&sc->atrq == dbch){ 924103285Sikob off = OHCI_ATQOFF; 925103285Sikob }else if(&sc->atrs == dbch){ 926103285Sikob off = OHCI_ATSOFF; 927103285Sikob }else{ 928103285Sikob return; 929103285Sikob } 930103285Sikob s = splfw(); 931103285Sikob tr = dbch->bottom; 932103285Sikob packets = 0; 933103285Sikob while(dbch->xferq.queued > 0){ 934103285Sikob#if 0 935103285Sikob cmd = 0xfffffff0 & OREAD(sc, OHCI_DMACMD(off)); 936103285Sikob#endif 937103285Sikob LAST_DB(tr, db); 938103285Sikob if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 939103285Sikob if (fc->status != FWBUSRESET) 940103285Sikob /* maybe out of order?? */ 941103285Sikob goto out; 942103285Sikob } 943103285Sikob#if 0 944103285Sikob if(OREAD(sc, OHCI_DMACTL(off)) & OHCI_CNTL_DMA_DEAD ){ 945103285Sikob#else 946103285Sikob if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 947103285Sikob#endif 948103285Sikob#ifdef OHCI_DEBUG 949103285Sikob dump_dma(sc, ch); 950103285Sikob dump_db(sc, ch); 951103285Sikob#endif 952103285Sikob/* Stop DMA */ 953103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 954103285Sikob device_printf(sc->fc.dev, "force reset AT FIFO\n"); 955103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 956103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 957103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 958103285Sikob } 959103285Sikob stat = db->db.desc.status & FWOHCIEV_MASK; 960103285Sikob switch(stat){ 961103285Sikob case FWOHCIEV_ACKCOMPL: 962103285Sikob case FWOHCIEV_ACKPEND: 963103285Sikob err = 0; 964103285Sikob break; 965103285Sikob case FWOHCIEV_ACKBSA: 966103285Sikob case FWOHCIEV_ACKBSB: 967103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 968103285Sikob case FWOHCIEV_ACKBSX: 969103285Sikob err = EBUSY; 970103285Sikob break; 971103285Sikob case FWOHCIEV_FLUSHED: 972103285Sikob case FWOHCIEV_ACKTARD: 973103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 974103285Sikob err = EAGAIN; 975103285Sikob break; 976103285Sikob case FWOHCIEV_MISSACK: 977103285Sikob case FWOHCIEV_UNDRRUN: 978103285Sikob case FWOHCIEV_OVRRUN: 979103285Sikob case FWOHCIEV_DESCERR: 980103285Sikob case FWOHCIEV_DTRDERR: 981103285Sikob case FWOHCIEV_TIMEOUT: 982103285Sikob case FWOHCIEV_TCODERR: 983103285Sikob case FWOHCIEV_UNKNOWN: 984103285Sikob case FWOHCIEV_ACKDERR: 985103285Sikob case FWOHCIEV_ACKTERR: 986103285Sikob default: 987103285Sikob device_printf(sc->fc.dev, "txd err=%2x %s\n", 988103285Sikob stat, fwohcicode[stat]); 989103285Sikob err = EINVAL; 990103285Sikob break; 991103285Sikob } 992103285Sikob if(tr->xfer != NULL){ 993103285Sikob xfer = tr->xfer; 994103285Sikob xfer->state = FWXF_SENT; 995103285Sikob if(err == EBUSY && fc->status != FWBUSRESET){ 996103285Sikob xfer->state = FWXF_BUSY; 997103285Sikob switch(xfer->act_type){ 998103285Sikob case FWACT_XFER: 999103285Sikob xfer->resp = err; 1000103285Sikob if(xfer->retry_req != NULL){ 1001103285Sikob xfer->retry_req(xfer); 1002103285Sikob } 1003103285Sikob break; 1004103285Sikob default: 1005103285Sikob break; 1006103285Sikob } 1007103285Sikob } else if( stat != FWOHCIEV_ACKPEND){ 1008103285Sikob if (stat != FWOHCIEV_ACKCOMPL) 1009103285Sikob xfer->state = FWXF_SENTERR; 1010103285Sikob xfer->resp = err; 1011103285Sikob switch(xfer->act_type){ 1012103285Sikob case FWACT_XFER: 1013103285Sikob fw_xfer_done(xfer); 1014103285Sikob break; 1015103285Sikob default: 1016103285Sikob break; 1017103285Sikob } 1018103285Sikob } 1019103285Sikob dbch->xferq.queued --; 1020103285Sikob#if 0 1021103285Sikob } else { 1022103285Sikob /* already drained after timeout or getting response? */ 1023103285Sikob printf("fwohci_txd: no xfer stat=%d\n", stat); 1024103285Sikob#endif 1025103285Sikob } 1026103285Sikob tr->xfer = NULL; 1027103285Sikob 1028103285Sikob packets ++; 1029103285Sikob tr = STAILQ_NEXT(tr, link); 1030103285Sikob dbch->bottom = tr; 1031103285Sikob } 1032103285Sikobout: 1033103285Sikob#if 0 1034103285Sikob if (packets < 1) 1035103285Sikob printf("fwohci_txd: no packets..out of order execution??\n"); 1036103285Sikob#endif 1037103285Sikob if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1038103285Sikob printf("make free slot\n"); 1039103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1040103285Sikob fwohci_start(sc, dbch); 1041103285Sikob } 1042103285Sikob splx(s); 1043103285Sikob} 1044103285Sikobstatic void fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1045103285Sikob{ 1046103285Sikob int i, s; 1047103285Sikob struct fwohcidb_tr *tr; 1048103285Sikob 1049103285Sikob if(xfer->state != FWXF_START) return; 1050103285Sikob 1051103285Sikob s = splfw(); 1052103285Sikob tr = dbch->bottom; 1053103285Sikob for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1054103285Sikob if(tr->xfer == xfer){ 1055103285Sikob s = splfw(); 1056103285Sikob tr->xfer = NULL; 1057103285Sikob dbch->xferq.queued --; 1058103285Sikob#if 1 1059103285Sikob /* XXX */ 1060103285Sikob if (tr == dbch->bottom) 1061103285Sikob dbch->bottom = STAILQ_NEXT(tr, link); 1062103285Sikob#endif 1063103285Sikob if (dbch->flags & FWOHCI_DBCH_FULL) { 1064103285Sikob printf("fwohci_drain: make slot\n"); 1065103285Sikob dbch->flags &= ~FWOHCI_DBCH_FULL; 1066103285Sikob fwohci_start((struct fwohci_softc *)fc, dbch); 1067103285Sikob } 1068103285Sikob 1069103285Sikob splx(s); 1070103285Sikob break; 1071103285Sikob } 1072103285Sikob tr = STAILQ_NEXT(tr, link); 1073103285Sikob } 1074103285Sikob splx(s); 1075103285Sikob return; 1076103285Sikob} 1077103285Sikob 1078103285Sikobstatic void fwohci_db_free(struct fwohci_dbch *dbch) 1079103285Sikob{ 1080103285Sikob struct fwohcidb_tr *db_tr; 1081103285Sikob int idb; 1082103285Sikob 1083103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1084103285Sikob for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1085103285Sikob idb < dbch->ndb; 1086103285Sikob db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1087103285Sikob free(db_tr->buf, M_DEVBUF); 1088103285Sikob db_tr->buf = NULL; 1089103285Sikob } 1090103285Sikob } 1091103285Sikob dbch->ndb = 0; 1092103285Sikob db_tr = STAILQ_FIRST(&dbch->db_trq); 1093103285Sikob contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1094103285Sikob sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1095103285Sikob /* Attach DB to DMA ch. */ 1096103285Sikob free(db_tr, M_DEVBUF); 1097103285Sikob STAILQ_INIT(&dbch->db_trq); 1098103285Sikob} 1099103285Sikobstatic void fwohci_db_init(struct fwohci_dbch *dbch) 1100103285Sikob{ 1101103285Sikob int idb; 1102103285Sikob struct fwohcidb *db; 1103103285Sikob struct fwohcidb_tr *db_tr; 1104103285Sikob /* allocate DB entries and attach one to each DMA channels */ 1105103285Sikob /* DB entry must start at 16 bytes bounary. */ 1106103285Sikob dbch->frag.buf = NULL; 1107103285Sikob dbch->frag.len = 0; 1108103285Sikob dbch->frag.plen = 0; 1109103285Sikob dbch->xferq.queued = 0; 1110103285Sikob dbch->pdb_tr = NULL; 1111103285Sikob 1112103285Sikob STAILQ_INIT(&dbch->db_trq); 1113103285Sikob db_tr = (struct fwohcidb_tr *) 1114103285Sikob malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1115103285Sikob M_DEVBUF, M_DONTWAIT); 1116103285Sikob if(db_tr == NULL){ 1117103285Sikob return; 1118103285Sikob } 1119103285Sikob db = (struct fwohcidb *) 1120103285Sikob contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1121103285Sikob M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1122103285Sikob if(db == NULL){ 1123103285Sikob printf("fwochi_db_init: contigmalloc failed\n"); 1124103285Sikob return; 1125103285Sikob } 1126103285Sikob bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1127103285Sikob /* Attach DB to DMA ch. */ 1128103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb++){ 1129103285Sikob db_tr->dbcnt = 0; 1130103285Sikob db_tr->db = &db[idb * dbch->ndesc]; 1131103285Sikob STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1132103285Sikob if(!(dbch->xferq.flag & FWXFERQ_PACKET) && 1133103285Sikob (idb % dbch->xferq.bnpacket == 0)){ 1134103285Sikob dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].start 1135103285Sikob = (caddr_t)db_tr; 1136103285Sikob } 1137103285Sikob if((!(dbch->xferq.flag & FWXFERQ_PACKET)) && 1138103285Sikob ((idb + 1)% dbch->xferq.bnpacket == 0)){ 1139103285Sikob dbch->xferq.bulkxfer[idb/dbch->xferq.bnpacket].end 1140103285Sikob = (caddr_t)db_tr; 1141103285Sikob } 1142103285Sikob db_tr++; 1143103285Sikob } 1144103285Sikob STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1145103285Sikob = STAILQ_FIRST(&dbch->db_trq); 1146103285Sikob dbch->top = STAILQ_FIRST(&dbch->db_trq); 1147103285Sikob dbch->bottom = dbch->top; 1148103285Sikob} 1149103285Sikobstatic int fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1150103285Sikob{ 1151103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1152103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1153103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1154103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1155103285Sikob fwohci_db_free(&sc->it[dmach]); 1156103285Sikob sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1157103285Sikob return 0; 1158103285Sikob} 1159103285Sikobstatic int fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1160103285Sikob{ 1161103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1162103285Sikob 1163103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1164103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1165103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1166103285Sikob if(sc->ir[dmach].dummy != NULL){ 1167103285Sikob free(sc->ir[dmach].dummy, M_DEVBUF); 1168103285Sikob } 1169103285Sikob sc->ir[dmach].dummy = NULL; 1170103285Sikob fwohci_db_free(&sc->ir[dmach]); 1171103285Sikob sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1172103285Sikob return 0; 1173103285Sikob} 1174103285Sikobstatic void fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1175103285Sikob{ 1176103285Sikob qld[0] = ntohl(qld[0]); 1177103285Sikob return; 1178103285Sikob} 1179103285Sikobstatic int fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1180103285Sikob{ 1181103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1182103285Sikob int err = 0; 1183103285Sikob unsigned short tag, ich; 1184103285Sikob 1185103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1186103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1187103285Sikob 1188103285Sikob#if 0 1189103285Sikob if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1190103285Sikob wakeup(fc->ir[dmach]); 1191103285Sikob return err; 1192103285Sikob } 1193103285Sikob#endif 1194103285Sikob 1195103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1196103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1197103285Sikob sc->ir[dmach].xferq.queued = 0; 1198103285Sikob sc->ir[dmach].ndb = NDB; 1199103285Sikob sc->ir[dmach].xferq.psize = FWPMAX_S400; 1200103285Sikob sc->ir[dmach].ndesc = 1; 1201103285Sikob fwohci_db_init(&sc->ir[dmach]); 1202103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1203103285Sikob } 1204103285Sikob if(err){ 1205103285Sikob device_printf(sc->fc.dev, "err in IRX setting\n"); 1206103285Sikob return err; 1207103285Sikob } 1208103285Sikob if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1209103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1210103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1211103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1212103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1213103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1214103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1215103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1216103285Sikob vtophys(sc->ir[dmach].top->db) | 1); 1217103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1218103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1219103285Sikob } 1220103285Sikob return err; 1221103285Sikob} 1222103285Sikobstatic int fwohci_tx_enable(struct fwohci_softc *sc, 1223103285Sikob struct fwohci_dbch *dbch) 1224103285Sikob{ 1225103285Sikob int err = 0; 1226103285Sikob int idb, z, i, dmach = 0; 1227103285Sikob u_int32_t off = NULL; 1228103285Sikob struct fwohcidb_tr *db_tr; 1229103285Sikob 1230103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1231103285Sikob err = EINVAL; 1232103285Sikob return err; 1233103285Sikob } 1234103285Sikob z = dbch->ndesc; 1235103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1236103285Sikob if( &sc->it[dmach] == dbch){ 1237103285Sikob off = OHCI_ITOFF(dmach); 1238103285Sikob break; 1239103285Sikob } 1240103285Sikob } 1241103285Sikob if(off == NULL){ 1242103285Sikob err = EINVAL; 1243103285Sikob return err; 1244103285Sikob } 1245103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1246103285Sikob return err; 1247103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1248103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1249103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1250103285Sikob } 1251103285Sikob db_tr = dbch->top; 1252103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1253103285Sikob fwohci_add_tx_buf(db_tr, 1254103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1255103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb); 1256103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1257103285Sikob break; 1258103285Sikob } 1259103285Sikob db_tr->db[0].db.desc.depend 1260103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1261103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1262103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1263103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1264103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1265103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1266103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1267103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 1268103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1269103285Sikob ~0xf; 1270103285Sikob } 1271103285Sikob } 1272103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1273103285Sikob } 1274103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1275103285Sikob return err; 1276103285Sikob} 1277103285Sikobstatic int fwohci_rx_enable(struct fwohci_softc *sc, 1278103285Sikob struct fwohci_dbch *dbch) 1279103285Sikob{ 1280103285Sikob int err = 0; 1281103285Sikob int idb, z, i, dmach = 0; 1282103285Sikob u_int32_t off = NULL; 1283103285Sikob struct fwohcidb_tr *db_tr; 1284103285Sikob 1285103285Sikob z = dbch->ndesc; 1286103285Sikob if(&sc->arrq == dbch){ 1287103285Sikob off = OHCI_ARQOFF; 1288103285Sikob }else if(&sc->arrs == dbch){ 1289103285Sikob off = OHCI_ARSOFF; 1290103285Sikob }else{ 1291103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1292103285Sikob if( &sc->ir[dmach] == dbch){ 1293103285Sikob off = OHCI_IROFF(dmach); 1294103285Sikob break; 1295103285Sikob } 1296103285Sikob } 1297103285Sikob } 1298103285Sikob if(off == NULL){ 1299103285Sikob err = EINVAL; 1300103285Sikob return err; 1301103285Sikob } 1302103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1303103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING) 1304103285Sikob return err; 1305103285Sikob }else{ 1306103285Sikob if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1307103285Sikob err = EBUSY; 1308103285Sikob return err; 1309103285Sikob } 1310103285Sikob } 1311103285Sikob dbch->xferq.flag |= FWXFERQ_RUNNING; 1312103285Sikob for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1313103285Sikob dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1314103285Sikob } 1315103285Sikob db_tr = dbch->top; 1316103285Sikob for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1317103285Sikob if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1318103285Sikob fwohci_add_rx_buf(db_tr, 1319103285Sikob dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1320103285Sikob }else{ 1321103285Sikob fwohci_add_rx_buf(db_tr, 1322103285Sikob dbch->xferq.psize, dbch->xferq.flag, 1323103285Sikob dbch->xferq.buf + dbch->xferq.psize * idb, 1324103285Sikob dbch->dummy + sizeof(u_int32_t) * idb); 1325103285Sikob } 1326103285Sikob if(STAILQ_NEXT(db_tr, link) == NULL){ 1327103285Sikob break; 1328103285Sikob } 1329103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1330103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1331103285Sikob if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1332103285Sikob if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1333103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1334103285Sikob |= OHCI_INTERRUPT_ALWAYS; 1335103285Sikob db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1336103285Sikob ~0xf; 1337103285Sikob } 1338103285Sikob } 1339103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 1340103285Sikob } 1341103285Sikob dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1342103285Sikob dbch->buf_offset = 0; 1343103285Sikob if(dbch->xferq.flag & FWXFERQ_STREAM){ 1344103285Sikob return err; 1345103285Sikob }else{ 1346103285Sikob OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1347103285Sikob } 1348103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1349103285Sikob return err; 1350103285Sikob} 1351103285Sikobstatic int fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1352103285Sikob{ 1353103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1354103285Sikob int err = 0; 1355103285Sikob unsigned short tag, ich; 1356103285Sikob struct fwohci_dbch *dbch; 1357103285Sikob struct fw_pkt *fp; 1358103285Sikob struct fwohcidb_tr *db_tr; 1359103285Sikob 1360103285Sikob tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1361103285Sikob ich = sc->it[dmach].xferq.flag & 0x3f; 1362103285Sikob dbch = &sc->it[dmach]; 1363103285Sikob if(dbch->ndb == 0){ 1364103285Sikob dbch->xferq.queued = 0; 1365103285Sikob dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1366103285Sikob dbch->ndesc = 3; 1367103285Sikob fwohci_db_init(dbch); 1368103285Sikob err = fwohci_tx_enable(sc, dbch); 1369103285Sikob } 1370103285Sikob if(err) 1371103285Sikob return err; 1372103285Sikob if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1373103285Sikob if(dbch->xferq.stdma2 != NULL){ 1374103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1375103285Sikob ((struct fwohcidb_tr *) 1376103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1377103285Sikob |= OHCI_BRANCH_ALWAYS; 1378103285Sikob ((struct fwohcidb_tr *) 1379103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1380103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1381103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1382103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1383103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1384103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1385103285Sikob } 1386103285Sikob }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1387103285Sikob fw_tbuf_update(&sc->fc, dmach, 0); 1388103285Sikob if(dbch->xferq.stdma == NULL){ 1389103285Sikob return err; 1390103285Sikob } 1391103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1392103285Sikob OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1393103285Sikob OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1394103285Sikob OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1395103285Sikob OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1396103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1397103285Sikob if(dbch->xferq.stdma2 != NULL){ 1398103285Sikob fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1399103285Sikob ((struct fwohcidb_tr *) 1400103285Sikob (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1401103285Sikob |= OHCI_BRANCH_ALWAYS; 1402103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1403103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1404103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1405103285Sikob vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1406103285Sikob ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1407103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1408103285Sikob }else{ 1409103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1410103285Sikob ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1411103285Sikob } 1412103285Sikob OWRITE(sc, OHCI_ITCMD(dmach), 1413103285Sikob vtophys(((struct fwohcidb_tr *) 1414103285Sikob (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1415103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 1416103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1417103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1418103285Sikob fp->mode.ld[2] = htonl(0x80000000 + 1419103285Sikob ((fc->cyctimer(fc) + 0x3000) & 0xf000)); 1420103285Sikob } 1421103285Sikob 1422103285Sikob OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1423103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1424103285Sikob } 1425103285Sikob return err; 1426103285Sikob} 1427103285Sikobstatic int fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1428103285Sikob{ 1429103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1430103285Sikob int err = 0; 1431103285Sikob unsigned short tag, ich; 1432103285Sikob tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1433103285Sikob ich = sc->ir[dmach].xferq.flag & 0x3f; 1434103285Sikob OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1435103285Sikob 1436103285Sikob if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1437103285Sikob sc->ir[dmach].xferq.queued = 0; 1438103285Sikob sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1439103285Sikob sc->ir[dmach].xferq.bnchunk; 1440103285Sikob sc->ir[dmach].dummy = 1441103285Sikob malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1442103285Sikob M_DEVBUF, M_DONTWAIT); 1443103285Sikob if(sc->ir[dmach].dummy == NULL){ 1444103285Sikob err = ENOMEM; 1445103285Sikob return err; 1446103285Sikob } 1447103285Sikob sc->ir[dmach].ndesc = 2; 1448103285Sikob fwohci_db_init(&sc->ir[dmach]); 1449103285Sikob err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1450103285Sikob } 1451103285Sikob if(err) 1452103285Sikob return err; 1453103285Sikob 1454103285Sikob if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1455103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1456103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1457103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1458103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1459103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1460103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1461103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1462103285Sikob } 1463103285Sikob }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1464103285Sikob && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1465103285Sikob fw_rbuf_update(&sc->fc, dmach, 0); 1466103285Sikob 1467103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1468103285Sikob OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1469103285Sikob OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1470103285Sikob OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1471103285Sikob OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1472103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1473103285Sikob if(sc->ir[dmach].xferq.stdma2 != NULL){ 1474103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1475103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1476103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1477103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1478103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1479103285Sikob }else{ 1480103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1481103285Sikob ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1482103285Sikob } 1483103285Sikob OWRITE(sc, OHCI_IRCMD(dmach), 1484103285Sikob vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1485103285Sikob OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1486103285Sikob } 1487103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1488103285Sikob return err; 1489103285Sikob} 1490103285Sikobstatic int fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1491103285Sikob{ 1492103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1493103285Sikob int err = 0; 1494103285Sikob 1495103285Sikob if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1496103285Sikob err = fwohci_irxpp_enable(fc, dmach); 1497103285Sikob return err; 1498103285Sikob }else{ 1499103285Sikob err = fwohci_irxbuf_enable(fc, dmach); 1500103285Sikob return err; 1501103285Sikob } 1502103285Sikob} 1503103285Sikobint fwohci_shutdown(device_t dev) 1504103285Sikob{ 1505103285Sikob u_int i; 1506103285Sikob struct fwohci_softc *sc = device_get_softc(dev); 1507103285Sikob 1508103285Sikob/* Now stopping all DMA channel */ 1509103285Sikob OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1510103285Sikob OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1511103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1512103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1513103285Sikob 1514103285Sikob for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1515103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1516103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1517103285Sikob } 1518103285Sikob 1519103285Sikob/* FLUSH FIFO and reset Transmitter/Reciever */ 1520103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1521103285Sikob 1522103285Sikob/* Stop interrupt */ 1523103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, 1524103285Sikob OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1525103285Sikob | OHCI_INT_PHY_INT 1526103285Sikob | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1527103285Sikob | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1528103285Sikob | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1529103285Sikob | OHCI_INT_PHY_BUS_R); 1530103285Sikob return 0; 1531103285Sikob} 1532103285Sikob 1533103285Sikob#define ACK_ALL 1534103285Sikobstatic void 1535103285Sikobfwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat) 1536103285Sikob{ 1537103285Sikob u_int32_t irstat, itstat; 1538103285Sikob u_int i; 1539103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 1540103285Sikob 1541103285Sikob#define OHCI_DEBUG 1542103285Sikob#undef OHCI_DEBUG 1543103285Sikob#ifdef OHCI_DEBUG 1544103285Sikob if(stat & OREAD(sc, FWOHCI_INTMASK)) 1545103285Sikob device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1546103285Sikob stat & OHCI_INT_EN ? "DMA_EN ":"", 1547103285Sikob stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1548103285Sikob stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1549103285Sikob stat & OHCI_INT_ERR ? "INT_ERR ":"", 1550103285Sikob stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1551103285Sikob stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1552103285Sikob stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1553103285Sikob stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1554103285Sikob stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1555103285Sikob stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1556103285Sikob stat & OHCI_INT_PHY_SID ? "SID ":"", 1557103285Sikob stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1558103285Sikob stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1559103285Sikob stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1560103285Sikob stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1561103285Sikob stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1562103285Sikob stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1563103285Sikob stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1564103285Sikob stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1565103285Sikob stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1566103285Sikob stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1567103285Sikob stat, OREAD(sc, FWOHCI_INTMASK) 1568103285Sikob ); 1569103285Sikob#endif 1570103285Sikob/* Bus reset */ 1571103285Sikob if(stat & OHCI_INT_PHY_BUS_R ){ 1572103285Sikob device_printf(fc->dev, "BUS reset\n"); 1573103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1574103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1575103285Sikob 1576103285Sikob OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1577103285Sikob sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1578103285Sikob OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1579103285Sikob sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1580103285Sikob 1581103285Sikob#if 0 1582103285Sikob for( i = 0 ; i < fc->nisodma ; i ++ ){ 1583103285Sikob OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1584103285Sikob OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1585103285Sikob } 1586103285Sikob 1587103285Sikob#endif 1588103285Sikob fw_busreset(fc); 1589103285Sikob 1590103285Sikob /* XXX need to wait DMA to stop */ 1591103285Sikob#ifndef ACK_ALL 1592103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1593103285Sikob#endif 1594103285Sikob#if 1 1595103285Sikob /* pending all pre-bus_reset packets */ 1596103285Sikob fwohci_txd(sc, &sc->atrq); 1597103285Sikob fwohci_txd(sc, &sc->atrs); 1598103285Sikob fwohci_arcv(sc, &sc->arrs); 1599103285Sikob fwohci_arcv(sc, &sc->arrq); 1600103285Sikob#endif 1601103285Sikob 1602103285Sikob 1603103285Sikob OWRITE(sc, OHCI_AREQHI, 1 << 31); 1604103285Sikob /* XXX insecure ?? */ 1605103285Sikob OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1606103285Sikob OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1607103285Sikob OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1608103285Sikob#if 0 1609103285Sikob OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 1610103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 1611103285Sikob OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 1612103285Sikob#endif 1613103285Sikob 1614103285Sikob } 1615103285Sikob if((stat & OHCI_INT_DMA_IR )){ 1616103285Sikob#ifndef ACK_ALL 1617103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1618103285Sikob#endif 1619103285Sikob#if 0 1620103285Sikob irstat = OREAD(sc, OHCI_IR_STAT) & OREAD(sc, OHCI_IR_MASK); 1621103285Sikob#else 1622103285Sikob irstat = OREAD(sc, OHCI_IR_STAT); 1623103285Sikob#endif 1624103285Sikob OWRITE(sc, OHCI_IR_STATCLR, ~0); 1625103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1626103285Sikob if((irstat & (1 << i)) != 0){ 1627103285Sikob if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1628103285Sikob fwohci_ircv(sc, &sc->ir[i]); 1629103285Sikob }else{ 1630103285Sikob fwohci_rbuf_update(sc, i); 1631103285Sikob } 1632103285Sikob } 1633103285Sikob } 1634103285Sikob } 1635103285Sikob if((stat & OHCI_INT_DMA_IT )){ 1636103285Sikob#ifndef ACK_ALL 1637103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1638103285Sikob#endif 1639103285Sikob#if 0 1640103285Sikob itstat = OREAD(sc, OHCI_IT_STAT) & OREAD(sc, OHCI_IT_MASK); 1641103285Sikob#else 1642103285Sikob itstat = OREAD(sc, OHCI_IT_STAT); 1643103285Sikob#endif 1644103285Sikob OWRITE(sc, OHCI_IT_STATCLR, ~0); 1645103285Sikob for(i = 0; i < fc->nisodma ; i++){ 1646103285Sikob if((itstat & (1 << i)) != 0){ 1647103285Sikob fwohci_tbuf_update(sc, i); 1648103285Sikob } 1649103285Sikob } 1650103285Sikob } 1651103285Sikob if((stat & OHCI_INT_DMA_PRRS )){ 1652103285Sikob#ifndef ACK_ALL 1653103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1654103285Sikob#endif 1655103285Sikob#if 0 1656103285Sikob dump_dma(sc, ARRS_CH); 1657103285Sikob dump_db(sc, ARRS_CH); 1658103285Sikob#endif 1659103285Sikob fwohci_arcv(sc, &sc->arrs); 1660103285Sikob } 1661103285Sikob if((stat & OHCI_INT_DMA_PRRQ )){ 1662103285Sikob#ifndef ACK_ALL 1663103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1664103285Sikob#endif 1665103285Sikob#if 0 1666103285Sikob dump_dma(sc, ARRQ_CH); 1667103285Sikob dump_db(sc, ARRQ_CH); 1668103285Sikob#endif 1669103285Sikob fwohci_arcv(sc, &sc->arrq); 1670103285Sikob } 1671103285Sikob if(stat & OHCI_INT_PHY_SID){ 1672103285Sikob caddr_t buf; 1673103285Sikob int plen; 1674103285Sikob 1675103285Sikob#ifndef ACK_ALL 1676103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1677103285Sikob#endif 1678103285Sikob/* 1679103285Sikob** Checking whether the node is root or not. If root, turn on 1680103285Sikob** cycle master. 1681103285Sikob*/ 1682103285Sikob#if 0 1683103285Sikob OWRITE(sc, FWOHCI_NODEID, (OREAD(sc, FWOHCI_NODEID)) & 0xffff003f); 1684103285Sikob#endif 1685103285Sikob device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1686103285Sikob if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1687103285Sikob printf("Bus reset failure\n"); 1688103285Sikob#if 0 1689103285Sikob fwohci_ibr(sc); 1690103285Sikob#endif 1691103285Sikob goto sidout; 1692103285Sikob } 1693103285Sikob if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1694103285Sikob printf("CYCLEMASTER mode\n"); 1695103285Sikob OWRITE(sc, OHCI_LNKCTL, 1696103285Sikob OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1697103285Sikob }else{ 1698103285Sikob printf("non CYCLEMASTER mode\n"); 1699103285Sikob OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1700103285Sikob OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1701103285Sikob } 1702103285Sikob fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1703103285Sikob 1704103285Sikob plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1705103285Sikob plen -= 4; /* chop control info */ 1706103285Sikob buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1707103285Sikob if(buf == NULL) goto sidout; 1708103285Sikob bcopy((void *)(uintptr_t)(volatile void *)fc->sid_buf, 1709103285Sikob buf, plen); 1710103285Sikob fw_sidrcv(fc, buf, plen, 0); 1711103285Sikob } 1712103285Sikobsidout: 1713103285Sikob if((stat & OHCI_INT_DMA_ATRQ )){ 1714103285Sikob#ifndef ACK_ALL 1715103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1716103285Sikob#endif 1717103285Sikob fwohci_txd(sc, &(sc->atrq)); 1718103285Sikob } 1719103285Sikob if((stat & OHCI_INT_DMA_ATRS )){ 1720103285Sikob#ifndef ACK_ALL 1721103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1722103285Sikob#endif 1723103285Sikob fwohci_txd(sc, &(sc->atrs)); 1724103285Sikob } 1725103285Sikob if((stat & OHCI_INT_PW_ERR )){ 1726103285Sikob#ifndef ACK_ALL 1727103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1728103285Sikob#endif 1729103285Sikob device_printf(fc->dev, "posted write error\n"); 1730103285Sikob } 1731103285Sikob if((stat & OHCI_INT_ERR )){ 1732103285Sikob#ifndef ACK_ALL 1733103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1734103285Sikob#endif 1735103285Sikob device_printf(fc->dev, "unrecoverable error\n"); 1736103285Sikob } 1737103285Sikob if((stat & OHCI_INT_PHY_INT)) { 1738103285Sikob#ifndef ACK_ALL 1739103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1740103285Sikob#endif 1741103285Sikob device_printf(fc->dev, "phy int\n"); 1742103285Sikob } 1743103285Sikob 1744103285Sikob return; 1745103285Sikob} 1746103285Sikob 1747103285Sikobvoid 1748103285Sikobfwohci_intr(void *arg) 1749103285Sikob{ 1750103285Sikob struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1751103285Sikob u_int32_t stat; 1752103285Sikob 1753103285Sikob if (!(sc->intmask & OHCI_INT_EN)) { 1754103285Sikob /* polling mode */ 1755103285Sikob return; 1756103285Sikob } 1757103285Sikob 1758103285Sikob while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1759103285Sikob if (stat == 0xffffffff) { 1760103285Sikob device_printf(sc->fc.dev, 1761103285Sikob "device physically ejected?\n"); 1762103285Sikob return; 1763103285Sikob } 1764103285Sikob#ifdef ACK_ALL 1765103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1766103285Sikob#endif 1767103285Sikob fwohci_intr_body(sc, stat); 1768103285Sikob } 1769103285Sikob} 1770103285Sikob 1771103285Sikobstatic void 1772103285Sikobfwohci_poll(struct firewire_comm *fc, int quick, int count) 1773103285Sikob{ 1774103285Sikob int s; 1775103285Sikob u_int32_t stat; 1776103285Sikob struct fwohci_softc *sc; 1777103285Sikob 1778103285Sikob 1779103285Sikob sc = (struct fwohci_softc *)fc; 1780103285Sikob stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1781103285Sikob OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1782103285Sikob OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1783103285Sikob#if 0 1784103285Sikob if (!quick) { 1785103285Sikob#else 1786103285Sikob if (1) { 1787103285Sikob#endif 1788103285Sikob stat = OREAD(sc, FWOHCI_INTSTAT); 1789103285Sikob if (stat == 0) 1790103285Sikob return; 1791103285Sikob if (stat == 0xffffffff) { 1792103285Sikob device_printf(sc->fc.dev, 1793103285Sikob "device physically ejected?\n"); 1794103285Sikob return; 1795103285Sikob } 1796103285Sikob#ifdef ACK_ALL 1797103285Sikob OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1798103285Sikob#endif 1799103285Sikob } 1800103285Sikob s = splfw(); 1801103285Sikob fwohci_intr_body(sc, stat); 1802103285Sikob splx(s); 1803103285Sikob} 1804103285Sikob 1805103285Sikobstatic void 1806103285Sikobfwohci_set_intr(struct firewire_comm *fc, int enable) 1807103285Sikob{ 1808103285Sikob struct fwohci_softc *sc; 1809103285Sikob 1810103285Sikob sc = (struct fwohci_softc *)fc; 1811103285Sikob printf("fwochi_set_intr: %d\n", enable); 1812103285Sikob if (enable) { 1813103285Sikob sc->intmask |= OHCI_INT_EN; 1814103285Sikob OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1815103285Sikob } else { 1816103285Sikob sc->intmask &= ~OHCI_INT_EN; 1817103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1818103285Sikob } 1819103285Sikob} 1820103285Sikob 1821103285Sikobstatic void fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1822103285Sikob{ 1823103285Sikob int stat; 1824103285Sikob struct firewire_comm *fc = &sc->fc; 1825103285Sikob struct fw_pkt *fp; 1826103285Sikob struct fwohci_dbch *dbch; 1827103285Sikob struct fwohcidb_tr *db_tr; 1828103285Sikob 1829103285Sikob dbch = &sc->it[dmach]; 1830103285Sikob if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1831103285Sikob db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1832103285Sikob/* 1833103285Sikob * Overwrite highest significant 4 bits timestamp information 1834103285Sikob */ 1835103285Sikob fp = (struct fw_pkt *)db_tr->buf; 1836103285Sikob fp->mode.ld[2] |= htonl(0x80000000 | 1837103285Sikob ((fc->cyctimer(fc) + 0x4000) & 0xf000)); 1838103285Sikob } 1839103285Sikob stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1840103285Sikob switch(stat){ 1841103285Sikob case FWOHCIEV_ACKCOMPL: 1842103285Sikob fw_tbuf_update(fc, dmach, 1); 1843103285Sikob break; 1844103285Sikob default: 1845103285Sikob fw_tbuf_update(fc, dmach, 0); 1846103285Sikob break; 1847103285Sikob } 1848103285Sikob fwohci_itxbuf_enable(&sc->fc, dmach); 1849103285Sikob} 1850103285Sikobstatic void fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1851103285Sikob{ 1852103285Sikob int stat; 1853103285Sikob stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1854103285Sikob switch(stat){ 1855103285Sikob case FWOHCIEV_ACKCOMPL: 1856103285Sikob fw_rbuf_update(&sc->fc, dmach, 1); 1857103285Sikob wakeup(sc->fc.ir[dmach]); 1858103285Sikob fwohci_irx_enable(&sc->fc, dmach); 1859103285Sikob break; 1860103285Sikob default: 1861103285Sikob break; 1862103285Sikob } 1863103285Sikob} 1864103285Sikobvoid dump_dma(struct fwohci_softc *sc, u_int32_t ch){ 1865103285Sikob u_int32_t off, cntl, stat, cmd, match; 1866103285Sikob 1867103285Sikob if(ch == 0){ 1868103285Sikob off = OHCI_ATQOFF; 1869103285Sikob }else if(ch == 1){ 1870103285Sikob off = OHCI_ATSOFF; 1871103285Sikob }else if(ch == 2){ 1872103285Sikob off = OHCI_ARQOFF; 1873103285Sikob }else if(ch == 3){ 1874103285Sikob off = OHCI_ARSOFF; 1875103285Sikob }else if(ch < IRX_CH){ 1876103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1877103285Sikob }else{ 1878103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1879103285Sikob } 1880103285Sikob cntl = stat = OREAD(sc, off); 1881103285Sikob cmd = OREAD(sc, off + 0xc); 1882103285Sikob match = OREAD(sc, off + 0x10); 1883103285Sikob 1884103285Sikob device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1885103285Sikob ch, 1886103285Sikob cntl, 1887103285Sikob stat, 1888103285Sikob cmd, 1889103285Sikob match); 1890103285Sikob stat &= 0xffff ; 1891103285Sikob if(stat & 0xff00){ 1892103285Sikob device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 1893103285Sikob ch, 1894103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1895103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1896103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1897103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1898103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1899103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1900103285Sikob fwohcicode[stat & 0x1f], 1901103285Sikob stat & 0x1f 1902103285Sikob ); 1903103285Sikob }else{ 1904103285Sikob device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 1905103285Sikob } 1906103285Sikob} 1907103285Sikobvoid dump_db(struct fwohci_softc *sc, u_int32_t ch){ 1908103285Sikob struct fwohci_dbch *dbch; 1909103285Sikob struct fwohcidb_tr *cp = NULL, *pp, *np; 1910103285Sikob volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 1911103285Sikob int idb, jdb; 1912103285Sikob u_int32_t cmd, off; 1913103285Sikob if(ch == 0){ 1914103285Sikob off = OHCI_ATQOFF; 1915103285Sikob dbch = &sc->atrq; 1916103285Sikob }else if(ch == 1){ 1917103285Sikob off = OHCI_ATSOFF; 1918103285Sikob dbch = &sc->atrs; 1919103285Sikob }else if(ch == 2){ 1920103285Sikob off = OHCI_ARQOFF; 1921103285Sikob dbch = &sc->arrq; 1922103285Sikob }else if(ch == 3){ 1923103285Sikob off = OHCI_ARSOFF; 1924103285Sikob dbch = &sc->arrs; 1925103285Sikob }else if(ch < IRX_CH){ 1926103285Sikob off = OHCI_ITCTL(ch - ITX_CH); 1927103285Sikob dbch = &sc->it[ch - ITX_CH]; 1928103285Sikob }else { 1929103285Sikob off = OHCI_IRCTL(ch - IRX_CH); 1930103285Sikob dbch = &sc->ir[ch - IRX_CH]; 1931103285Sikob } 1932103285Sikob cmd = OREAD(sc, off + 0xc); 1933103285Sikob 1934103285Sikob if( dbch->ndb == 0 ){ 1935103285Sikob device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 1936103285Sikob return; 1937103285Sikob } 1938103285Sikob pp = dbch->top; 1939103285Sikob prev = pp->db; 1940103285Sikob for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 1941103285Sikob if(pp == NULL){ 1942103285Sikob curr = NULL; 1943103285Sikob goto outdb; 1944103285Sikob } 1945103285Sikob cp = STAILQ_NEXT(pp, link); 1946103285Sikob if(cp == NULL){ 1947103285Sikob curr = NULL; 1948103285Sikob goto outdb; 1949103285Sikob } 1950103285Sikob np = STAILQ_NEXT(cp, link); 1951103285Sikob if(cp == NULL) break; 1952103285Sikob for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 1953103285Sikob if((cmd & 0xfffffff0) 1954103285Sikob == vtophys(&(cp->db[jdb]))){ 1955103285Sikob curr = cp->db; 1956103285Sikob if(np != NULL){ 1957103285Sikob next = np->db; 1958103285Sikob }else{ 1959103285Sikob next = NULL; 1960103285Sikob } 1961103285Sikob goto outdb; 1962103285Sikob } 1963103285Sikob } 1964103285Sikob pp = STAILQ_NEXT(pp, link); 1965103285Sikob prev = pp->db; 1966103285Sikob } 1967103285Sikoboutdb: 1968103285Sikob if( curr != NULL){ 1969103285Sikob printf("Prev DB %d\n", ch); 1970103285Sikob print_db(prev, ch, dbch->ndesc); 1971103285Sikob printf("Current DB %d\n", ch); 1972103285Sikob print_db(curr, ch, dbch->ndesc); 1973103285Sikob printf("Next DB %d\n", ch); 1974103285Sikob print_db(next, ch, dbch->ndesc); 1975103285Sikob }else{ 1976103285Sikob printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 1977103285Sikob } 1978103285Sikob return; 1979103285Sikob} 1980103285Sikobvoid print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max){ 1981103285Sikob fwohcireg_t stat; 1982103285Sikob int i, key; 1983103285Sikob 1984103285Sikob if(db == NULL){ 1985103285Sikob printf("No Descriptor is found\n"); 1986103285Sikob return; 1987103285Sikob } 1988103285Sikob 1989103285Sikob printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 1990103285Sikob ch, 1991103285Sikob "Current", 1992103285Sikob "OP ", 1993103285Sikob "KEY", 1994103285Sikob "INT", 1995103285Sikob "BR ", 1996103285Sikob "len", 1997103285Sikob "Addr", 1998103285Sikob "Depend", 1999103285Sikob "Stat", 2000103285Sikob "Cnt"); 2001103285Sikob for( i = 0 ; i <= max ; i ++){ 2002103285Sikob key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2003103285Sikob printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", 2004103285Sikob vtophys(&db[i]), 2005103285Sikob dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2006103285Sikob dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2007103285Sikob dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2008103285Sikob dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2009103285Sikob db[i].db.desc.cmd & 0xffff, 2010103285Sikob db[i].db.desc.addr, 2011103285Sikob db[i].db.desc.depend, 2012103285Sikob db[i].db.desc.status, 2013103285Sikob db[i].db.desc.count); 2014103285Sikob stat = db[i].db.desc.status; 2015103285Sikob if(stat & 0xff00){ 2016103285Sikob printf(" %s%s%s%s%s%s %s(%x)\n", 2017103285Sikob stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2018103285Sikob stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2019103285Sikob stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2020103285Sikob stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2021103285Sikob stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2022103285Sikob stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2023103285Sikob fwohcicode[stat & 0x1f], 2024103285Sikob stat & 0x1f 2025103285Sikob ); 2026103285Sikob }else{ 2027103285Sikob printf(" Nostat\n"); 2028103285Sikob } 2029103285Sikob if(key == OHCI_KEY_ST2 ){ 2030103285Sikob printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2031103285Sikob db[i+1].db.immed[0], 2032103285Sikob db[i+1].db.immed[1], 2033103285Sikob db[i+1].db.immed[2], 2034103285Sikob db[i+1].db.immed[3]); 2035103285Sikob } 2036103285Sikob if(key == OHCI_KEY_DEVICE){ 2037103285Sikob return; 2038103285Sikob } 2039103285Sikob if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2040103285Sikob == OHCI_BRANCH_ALWAYS){ 2041103285Sikob return; 2042103285Sikob } 2043103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2044103285Sikob == OHCI_OUTPUT_LAST){ 2045103285Sikob return; 2046103285Sikob } 2047103285Sikob if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2048103285Sikob == OHCI_INPUT_LAST){ 2049103285Sikob return; 2050103285Sikob } 2051103285Sikob if(key == OHCI_KEY_ST2 ){ 2052103285Sikob i++; 2053103285Sikob } 2054103285Sikob } 2055103285Sikob return; 2056103285Sikob} 2057103285Sikobvoid fwohci_ibr(struct firewire_comm *fc) 2058103285Sikob{ 2059103285Sikob struct fwohci_softc *sc; 2060103285Sikob u_int32_t fun; 2061103285Sikob 2062103285Sikob sc = (struct fwohci_softc *)fc; 2063103285Sikob#if 1 2064103285Sikob fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2065103285Sikob fun |= FW_PHY_IBR; 2066103285Sikob fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2067103285Sikob#else 2068103285Sikob fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2069103285Sikob fun |= FW_PHY_ISBR; 2070103285Sikob fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2071103285Sikob#endif 2072103285Sikob} 2073103285Sikobvoid fwohci_txbufdb(struct fwohci_softc *sc, int dmach, 2074103285Sikob struct fw_bulkxfer *bulkxfer) 2075103285Sikob{ 2076103285Sikob struct fwohcidb_tr *db_tr, *fdb_tr; 2077103285Sikob struct fwohci_dbch *dbch; 2078103285Sikob struct fw_pkt *fp; 2079103285Sikob volatile struct fwohci_txpkthdr *ohcifp; 2080103285Sikob unsigned short chtag; 2081103285Sikob int idb; 2082103285Sikob 2083103285Sikob dbch = &sc->it[dmach]; 2084103285Sikob chtag = sc->it[dmach].xferq.flag & 0xff; 2085103285Sikob 2086103285Sikob db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2087103285Sikob fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2088103285Sikob/* 2089103285Sikobdevice_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2090103285Sikob*/ 2091103285Sikob if(bulkxfer->flag != 0){ 2092103285Sikob return; 2093103285Sikob } 2094103285Sikob bulkxfer->flag = 1; 2095103285Sikob for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2096103285Sikob db_tr->db[0].db.desc.cmd 2097103285Sikob = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2098103285Sikob fp = (struct fw_pkt *)db_tr->buf; 2099103285Sikob ohcifp = (volatile struct fwohci_txpkthdr *) 2100103285Sikob db_tr->db[1].db.immed; 2101103285Sikob ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2102103285Sikob ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2103103285Sikob ohcifp->mode.stream.chtag = chtag; 2104103285Sikob ohcifp->mode.stream.tcode = 0xa; 2105103285Sikob ohcifp->mode.stream.spd = 4; 2106103285Sikob ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2107103285Sikob ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2108103285Sikob 2109103285Sikob db_tr->db[2].db.desc.cmd 2110103285Sikob = OHCI_OUTPUT_LAST 2111103285Sikob | OHCI_UPDATE 2112103285Sikob | OHCI_BRANCH_ALWAYS 2113103285Sikob | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2114103285Sikob db_tr->db[2].db.desc.status = 0; 2115103285Sikob db_tr->db[2].db.desc.count = 0; 2116103285Sikob if(dbch->xferq.flag & FWXFERQ_DV){ 2117103285Sikob db_tr->db[0].db.desc.depend 2118103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2119103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2120103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2121103285Sikob }else{ 2122103285Sikob db_tr->db[0].db.desc.depend 2123103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2124103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend 2125103285Sikob = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2126103285Sikob } 2127103285Sikob bulkxfer->end = (caddr_t)db_tr; 2128103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2129103285Sikob } 2130103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2131103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2132103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2133103285Sikob/**/ 2134103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2135103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2136103285Sikob/**/ 2137103285Sikob db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2138103285Sikob 2139103285Sikob db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2140103285Sikob fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2141103285Sikob/* 2142103285Sikobdevice_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2143103285Sikob*/ 2144103285Sikob return; 2145103285Sikob} 2146103285Sikobstatic int fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, void *buf) 2147103285Sikob{ 2148103285Sikob volatile struct fwohcidb *db = db_tr->db; 2149103285Sikob int err = 0; 2150103285Sikob if(buf == 0){ 2151103285Sikob err = EINVAL; 2152103285Sikob return err; 2153103285Sikob } 2154103285Sikob db_tr->buf = buf; 2155103285Sikob db_tr->dbcnt = 3; 2156103285Sikob db_tr->dummy = NULL; 2157103285Sikob 2158103285Sikob db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2159103285Sikob 2160103285Sikob db[2].db.desc.depend = 0; 2161103285Sikob db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2162103285Sikob db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2163103285Sikob 2164103285Sikob db[0].db.desc.status = 0; 2165103285Sikob db[0].db.desc.count = 0; 2166103285Sikob 2167103285Sikob db[2].db.desc.status = 0; 2168103285Sikob db[2].db.desc.count = 0; 2169103285Sikob if( mode & FWXFERQ_STREAM ){ 2170103285Sikob db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2171103285Sikob if(mode & FWXFERQ_PACKET ){ 2172103285Sikob db[2].db.desc.cmd 2173103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2174103285Sikob } 2175103285Sikob } 2176103285Sikob db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2177103285Sikob return 1; 2178103285Sikob} 2179103285Sikobint fwohci_add_rx_buf(db_tr, size, mode, buf, dummy) 2180103285Sikobstruct fwohcidb_tr *db_tr; 2181103285Sikobunsigned short size; 2182103285Sikobint mode; 2183103285Sikobvoid *buf, *dummy; 2184103285Sikob{ 2185103285Sikob volatile struct fwohcidb *db = db_tr->db; 2186103285Sikob int i; 2187103285Sikob void *dbuf[2]; 2188103285Sikob int dsiz[2]; 2189103285Sikob 2190103285Sikob if(buf == 0){ 2191103285Sikob buf = malloc(size, M_DEVBUF, M_NOWAIT); 2192103285Sikob if(buf == NULL) return 0; 2193103285Sikob db_tr->buf = buf; 2194103285Sikob db_tr->dbcnt = 1; 2195103285Sikob db_tr->dummy = NULL; 2196103285Sikob dsiz[0] = size; 2197103285Sikob dbuf[0] = buf; 2198103285Sikob }else if(dummy == NULL){ 2199103285Sikob db_tr->buf = buf; 2200103285Sikob db_tr->dbcnt = 1; 2201103285Sikob db_tr->dummy = NULL; 2202103285Sikob dsiz[0] = size; 2203103285Sikob dbuf[0] = buf; 2204103285Sikob }else{ 2205103285Sikob db_tr->buf = buf; 2206103285Sikob db_tr->dbcnt = 2; 2207103285Sikob db_tr->dummy = dummy; 2208103285Sikob dsiz[0] = sizeof(u_int32_t); 2209103285Sikob dsiz[1] = size; 2210103285Sikob dbuf[0] = dummy; 2211103285Sikob dbuf[1] = buf; 2212103285Sikob } 2213103285Sikob for(i = 0 ; i < db_tr->dbcnt ; i++){ 2214103285Sikob#if 0 2215103285Sikob db[i].db.desc.depend = 0; 2216103285Sikob#endif 2217103285Sikob db[i].db.desc.addr = vtophys(dbuf[i]) ; 2218103285Sikob db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2219103285Sikob if( mode & FWXFERQ_STREAM ){ 2220103285Sikob db[i].db.desc.cmd |= OHCI_UPDATE; 2221103285Sikob } 2222103285Sikob db[i].db.desc.status = 0; 2223103285Sikob db[i].db.desc.count = dsiz[i]; 2224103285Sikob } 2225103285Sikob if( mode & FWXFERQ_STREAM ){ 2226103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2227103285Sikob if(mode & FWXFERQ_PACKET ){ 2228103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd 2229103285Sikob |= OHCI_INTERRUPT_ALWAYS; 2230103285Sikob } 2231103285Sikob } 2232103285Sikob db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2233103285Sikob return 1; 2234103285Sikob} 2235103285Sikob#if 0 2236103285Sikob/* BUS parameter initialization after BUS reset */ 2237103285Sikobvoid fwohci_busreset(sc) 2238103285Sikobstruct fwohci_softc *sc; 2239103285Sikob{ 2240103285Sikob} 2241103285Sikob#endif 2242103285Sikobstatic void fwohci_ircv(sc, dbch) 2243103285Sikobstruct fwohci_softc *sc; 2244103285Sikobstruct fwohci_dbch *dbch; 2245103285Sikob{ 2246103285Sikob struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2247103285Sikob struct firewire_comm *fc = (struct firewire_comm *)sc; 2248103285Sikob int z = 1; 2249103285Sikob struct fw_pkt *fp; 2250103285Sikob u_int8_t *ld; 2251103285Sikob u_int32_t off = NULL; 2252103285Sikob u_int32_t stat; 2253103285Sikob u_int32_t *qld; 2254103285Sikob u_int32_t reg; 2255103285Sikob u_int spd; 2256103285Sikob u_int dmach; 2257103285Sikob int len, i, plen; 2258103285Sikob caddr_t buf; 2259103285Sikob 2260103285Sikob for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2261103285Sikob if( &sc->ir[dmach] == dbch){ 2262103285Sikob off = OHCI_IROFF(dmach); 2263103285Sikob break; 2264103285Sikob } 2265103285Sikob } 2266103285Sikob if(off == NULL){ 2267103285Sikob return; 2268103285Sikob } 2269103285Sikob if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2270103285Sikob fwohci_irx_disable(&sc->fc, dmach); 2271103285Sikob return; 2272103285Sikob } 2273103285Sikob 2274103285Sikob odb_tr = NULL; 2275103285Sikob db_tr = dbch->top; 2276103285Sikob i = 0; 2277103285Sikob while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2278103285Sikob ld = (u_int8_t *)db_tr->buf; 2279103285Sikob if (dbch->xferq.flag & FWXFERQ_PACKET) { 2280103285Sikob /* skip timeStamp */ 2281103285Sikob ld += sizeof(struct fwohci_trailer); 2282103285Sikob } 2283103285Sikob qld = (u_int32_t *)ld; 2284103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2285103285Sikob/* 2286103285Sikob{ 2287103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2288103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2289103285Sikob} 2290103285Sikob*/ 2291103285Sikob#if 0 2292103285Sikob fp=(struct fw_pkt *)(ld + sizeof(struct fwohci_trailer)); 2293103285Sikob#else 2294103285Sikob fp=(struct fw_pkt *)ld; 2295103285Sikob#endif 2296103285Sikob qld[0] = htonl(qld[0]); 2297103285Sikob plen = sizeof(struct fw_isohdr) 2298103285Sikob + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2299103285Sikob ld += plen; 2300103285Sikob len -= plen; 2301103285Sikob buf = db_tr->buf; 2302103285Sikob db_tr->buf = NULL; 2303103285Sikob stat = reg & 0x1f; 2304103285Sikob spd = reg & 0x3; 2305103285Sikob switch(stat){ 2306103285Sikob case FWOHCIEV_ACKCOMPL: 2307103285Sikob case FWOHCIEV_ACKPEND: 2308103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2309103285Sikob break; 2310103285Sikob default: 2311103285Sikob free(buf, M_DEVBUF); 2312103285Sikob device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2313103285Sikob break; 2314103285Sikob } 2315103285Sikob i++; 2316103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2317103285Sikob dbch->xferq.flag, 0, NULL); 2318103285Sikob db_tr->db[0].db.desc.depend &= ~0xf; 2319103285Sikob if(dbch->pdb_tr != NULL){ 2320103285Sikob dbch->pdb_tr->db[0].db.desc.depend |= z; 2321103285Sikob } else { 2322103285Sikob /* XXX should be rewritten in better way */ 2323103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2324103285Sikob } 2325103285Sikob dbch->pdb_tr = db_tr; 2326103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2327103285Sikob#if 0 2328103285Sikob if (!(reg & OHCI_CNTL_DMA_RUN) || 2329103285Sikob !(reg & OHCI_CNTL_DMA_ACTIVE) || 2330103285Sikob (reg & OHCI_CNTL_DMA_DEAD)) { 2331103285Sikob printf("reg = %x\n", reg); 2332103285Sikob } 2333103285Sikob#endif 2334103285Sikob } 2335103285Sikob dbch->top = db_tr; 2336103285Sikob reg = OREAD(sc, OHCI_DMACTL(off)); 2337103285Sikob if (reg & OHCI_CNTL_DMA_ACTIVE) 2338103285Sikob return; 2339103285Sikob device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2340103285Sikob dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2341103285Sikob dbch->top = db_tr; 2342103285Sikob fwohci_irx_enable(fc, dmach); 2343103285Sikob} 2344103285Sikob 2345103285Sikob#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2346103285Sikobstatic int 2347103285Sikobfwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2348103285Sikob{ 2349103285Sikob int i; 2350103285Sikob 2351103285Sikob for( i = 4; i < hlen ; i+=4){ 2352103285Sikob fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2353103285Sikob } 2354103285Sikob 2355103285Sikob switch(fp->mode.common.tcode){ 2356103285Sikob case FWTCODE_RREQQ: 2357103285Sikob return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2358103285Sikob case FWTCODE_WRES: 2359103285Sikob return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2360103285Sikob case FWTCODE_WREQQ: 2361103285Sikob return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2362103285Sikob case FWTCODE_RREQB: 2363103285Sikob return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2364103285Sikob case FWTCODE_RRESQ: 2365103285Sikob return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2366103285Sikob case FWTCODE_WREQB: 2367103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2368103285Sikob + sizeof(u_int32_t); 2369103285Sikob case FWTCODE_LREQ: 2370103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2371103285Sikob + sizeof(u_int32_t); 2372103285Sikob case FWTCODE_RRESB: 2373103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2374103285Sikob + sizeof(u_int32_t); 2375103285Sikob case FWTCODE_LRES: 2376103285Sikob return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2377103285Sikob + sizeof(u_int32_t); 2378103285Sikob case FWOHCITCODE_PHY: 2379103285Sikob return 16; 2380103285Sikob } 2381103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2382103285Sikob return 0; 2383103285Sikob} 2384103285Sikob 2385103285Sikobstatic void fwohci_arcv(sc, dbch) 2386103285Sikobstruct fwohci_softc *sc; 2387103285Sikobstruct fwohci_dbch *dbch; 2388103285Sikob{ 2389103285Sikob struct fwohcidb_tr *db_tr; 2390103285Sikob int z = 1; 2391103285Sikob struct fw_pkt *fp; 2392103285Sikob u_int8_t *ld; 2393103285Sikob u_int32_t stat, off; 2394103285Sikob#if 0 2395103285Sikob u_int32_t *qld; 2396103285Sikob u_int32_t dbcmd; 2397103285Sikob int itr, i; 2398103285Sikob#endif 2399103285Sikob u_int spd; 2400103285Sikob int len, plen, hlen, pcnt, poff = 0, rlen; 2401103285Sikob int s; 2402103285Sikob caddr_t buf; 2403103285Sikob int resCount; 2404103285Sikob 2405103285Sikob if(&sc->arrq == dbch){ 2406103285Sikob off = OHCI_ARQOFF; 2407103285Sikob }else if(&sc->arrs == dbch){ 2408103285Sikob off = OHCI_ARSOFF; 2409103285Sikob }else{ 2410103285Sikob return; 2411103285Sikob } 2412103285Sikob 2413103285Sikob s = splfw(); 2414103285Sikob#if 0 2415103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 2416103285Sikob dbcmd = OREAD(sc, OHCI_DMACMD(off)) & ~0xf; 2417103285Sikob 2418103285Sikob/* 2419103285Sikob{ 2420103285Sikobdb_tr = dbch->top; 2421103285Sikobld = (u_int8_t *)db_tr->buf; 2422103285Sikobqld = (u_int32_t *)ld; 2423103285Sikoblen = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2424103285Sikobdevice_printf(sc->fc.dev, "%08x %04x %2x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", ld, len, 2425103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3], dbcmd, vtophys(db_tr->db)); 2426103285Sikob} 2427103285Sikob*/ 2428103285Sikob for( db_tr = dbch->top, itr = 1; 2429103285Sikob dbcmd != vtophys(db_tr->db); itr++){ 2430103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2431103285Sikob if( itr >= dbch->ndb ) break; 2432103285Sikob/* 2433103285Sikobif(itr != 1){ 2434103285Sikobld = (u_int8_t *)db_tr->buf; 2435103285Sikobqld = (u_int32_t *)ld; 2436103285Sikoblen = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2437103285Sikobdevice_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2438103285Sikob db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3], dbcmd, vtophys(db_tr->db)); 2439103285Sikob} 2440103285Sikob*/ 2441103285Sikob } 2442103285Sikob/* OHCI does not support per packet receive mode in Aync receive. */ 2443103285Sikob if( dbcmd != vtophys(db_tr->db)){ 2444103285Sikob if(&sc->arrq == dbch){ 2445103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_DMA_PRRQ); 2446103285Sikob }else if(&sc->arrs == dbch){ 2447103285Sikob OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_DMA_PRRS); 2448103285Sikob } 2449103285Sikob OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 2450103285Sikob splx(s); 2451103285Sikob return; 2452103285Sikob }else{ 2453103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2454103285Sikob dbch->top = db_tr; 2455103285Sikob OWRITE(sc, OHCI_DMACMD(off),vtophys(dbch->top->db) | 1); 2456103285Sikob OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 2457103285Sikob } 2458103285Sikob 2459103285Sikob db_tr = dbch->bottom; 2460103285Sikob while(itr > 0){ 2461103285Sikob db_tr->db[0].db.desc.depend |= z; 2462103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2463103285Sikob ld = (u_int8_t *)db_tr->buf; 2464103285Sikob qld = (u_int32_t *)db_tr->buf; 2465103285Sikob len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2466103285Sikob pcnt = 0; 2467103285Sikob do{ 2468103285Sikob#else 2469103285Sikob db_tr = dbch->top; 2470103285Sikob pcnt = 0; 2471103285Sikob /* XXX we cannot handle a packet which lies in more than two buf */ 2472103285Sikob while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2473103285Sikob ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2474103285Sikob resCount = db_tr->db[0].db.desc.count; 2475103285Sikob len = dbch->xferq.psize - resCount 2476103285Sikob - dbch->buf_offset; 2477103285Sikob#if 0 2478103285Sikob printf("len: %d resCount: %d offset: %d\n", 2479103285Sikob len, resCount, dbch->buf_offset); 2480103285Sikob#endif 2481103285Sikob while (len > 0 ) { 2482103285Sikob#endif 2483103285Sikob if(dbch->frag.buf != NULL){ 2484103285Sikob buf = dbch->frag.buf; 2485103285Sikob if (dbch->frag.plen < 0) { 2486103285Sikob /* incomplete header */ 2487103285Sikob int hlen; 2488103285Sikob 2489103285Sikob hlen = - dbch->frag.plen; 2490103285Sikob rlen = hlen - dbch->frag.len; 2491103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2492103285Sikob ld += rlen; 2493103285Sikob len -= rlen; 2494103285Sikob dbch->frag.len += rlen; 2495103285Sikob#if 0 2496103285Sikob printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2497103285Sikob#endif 2498103285Sikob fp=(struct fw_pkt *)dbch->frag.buf; 2499103285Sikob dbch->frag.plen 2500103285Sikob = fwohci_get_plen(sc, fp, hlen); 2501103285Sikob if (dbch->frag.plen == 0) 2502103285Sikob goto out; 2503103285Sikob } 2504103285Sikob rlen = dbch->frag.plen - dbch->frag.len; 2505103285Sikob#if 0 2506103285Sikob printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2507103285Sikob#endif 2508103285Sikob bcopy(ld, dbch->frag.buf + dbch->frag.len, 2509103285Sikob rlen); 2510103285Sikob ld += rlen; 2511103285Sikob len -= rlen; 2512103285Sikob plen = dbch->frag.plen; 2513103285Sikob dbch->frag.buf = NULL; 2514103285Sikob dbch->frag.plen = 0; 2515103285Sikob dbch->frag.len = 0; 2516103285Sikob poff = 0; 2517103285Sikob }else{ 2518103285Sikob fp=(struct fw_pkt *)ld; 2519103285Sikob fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2520103285Sikob switch(fp->mode.common.tcode){ 2521103285Sikob case FWTCODE_RREQQ: 2522103285Sikob case FWTCODE_WRES: 2523103285Sikob case FWTCODE_WREQQ: 2524103285Sikob case FWTCODE_RRESQ: 2525103285Sikob case FWOHCITCODE_PHY: 2526103285Sikob hlen = 12; 2527103285Sikob break; 2528103285Sikob case FWTCODE_RREQB: 2529103285Sikob case FWTCODE_WREQB: 2530103285Sikob case FWTCODE_LREQ: 2531103285Sikob case FWTCODE_RRESB: 2532103285Sikob case FWTCODE_LRES: 2533103285Sikob hlen = 16; 2534103285Sikob break; 2535103285Sikob default: 2536103285Sikob device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2537103285Sikob goto out; 2538103285Sikob } 2539103285Sikob if (len >= hlen) { 2540103285Sikob plen = fwohci_get_plen(sc, fp, hlen); 2541103285Sikob if (plen == 0) 2542103285Sikob goto out; 2543103285Sikob plen = (plen + 3) & ~3; 2544103285Sikob len -= plen; 2545103285Sikob } else { 2546103285Sikob plen = -hlen; 2547103285Sikob len -= hlen; 2548103285Sikob } 2549103285Sikob if(resCount > 0 || len > 0){ 2550103285Sikob buf = malloc( dbch->xferq.psize, 2551103285Sikob M_DEVBUF, M_NOWAIT); 2552103285Sikob if(buf == NULL){ 2553103285Sikob printf("cannot malloc!\n"); 2554103285Sikob free(db_tr->buf, M_DEVBUF); 2555103285Sikob goto out; 2556103285Sikob } 2557103285Sikob bcopy(ld, buf, plen); 2558103285Sikob poff = 0; 2559103285Sikob dbch->frag.buf = NULL; 2560103285Sikob dbch->frag.plen = 0; 2561103285Sikob dbch->frag.len = 0; 2562103285Sikob }else if(len < 0){ 2563103285Sikob dbch->frag.buf = db_tr->buf; 2564103285Sikob if (plen < 0) { 2565103285Sikob#if 0 2566103285Sikob printf("plen < 0:" 2567103285Sikob "hlen: %d len: %d\n", 2568103285Sikob hlen, len); 2569103285Sikob#endif 2570103285Sikob dbch->frag.len = hlen + len; 2571103285Sikob dbch->frag.plen = -hlen; 2572103285Sikob } else { 2573103285Sikob dbch->frag.len = plen + len; 2574103285Sikob dbch->frag.plen = plen; 2575103285Sikob } 2576103285Sikob bcopy(ld, db_tr->buf, dbch->frag.len); 2577103285Sikob buf = NULL; 2578103285Sikob }else{ 2579103285Sikob buf = db_tr->buf; 2580103285Sikob poff = ld - (u_int8_t *)buf; 2581103285Sikob dbch->frag.buf = NULL; 2582103285Sikob dbch->frag.plen = 0; 2583103285Sikob dbch->frag.len = 0; 2584103285Sikob } 2585103285Sikob ld += plen; 2586103285Sikob } 2587103285Sikob if( buf != NULL){ 2588103285Sikob/* DMA result-code will be written at the tail of packet */ 2589103285Sikob stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2590103285Sikob spd = (stat >> 5) & 0x3; 2591103285Sikob stat &= 0x1f; 2592103285Sikob switch(stat){ 2593103285Sikob case FWOHCIEV_ACKPEND: 2594103285Sikob#if 0 2595103285Sikob printf("fwohci_arcv: ack pending..\n"); 2596103285Sikob#endif 2597103285Sikob /* fall through */ 2598103285Sikob case FWOHCIEV_ACKCOMPL: 2599103285Sikob if( poff != 0 ) 2600103285Sikob bcopy(buf+poff, buf, plen - 4); 2601103285Sikob fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2602103285Sikob break; 2603103285Sikob case FWOHCIEV_BUSRST: 2604103285Sikob free(buf, M_DEVBUF); 2605103285Sikob if (sc->fc.status != FWBUSRESET) 2606103285Sikob printf("got BUSRST packet!?\n"); 2607103285Sikob break; 2608103285Sikob default: 2609103285Sikob device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2610103285Sikob#if 0 /* XXX */ 2611103285Sikob goto out; 2612103285Sikob#endif 2613103285Sikob break; 2614103285Sikob } 2615103285Sikob } 2616103285Sikob pcnt ++; 2617103285Sikob }; 2618103285Sikobout: 2619103285Sikob#if 0 2620103285Sikob itr--; 2621103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 2622103285Sikob#else 2623103285Sikob if (resCount == 0) { 2624103285Sikob /* done on this buffer */ 2625103285Sikob fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2626103285Sikob dbch->xferq.flag, 0, NULL); 2627103285Sikob dbch->bottom->db[0].db.desc.depend |= z; 2628103285Sikob dbch->bottom = db_tr; 2629103285Sikob db_tr = STAILQ_NEXT(db_tr, link); 2630103285Sikob dbch->top = db_tr; 2631103285Sikob dbch->buf_offset = 0; 2632103285Sikob } else { 2633103285Sikob dbch->buf_offset = dbch->xferq.psize - resCount; 2634103285Sikob break; 2635103285Sikob } 2636103285Sikob#endif 2637103285Sikob /* XXX make sure DMA is not dead */ 2638103285Sikob } 2639103285Sikob#if 0 2640103285Sikob dbch->bottom = db_tr; 2641103285Sikob dbch->bottom->db[0].db.desc.depend &= 0xfffffff0; 2642103285Sikob#else 2643103285Sikob#if 0 2644103285Sikob if (pcnt < 1) 2645103285Sikob printf("fwohci_arcv: no packets\n"); 2646103285Sikob#endif 2647103285Sikob#endif 2648103285Sikob splx(s); 2649103285Sikob} 2650