1139749Simp/*- 2116735Sharti * Copyright (c) 2001-2003 3116735Sharti * Fraunhofer Institute for Open Communication Systems (FhG Fokus). 4116735Sharti * All rights reserved. 5116735Sharti * 6116735Sharti * Redistribution and use in source and binary forms, with or without 7116735Sharti * modification, are permitted provided that the following conditions 8116735Sharti * are met: 9116735Sharti * 1. Redistributions of source code must retain the above copyright 10116735Sharti * notice, this list of conditions and the following disclaimer. 11116735Sharti * 2. Redistributions in binary form must reproduce the above copyright 12116735Sharti * notice, this list of conditions and the following disclaimer in the 13116735Sharti * documentation and/or other materials provided with the distribution. 14116735Sharti * 15116735Sharti * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16116735Sharti * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17116735Sharti * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18116735Sharti * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19116735Sharti * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20116735Sharti * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21116735Sharti * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22116735Sharti * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23116735Sharti * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24116735Sharti * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25116735Sharti * SUCH DAMAGE. 26116735Sharti * 27116735Sharti * Author: Hartmut Brandt <harti@freebsd.org> 28116735Sharti * 29116735Sharti * $FreeBSD$ 30116735Sharti * 31116735Sharti * Fore PCA200E hardware definitions. 32116735Sharti */ 33116735Sharti 34116735Sharti/* 35116735Sharti * Fore implements some additional PCI registers. One of them is the 36116735Sharti * master control register. One of the bits allow to automatically byte 37116735Sharti * swap accesses to the on-board RAM. 38116735Sharti */ 39116735Sharti#define FATM_PCIR_MCTL 0x41 40116735Sharti#define FATM_PCIM_SWAB 0x100 41116735Sharti 42116735Sharti/* 43116735Sharti * Operations codes for commands. 44116735Sharti */ 45116735Shartienum { 46116735Sharti FATM_OP_INITIALIZE = 0x01, /* Initialize the card */ 47116735Sharti FATM_OP_ACTIVATE_VCIN = 0x02, /* Start reassembly on a channel */ 48116735Sharti FATM_OP_ACTIVATE_VCOUT = 0x03, /* (not used) */ 49116735Sharti FATM_OP_DEACTIVATE_VCIN = 0x04, /* Stop reassembly on a channel */ 50116735Sharti FATM_OP_DEACTIVATE_VCOUT= 0x05, /* (not used) */ 51116735Sharti FATM_OP_REQUEST_STATS = 0x06, /* Get statistics */ 52116735Sharti FATM_OP_OC3_SET_REG = 0x07, /* Set OC3 chip register */ 53116735Sharti FATM_OP_OC3_GET_REG = 0x08, /* Get OC3 chip registers */ 54116735Sharti FATM_OP_ZERO_STATS = 0x09, /* Zero out statistics */ 55116735Sharti FATM_OP_GET_PROM_DATA = 0x0a, /* Return expansion ROM data */ 56116735Sharti FATM_OP_SETVPI_BITS = 0x0b, /* (not used, not implemented) */ 57116735Sharti 58116735Sharti FATM_OP_INTERRUPT_SEL = 0x80, /* Request interrupt on completion */ 59116735Sharti}; 60116735Sharti 61116735Sharti/* 62116735Sharti * Status word definitions. Before initiating an operation the host sets the 63116735Sharti * status word to PENDING. The card sets it to COMPLETE upon completion of 64116735Sharti * the transmit/receive or command. An unused queue entry contains FREE. 65116735Sharti * The ERROR can be ored into the COMPLETE. Note, that there are circumstances 66298955Spfg * when ERROR is set without COMPLETE being set (when you try to activate 67116735Sharti * a bad VCI like, for example, VCI 0). 68116735Sharti */ 69116735Shartienum { 70116735Sharti FATM_STAT_PENDING = 0x01, 71116735Sharti FATM_STAT_COMPLETE = 0x02, 72116735Sharti FATM_STAT_FREE = 0x04, 73116735Sharti FATM_STAT_ERROR = 0x08, 74116735Sharti}; 75116735Sharti 76116735Sharti/* 77116735Sharti * On board queue offsets. There are two fundamentally different queue types: 78116735Sharti * the command queue and all other queues. The command queue has 32 byte 79116735Sharti * entries on the card which contain the operation code, parameters and the 80116735Sharti * DMA pointer to the status word. All other queues have 8 byte entries, which 81116735Sharti * contain a DMA pointer to the i/o block, that contains the parameters, and 82116735Sharti * a DMA pointer to the status word. 83116735Sharti */ 84116735Sharti#define FATMOC_OP 0 /* cmd queue: offset to op code */ 85116735Sharti#define FATMOC_PARAM 4 /* cmd queue: offset to parameters */ 86116735Sharti#define FATMOC_STATP 16 /* cmd queue: offset to status ptr */ 87116735Sharti#define FATMOC_END 32 /* cmd queue: element size */ 88116735Sharti 89116735Sharti#define FATMOC_ACTIN_VPVC (FATMOC_PARAM + 0) 90116735Sharti#define FATMOC_ACTIN_MTU (FATMOC_PARAM + 4) 91116735Sharti#define FATMOC_DEACTIN_VPVC (FATMOC_PARAM + 0) 92116735Sharti#define FATMOC_GETOC3_BUF (FATMOC_PARAM + 0) 93116735Sharti#define FATMOC_GSTAT_BUF (FATMOC_PARAM + 0) 94116735Sharti#define FATMOC_GPROM_BUF (FATMOC_PARAM + 0) 95116735Sharti 96116735Sharti#define FATMOS_IOBLK 0 /* other queues: offset to ioblk ptr */ 97116735Sharti#define FATMOS_STATP 4 /* other queues: offset to status ptr */ 98116735Sharti 99116735Sharti#define FATM_MAKE_SETOC3(REG,VAL,MASK) \ 100116735Sharti (FATM_OP_OC3_SET_REG | (((REG) & 0xff) << 8) | \ 101116735Sharti (((VAL) & 0xff) << 16) | (((MASK) & 0xff) << 24)) 102116735Sharti#define FATM_NREGS 128 103116735Sharti 104116735Sharti 105116735Sharti/* 106116735Sharti * On board memory layout. 107116735Sharti * 108116735Sharti * The card contains up to 2MByte memory that is mapped at virtual offset 0. 109116735Sharti * It is followed by three registers. The memory contains two areas at 110116735Sharti * fixed addresses: the mon960 area that is used for communication with 111116735Sharti * the card's operating system and the common block that is used by the 112116735Sharti * firmware to communicate with the driver. 113116735Sharti */ 114116735Sharti#define FATM_RAM_SIZE (256 * 1024) /* normal RAM size */ 115116735Sharti 116116735Sharti#define FATMO_RAM (0x0) /* virtual RAM start */ 117116735Sharti#define FATMO_MON960 (0x400) /* mon960 communication area */ 118116735Sharti#define FATMO_COMMON_ORIGIN (0x4d40) /* firmware comm. area */ 119116735Sharti 120116735Sharti#define FATMO_HCR (0x100000) /* host control registers */ 121116735Sharti#define FATMO_HIMR (0x100004) /* host interrupt mask */ 122116735Sharti#define FATMO_PSR (0x100008) /* PCI control register */ 123116735Sharti 124116735Sharti#define FATMO_END (0x200000) /* end of mapped area */ 125116735Sharti 126116735Sharti/* 127116735Sharti * The mon960 area contains two cells that are used as a virtual serial 128116735Sharti * interface, a status word, the base for loading the application (i.e. 129116735Sharti * firmware) and a version number. 130116735Sharti */ 131116735Sharti#define FATMO_UART_TO_960 (FATMO_MON960 + 0) 132116735Sharti#define FATMO_UART_TO_HOST (FATMO_MON960 + 4) 133116735Sharti#define FATMO_BOOT_STATUS (FATMO_MON960 + 8) 134116735Sharti#define FATMO_APP_BASE (FATMO_MON960 + 12) 135116735Sharti#define FATMO_VERSION (FATMO_MON960 + 16) 136116735Sharti 137116735Sharti 138116735Sharti/* 139116735Sharti * The host control register allows to hold the i960 or send it interrupts. 140116735Sharti * The bits have different meaning on read and write. 141116735Sharti */ 142116735Sharti#define FATM_HCR_RESET 0x01 /* (W) reset the card */ 143116735Sharti#define FATM_HCR_LOCK_HOLD 0x02 /* (W) hold the i960 */ 144116735Sharti#define FATM_HCR_I960FAIL 0x04 /* (R) internal self-test failed */ 145116735Sharti#define FATM_HCR_INTR2 0x04 /* (W) assert i960 interrupt 2 */ 146116735Sharti#define FATM_HCR_HOLDA 0x08 /* (R) hold ack from i960 */ 147116735Sharti#define FATM_HCR_INTR1 0x08 /* (W) assert i960 interrupt 1 */ 148116735Sharti#define FATM_HCR_OFIFO 0x10 /* (R) DMA request FIFO full */ 149116735Sharti#define FATM_HCR_CLRIRQ 0x10 /* (W) clear interrupt request */ 150116735Sharti#define FATM_HCR_ESP_HOLD 0x20 /* (R) SAR chip holds i960 */ 151116735Sharti#define FATM_HCR_IFIFO 0x40 /* (R) input FIFO full */ 152116735Sharti#define FATM_HCR_TESTMODE 0x80 /* (R) board is in test mode */ 153116735Sharti 154116735Sharti/* 155116735Sharti * The mon960 area contains a virtual UART and a status word. 156116735Sharti * The UART uses a simple protocol: a zero means, that there is no 157116735Sharti * character available from the i960 or that one can write the next 158116735Sharti * character to the i960. This character has to be ored with 0x1000000 159116735Sharti * to signal to the i960 that there is a new character. 160116735Sharti * The cold_start values must be written to the status word, the others 161116735Sharti * denote certain stages of initializing. 162116735Sharti */ 163116735Sharti#define XMIT_READY 0 164116735Sharti#define CHAR_AVAIL 0x1000000 165116735Sharti 166116735Sharti#define COLD_START 0xc01dc01d 167116735Sharti#define SELF_TEST_OK 0x02201958 168116735Sharti#define SELF_TEST_FAIL 0xadbadbad 169116735Sharti#define CP_RUNNING 0xce11feed 170116735Sharti#define MON906_TOO_BIG 0x10aded00 171116735Sharti 172116735Sharti/* 173116735Sharti * The firmware communication area contains a big structure most of which 174116735Sharti * is used only during initialisation. 175116735Sharti */ 176116735Sharti/* 177116735Sharti * These are the offsets to the onboard queues that are valid after the 178116735Sharti * initialisation command has completed. 179116735Sharti */ 180116735Sharti#define FATMO_COMMAND_QUEUE (FATMO_COMMON_ORIGIN + 0) 181116735Sharti#define FATMO_TRANSMIT_QUEUE (FATMO_COMMON_ORIGIN + 4) 182116735Sharti#define FATMO_RECEIVE_QUEUE (FATMO_COMMON_ORIGIN + 8) 183116735Sharti#define FATMO_SMALL_B1_QUEUE (FATMO_COMMON_ORIGIN + 12) 184116735Sharti#define FATMO_LARGE_B1_QUEUE (FATMO_COMMON_ORIGIN + 16) 185116735Sharti#define FATMO_SMALL_B2_QUEUE (FATMO_COMMON_ORIGIN + 20) 186116735Sharti#define FATMO_LARGE_B2_QUEUE (FATMO_COMMON_ORIGIN + 24) 187116735Sharti 188116735Sharti/* 189116735Sharti * If the interrupt mask is set to 1, interrupts to the host are queued, but 190116735Sharti * inhbited. The istat variable is set, when this card has posted an interrupt. 191116735Sharti */ 192116735Sharti#define FATMO_IMASK (FATMO_COMMON_ORIGIN + 28) 193116735Sharti#define FATMO_ISTAT (FATMO_COMMON_ORIGIN + 32) 194116735Sharti 195116735Sharti/* 196116735Sharti * This is the offset and the size of the queue area. Could be used to 197116735Sharti * dynamically compute queue sizes. 198116735Sharti */ 199116735Sharti#define FATMO_HEAP_BASE (FATMO_COMMON_ORIGIN + 36) 200116735Sharti#define FATMO_HEAP_SIZE (FATMO_COMMON_ORIGIN + 40) 201116735Sharti 202116735Sharti#define FATMO_HLOGGER (FATMO_COMMON_ORIGIN + 44) 203116735Sharti 204116735Sharti/* 205116735Sharti * The heartbeat variable is incremented in each loop of the normal processing. 206116735Sharti * If it is stuck this means, that the card had a fatal error. In this case 207116735Sharti * it may set the word to a number of values of the form 0xdeadXXXX where 208116735Sharti * XXXX is an error code. 209116735Sharti */ 210116735Sharti#define FATMO_HEARTBEAT (FATMO_COMMON_ORIGIN + 48) 211116735Sharti 212116735Sharti#define FATMO_FIRMWARE_RELEASE (FATMO_COMMON_ORIGIN + 52) 213116735Sharti#define FATMO_MON960_RELEASE (FATMO_COMMON_ORIGIN + 56) 214116735Sharti#define FATMO_TQ_PLEN (FATMO_COMMON_ORIGIN + 60) 215116735Sharti 216116735Sharti/* 217116735Sharti * At this offset the init command block is located. The init command cannot 218116735Sharti * use the normal queue mechanism because it is used to initialize the 219116735Sharti * queues. For this reason it is located at this fixed offset. 220116735Sharti */ 221116735Sharti#define FATMO_INIT (FATMO_COMMON_ORIGIN + 64) 222116735Sharti 223116735Sharti/* 224116735Sharti * physical media type 225116735Sharti */ 226116735Sharti#define FATMO_MEDIA_TYPE (FATMO_COMMON_ORIGIN + 176) 227116735Sharti#define FATMO_OC3_REVISION (FATMO_COMMON_ORIGIN + 180) 228116735Sharti 229116735Sharti/* 230116735Sharti * End of the common block 231116735Sharti */ 232116735Sharti#define FATMO_COMMON_END (FATMO_COMMON_ORIGIN + 184) 233116735Sharti 234116735Sharti/* 235116735Sharti * The INITIALIZE command block. This is embedded into the above common 236116735Sharti * block. The offsets are from the beginning of the command block. 237116735Sharti */ 238116735Sharti#define FATMOI_OP 0 /* operation code */ 239116735Sharti#define FATMOI_STATUS 4 /* status word */ 240116735Sharti#define FATMOI_RECEIVE_TRESHOLD 8 /* when to start interrupting */ 241116735Sharti#define FATMOI_NUM_CONNECT 12 /* max number of VCIs */ 242116735Sharti#define FATMOI_CQUEUE_LEN 16 /* length of command queue */ 243116735Sharti#define FATMOI_TQUEUE_LEN 20 /* length of transmit queue */ 244116735Sharti#define FATMOI_RQUEUE_LEN 24 /* length of receive queue */ 245116735Sharti#define FATMOI_RPD_EXTENSION 28 /* additional 32 byte blocks */ 246116735Sharti#define FATMOI_TPD_EXTENSION 32 /* additional 32 byte blocks */ 247116735Sharti#define FATMOI_CONLESS_VPVC 36 /* (not used) */ 248116735Sharti#define FATMOI_SMALL_B1 48 /* small buffer 1 pool */ 249116735Sharti#define FATMOI_LARGE_B1 64 /* small buffer 2 pool */ 250116735Sharti#define FATMOI_SMALL_B2 80 /* large buffer 1 pool */ 251116735Sharti#define FATMOI_LARGE_B2 96 /* large buffer 2 pool */ 252116735Sharti#define FATMOI_END 112 /* size of init block */ 253116735Sharti 254116735Sharti/* 255116735Sharti * Each of the four buffer schemes is initialized with a block that 256116735Sharti * contains four words: 257116735Sharti */ 258116735Sharti#define FATMOB_QUEUE_LENGTH 0 /* supply queue length */ 259116735Sharti#define FATMOB_BUFFER_SIZE 4 /* size of each buffer */ 260116735Sharti#define FATMOB_POOL_SIZE 8 /* size of on-board pool */ 261116735Sharti#define FATMOB_SUPPLY_BLKSIZE 12 /* number of buffers/supply */ 262116735Sharti 263116735Sharti/* 264116735Sharti * The fore firmware is a binary file, that starts with a header. The 265116735Sharti * header contains the offset to where the file must be loaded and the 266116735Sharti * entry for execution. The header must also be loaded onto the card! 267116735Sharti */ 268116735Shartistruct firmware { 269116735Sharti uint32_t id; /* "FORE" */ 270116735Sharti uint32_t version; /* firmware version */ 271116735Sharti uint32_t offset; /* load offset */ 272116735Sharti uint32_t entry; /* entry point */ 273116735Sharti}; 274116735Sharti#define FATM_FWID 0x65726f66 /* "FORE" */ 275116735Sharti#define FATM_FWVERSION 0x100 /* supported version */ 276116735Sharti 277116735Sharti/* 278116735Sharti * PDUs to be transmitted are described by Transmit PDU Descriptors. 279116735Sharti * These descriptors are held in host memory, but referenced from the ioblk 280116735Sharti * member of the queue structure on the card. The card DMAs the descriptor 281116735Sharti * and than gather-DMAs the PDU transmitting it on-the-fly. Tpds are variable 282116735Sharti * length in blocks of 32 byte (8 words). The minimum length is one block, 283116735Sharti * maximum 15. The number of blocks beyond 1 is configured during the 284116735Sharti * initialisation command (tpd_extension). 285116735Sharti * Each gather-DMA segment is described by a segment descriptor. The buffer 286116735Sharti * address and the length must be a multiple of four. 287116735Sharti * Tpd must also be 4 byte aligned. 288116735Sharti * Because of the minimum length of 32 byte, the first blocks contains already 289116735Sharti * 2 segement descriptors. Each extension block holds four descriptors. 290116735Sharti */ 291116735Sharti#define TXD_FIXED 2 292116735Sharti#define SEGS_PER_BLOCK 4 /* segment descriptors per extension block */ 293116735Shartistruct txseg { 294116735Sharti uint32_t buffer; /* DMA buffer address */ 295116735Sharti uint32_t length; /* and length */ 296116735Sharti}; 297116735Shartistruct tpd { 298116735Sharti uint32_t atm_header; /* header for the transmitted cells */ 299116735Sharti uint32_t spec; /* PDU description */ 300116735Sharti uint32_t stream; /* traffic shaping word */ 301116735Sharti uint32_t pad[1]; 302116735Sharti struct txseg segment[TXD_FIXED]; 303116735Sharti}; 304116735Sharti 305116735Sharti#define TDX_MKSPEC(INTR,AAL,NSEG,LEN) \ 306116735Sharti (((INTR) << 28) | ((AAL) << 24) | ((NSEG) << 16) | (LEN)) 307116735Sharti#define TDX_MKSTR(DATA,IDLE) \ 308116735Sharti (((DATA) << 16) | (IDLE)) 309116735Sharti#define TDX_MKHDR(VPI,VCI,PT,CLP) \ 310116735Sharti (((VPI) << 20) | ((VCI) << 4) | ((PT) << 1) | (CLP)) 311116735Sharti#define TDX_SEGS2BLKS(SEGS) \ 312116735Sharti (1 + ((SEGS)-TXD_FIXED+SEGS_PER_BLOCK-1)/SEGS_PER_BLOCK) 313116735Sharti 314116735Sharti/* 315116735Sharti * We want probably support scatter transmission, so we use the maximum 316116735Sharti * transmit descriptor extension that is possible. Because the size of the 317116735Sharti * Tpd is encoded in 32-byte blocks in a 4-bit field, the maximum extension 318116735Sharti * is 14 such blocks. The value for the init command is the number of 319116735Sharti * additional descriptor entries NOT the number of 32 byte blocks. 320116735Sharti */ 321116735Sharti#define TPD_EXTENSION_BLOCKS 14 322116735Sharti#define TPD_EXTENSIONS (TPD_EXTENSION_BLOCKS * 4) 323116735Sharti#define TPD_SIZE ((size_t)((TPD_EXTENSION_BLOCKS+1) * 32)) 324116735Sharti 325116735Sharti/* 326116735Sharti * Received PDUs are handed from the card to the host by means of Receive 327116735Sharti * PDU descriptors. Each segment describes on part of the PDU. The buffer 328116735Sharti * handle is a 32 bit value that is supplied by the host and passed 329116735Sharti * transparently back to the host by the card. It is used to locate the buffer. 330116735Sharti * The length field is the number of actual bytes in that buffer. 331116735Sharti */ 332116735Sharti#define RXD_FIXED 3 333116735Shartistruct rxseg { 334116735Sharti uint32_t handle; /* buffer handle */ 335116735Sharti uint32_t length; /* number of bytes */ 336116735Sharti}; 337116735Shartistruct rpd { 338116735Sharti uint32_t atm_header; 339116735Sharti uint32_t nseg; 340116735Sharti struct rxseg segment[RXD_FIXED]; 341116735Sharti}; 342116735Sharti 343116735Sharti/* 344116735Sharti * PDUs received are stored in buffers supplied to the card. We use only 345116735Sharti * buffer scheme 1: small buffers are normal mbuf's which can hold three 346116735Sharti * cells in their default size (256 byte) and mbuf clusters which can 347116735Sharti * hold 42 cells (2 kbyte). 348116735Sharti * The number of receive segments can be computed from these sizes: 349116735Sharti */ 350116735Sharti#define FATM_MAXPDU 65535 351116735Sharti#define MAXPDU_CELLS ((FATM_MAXPDU+47)/48) 352116735Sharti 353116735Sharti#define SMALL_BUFFER_CELLS (MHLEN/48) 354116735Sharti#define LARGE_BUFFER_CELLS (MCLBYTES/48) 355116735Sharti 356116735Sharti#define SMALL_BUFFER_LEN (SMALL_BUFFER_CELLS * 48) 357116735Sharti#define LARGE_BUFFER_LEN (LARGE_BUFFER_CELLS * 48) 358116735Sharti 359116735Sharti/* 360116735Sharti * The card first alloctes a small buffer and the switches to large 361116735Sharti * buffers. So the number of large buffers needed to store the maximum 362116735Sharti * PDU is: 363116735Sharti */ 364116735Sharti#define MAX_LARGE_BUFFERS ((MAXPDU_CELLS - SMALL_BUFFER_CELLS \ 365116735Sharti + LARGE_BUFFER_CELLS - 1) \ 366116735Sharti / LARGE_BUFFER_CELLS) \ 367116735Sharti 368116735Sharti/* 369116735Sharti * From this we get the number of extension blocks for the Rpds as: 370116735Sharti */ 371116735Sharti#define RPD_EXTENSION_BLOCKS ((MAX_LARGE_BUFFERS + 1 - RXD_FIXED \ 372116735Sharti + SEGS_PER_BLOCK - 1) \ 373116735Sharti / SEGS_PER_BLOCK) 374116735Sharti#define RPD_EXTENSIONS (RPD_EXTENSION_BLOCKS * 4) 375116735Sharti#define RPD_SIZE ((size_t)((RPD_EXTENSION_BLOCKS+1) * 32)) 376116735Sharti 377116735Sharti/* 378116735Sharti * Buffers are supplied to the card prior receiving by the supply queues. 379116735Sharti * We use two queues: scheme 1 small buffers and scheme 1 large buffers. 380116735Sharti * The queues and on-card pools are initialized by the initialize command. 381116735Sharti * Buffers are supplied in chunks. Each chunk can contain from 4 to 124 382116735Sharti * buffers in multiples of four. The chunk sizes are configured by the 383116735Sharti * initialize command. Each buffer in a chunk is described by a Receive 384116735Sharti * Buffer Descriptor that is held in host memory and given as the ioblk 385116735Sharti * to the card. 386116735Sharti */ 387116735Sharti#define BSUP_BLK2SIZE(CHUNK) (8 * (CHUNK)) 388116735Sharti 389116735Shartistruct rbd { 390116735Sharti uint32_t handle; 391116735Sharti uint32_t buffer; /* DMA address for card */ 392116735Sharti}; 393116735Sharti 394116735Sharti/* 395116735Sharti * The PCA200E has an expansion ROM that contains version information and 396116735Sharti * the FORE-assigned MAC address. It can be read via the get_prom_data 397116735Sharti * operation. 398116735Sharti */ 399116735Shartistruct prom { 400116735Sharti uint32_t version; 401116735Sharti uint32_t serial; 402116735Sharti uint8_t mac[8]; 403116735Sharti}; 404116735Sharti 405116735Sharti/* 406116735Sharti * The media type member of the firmware communication block contains a 407116735Sharti * code that describes the physical medium and physical protocol. 408116735Sharti */ 409116735Sharti#define FORE_MT_TAXI_100 0x04 410116735Sharti#define FORE_MT_TAXI_140 0x05 411116735Sharti#define FORE_MT_UTP_SONET 0x06 412116735Sharti#define FORE_MT_MM_OC3_ST 0x16 413116735Sharti#define FORE_MT_MM_OC3_SC 0x26 414116735Sharti#define FORE_MT_SM_OC3_ST 0x36 415116735Sharti#define FORE_MT_SM_OC3_SC 0x46 416116735Sharti 417116735Sharti/* 418116735Sharti * Assorted constants 419116735Sharti */ 420116735Sharti#define FORE_MAX_VCC 1024 /* max. number of VCIs supported */ 421116735Sharti#define FORE_VCIBITS 10 422116735Sharti 423116735Sharti#define FATM_STATE_TIMEOUT 500 /* msec */ 424116735Sharti 425116735Sharti/* 426116735Sharti * Statistics as delivered by the FORE cards 427116735Sharti */ 428116735Shartistruct fatm_stats { 429116735Sharti struct { 430116735Sharti uint32_t crc_header_errors; 431116735Sharti uint32_t framing_errors; 432116735Sharti uint32_t pad[2]; 433116735Sharti } phy_4b5b; 434116735Sharti 435116735Sharti struct { 436116735Sharti uint32_t section_bip8_errors; 437116735Sharti uint32_t path_bip8_errors; 438116735Sharti uint32_t line_bip24_errors; 439116735Sharti uint32_t line_febe_errors; 440116735Sharti uint32_t path_febe_errors; 441116735Sharti uint32_t corr_hcs_errors; 442116735Sharti uint32_t ucorr_hcs_errors; 443116735Sharti uint32_t pad[1]; 444116735Sharti } phy_oc3; 445116735Sharti 446116735Sharti struct { 447116735Sharti uint32_t cells_transmitted; 448116735Sharti uint32_t cells_received; 449116735Sharti uint32_t vpi_bad_range; 450116735Sharti uint32_t vpi_no_conn; 451116735Sharti uint32_t vci_bad_range; 452116735Sharti uint32_t vci_no_conn; 453116735Sharti uint32_t pad[2]; 454116735Sharti } atm; 455116735Sharti 456116735Sharti struct { 457116735Sharti uint32_t cells_transmitted; 458116735Sharti uint32_t cells_received; 459116735Sharti uint32_t cells_dropped; 460116735Sharti uint32_t pad[1]; 461116735Sharti } aal0; 462116735Sharti 463116735Sharti struct { 464116735Sharti uint32_t cells_transmitted; 465116735Sharti uint32_t cells_received; 466116735Sharti uint32_t cells_crc_errors; 467116735Sharti uint32_t cels_protocol_errors; 468116735Sharti uint32_t cells_dropped; 469116735Sharti uint32_t cspdus_transmitted; 470116735Sharti uint32_t cspdus_received; 471116735Sharti uint32_t cspdus_protocol_errors; 472116735Sharti uint32_t cspdus_dropped; 473116735Sharti uint32_t pad[3]; 474116735Sharti } aal4; 475116735Sharti 476116735Sharti struct { 477116735Sharti uint32_t cells_transmitted; 478116735Sharti uint32_t cells_received; 479116735Sharti uint32_t congestion_experienced; 480116735Sharti uint32_t cells_dropped; 481116735Sharti uint32_t cspdus_transmitted; 482116735Sharti uint32_t cspdus_received; 483116735Sharti uint32_t cspdus_crc_errors; 484116735Sharti uint32_t cspdus_protocol_errors; 485116735Sharti uint32_t cspdus_dropped; 486116735Sharti uint32_t pad[3]; 487116735Sharti } aal5; 488116735Sharti 489116735Sharti struct { 490116735Sharti uint32_t small_b1_failed; 491116735Sharti uint32_t large_b1_failed; 492116735Sharti uint32_t small_b2_failed; 493116735Sharti uint32_t large_b2_failed; 494116735Sharti uint32_t rpd_alloc_failed; 495116735Sharti uint32_t receive_carrier; 496116735Sharti uint32_t pad[2]; 497116735Sharti } aux; 498116735Sharti}; 499116735Sharti#define FATM_NSTATS 42 500