if_et.c revision 228336
1/*- 2 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/et/if_et.c 228336 2011-12-07 23:20:14Z yongari $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/endian.h> 43#include <sys/kernel.h> 44#include <sys/bus.h> 45#include <sys/malloc.h> 46#include <sys/mbuf.h> 47#include <sys/proc.h> 48#include <sys/rman.h> 49#include <sys/module.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/ethernet.h> 55#include <net/if.h> 56#include <net/if_dl.h> 57#include <net/if_types.h> 58#include <net/bpf.h> 59#include <net/if_arp.h> 60#include <net/if_media.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <dev/et/if_etreg.h> 72#include <dev/et/if_etvar.h> 73 74#include "miibus_if.h" 75 76MODULE_DEPEND(et, pci, 1, 1, 1); 77MODULE_DEPEND(et, ether, 1, 1, 1); 78MODULE_DEPEND(et, miibus, 1, 1, 1); 79 80/* Tunables. */ 81static int msi_disable = 0; 82TUNABLE_INT("hw.et.msi_disable", &msi_disable); 83 84#define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 86static int et_probe(device_t); 87static int et_attach(device_t); 88static int et_detach(device_t); 89static int et_shutdown(device_t); 90static int et_suspend(device_t); 91static int et_resume(device_t); 92 93static int et_miibus_readreg(device_t, int, int); 94static int et_miibus_writereg(device_t, int, int, int); 95static void et_miibus_statchg(device_t); 96 97static void et_init_locked(struct et_softc *); 98static void et_init(void *); 99static int et_ioctl(struct ifnet *, u_long, caddr_t); 100static void et_start_locked(struct ifnet *); 101static void et_start(struct ifnet *); 102static int et_watchdog(struct et_softc *); 103static int et_ifmedia_upd_locked(struct ifnet *); 104static int et_ifmedia_upd(struct ifnet *); 105static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 106 107static void et_add_sysctls(struct et_softc *); 108static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 109static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 110 111static void et_intr(void *); 112static void et_rxeof(struct et_softc *); 113static void et_txeof(struct et_softc *); 114 115static int et_dma_alloc(struct et_softc *); 116static void et_dma_free(struct et_softc *); 117static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 118static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 119 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 120 const char *); 121static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 122 bus_dmamap_t *); 123static void et_init_tx_ring(struct et_softc *); 124static int et_init_rx_ring(struct et_softc *); 125static void et_free_tx_ring(struct et_softc *); 126static void et_free_rx_ring(struct et_softc *); 127static int et_encap(struct et_softc *, struct mbuf **); 128static int et_newbuf_cluster(struct et_rxbuf_data *, int); 129static int et_newbuf_hdr(struct et_rxbuf_data *, int); 130static void et_rxbuf_discard(struct et_rxbuf_data *, int); 131 132static void et_stop(struct et_softc *); 133static int et_chip_init(struct et_softc *); 134static void et_chip_attach(struct et_softc *); 135static void et_init_mac(struct et_softc *); 136static void et_init_rxmac(struct et_softc *); 137static void et_init_txmac(struct et_softc *); 138static int et_init_rxdma(struct et_softc *); 139static int et_init_txdma(struct et_softc *); 140static int et_start_rxdma(struct et_softc *); 141static int et_start_txdma(struct et_softc *); 142static int et_stop_rxdma(struct et_softc *); 143static int et_stop_txdma(struct et_softc *); 144static void et_reset(struct et_softc *); 145static int et_bus_config(struct et_softc *); 146static void et_get_eaddr(device_t, uint8_t[]); 147static void et_setmulti(struct et_softc *); 148static void et_tick(void *); 149static void et_stats_update(struct et_softc *); 150 151static const struct et_dev { 152 uint16_t vid; 153 uint16_t did; 154 const char *desc; 155} et_devices[] = { 156 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 157 "Agere ET1310 Gigabit Ethernet" }, 158 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 159 "Agere ET1310 Fast Ethernet" }, 160 { 0, 0, NULL } 161}; 162 163static device_method_t et_methods[] = { 164 DEVMETHOD(device_probe, et_probe), 165 DEVMETHOD(device_attach, et_attach), 166 DEVMETHOD(device_detach, et_detach), 167 DEVMETHOD(device_shutdown, et_shutdown), 168 DEVMETHOD(device_suspend, et_suspend), 169 DEVMETHOD(device_resume, et_resume), 170 171 DEVMETHOD(miibus_readreg, et_miibus_readreg), 172 DEVMETHOD(miibus_writereg, et_miibus_writereg), 173 DEVMETHOD(miibus_statchg, et_miibus_statchg), 174 175 DEVMETHOD_END 176}; 177 178static driver_t et_driver = { 179 "et", 180 et_methods, 181 sizeof(struct et_softc) 182}; 183 184static devclass_t et_devclass; 185 186DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 187DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 188 189static int et_rx_intr_npkts = 32; 190static int et_rx_intr_delay = 20; /* x10 usec */ 191static int et_tx_intr_nsegs = 126; 192static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 193 194TUNABLE_INT("hw.et.timer", &et_timer); 195TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 196TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 197TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 198 199static int 200et_probe(device_t dev) 201{ 202 const struct et_dev *d; 203 uint16_t did, vid; 204 205 vid = pci_get_vendor(dev); 206 did = pci_get_device(dev); 207 208 for (d = et_devices; d->desc != NULL; ++d) { 209 if (vid == d->vid && did == d->did) { 210 device_set_desc(dev, d->desc); 211 return (BUS_PROBE_DEFAULT); 212 } 213 } 214 return (ENXIO); 215} 216 217static int 218et_attach(device_t dev) 219{ 220 struct et_softc *sc; 221 struct ifnet *ifp; 222 uint8_t eaddr[ETHER_ADDR_LEN]; 223 uint32_t pmcfg; 224 int cap, error, msic; 225 226 sc = device_get_softc(dev); 227 sc->dev = dev; 228 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 229 MTX_DEF); 230 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 231 232 ifp = sc->ifp = if_alloc(IFT_ETHER); 233 if (ifp == NULL) { 234 device_printf(dev, "can not if_alloc()\n"); 235 error = ENOSPC; 236 goto fail; 237 } 238 239 /* 240 * Initialize tunables 241 */ 242 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 243 sc->sc_rx_intr_delay = et_rx_intr_delay; 244 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 245 sc->sc_timer = et_timer; 246 247 /* Enable bus mastering */ 248 pci_enable_busmaster(dev); 249 250 /* 251 * Allocate IO memory 252 */ 253 sc->sc_mem_rid = ET_PCIR_BAR; 254 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 255 &sc->sc_mem_rid, RF_ACTIVE); 256 if (sc->sc_mem_res == NULL) { 257 device_printf(dev, "can't allocate IO memory\n"); 258 return (ENXIO); 259 } 260 261 msic = 0; 262 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 263 sc->sc_expcap = cap; 264 sc->sc_flags |= ET_FLAG_PCIE; 265 msic = pci_msi_count(dev); 266 if (bootverbose) 267 device_printf(dev, "MSI count: %d\n", msic); 268 } 269 if (msic > 0 && msi_disable == 0) { 270 msic = 1; 271 if (pci_alloc_msi(dev, &msic) == 0) { 272 if (msic == 1) { 273 device_printf(dev, "Using %d MSI message\n", 274 msic); 275 sc->sc_flags |= ET_FLAG_MSI; 276 } else 277 pci_release_msi(dev); 278 } 279 } 280 281 /* 282 * Allocate IRQ 283 */ 284 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 285 sc->sc_irq_rid = 0; 286 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 287 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 288 } else { 289 sc->sc_irq_rid = 1; 290 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 291 &sc->sc_irq_rid, RF_ACTIVE); 292 } 293 if (sc->sc_irq_res == NULL) { 294 device_printf(dev, "can't allocate irq\n"); 295 error = ENXIO; 296 goto fail; 297 } 298 299 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 300 sc->sc_flags |= ET_FLAG_FASTETHER; 301 302 error = et_bus_config(sc); 303 if (error) 304 goto fail; 305 306 et_get_eaddr(dev, eaddr); 307 308 /* Take PHY out of COMA and enable clocks. */ 309 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 310 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 311 pmcfg |= EM_PM_GIGEPHY_ENB; 312 CSR_WRITE_4(sc, ET_PM, pmcfg); 313 314 et_reset(sc); 315 316 error = et_dma_alloc(sc); 317 if (error) 318 goto fail; 319 320 ifp->if_softc = sc; 321 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 322 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 323 ifp->if_init = et_init; 324 ifp->if_ioctl = et_ioctl; 325 ifp->if_start = et_start; 326 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 327 ifp->if_capenable = ifp->if_capabilities; 328 ifp->if_snd.ifq_drv_maxlen = ET_TX_NDESC - 1; 329 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC - 1); 330 IFQ_SET_READY(&ifp->if_snd); 331 332 et_chip_attach(sc); 333 334 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 335 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 336 if (error) { 337 device_printf(dev, "attaching PHYs failed\n"); 338 goto fail; 339 } 340 341 ether_ifattach(ifp, eaddr); 342 343 /* Tell the upper layer(s) we support long frames. */ 344 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 345 346 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 347 NULL, et_intr, sc, &sc->sc_irq_handle); 348 if (error) { 349 ether_ifdetach(ifp); 350 device_printf(dev, "can't setup intr\n"); 351 goto fail; 352 } 353 354 et_add_sysctls(sc); 355 356 return (0); 357fail: 358 et_detach(dev); 359 return (error); 360} 361 362static int 363et_detach(device_t dev) 364{ 365 struct et_softc *sc = device_get_softc(dev); 366 367 if (device_is_attached(dev)) { 368 ether_ifdetach(sc->ifp); 369 ET_LOCK(sc); 370 et_stop(sc); 371 ET_UNLOCK(sc); 372 callout_drain(&sc->sc_tick); 373 } 374 375 if (sc->sc_miibus != NULL) 376 device_delete_child(dev, sc->sc_miibus); 377 bus_generic_detach(dev); 378 379 if (sc->sc_irq_handle != NULL) 380 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 381 if (sc->sc_irq_res != NULL) 382 bus_release_resource(dev, SYS_RES_IRQ, 383 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 384 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 385 pci_release_msi(dev); 386 if (sc->sc_mem_res != NULL) 387 bus_release_resource(dev, SYS_RES_MEMORY, 388 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 389 390 if (sc->ifp != NULL) 391 if_free(sc->ifp); 392 393 et_dma_free(sc); 394 395 mtx_destroy(&sc->sc_mtx); 396 397 return (0); 398} 399 400static int 401et_shutdown(device_t dev) 402{ 403 struct et_softc *sc = device_get_softc(dev); 404 405 ET_LOCK(sc); 406 et_stop(sc); 407 ET_UNLOCK(sc); 408 return (0); 409} 410 411static int 412et_miibus_readreg(device_t dev, int phy, int reg) 413{ 414 struct et_softc *sc = device_get_softc(dev); 415 uint32_t val; 416 int i, ret; 417 418 /* Stop any pending operations */ 419 CSR_WRITE_4(sc, ET_MII_CMD, 0); 420 421 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 422 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 423 CSR_WRITE_4(sc, ET_MII_ADDR, val); 424 425 /* Start reading */ 426 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 427 428#define NRETRY 50 429 430 for (i = 0; i < NRETRY; ++i) { 431 val = CSR_READ_4(sc, ET_MII_IND); 432 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 433 break; 434 DELAY(50); 435 } 436 if (i == NRETRY) { 437 if_printf(sc->ifp, 438 "read phy %d, reg %d timed out\n", phy, reg); 439 ret = 0; 440 goto back; 441 } 442 443#undef NRETRY 444 445 val = CSR_READ_4(sc, ET_MII_STAT); 446 ret = val & ET_MII_STAT_VALUE_MASK; 447 448back: 449 /* Make sure that the current operation is stopped */ 450 CSR_WRITE_4(sc, ET_MII_CMD, 0); 451 return (ret); 452} 453 454static int 455et_miibus_writereg(device_t dev, int phy, int reg, int val0) 456{ 457 struct et_softc *sc = device_get_softc(dev); 458 uint32_t val; 459 int i; 460 461 /* Stop any pending operations */ 462 CSR_WRITE_4(sc, ET_MII_CMD, 0); 463 464 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 465 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 466 CSR_WRITE_4(sc, ET_MII_ADDR, val); 467 468 /* Start writing */ 469 CSR_WRITE_4(sc, ET_MII_CTRL, 470 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 471 472#define NRETRY 100 473 474 for (i = 0; i < NRETRY; ++i) { 475 val = CSR_READ_4(sc, ET_MII_IND); 476 if ((val & ET_MII_IND_BUSY) == 0) 477 break; 478 DELAY(50); 479 } 480 if (i == NRETRY) { 481 if_printf(sc->ifp, 482 "write phy %d, reg %d timed out\n", phy, reg); 483 et_miibus_readreg(dev, phy, reg); 484 } 485 486#undef NRETRY 487 488 /* Make sure that the current operation is stopped */ 489 CSR_WRITE_4(sc, ET_MII_CMD, 0); 490 return (0); 491} 492 493static void 494et_miibus_statchg(device_t dev) 495{ 496 struct et_softc *sc; 497 struct mii_data *mii; 498 struct ifnet *ifp; 499 uint32_t cfg1, cfg2, ctrl; 500 int i; 501 502 sc = device_get_softc(dev); 503 504 mii = device_get_softc(sc->sc_miibus); 505 ifp = sc->ifp; 506 if (mii == NULL || ifp == NULL || 507 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 508 return; 509 510 sc->sc_flags &= ~ET_FLAG_LINK; 511 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 512 (IFM_ACTIVE | IFM_AVALID)) { 513 switch (IFM_SUBTYPE(mii->mii_media_active)) { 514 case IFM_10_T: 515 case IFM_100_TX: 516 sc->sc_flags |= ET_FLAG_LINK; 517 break; 518 case IFM_1000_T: 519 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 520 sc->sc_flags |= ET_FLAG_LINK; 521 break; 522 } 523 } 524 525 /* XXX Stop TX/RX MAC? */ 526 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 527 return; 528 529 /* Program MACs with resolved speed/duplex/flow-control. */ 530 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 531 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 532 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 533 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 534 ET_MAC_CFG1_LOOPBACK); 535 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 536 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 537 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 538 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 539 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 540 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 541 542 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 543 cfg2 |= ET_MAC_CFG2_MODE_GMII; 544 else { 545 cfg2 |= ET_MAC_CFG2_MODE_MII; 546 ctrl |= ET_MAC_CTRL_MODE_MII; 547 } 548 549 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 550 cfg2 |= ET_MAC_CFG2_FDX; 551#ifdef notyet 552 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 553 cfg1 |= ET_MAC_CFG1_TXFLOW; 554 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 555 cfg1 |= ET_MAC_CFG1_RXFLOW; 556#endif 557 } else 558 ctrl |= ET_MAC_CTRL_GHDX; 559 560 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 561 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 562 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 563 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 564 565#define NRETRY 50 566 567 for (i = 0; i < NRETRY; ++i) { 568 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 569 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 570 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 571 break; 572 DELAY(100); 573 } 574 if (i == NRETRY) 575 if_printf(ifp, "can't enable RX/TX\n"); 576 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 577 578#undef NRETRY 579} 580 581static int 582et_ifmedia_upd_locked(struct ifnet *ifp) 583{ 584 struct et_softc *sc = ifp->if_softc; 585 struct mii_data *mii = device_get_softc(sc->sc_miibus); 586 struct mii_softc *miisc; 587 588 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 589 PHY_RESET(miisc); 590 return (mii_mediachg(mii)); 591} 592 593static int 594et_ifmedia_upd(struct ifnet *ifp) 595{ 596 struct et_softc *sc = ifp->if_softc; 597 int res; 598 599 ET_LOCK(sc); 600 res = et_ifmedia_upd_locked(ifp); 601 ET_UNLOCK(sc); 602 603 return (res); 604} 605 606static void 607et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 608{ 609 struct et_softc *sc; 610 struct mii_data *mii; 611 612 sc = ifp->if_softc; 613 ET_LOCK(sc); 614 if ((ifp->if_flags & IFF_UP) == 0) { 615 ET_UNLOCK(sc); 616 return; 617 } 618 619 mii = device_get_softc(sc->sc_miibus); 620 mii_pollstat(mii); 621 ifmr->ifm_active = mii->mii_media_active; 622 ifmr->ifm_status = mii->mii_media_status; 623 ET_UNLOCK(sc); 624} 625 626static void 627et_stop(struct et_softc *sc) 628{ 629 struct ifnet *ifp = sc->ifp; 630 631 ET_LOCK_ASSERT(sc); 632 633 callout_stop(&sc->sc_tick); 634 /* Disable interrupts. */ 635 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 636 637 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 638 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 639 DELAY(100); 640 641 et_stop_rxdma(sc); 642 et_stop_txdma(sc); 643 et_stats_update(sc); 644 645 et_free_tx_ring(sc); 646 et_free_rx_ring(sc); 647 648 sc->sc_tx = 0; 649 sc->sc_tx_intr = 0; 650 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 651 652 sc->watchdog_timer = 0; 653 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 654} 655 656static int 657et_bus_config(struct et_softc *sc) 658{ 659 uint32_t val, max_plsz; 660 uint16_t ack_latency, replay_timer; 661 662 /* 663 * Test whether EEPROM is valid 664 * NOTE: Read twice to get the correct value 665 */ 666 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 667 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 668 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 669 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 670 return (ENXIO); 671 } 672 673 /* TODO: LED */ 674 675 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 676 return (0); 677 678 /* 679 * Configure ACK latency and replay timer according to 680 * max playload size 681 */ 682 val = pci_read_config(sc->dev, 683 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4); 684 max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD; 685 686 switch (max_plsz) { 687 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 688 ack_latency = ET_PCIV_ACK_LATENCY_128; 689 replay_timer = ET_PCIV_REPLAY_TIMER_128; 690 break; 691 692 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 693 ack_latency = ET_PCIV_ACK_LATENCY_256; 694 replay_timer = ET_PCIV_REPLAY_TIMER_256; 695 break; 696 697 default: 698 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 699 replay_timer = pci_read_config(sc->dev, 700 ET_PCIR_REPLAY_TIMER, 2); 701 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 702 ack_latency, replay_timer); 703 break; 704 } 705 if (ack_latency != 0) { 706 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 707 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 708 2); 709 } 710 711 /* 712 * Set L0s and L1 latency timer to 2us 713 */ 714 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 715 val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT); 716 /* L0s exit latency : 2us */ 717 val |= 0x00005000; 718 /* L1 exit latency : 2us */ 719 val |= 0x00028000; 720 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 721 722 /* 723 * Set max read request size to 2048 bytes 724 */ 725 val = pci_read_config(sc->dev, 726 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 727 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 728 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 729 pci_write_config(sc->dev, 730 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2); 731 732 return (0); 733} 734 735static void 736et_get_eaddr(device_t dev, uint8_t eaddr[]) 737{ 738 uint32_t val; 739 int i; 740 741 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 742 for (i = 0; i < 4; ++i) 743 eaddr[i] = (val >> (8 * i)) & 0xff; 744 745 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 746 for (; i < ETHER_ADDR_LEN; ++i) 747 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 748} 749 750static void 751et_reset(struct et_softc *sc) 752{ 753 CSR_WRITE_4(sc, ET_MAC_CFG1, 754 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 755 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 756 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 757 758 CSR_WRITE_4(sc, ET_SWRST, 759 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 760 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 761 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 762 763 CSR_WRITE_4(sc, ET_MAC_CFG1, 764 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 765 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 766 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 767 /* Disable interrupts. */ 768 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 769} 770 771struct et_dmamap_arg { 772 bus_addr_t et_busaddr; 773}; 774 775static void 776et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 777{ 778 struct et_dmamap_arg *ctx; 779 780 if (error) 781 return; 782 783 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 784 785 ctx = arg; 786 ctx->et_busaddr = segs->ds_addr; 787} 788 789static int 790et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 791 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 792 const char *msg) 793{ 794 struct et_dmamap_arg ctx; 795 int error; 796 797 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 798 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 799 tag); 800 if (error != 0) { 801 device_printf(sc->dev, "could not create %s dma tag\n", msg); 802 return (error); 803 } 804 /* Allocate DMA'able memory for ring. */ 805 error = bus_dmamem_alloc(*tag, (void **)ring, 806 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 807 if (error != 0) { 808 device_printf(sc->dev, 809 "could not allocate DMA'able memory for %s\n", msg); 810 return (error); 811 } 812 /* Load the address of the ring. */ 813 ctx.et_busaddr = 0; 814 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 815 &ctx, BUS_DMA_NOWAIT); 816 if (error != 0) { 817 device_printf(sc->dev, 818 "could not load DMA'able memory for %s\n", msg); 819 return (error); 820 } 821 *paddr = ctx.et_busaddr; 822 return (0); 823} 824 825static void 826et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 827 bus_dmamap_t *map) 828{ 829 830 if (*map != NULL) 831 bus_dmamap_unload(*tag, *map); 832 if (*map != NULL && *ring != NULL) { 833 bus_dmamem_free(*tag, *ring, *map); 834 *ring = NULL; 835 *map = NULL; 836 } 837 if (*tag) { 838 bus_dma_tag_destroy(*tag); 839 *tag = NULL; 840 } 841} 842 843static int 844et_dma_alloc(struct et_softc *sc) 845{ 846 struct et_txdesc_ring *tx_ring; 847 struct et_rxdesc_ring *rx_ring; 848 struct et_rxstat_ring *rxst_ring; 849 struct et_rxstatus_data *rxsd; 850 struct et_rxbuf_data *rbd; 851 struct et_txbuf_data *tbd; 852 struct et_txstatus_data *txsd; 853 int i, error; 854 855 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 856 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 857 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 858 &sc->sc_dtag); 859 if (error != 0) { 860 device_printf(sc->dev, "could not allocate parent dma tag\n"); 861 return (error); 862 } 863 864 /* TX ring. */ 865 tx_ring = &sc->sc_tx_ring; 866 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 867 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 868 &tx_ring->tr_paddr, "TX ring"); 869 if (error) 870 return (error); 871 872 /* TX status block. */ 873 txsd = &sc->sc_tx_status; 874 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 875 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 876 &txsd->txsd_paddr, "TX status block"); 877 if (error) 878 return (error); 879 880 /* RX ring 0, used as to recive small sized frames. */ 881 rx_ring = &sc->sc_rx_ring[0]; 882 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 883 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 884 &rx_ring->rr_paddr, "RX ring 0"); 885 rx_ring->rr_posreg = ET_RX_RING0_POS; 886 if (error) 887 return (error); 888 889 /* RX ring 1, used as to store normal sized frames. */ 890 rx_ring = &sc->sc_rx_ring[1]; 891 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 892 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 893 &rx_ring->rr_paddr, "RX ring 1"); 894 rx_ring->rr_posreg = ET_RX_RING1_POS; 895 if (error) 896 return (error); 897 898 /* RX stat ring. */ 899 rxst_ring = &sc->sc_rxstat_ring; 900 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 901 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 902 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 903 if (error) 904 return (error); 905 906 /* RX status block. */ 907 rxsd = &sc->sc_rx_status; 908 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 909 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 910 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 911 &rxsd->rxsd_paddr, "RX status block"); 912 if (error) 913 return (error); 914 915 /* Create parent DMA tag for mbufs. */ 916 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 917 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 918 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 919 &sc->sc_mbuf_dtag); 920 if (error != 0) { 921 device_printf(sc->dev, 922 "could not allocate parent dma tag for mbuf\n"); 923 return (error); 924 } 925 926 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 927 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 928 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 929 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 930 if (error) { 931 device_printf(sc->dev, "could not create mini RX dma tag\n"); 932 return (error); 933 } 934 935 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 936 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 937 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 938 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 939 if (error) { 940 device_printf(sc->dev, "could not create RX dma tag\n"); 941 return (error); 942 } 943 944 /* Create DMA tag for TX mbufs. */ 945 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 946 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 947 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 948 &sc->sc_tx_tag); 949 if (error) { 950 device_printf(sc->dev, "could not create TX dma tag\n"); 951 return (error); 952 } 953 954 /* Initialize RX ring 0. */ 955 rbd = &sc->sc_rx_data[0]; 956 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 957 rbd->rbd_newbuf = et_newbuf_hdr; 958 rbd->rbd_discard = et_rxbuf_discard; 959 rbd->rbd_softc = sc; 960 rbd->rbd_ring = &sc->sc_rx_ring[0]; 961 /* Create DMA maps for mini RX buffers, ring 0. */ 962 for (i = 0; i < ET_RX_NDESC; i++) { 963 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 964 &rbd->rbd_buf[i].rb_dmap); 965 if (error) { 966 device_printf(sc->dev, 967 "could not create DMA map for mini RX mbufs\n"); 968 return (error); 969 } 970 } 971 972 /* Create a spare DMA map for mini RX buffers, ring 0. */ 973 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 974 &sc->sc_rx_mini_sparemap); 975 if (error) { 976 device_printf(sc->dev, 977 "could not create spare DMA map for mini RX mbuf\n"); 978 return (error); 979 } 980 981 /* Initialize RX ring 1. */ 982 rbd = &sc->sc_rx_data[1]; 983 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 984 rbd->rbd_newbuf = et_newbuf_cluster; 985 rbd->rbd_discard = et_rxbuf_discard; 986 rbd->rbd_softc = sc; 987 rbd->rbd_ring = &sc->sc_rx_ring[1]; 988 /* Create DMA maps for standard RX buffers, ring 1. */ 989 for (i = 0; i < ET_RX_NDESC; i++) { 990 error = bus_dmamap_create(sc->sc_rx_tag, 0, 991 &rbd->rbd_buf[i].rb_dmap); 992 if (error) { 993 device_printf(sc->dev, 994 "could not create DMA map for mini RX mbufs\n"); 995 return (error); 996 } 997 } 998 999 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1000 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1001 if (error) { 1002 device_printf(sc->dev, 1003 "could not create spare DMA map for RX mbuf\n"); 1004 return (error); 1005 } 1006 1007 /* Create DMA maps for TX buffers. */ 1008 tbd = &sc->sc_tx_data; 1009 for (i = 0; i < ET_TX_NDESC; i++) { 1010 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1011 &tbd->tbd_buf[i].tb_dmap); 1012 if (error) { 1013 device_printf(sc->dev, 1014 "could not create DMA map for TX mbufs\n"); 1015 return (error); 1016 } 1017 } 1018 1019 return (0); 1020} 1021 1022static void 1023et_dma_free(struct et_softc *sc) 1024{ 1025 struct et_txdesc_ring *tx_ring; 1026 struct et_rxdesc_ring *rx_ring; 1027 struct et_txstatus_data *txsd; 1028 struct et_rxstat_ring *rxst_ring; 1029 struct et_rxstatus_data *rxsd; 1030 struct et_rxbuf_data *rbd; 1031 struct et_txbuf_data *tbd; 1032 int i; 1033 1034 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1035 rbd = &sc->sc_rx_data[0]; 1036 for (i = 0; i < ET_RX_NDESC; i++) { 1037 if (rbd->rbd_buf[i].rb_dmap) { 1038 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1039 rbd->rbd_buf[i].rb_dmap); 1040 rbd->rbd_buf[i].rb_dmap = NULL; 1041 } 1042 } 1043 if (sc->sc_rx_mini_sparemap) { 1044 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1045 sc->sc_rx_mini_sparemap = NULL; 1046 } 1047 if (sc->sc_rx_mini_tag) { 1048 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1049 sc->sc_rx_mini_tag = NULL; 1050 } 1051 1052 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1053 rbd = &sc->sc_rx_data[1]; 1054 for (i = 0; i < ET_RX_NDESC; i++) { 1055 if (rbd->rbd_buf[i].rb_dmap) { 1056 bus_dmamap_destroy(sc->sc_rx_tag, 1057 rbd->rbd_buf[i].rb_dmap); 1058 rbd->rbd_buf[i].rb_dmap = NULL; 1059 } 1060 } 1061 if (sc->sc_rx_sparemap) { 1062 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1063 sc->sc_rx_sparemap = NULL; 1064 } 1065 if (sc->sc_rx_tag) { 1066 bus_dma_tag_destroy(sc->sc_rx_tag); 1067 sc->sc_rx_tag = NULL; 1068 } 1069 1070 /* Destroy DMA maps for TX buffers. */ 1071 tbd = &sc->sc_tx_data; 1072 for (i = 0; i < ET_TX_NDESC; i++) { 1073 if (tbd->tbd_buf[i].tb_dmap) { 1074 bus_dmamap_destroy(sc->sc_tx_tag, 1075 tbd->tbd_buf[i].tb_dmap); 1076 tbd->tbd_buf[i].tb_dmap = NULL; 1077 } 1078 } 1079 if (sc->sc_tx_tag) { 1080 bus_dma_tag_destroy(sc->sc_tx_tag); 1081 sc->sc_tx_tag = NULL; 1082 } 1083 1084 /* Destroy mini RX ring, ring 0. */ 1085 rx_ring = &sc->sc_rx_ring[0]; 1086 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1087 &rx_ring->rr_dmap); 1088 /* Destroy standard RX ring, ring 1. */ 1089 rx_ring = &sc->sc_rx_ring[1]; 1090 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1091 &rx_ring->rr_dmap); 1092 /* Destroy RX stat ring. */ 1093 rxst_ring = &sc->sc_rxstat_ring; 1094 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1095 &rxst_ring->rsr_dmap); 1096 /* Destroy RX status block. */ 1097 rxsd = &sc->sc_rx_status; 1098 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1099 &rxst_ring->rsr_dmap); 1100 /* Destroy TX ring. */ 1101 tx_ring = &sc->sc_tx_ring; 1102 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1103 &tx_ring->tr_dmap); 1104 /* Destroy TX status block. */ 1105 txsd = &sc->sc_tx_status; 1106 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1107 &txsd->txsd_dmap); 1108 1109 /* Destroy the parent tag. */ 1110 if (sc->sc_dtag) { 1111 bus_dma_tag_destroy(sc->sc_dtag); 1112 sc->sc_dtag = NULL; 1113 } 1114} 1115 1116static void 1117et_chip_attach(struct et_softc *sc) 1118{ 1119 uint32_t val; 1120 1121 /* 1122 * Perform minimal initialization 1123 */ 1124 1125 /* Disable loopback */ 1126 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1127 1128 /* Reset MAC */ 1129 CSR_WRITE_4(sc, ET_MAC_CFG1, 1130 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1131 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1132 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1133 1134 /* 1135 * Setup half duplex mode 1136 */ 1137 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1138 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1139 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1140 ET_MAC_HDX_EXC_DEFER; 1141 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1142 1143 /* Clear MAC control */ 1144 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1145 1146 /* Reset MII */ 1147 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1148 1149 /* Bring MAC out of reset state */ 1150 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1151 1152 /* Enable memory controllers */ 1153 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1154} 1155 1156static void 1157et_intr(void *xsc) 1158{ 1159 struct et_softc *sc = xsc; 1160 struct ifnet *ifp; 1161 uint32_t intrs; 1162 1163 ET_LOCK(sc); 1164 ifp = sc->ifp; 1165 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1166 ET_UNLOCK(sc); 1167 return; 1168 } 1169 1170 /* Disable further interrupts. */ 1171 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1172 1173 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 1174 if ((intrs & ET_INTRS) == 0) 1175 goto done; 1176 1177 if (intrs & ET_INTR_RXEOF) 1178 et_rxeof(sc); 1179 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 1180 et_txeof(sc); 1181 if (intrs & ET_INTR_TIMER) 1182 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1183done: 1184 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1185 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1186 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1187 et_start_locked(ifp); 1188 } 1189 ET_UNLOCK(sc); 1190} 1191 1192static void 1193et_init_locked(struct et_softc *sc) 1194{ 1195 struct ifnet *ifp; 1196 int error; 1197 1198 ET_LOCK_ASSERT(sc); 1199 1200 ifp = sc->ifp; 1201 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1202 return; 1203 1204 et_stop(sc); 1205 et_reset(sc); 1206 1207 et_init_tx_ring(sc); 1208 error = et_init_rx_ring(sc); 1209 if (error) 1210 return; 1211 1212 error = et_chip_init(sc); 1213 if (error) 1214 goto fail; 1215 1216 /* 1217 * Start TX/RX DMA engine 1218 */ 1219 error = et_start_rxdma(sc); 1220 if (error) 1221 return; 1222 1223 error = et_start_txdma(sc); 1224 if (error) 1225 return; 1226 1227 /* Enable interrupts. */ 1228 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1229 1230 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1231 1232 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1234 1235 sc->sc_flags &= ~ET_FLAG_LINK; 1236 et_ifmedia_upd_locked(ifp); 1237 1238 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1239 1240fail: 1241 if (error) 1242 et_stop(sc); 1243} 1244 1245static void 1246et_init(void *xsc) 1247{ 1248 struct et_softc *sc = xsc; 1249 1250 ET_LOCK(sc); 1251 et_init_locked(sc); 1252 ET_UNLOCK(sc); 1253} 1254 1255static int 1256et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1257{ 1258 struct et_softc *sc = ifp->if_softc; 1259 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1260 struct ifreq *ifr = (struct ifreq *)data; 1261 int error = 0, mask, max_framelen; 1262 1263/* XXX LOCKSUSED */ 1264 switch (cmd) { 1265 case SIOCSIFFLAGS: 1266 ET_LOCK(sc); 1267 if (ifp->if_flags & IFF_UP) { 1268 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1269 if ((ifp->if_flags ^ sc->sc_if_flags) & 1270 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1271 et_setmulti(sc); 1272 } else { 1273 et_init_locked(sc); 1274 } 1275 } else { 1276 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1277 et_stop(sc); 1278 } 1279 sc->sc_if_flags = ifp->if_flags; 1280 ET_UNLOCK(sc); 1281 break; 1282 1283 case SIOCSIFMEDIA: 1284 case SIOCGIFMEDIA: 1285 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1286 break; 1287 1288 case SIOCADDMULTI: 1289 case SIOCDELMULTI: 1290 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1291 ET_LOCK(sc); 1292 et_setmulti(sc); 1293 ET_UNLOCK(sc); 1294 } 1295 break; 1296 1297 case SIOCSIFMTU: 1298 ET_LOCK(sc); 1299#if 0 1300 if (sc->sc_flags & ET_FLAG_JUMBO) 1301 max_framelen = ET_JUMBO_FRAMELEN; 1302 else 1303#endif 1304 max_framelen = MCLBYTES - 1; 1305 1306 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1307 error = EOPNOTSUPP; 1308 ET_UNLOCK(sc); 1309 break; 1310 } 1311 1312 if (ifp->if_mtu != ifr->ifr_mtu) { 1313 ifp->if_mtu = ifr->ifr_mtu; 1314 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1315 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1316 et_init_locked(sc); 1317 } 1318 } 1319 ET_UNLOCK(sc); 1320 break; 1321 1322 case SIOCSIFCAP: 1323 ET_LOCK(sc); 1324 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1325 if ((mask & IFCAP_TXCSUM) != 0 && 1326 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1327 ifp->if_capenable ^= IFCAP_TXCSUM; 1328 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1329 ifp->if_hwassist |= ET_CSUM_FEATURES; 1330 else 1331 ifp->if_hwassist &= ~ET_CSUM_FEATURES; 1332 } 1333 ET_UNLOCK(sc); 1334 break; 1335 1336 default: 1337 error = ether_ioctl(ifp, cmd, data); 1338 break; 1339 } 1340 return (error); 1341} 1342 1343static void 1344et_start_locked(struct ifnet *ifp) 1345{ 1346 struct et_softc *sc; 1347 struct mbuf *m_head = NULL; 1348 struct et_txdesc_ring *tx_ring; 1349 struct et_txbuf_data *tbd; 1350 uint32_t tx_ready_pos; 1351 int enq; 1352 1353 sc = ifp->if_softc; 1354 ET_LOCK_ASSERT(sc); 1355 1356 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1357 IFF_DRV_RUNNING || 1358 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1359 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1360 return; 1361 1362 /* 1363 * Driver does not request TX completion interrupt for every 1364 * queued frames to prevent generating excessive interrupts. 1365 * This means driver may wait for TX completion interrupt even 1366 * though some frames were sucessfully transmitted. Reclaiming 1367 * transmitted frames will ensure driver see all available 1368 * descriptors. 1369 */ 1370 tbd = &sc->sc_tx_data; 1371 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1372 et_txeof(sc); 1373 1374 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1375 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1376 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1377 break; 1378 } 1379 1380 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1381 if (m_head == NULL) 1382 break; 1383 1384 if (et_encap(sc, &m_head)) { 1385 if (m_head == NULL) { 1386 ifp->if_oerrors++; 1387 break; 1388 } 1389 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1390 if (tbd->tbd_used > 0) 1391 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1392 break; 1393 } 1394 enq++; 1395 ETHER_BPF_MTAP(ifp, m_head); 1396 } 1397 1398 if (enq > 0) { 1399 tx_ring = &sc->sc_tx_ring; 1400 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1401 BUS_DMASYNC_PREWRITE); 1402 tx_ready_pos = tx_ring->tr_ready_index & 1403 ET_TX_READY_POS_INDEX_MASK; 1404 if (tx_ring->tr_ready_wrap) 1405 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1406 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1407 sc->watchdog_timer = 5; 1408 } 1409} 1410 1411static void 1412et_start(struct ifnet *ifp) 1413{ 1414 struct et_softc *sc = ifp->if_softc; 1415 1416 ET_LOCK(sc); 1417 et_start_locked(ifp); 1418 ET_UNLOCK(sc); 1419} 1420 1421static int 1422et_watchdog(struct et_softc *sc) 1423{ 1424 uint32_t status; 1425 1426 ET_LOCK_ASSERT(sc); 1427 1428 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1429 return (0); 1430 1431 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1432 BUS_DMASYNC_POSTREAD); 1433 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1434 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1435 status); 1436 1437 sc->ifp->if_oerrors++; 1438 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1439 et_init_locked(sc); 1440 return (EJUSTRETURN); 1441} 1442 1443static int 1444et_stop_rxdma(struct et_softc *sc) 1445{ 1446 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1447 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1448 1449 DELAY(5); 1450 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1451 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1452 return (ETIMEDOUT); 1453 } 1454 return (0); 1455} 1456 1457static int 1458et_stop_txdma(struct et_softc *sc) 1459{ 1460 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1461 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1462 return (0); 1463} 1464 1465static void 1466et_free_tx_ring(struct et_softc *sc) 1467{ 1468 struct et_txdesc_ring *tx_ring; 1469 struct et_txbuf_data *tbd; 1470 struct et_txbuf *tb; 1471 int i; 1472 1473 tbd = &sc->sc_tx_data; 1474 tx_ring = &sc->sc_tx_ring; 1475 for (i = 0; i < ET_TX_NDESC; ++i) { 1476 tb = &tbd->tbd_buf[i]; 1477 if (tb->tb_mbuf != NULL) { 1478 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1479 BUS_DMASYNC_POSTWRITE); 1480 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1481 m_freem(tb->tb_mbuf); 1482 tb->tb_mbuf = NULL; 1483 } 1484 } 1485} 1486 1487static void 1488et_free_rx_ring(struct et_softc *sc) 1489{ 1490 struct et_rxbuf_data *rbd; 1491 struct et_rxdesc_ring *rx_ring; 1492 struct et_rxbuf *rb; 1493 int i; 1494 1495 /* Ring 0 */ 1496 rx_ring = &sc->sc_rx_ring[0]; 1497 rbd = &sc->sc_rx_data[0]; 1498 for (i = 0; i < ET_RX_NDESC; ++i) { 1499 rb = &rbd->rbd_buf[i]; 1500 if (rb->rb_mbuf != NULL) { 1501 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1502 BUS_DMASYNC_POSTREAD); 1503 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1504 m_freem(rb->rb_mbuf); 1505 rb->rb_mbuf = NULL; 1506 } 1507 } 1508 1509 /* Ring 1 */ 1510 rx_ring = &sc->sc_rx_ring[1]; 1511 rbd = &sc->sc_rx_data[1]; 1512 for (i = 0; i < ET_RX_NDESC; ++i) { 1513 rb = &rbd->rbd_buf[i]; 1514 if (rb->rb_mbuf != NULL) { 1515 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1516 BUS_DMASYNC_POSTREAD); 1517 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1518 m_freem(rb->rb_mbuf); 1519 rb->rb_mbuf = NULL; 1520 } 1521 } 1522} 1523 1524static void 1525et_setmulti(struct et_softc *sc) 1526{ 1527 struct ifnet *ifp; 1528 uint32_t hash[4] = { 0, 0, 0, 0 }; 1529 uint32_t rxmac_ctrl, pktfilt; 1530 struct ifmultiaddr *ifma; 1531 int i, count; 1532 1533 ET_LOCK_ASSERT(sc); 1534 ifp = sc->ifp; 1535 1536 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1537 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1538 1539 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1540 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1541 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1542 goto back; 1543 } 1544 1545 count = 0; 1546 if_maddr_rlock(ifp); 1547 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1548 uint32_t *hp, h; 1549 1550 if (ifma->ifma_addr->sa_family != AF_LINK) 1551 continue; 1552 1553 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1554 ifma->ifma_addr), ETHER_ADDR_LEN); 1555 h = (h & 0x3f800000) >> 23; 1556 1557 hp = &hash[0]; 1558 if (h >= 32 && h < 64) { 1559 h -= 32; 1560 hp = &hash[1]; 1561 } else if (h >= 64 && h < 96) { 1562 h -= 64; 1563 hp = &hash[2]; 1564 } else if (h >= 96) { 1565 h -= 96; 1566 hp = &hash[3]; 1567 } 1568 *hp |= (1 << h); 1569 1570 ++count; 1571 } 1572 if_maddr_runlock(ifp); 1573 1574 for (i = 0; i < 4; ++i) 1575 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1576 1577 if (count > 0) 1578 pktfilt |= ET_PKTFILT_MCAST; 1579 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1580back: 1581 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1582 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1583} 1584 1585static int 1586et_chip_init(struct et_softc *sc) 1587{ 1588 struct ifnet *ifp = sc->ifp; 1589 uint32_t rxq_end; 1590 int error, frame_len, rxmem_size; 1591 1592 /* 1593 * Split 16Kbytes internal memory between TX and RX 1594 * according to frame length. 1595 */ 1596 frame_len = ET_FRAMELEN(ifp->if_mtu); 1597 if (frame_len < 2048) { 1598 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1599 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1600 rxmem_size = ET_MEM_SIZE / 2; 1601 } else { 1602 rxmem_size = ET_MEM_SIZE - 1603 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1604 } 1605 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1606 1607 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1608 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1609 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1610 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1611 1612 /* No loopback */ 1613 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1614 1615 /* Clear MSI configure */ 1616 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1617 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1618 1619 /* Disable timer */ 1620 CSR_WRITE_4(sc, ET_TIMER, 0); 1621 1622 /* Initialize MAC */ 1623 et_init_mac(sc); 1624 1625 /* Enable memory controllers */ 1626 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1627 1628 /* Initialize RX MAC */ 1629 et_init_rxmac(sc); 1630 1631 /* Initialize TX MAC */ 1632 et_init_txmac(sc); 1633 1634 /* Initialize RX DMA engine */ 1635 error = et_init_rxdma(sc); 1636 if (error) 1637 return (error); 1638 1639 /* Initialize TX DMA engine */ 1640 error = et_init_txdma(sc); 1641 if (error) 1642 return (error); 1643 1644 return (0); 1645} 1646 1647static void 1648et_init_tx_ring(struct et_softc *sc) 1649{ 1650 struct et_txdesc_ring *tx_ring; 1651 struct et_txbuf_data *tbd; 1652 struct et_txstatus_data *txsd; 1653 1654 tx_ring = &sc->sc_tx_ring; 1655 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1656 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1657 BUS_DMASYNC_PREWRITE); 1658 1659 tbd = &sc->sc_tx_data; 1660 tbd->tbd_start_index = 0; 1661 tbd->tbd_start_wrap = 0; 1662 tbd->tbd_used = 0; 1663 1664 txsd = &sc->sc_tx_status; 1665 bzero(txsd->txsd_status, sizeof(uint32_t)); 1666 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1667 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1668} 1669 1670static int 1671et_init_rx_ring(struct et_softc *sc) 1672{ 1673 struct et_rxstatus_data *rxsd; 1674 struct et_rxstat_ring *rxst_ring; 1675 struct et_rxbuf_data *rbd; 1676 int i, error, n; 1677 1678 for (n = 0; n < ET_RX_NRING; ++n) { 1679 rbd = &sc->sc_rx_data[n]; 1680 for (i = 0; i < ET_RX_NDESC; ++i) { 1681 error = rbd->rbd_newbuf(rbd, i); 1682 if (error) { 1683 if_printf(sc->ifp, "%d ring %d buf, " 1684 "newbuf failed: %d\n", n, i, error); 1685 return (error); 1686 } 1687 } 1688 } 1689 1690 rxsd = &sc->sc_rx_status; 1691 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1692 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1693 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1694 1695 rxst_ring = &sc->sc_rxstat_ring; 1696 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1697 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1698 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1699 1700 return (0); 1701} 1702 1703static int 1704et_init_rxdma(struct et_softc *sc) 1705{ 1706 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1707 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1708 struct et_rxdesc_ring *rx_ring; 1709 int error; 1710 1711 error = et_stop_rxdma(sc); 1712 if (error) { 1713 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1714 return (error); 1715 } 1716 1717 /* 1718 * Install RX status 1719 */ 1720 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1721 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1722 1723 /* 1724 * Install RX stat ring 1725 */ 1726 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1727 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1728 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1729 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1730 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1731 1732 /* Match ET_RXSTAT_POS */ 1733 rxst_ring->rsr_index = 0; 1734 rxst_ring->rsr_wrap = 0; 1735 1736 /* 1737 * Install the 2nd RX descriptor ring 1738 */ 1739 rx_ring = &sc->sc_rx_ring[1]; 1740 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1741 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1742 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1743 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1744 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1745 1746 /* Match ET_RX_RING1_POS */ 1747 rx_ring->rr_index = 0; 1748 rx_ring->rr_wrap = 1; 1749 1750 /* 1751 * Install the 1st RX descriptor ring 1752 */ 1753 rx_ring = &sc->sc_rx_ring[0]; 1754 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1755 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1756 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1757 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1758 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1759 1760 /* Match ET_RX_RING0_POS */ 1761 rx_ring->rr_index = 0; 1762 rx_ring->rr_wrap = 1; 1763 1764 /* 1765 * RX intr moderation 1766 */ 1767 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1768 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1769 1770 return (0); 1771} 1772 1773static int 1774et_init_txdma(struct et_softc *sc) 1775{ 1776 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1777 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1778 int error; 1779 1780 error = et_stop_txdma(sc); 1781 if (error) { 1782 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1783 return (error); 1784 } 1785 1786 /* 1787 * Install TX descriptor ring 1788 */ 1789 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1790 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1791 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1792 1793 /* 1794 * Install TX status 1795 */ 1796 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1797 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1798 1799 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1800 1801 /* Match ET_TX_READY_POS */ 1802 tx_ring->tr_ready_index = 0; 1803 tx_ring->tr_ready_wrap = 0; 1804 1805 return (0); 1806} 1807 1808static void 1809et_init_mac(struct et_softc *sc) 1810{ 1811 struct ifnet *ifp = sc->ifp; 1812 const uint8_t *eaddr = IF_LLADDR(ifp); 1813 uint32_t val; 1814 1815 /* Reset MAC */ 1816 CSR_WRITE_4(sc, ET_MAC_CFG1, 1817 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1818 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1819 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1820 1821 /* 1822 * Setup inter packet gap 1823 */ 1824 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1825 (88 << ET_IPG_NONB2B_2_SHIFT) | 1826 (80 << ET_IPG_MINIFG_SHIFT) | 1827 (96 << ET_IPG_B2B_SHIFT); 1828 CSR_WRITE_4(sc, ET_IPG, val); 1829 1830 /* 1831 * Setup half duplex mode 1832 */ 1833 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1834 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1835 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1836 ET_MAC_HDX_EXC_DEFER; 1837 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1838 1839 /* Clear MAC control */ 1840 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1841 1842 /* Reset MII */ 1843 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1844 1845 /* 1846 * Set MAC address 1847 */ 1848 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1849 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1850 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1851 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1852 1853 /* Set max frame length */ 1854 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1855 1856 /* Bring MAC out of reset state */ 1857 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1858} 1859 1860static void 1861et_init_rxmac(struct et_softc *sc) 1862{ 1863 struct ifnet *ifp = sc->ifp; 1864 const uint8_t *eaddr = IF_LLADDR(ifp); 1865 uint32_t val; 1866 int i; 1867 1868 /* Disable RX MAC and WOL */ 1869 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1870 1871 /* 1872 * Clear all WOL related registers 1873 */ 1874 for (i = 0; i < 3; ++i) 1875 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1876 for (i = 0; i < 20; ++i) 1877 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1878 1879 /* 1880 * Set WOL source address. XXX is this necessary? 1881 */ 1882 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1883 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1884 val = (eaddr[0] << 8) | eaddr[1]; 1885 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1886 1887 /* Clear packet filters */ 1888 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1889 1890 /* No ucast filtering */ 1891 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1892 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1893 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1894 1895 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1896 /* 1897 * In order to transmit jumbo packets greater than 1898 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1899 * RX MAC and RX DMA needs to be reduced in size to 1900 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1901 * order to implement this, we must use "cut through" 1902 * mode in the RX MAC, which chops packets down into 1903 * segments. In this case we selected 256 bytes, 1904 * since this is the size of the PCI-Express TLP's 1905 * that the ET1310 uses. 1906 */ 1907 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1908 ET_RXMAC_MC_SEGSZ_ENABLE; 1909 } else { 1910 val = 0; 1911 } 1912 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1913 1914 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1915 1916 /* Initialize RX MAC management register */ 1917 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1918 1919 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1920 1921 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1922 ET_RXMAC_MGT_PASS_ECRC | 1923 ET_RXMAC_MGT_PASS_ELEN | 1924 ET_RXMAC_MGT_PASS_ETRUNC | 1925 ET_RXMAC_MGT_CHECK_PKT); 1926 1927 /* 1928 * Configure runt filtering (may not work on certain chip generation) 1929 */ 1930 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1931 ET_PKTFILT_MINLEN_MASK; 1932 val |= ET_PKTFILT_FRAG; 1933 CSR_WRITE_4(sc, ET_PKTFILT, val); 1934 1935 /* Enable RX MAC but leave WOL disabled */ 1936 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1937 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1938 1939 /* 1940 * Setup multicast hash and allmulti/promisc mode 1941 */ 1942 et_setmulti(sc); 1943} 1944 1945static void 1946et_init_txmac(struct et_softc *sc) 1947{ 1948 /* Disable TX MAC and FC(?) */ 1949 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1950 1951 /* No flow control yet */ 1952 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1953 1954 /* Enable TX MAC but leave FC(?) diabled */ 1955 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1956 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1957} 1958 1959static int 1960et_start_rxdma(struct et_softc *sc) 1961{ 1962 uint32_t val = 0; 1963 1964 val |= (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 1965 ET_RXDMA_CTRL_RING0_ENABLE; 1966 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 1967 ET_RXDMA_CTRL_RING1_ENABLE; 1968 1969 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1970 1971 DELAY(5); 1972 1973 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1974 if_printf(sc->ifp, "can't start RX DMA engine\n"); 1975 return (ETIMEDOUT); 1976 } 1977 return (0); 1978} 1979 1980static int 1981et_start_txdma(struct et_softc *sc) 1982{ 1983 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1984 return (0); 1985} 1986 1987static void 1988et_rxeof(struct et_softc *sc) 1989{ 1990 struct et_rxstatus_data *rxsd; 1991 struct et_rxstat_ring *rxst_ring; 1992 struct et_rxbuf_data *rbd; 1993 struct et_rxdesc_ring *rx_ring; 1994 struct et_rxstat *st; 1995 struct ifnet *ifp; 1996 struct mbuf *m; 1997 uint32_t rxstat_pos, rxring_pos; 1998 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 1999 int buflen, buf_idx, npost[2], ring_idx; 2000 int rxst_index, rxst_wrap; 2001 2002 ET_LOCK_ASSERT(sc); 2003 2004 ifp = sc->ifp; 2005 rxsd = &sc->sc_rx_status; 2006 rxst_ring = &sc->sc_rxstat_ring; 2007 2008 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2009 return; 2010 2011 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2012 BUS_DMASYNC_POSTREAD); 2013 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2014 BUS_DMASYNC_POSTREAD); 2015 2016 npost[0] = npost[1] = 0; 2017 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2018 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2019 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2020 ET_RXS_STATRING_INDEX_SHIFT; 2021 2022 while (rxst_index != rxst_ring->rsr_index || 2023 rxst_wrap != rxst_ring->rsr_wrap) { 2024 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2025 break; 2026 2027 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2028 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2029 rxst_info1 = le32toh(st->rxst_info1); 2030 rxst_info2 = le32toh(st->rxst_info2); 2031 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2032 ET_RXST_INFO2_LEN_SHIFT; 2033 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2034 ET_RXST_INFO2_BUFIDX_SHIFT; 2035 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2036 ET_RXST_INFO2_RINGIDX_SHIFT; 2037 2038 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2039 rxst_ring->rsr_index = 0; 2040 rxst_ring->rsr_wrap ^= 1; 2041 } 2042 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2043 if (rxst_ring->rsr_wrap) 2044 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2045 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2046 2047 if (ring_idx >= ET_RX_NRING) { 2048 ifp->if_ierrors++; 2049 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2050 continue; 2051 } 2052 if (buf_idx >= ET_RX_NDESC) { 2053 ifp->if_ierrors++; 2054 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2055 continue; 2056 } 2057 2058 rbd = &sc->sc_rx_data[ring_idx]; 2059 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2060 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2061 /* Discard errored frame. */ 2062 rbd->rbd_discard(rbd, buf_idx); 2063 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2064 /* No available mbufs, discard it. */ 2065 ifp->if_iqdrops++; 2066 rbd->rbd_discard(rbd, buf_idx); 2067 } else { 2068 buflen -= ETHER_CRC_LEN; 2069 if (buflen < ETHER_HDR_LEN) { 2070 m_freem(m); 2071 ifp->if_ierrors++; 2072 } else { 2073 m->m_pkthdr.len = m->m_len = buflen; 2074 m->m_pkthdr.rcvif = ifp; 2075 ET_UNLOCK(sc); 2076 ifp->if_input(ifp, m); 2077 ET_LOCK(sc); 2078 } 2079 } 2080 2081 rx_ring = &sc->sc_rx_ring[ring_idx]; 2082 if (buf_idx != rx_ring->rr_index) { 2083 if_printf(ifp, 2084 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2085 ring_idx, buf_idx, rx_ring->rr_index); 2086 } 2087 2088 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2089 if (++rx_ring->rr_index == ET_RX_NDESC) { 2090 rx_ring->rr_index = 0; 2091 rx_ring->rr_wrap ^= 1; 2092 } 2093 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2094 if (rx_ring->rr_wrap) 2095 rxring_pos |= ET_RX_RING_POS_WRAP; 2096 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2097 } 2098 2099 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2100 BUS_DMASYNC_PREREAD); 2101 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2102 BUS_DMASYNC_PREREAD); 2103} 2104 2105static int 2106et_encap(struct et_softc *sc, struct mbuf **m0) 2107{ 2108 struct et_txdesc_ring *tx_ring; 2109 struct et_txbuf_data *tbd; 2110 struct et_txdesc *td; 2111 struct mbuf *m; 2112 bus_dma_segment_t segs[ET_NSEG_MAX]; 2113 bus_dmamap_t map; 2114 uint32_t csum_flags, last_td_ctrl2; 2115 int error, i, idx, first_idx, last_idx, nsegs; 2116 2117 tx_ring = &sc->sc_tx_ring; 2118 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2119 tbd = &sc->sc_tx_data; 2120 first_idx = tx_ring->tr_ready_index; 2121 map = tbd->tbd_buf[first_idx].tb_dmap; 2122 2123 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2124 0); 2125 if (error == EFBIG) { 2126 m = m_collapse(*m0, M_DONTWAIT, ET_NSEG_MAX); 2127 if (m == NULL) { 2128 m_freem(*m0); 2129 *m0 = NULL; 2130 return (ENOMEM); 2131 } 2132 *m0 = m; 2133 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2134 &nsegs, 0); 2135 if (error != 0) { 2136 m_freem(*m0); 2137 *m0 = NULL; 2138 return (error); 2139 } 2140 } else if (error != 0) 2141 return (error); 2142 2143 /* Check for descriptor overruns. */ 2144 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2145 bus_dmamap_unload(sc->sc_tx_tag, map); 2146 return (ENOBUFS); 2147 } 2148 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2149 2150 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2151 sc->sc_tx += nsegs; 2152 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2153 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2154 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2155 } 2156 2157 m = *m0; 2158 csum_flags = 0; 2159 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2160 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2161 csum_flags |= ET_TDCTRL2_CSUM_IP; 2162 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2163 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2164 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2165 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2166 } 2167 last_idx = -1; 2168 for (i = 0; i < nsegs; ++i) { 2169 idx = (first_idx + i) % ET_TX_NDESC; 2170 td = &tx_ring->tr_desc[idx]; 2171 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2172 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2173 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2174 if (i == nsegs - 1) { 2175 /* Last frag */ 2176 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2177 last_idx = idx; 2178 } else 2179 td->td_ctrl2 = htole32(csum_flags); 2180 2181 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2182 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2183 tx_ring->tr_ready_index = 0; 2184 tx_ring->tr_ready_wrap ^= 1; 2185 } 2186 } 2187 td = &tx_ring->tr_desc[first_idx]; 2188 /* First frag */ 2189 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2190 2191 MPASS(last_idx >= 0); 2192 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2193 tbd->tbd_buf[last_idx].tb_dmap = map; 2194 tbd->tbd_buf[last_idx].tb_mbuf = m; 2195 2196 tbd->tbd_used += nsegs; 2197 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2198 2199 return (0); 2200} 2201 2202static void 2203et_txeof(struct et_softc *sc) 2204{ 2205 struct et_txdesc_ring *tx_ring; 2206 struct et_txbuf_data *tbd; 2207 struct et_txbuf *tb; 2208 struct ifnet *ifp; 2209 uint32_t tx_done; 2210 int end, wrap; 2211 2212 ET_LOCK_ASSERT(sc); 2213 2214 ifp = sc->ifp; 2215 tx_ring = &sc->sc_tx_ring; 2216 tbd = &sc->sc_tx_data; 2217 2218 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2219 return; 2220 2221 if (tbd->tbd_used == 0) 2222 return; 2223 2224 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2225 BUS_DMASYNC_POSTWRITE); 2226 2227 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2228 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2229 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2230 2231 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2232 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2233 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2234 if (tb->tb_mbuf != NULL) { 2235 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2236 BUS_DMASYNC_POSTWRITE); 2237 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2238 m_freem(tb->tb_mbuf); 2239 tb->tb_mbuf = NULL; 2240 } 2241 2242 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2243 tbd->tbd_start_index = 0; 2244 tbd->tbd_start_wrap ^= 1; 2245 } 2246 2247 MPASS(tbd->tbd_used > 0); 2248 tbd->tbd_used--; 2249 } 2250 2251 if (tbd->tbd_used == 0) 2252 sc->watchdog_timer = 0; 2253 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2254 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2255} 2256 2257static void 2258et_tick(void *xsc) 2259{ 2260 struct et_softc *sc = xsc; 2261 struct ifnet *ifp; 2262 struct mii_data *mii; 2263 2264 ET_LOCK_ASSERT(sc); 2265 ifp = sc->ifp; 2266 mii = device_get_softc(sc->sc_miibus); 2267 2268 mii_tick(mii); 2269 et_stats_update(sc); 2270 if (et_watchdog(sc) == EJUSTRETURN) 2271 return; 2272 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2273} 2274 2275static int 2276et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2277{ 2278 struct et_softc *sc; 2279 struct et_rxdesc *desc; 2280 struct et_rxbuf *rb; 2281 struct mbuf *m; 2282 bus_dma_segment_t segs[1]; 2283 bus_dmamap_t dmap; 2284 int nsegs; 2285 2286 MPASS(buf_idx < ET_RX_NDESC); 2287 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2288 if (m == NULL) 2289 return (ENOBUFS); 2290 m->m_len = m->m_pkthdr.len = MCLBYTES; 2291 m_adj(m, ETHER_ALIGN); 2292 2293 sc = rbd->rbd_softc; 2294 rb = &rbd->rbd_buf[buf_idx]; 2295 2296 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2297 segs, &nsegs, 0) != 0) { 2298 m_freem(m); 2299 return (ENOBUFS); 2300 } 2301 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2302 2303 if (rb->rb_mbuf != NULL) { 2304 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2305 BUS_DMASYNC_POSTREAD); 2306 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2307 } 2308 dmap = rb->rb_dmap; 2309 rb->rb_dmap = sc->sc_rx_sparemap; 2310 sc->sc_rx_sparemap = dmap; 2311 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2312 2313 rb->rb_mbuf = m; 2314 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2315 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2316 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2317 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2318 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2319 BUS_DMASYNC_PREWRITE); 2320 return (0); 2321} 2322 2323static void 2324et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2325{ 2326 struct et_rxdesc *desc; 2327 2328 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2329 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2330 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2331 BUS_DMASYNC_PREWRITE); 2332} 2333 2334static int 2335et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2336{ 2337 struct et_softc *sc; 2338 struct et_rxdesc *desc; 2339 struct et_rxbuf *rb; 2340 struct mbuf *m; 2341 bus_dma_segment_t segs[1]; 2342 bus_dmamap_t dmap; 2343 int nsegs; 2344 2345 MPASS(buf_idx < ET_RX_NDESC); 2346 MGETHDR(m, M_DONTWAIT, MT_DATA); 2347 if (m == NULL) 2348 return (ENOBUFS); 2349 m->m_len = m->m_pkthdr.len = MHLEN; 2350 m_adj(m, ETHER_ALIGN); 2351 2352 sc = rbd->rbd_softc; 2353 rb = &rbd->rbd_buf[buf_idx]; 2354 2355 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2356 m, segs, &nsegs, 0) != 0) { 2357 m_freem(m); 2358 return (ENOBUFS); 2359 } 2360 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2361 2362 if (rb->rb_mbuf != NULL) { 2363 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2364 BUS_DMASYNC_POSTREAD); 2365 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2366 } 2367 dmap = rb->rb_dmap; 2368 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2369 sc->sc_rx_mini_sparemap = dmap; 2370 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2371 2372 rb->rb_mbuf = m; 2373 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2374 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2375 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2376 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2377 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2378 BUS_DMASYNC_PREWRITE); 2379 return (0); 2380} 2381 2382#define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2383 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2384#define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2385 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2386 2387/* 2388 * Create sysctl tree 2389 */ 2390static void 2391et_add_sysctls(struct et_softc * sc) 2392{ 2393 struct sysctl_ctx_list *ctx; 2394 struct sysctl_oid_list *children, *parent; 2395 struct sysctl_oid *tree; 2396 struct et_hw_stats *stats; 2397 2398 ctx = device_get_sysctl_ctx(sc->dev); 2399 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2400 2401 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2402 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I", 2403 "RX IM, # packets per RX interrupt"); 2404 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2405 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I", 2406 "RX IM, RX interrupt delay (x10 usec)"); 2407 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2408 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2409 "TX IM, # segments per TX interrupt"); 2410 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2411 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2412 2413 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 2414 NULL, "ET statistics"); 2415 parent = SYSCTL_CHILDREN(tree); 2416 2417 /* TX/RX statistics. */ 2418 stats = &sc->sc_stats; 2419 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2420 "0 to 64 bytes frames"); 2421 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2422 "65 to 127 bytes frames"); 2423 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2424 "128 to 255 bytes frames"); 2425 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2426 "256 to 511 bytes frames"); 2427 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2428 "512 to 1023 bytes frames"); 2429 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2430 "1024 to 1518 bytes frames"); 2431 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2432 "1519 to 1522 bytes frames"); 2433 2434 /* RX statistics. */ 2435 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2436 NULL, "RX MAC statistics"); 2437 children = SYSCTL_CHILDREN(tree); 2438 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2439 &stats->rx_bytes, "Good bytes"); 2440 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2441 &stats->rx_frames, "Good frames"); 2442 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2443 &stats->rx_crcerrs, "CRC errors"); 2444 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2445 &stats->rx_mcast, "Multicast frames"); 2446 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2447 &stats->rx_bcast, "Broadcast frames"); 2448 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2449 &stats->rx_control, "Control frames"); 2450 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2451 &stats->rx_pause, "Pause frames"); 2452 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2453 &stats->rx_unknown_control, "Unknown control frames"); 2454 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2455 &stats->rx_alignerrs, "Alignment errors"); 2456 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2457 &stats->rx_lenerrs, "Frames with length mismatched"); 2458 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2459 &stats->rx_codeerrs, "Frames with code error"); 2460 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2461 &stats->rx_cserrs, "Frames with carrier sense error"); 2462 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2463 &stats->rx_runts, "Too short frames"); 2464 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2465 &stats->rx_oversize, "Oversized frames"); 2466 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2467 &stats->rx_fragments, "Fragmented frames"); 2468 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2469 &stats->rx_jabbers, "Frames with jabber error"); 2470 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2471 &stats->rx_drop, "Dropped frames"); 2472 2473 /* TX statistics. */ 2474 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2475 NULL, "TX MAC statistics"); 2476 children = SYSCTL_CHILDREN(tree); 2477 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2478 &stats->tx_bytes, "Good bytes"); 2479 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2480 &stats->tx_frames, "Good frames"); 2481 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2482 &stats->tx_mcast, "Multicast frames"); 2483 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2484 &stats->tx_bcast, "Broadcast frames"); 2485 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2486 &stats->tx_pause, "Pause frames"); 2487 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2488 &stats->tx_deferred, "Deferred frames"); 2489 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2490 &stats->tx_excess_deferred, "Excessively deferred frames"); 2491 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2492 &stats->tx_single_colls, "Single collisions"); 2493 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2494 &stats->tx_multi_colls, "Multiple collisions"); 2495 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2496 &stats->tx_late_colls, "Late collisions"); 2497 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2498 &stats->tx_excess_colls, "Excess collisions"); 2499 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2500 &stats->tx_total_colls, "Total collisions"); 2501 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2502 &stats->tx_pause_honored, "Honored pause frames"); 2503 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2504 &stats->tx_drop, "Dropped frames"); 2505 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2506 &stats->tx_jabbers, "Frames with jabber errors"); 2507 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2508 &stats->tx_crcerrs, "Frames with CRC errors"); 2509 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2510 &stats->tx_control, "Control frames"); 2511 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2512 &stats->tx_oversize, "Oversized frames"); 2513 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2514 &stats->tx_undersize, "Undersized frames"); 2515 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2516 &stats->tx_fragments, "Fragmented frames"); 2517} 2518 2519#undef ET_SYSCTL_STAT_ADD32 2520#undef ET_SYSCTL_STAT_ADD64 2521 2522static int 2523et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2524{ 2525 struct et_softc *sc = arg1; 2526 struct ifnet *ifp = sc->ifp; 2527 int error = 0, v; 2528 2529 v = sc->sc_rx_intr_npkts; 2530 error = sysctl_handle_int(oidp, &v, 0, req); 2531 if (error || req->newptr == NULL) 2532 goto back; 2533 if (v <= 0) { 2534 error = EINVAL; 2535 goto back; 2536 } 2537 2538 if (sc->sc_rx_intr_npkts != v) { 2539 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2540 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2541 sc->sc_rx_intr_npkts = v; 2542 } 2543back: 2544 return (error); 2545} 2546 2547static int 2548et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2549{ 2550 struct et_softc *sc = arg1; 2551 struct ifnet *ifp = sc->ifp; 2552 int error = 0, v; 2553 2554 v = sc->sc_rx_intr_delay; 2555 error = sysctl_handle_int(oidp, &v, 0, req); 2556 if (error || req->newptr == NULL) 2557 goto back; 2558 if (v <= 0) { 2559 error = EINVAL; 2560 goto back; 2561 } 2562 2563 if (sc->sc_rx_intr_delay != v) { 2564 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2565 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2566 sc->sc_rx_intr_delay = v; 2567 } 2568back: 2569 return (error); 2570} 2571 2572static void 2573et_stats_update(struct et_softc *sc) 2574{ 2575 struct ifnet *ifp; 2576 struct et_hw_stats *stats; 2577 2578 stats = &sc->sc_stats; 2579 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2580 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2581 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2582 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2583 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2584 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2585 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2586 2587 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2588 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2589 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2590 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2591 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2592 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2593 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2594 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2595 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2596 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2597 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2598 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2599 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2600 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2601 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2602 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2603 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2604 2605 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2606 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2607 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2608 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2609 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2610 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2611 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2612 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2613 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2614 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2615 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2616 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2617 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2618 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2619 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2620 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2621 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2622 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2623 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2624 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2625 2626 /* Update ifnet counters. */ 2627 ifp = sc->ifp; 2628 ifp->if_opackets = (u_long)stats->tx_frames; 2629 ifp->if_collisions = stats->tx_total_colls; 2630 ifp->if_oerrors = stats->tx_drop + stats->tx_jabbers + 2631 stats->tx_crcerrs + stats->tx_excess_deferred + 2632 stats->tx_late_colls; 2633 ifp->if_ipackets = (u_long)stats->rx_frames; 2634 ifp->if_ierrors = stats->rx_crcerrs + stats->rx_alignerrs + 2635 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2636 stats->rx_runts + stats->rx_jabbers + stats->rx_drop; 2637} 2638 2639static int 2640et_suspend(device_t dev) 2641{ 2642 struct et_softc *sc; 2643 uint32_t pmcfg; 2644 2645 sc = device_get_softc(dev); 2646 ET_LOCK(sc); 2647 if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2648 et_stop(sc); 2649 /* Diable all clocks and put PHY into COMA. */ 2650 pmcfg = CSR_READ_4(sc, ET_PM); 2651 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2652 ET_PM_RXCLK_GATE); 2653 pmcfg |= ET_PM_PHY_SW_COMA; 2654 CSR_WRITE_4(sc, ET_PM, pmcfg); 2655 ET_UNLOCK(sc); 2656 return (0); 2657} 2658 2659static int 2660et_resume(device_t dev) 2661{ 2662 struct et_softc *sc; 2663 uint32_t pmcfg; 2664 2665 sc = device_get_softc(dev); 2666 ET_LOCK(sc); 2667 /* Take PHY out of COMA and enable clocks. */ 2668 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2669 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2670 pmcfg |= EM_PM_GIGEPHY_ENB; 2671 CSR_WRITE_4(sc, ET_PM, pmcfg); 2672 if ((sc->ifp->if_flags & IFF_UP) != 0) 2673 et_init_locked(sc); 2674 ET_UNLOCK(sc); 2675 return (0); 2676} 2677