if_et.c revision 212969
1/*-
2 * Copyright (c) 2007 Sepherosa Ziehau.  All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in
15 *    the documentation and/or other materials provided with the
16 *    distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 *    contributors may be used to endorse or promote products derived
19 *    from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $
35 */
36
37#include <sys/cdefs.h>
38__FBSDID("$FreeBSD: head/sys/dev/et/if_et.c 212969 2010-09-21 17:31:14Z yongari $");
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/endian.h>
43#include <sys/kernel.h>
44#include <sys/bus.h>
45#include <sys/malloc.h>
46#include <sys/mbuf.h>
47#include <sys/proc.h>
48#include <sys/rman.h>
49#include <sys/module.h>
50#include <sys/socket.h>
51#include <sys/sockio.h>
52#include <sys/sysctl.h>
53
54#include <net/ethernet.h>
55#include <net/if.h>
56#include <net/if_dl.h>
57#include <net/if_types.h>
58#include <net/bpf.h>
59#include <net/if_arp.h>
60#include <net/if_dl.h>
61#include <net/if_media.h>
62#include <net/if_vlan_var.h>
63
64#include <machine/bus.h>
65
66#include <dev/mii/miivar.h>
67#include <dev/mii/truephyreg.h>
68
69#include <dev/pci/pcireg.h>
70#include <dev/pci/pcivar.h>
71
72#include <dev/et/if_etreg.h>
73#include <dev/et/if_etvar.h>
74
75#include "miibus_if.h"
76
77MODULE_DEPEND(et, pci, 1, 1, 1);
78MODULE_DEPEND(et, ether, 1, 1, 1);
79MODULE_DEPEND(et, miibus, 1, 1, 1);
80
81/* Tunables. */
82static int msi_disable = 0;
83TUNABLE_INT("hw.et.msi_disable", &msi_disable);
84
85#define	ET_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
86
87static int	et_probe(device_t);
88static int	et_attach(device_t);
89static int	et_detach(device_t);
90static int	et_shutdown(device_t);
91
92static int	et_miibus_readreg(device_t, int, int);
93static int	et_miibus_writereg(device_t, int, int, int);
94static void	et_miibus_statchg(device_t);
95
96static void	et_init_locked(struct et_softc *);
97static void	et_init(void *);
98static int	et_ioctl(struct ifnet *, u_long, caddr_t);
99static void	et_start_locked(struct ifnet *);
100static void	et_start(struct ifnet *);
101static void	et_watchdog(struct et_softc *);
102static int	et_ifmedia_upd_locked(struct ifnet *);
103static int	et_ifmedia_upd(struct ifnet *);
104static void	et_ifmedia_sts(struct ifnet *, struct ifmediareq *);
105
106static void	et_add_sysctls(struct et_softc *);
107static int	et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS);
108static int	et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS);
109
110static void	et_intr(void *);
111static void	et_enable_intrs(struct et_softc *, uint32_t);
112static void	et_disable_intrs(struct et_softc *);
113static void	et_rxeof(struct et_softc *);
114static void	et_txeof(struct et_softc *);
115
116static int	et_dma_alloc(device_t);
117static void	et_dma_free(device_t);
118static int	et_dma_mem_create(device_t, bus_size_t, bus_dma_tag_t *,
119				  void **, bus_addr_t *, bus_dmamap_t *);
120static void	et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
121static int	et_dma_mbuf_create(device_t);
122static void	et_dma_mbuf_destroy(device_t, int, const int[]);
123static void	et_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
124static void	et_dma_buf_addr(void *, bus_dma_segment_t *, int,
125				bus_size_t, int);
126static int	et_init_tx_ring(struct et_softc *);
127static int	et_init_rx_ring(struct et_softc *);
128static void	et_free_tx_ring(struct et_softc *);
129static void	et_free_rx_ring(struct et_softc *);
130static int	et_encap(struct et_softc *, struct mbuf **);
131static int	et_newbuf(struct et_rxbuf_data *, int, int, int);
132static int	et_newbuf_cluster(struct et_rxbuf_data *, int, int);
133static int	et_newbuf_hdr(struct et_rxbuf_data *, int, int);
134
135static void	et_stop(struct et_softc *);
136static int	et_chip_init(struct et_softc *);
137static void	et_chip_attach(struct et_softc *);
138static void	et_init_mac(struct et_softc *);
139static void	et_init_rxmac(struct et_softc *);
140static void	et_init_txmac(struct et_softc *);
141static int	et_init_rxdma(struct et_softc *);
142static int	et_init_txdma(struct et_softc *);
143static int	et_start_rxdma(struct et_softc *);
144static int	et_start_txdma(struct et_softc *);
145static int	et_stop_rxdma(struct et_softc *);
146static int	et_stop_txdma(struct et_softc *);
147static int	et_enable_txrx(struct et_softc *, int);
148static void	et_reset(struct et_softc *);
149static int	et_bus_config(struct et_softc *);
150static void	et_get_eaddr(device_t, uint8_t[]);
151static void	et_setmulti(struct et_softc *);
152static void	et_tick(void *);
153static void	et_setmedia(struct et_softc *);
154static void	et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t);
155
156static const struct et_dev {
157	uint16_t	vid;
158	uint16_t	did;
159	const char	*desc;
160} et_devices[] = {
161	{ PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310,
162	  "Agere ET1310 Gigabit Ethernet" },
163	{ PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST,
164	  "Agere ET1310 Fast Ethernet" },
165	{ 0, 0, NULL }
166};
167
168static device_method_t et_methods[] = {
169	DEVMETHOD(device_probe,		et_probe),
170	DEVMETHOD(device_attach,	et_attach),
171	DEVMETHOD(device_detach,	et_detach),
172	DEVMETHOD(device_shutdown,	et_shutdown),
173
174	DEVMETHOD(bus_print_child,	bus_generic_print_child),
175	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
176
177	DEVMETHOD(miibus_readreg,	et_miibus_readreg),
178	DEVMETHOD(miibus_writereg,	et_miibus_writereg),
179	DEVMETHOD(miibus_statchg,	et_miibus_statchg),
180
181	{ 0, 0 }
182};
183
184static driver_t et_driver = {
185	"et",
186	et_methods,
187	sizeof(struct et_softc)
188};
189
190static devclass_t et_devclass;
191
192DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0);
193DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0);
194
195static int	et_rx_intr_npkts = 32;
196static int	et_rx_intr_delay = 20;		/* x10 usec */
197static int	et_tx_intr_nsegs = 126;
198static uint32_t	et_timer = 1000 * 1000 * 1000;	/* nanosec */
199
200TUNABLE_INT("hw.et.timer", &et_timer);
201TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts);
202TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay);
203TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs);
204
205struct et_bsize {
206	int		bufsize;
207	et_newbuf_t	newbuf;
208};
209
210static const struct et_bsize	et_bufsize_std[ET_RX_NRING] = {
211	{ .bufsize = ET_RXDMA_CTRL_RING0_128,
212	  .newbuf = et_newbuf_hdr },
213	{ .bufsize = ET_RXDMA_CTRL_RING1_2048,
214	  .newbuf = et_newbuf_cluster },
215};
216
217static int
218et_probe(device_t dev)
219{
220	const struct et_dev *d;
221	uint16_t did, vid;
222
223	vid = pci_get_vendor(dev);
224	did = pci_get_device(dev);
225
226	for (d = et_devices; d->desc != NULL; ++d) {
227		if (vid == d->vid && did == d->did) {
228			device_set_desc(dev, d->desc);
229			return (0);
230		}
231	}
232	return (ENXIO);
233}
234
235static int
236et_attach(device_t dev)
237{
238	struct et_softc *sc;
239	struct ifnet *ifp;
240	uint8_t eaddr[ETHER_ADDR_LEN];
241	int cap, error, msic;
242
243	sc = device_get_softc(dev);
244	sc->dev = dev;
245	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
246	    MTX_DEF);
247
248	ifp = sc->ifp = if_alloc(IFT_ETHER);
249	if (ifp == NULL) {
250		device_printf(dev, "can not if_alloc()\n");
251		error = ENOSPC;
252		goto fail;
253	}
254
255	/*
256	 * Initialize tunables
257	 */
258	sc->sc_rx_intr_npkts = et_rx_intr_npkts;
259	sc->sc_rx_intr_delay = et_rx_intr_delay;
260	sc->sc_tx_intr_nsegs = et_tx_intr_nsegs;
261	sc->sc_timer = et_timer;
262
263	/* Enable bus mastering */
264	pci_enable_busmaster(dev);
265
266	/*
267	 * Allocate IO memory
268	 */
269	sc->sc_mem_rid = ET_PCIR_BAR;
270	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
271						&sc->sc_mem_rid, RF_ACTIVE);
272	if (sc->sc_mem_res == NULL) {
273		device_printf(dev, "can't allocate IO memory\n");
274		return (ENXIO);
275	}
276
277	msic = 0;
278	if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) {
279		sc->sc_expcap = cap;
280		sc->sc_flags |= ET_FLAG_PCIE;
281		msic = pci_msi_count(dev);
282		if (bootverbose)
283			device_printf(dev, "MSI count: %d\n", msic);
284	}
285	if (msic > 0 && msi_disable == 0) {
286		msic = 1;
287		if (pci_alloc_msi(dev, &msic) == 0) {
288			if (msic == 1) {
289				device_printf(dev, "Using %d MSI message\n",
290				    msic);
291				sc->sc_flags |= ET_FLAG_MSI;
292			} else
293				pci_release_msi(dev);
294		}
295	}
296
297	/*
298	 * Allocate IRQ
299	 */
300	if ((sc->sc_flags & ET_FLAG_MSI) == 0) {
301		sc->sc_irq_rid = 0;
302		sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
303		    &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE);
304	} else {
305		sc->sc_irq_rid = 1;
306		sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
307		    &sc->sc_irq_rid, RF_ACTIVE);
308	}
309	if (sc->sc_irq_res == NULL) {
310		device_printf(dev, "can't allocate irq\n");
311		error = ENXIO;
312		goto fail;
313	}
314
315	error = et_bus_config(sc);
316	if (error)
317		goto fail;
318
319	et_get_eaddr(dev, eaddr);
320
321	CSR_WRITE_4(sc, ET_PM,
322		    ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE);
323
324	et_reset(sc);
325
326	et_disable_intrs(sc);
327
328	error = et_dma_alloc(dev);
329	if (error)
330		goto fail;
331
332	ifp->if_softc = sc;
333	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
334	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
335	ifp->if_init = et_init;
336	ifp->if_ioctl = et_ioctl;
337	ifp->if_start = et_start;
338	ifp->if_mtu = ETHERMTU;
339	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU;
340	ifp->if_capenable = ifp->if_capabilities;
341	IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC);
342	IFQ_SET_READY(&ifp->if_snd);
343
344	et_chip_attach(sc);
345
346	error = mii_phy_probe(dev, &sc->sc_miibus,
347			      et_ifmedia_upd, et_ifmedia_sts);
348	if (error) {
349		device_printf(dev, "can't probe any PHY\n");
350		goto fail;
351	}
352
353	ether_ifattach(ifp, eaddr);
354	callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0);
355
356	error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE,
357	    NULL, et_intr, sc, &sc->sc_irq_handle);
358	if (error) {
359		ether_ifdetach(ifp);
360		device_printf(dev, "can't setup intr\n");
361		goto fail;
362	}
363
364	et_add_sysctls(sc);
365
366	return (0);
367fail:
368	et_detach(dev);
369	return (error);
370}
371
372static int
373et_detach(device_t dev)
374{
375	struct et_softc *sc = device_get_softc(dev);
376
377	if (device_is_attached(dev)) {
378		struct ifnet *ifp = sc->ifp;
379
380		ET_LOCK(sc);
381		et_stop(sc);
382		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
383		ET_UNLOCK(sc);
384
385		ether_ifdetach(ifp);
386	}
387
388	if (sc->sc_miibus != NULL)
389		device_delete_child(dev, sc->sc_miibus);
390	bus_generic_detach(dev);
391
392	if (sc->sc_irq_res != NULL) {
393		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
394				     sc->sc_irq_res);
395	}
396	if ((sc->sc_flags & ET_FLAG_MSI) != 0)
397		pci_release_msi(dev);
398
399	if (sc->sc_mem_res != NULL) {
400		bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
401				     sc->sc_mem_res);
402	}
403
404	if (sc->ifp != NULL)
405		if_free(sc->ifp);
406
407	et_dma_free(dev);
408
409	mtx_destroy(&sc->sc_mtx);
410
411	return (0);
412}
413
414static int
415et_shutdown(device_t dev)
416{
417	struct et_softc *sc = device_get_softc(dev);
418
419	ET_LOCK(sc);
420	et_stop(sc);
421	ET_UNLOCK(sc);
422	return (0);
423}
424
425static int
426et_miibus_readreg(device_t dev, int phy, int reg)
427{
428	struct et_softc *sc = device_get_softc(dev);
429	uint32_t val;
430	int i, ret;
431
432	/* Stop any pending operations */
433	CSR_WRITE_4(sc, ET_MII_CMD, 0);
434
435	val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;
436	val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK;
437	CSR_WRITE_4(sc, ET_MII_ADDR, val);
438
439	/* Start reading */
440	CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ);
441
442#define NRETRY	50
443
444	for (i = 0; i < NRETRY; ++i) {
445		val = CSR_READ_4(sc, ET_MII_IND);
446		if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0)
447			break;
448		DELAY(50);
449	}
450	if (i == NRETRY) {
451		if_printf(sc->ifp,
452			  "read phy %d, reg %d timed out\n", phy, reg);
453		ret = 0;
454		goto back;
455	}
456
457#undef NRETRY
458
459	val = CSR_READ_4(sc, ET_MII_STAT);
460	ret = val & ET_MII_STAT_VALUE_MASK;
461
462back:
463	/* Make sure that the current operation is stopped */
464	CSR_WRITE_4(sc, ET_MII_CMD, 0);
465	return (ret);
466}
467
468static int
469et_miibus_writereg(device_t dev, int phy, int reg, int val0)
470{
471	struct et_softc *sc = device_get_softc(dev);
472	uint32_t val;
473	int i;
474
475	/* Stop any pending operations */
476	CSR_WRITE_4(sc, ET_MII_CMD, 0);
477
478	val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;
479	val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK;
480	CSR_WRITE_4(sc, ET_MII_ADDR, val);
481
482	/* Start writing */
483	CSR_WRITE_4(sc, ET_MII_CTRL,
484	    (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK);
485
486#define NRETRY 100
487
488	for (i = 0; i < NRETRY; ++i) {
489		val = CSR_READ_4(sc, ET_MII_IND);
490		if ((val & ET_MII_IND_BUSY) == 0)
491			break;
492		DELAY(50);
493	}
494	if (i == NRETRY) {
495		if_printf(sc->ifp,
496			  "write phy %d, reg %d timed out\n", phy, reg);
497		et_miibus_readreg(dev, phy, reg);
498	}
499
500#undef NRETRY
501
502	/* Make sure that the current operation is stopped */
503	CSR_WRITE_4(sc, ET_MII_CMD, 0);
504	return (0);
505}
506
507static void
508et_miibus_statchg(device_t dev)
509{
510	et_setmedia(device_get_softc(dev));
511}
512
513static int
514et_ifmedia_upd_locked(struct ifnet *ifp)
515{
516	struct et_softc *sc = ifp->if_softc;
517	struct mii_data *mii = device_get_softc(sc->sc_miibus);
518
519	if (mii->mii_instance != 0) {
520		struct mii_softc *miisc;
521
522		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
523			mii_phy_reset(miisc);
524	}
525	mii_mediachg(mii);
526
527	return (0);
528}
529
530static int
531et_ifmedia_upd(struct ifnet *ifp)
532{
533	struct et_softc *sc = ifp->if_softc;
534	int res;
535
536	ET_LOCK(sc);
537	res = et_ifmedia_upd_locked(ifp);
538	ET_UNLOCK(sc);
539
540	return (res);
541}
542
543static void
544et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
545{
546	struct et_softc *sc = ifp->if_softc;
547	struct mii_data *mii = device_get_softc(sc->sc_miibus);
548
549	mii_pollstat(mii);
550	ifmr->ifm_active = mii->mii_media_active;
551	ifmr->ifm_status = mii->mii_media_status;
552}
553
554static void
555et_stop(struct et_softc *sc)
556{
557	struct ifnet *ifp = sc->ifp;
558
559	ET_LOCK_ASSERT(sc);
560
561	callout_stop(&sc->sc_tick);
562
563	et_stop_rxdma(sc);
564	et_stop_txdma(sc);
565
566	et_disable_intrs(sc);
567
568	et_free_tx_ring(sc);
569	et_free_rx_ring(sc);
570
571	et_reset(sc);
572
573	sc->sc_tx = 0;
574	sc->sc_tx_intr = 0;
575	sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED;
576
577	sc->watchdog_timer = 0;
578	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
579}
580
581static int
582et_bus_config(struct et_softc *sc)
583{
584	uint32_t val, max_plsz;
585	uint16_t ack_latency, replay_timer;
586
587	/*
588	 * Test whether EEPROM is valid
589	 * NOTE: Read twice to get the correct value
590	 */
591	pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1);
592	val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1);
593	if (val & ET_PCIM_EEPROM_STATUS_ERROR) {
594		device_printf(sc->dev, "EEPROM status error 0x%02x\n", val);
595		return (ENXIO);
596	}
597
598	/* TODO: LED */
599
600	if ((sc->sc_flags & ET_FLAG_PCIE) == 0)
601		return (0);
602
603	/*
604	 * Configure ACK latency and replay timer according to
605	 * max playload size
606	 */
607	val = pci_read_config(sc->dev,
608	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4);
609	max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD;
610
611	switch (max_plsz) {
612	case ET_PCIV_DEVICE_CAPS_PLSZ_128:
613		ack_latency = ET_PCIV_ACK_LATENCY_128;
614		replay_timer = ET_PCIV_REPLAY_TIMER_128;
615		break;
616
617	case ET_PCIV_DEVICE_CAPS_PLSZ_256:
618		ack_latency = ET_PCIV_ACK_LATENCY_256;
619		replay_timer = ET_PCIV_REPLAY_TIMER_256;
620		break;
621
622	default:
623		ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2);
624		replay_timer = pci_read_config(sc->dev,
625		    ET_PCIR_REPLAY_TIMER, 2);
626		device_printf(sc->dev, "ack latency %u, replay timer %u\n",
627			      ack_latency, replay_timer);
628		break;
629	}
630	if (ack_latency != 0) {
631		pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2);
632		pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer,
633		    2);
634	}
635
636	/*
637	 * Set L0s and L1 latency timer to 2us
638	 */
639	val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4);
640	val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT);
641	/* L0s exit latency : 2us */
642	val |= 0x00005000;
643	/* L1 exit latency : 2us */
644	val |= 0x00028000;
645	pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4);
646
647	/*
648	 * Set max read request size to 2048 bytes
649	 */
650	val = pci_read_config(sc->dev,
651	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
652	val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
653	val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
654	pci_write_config(sc->dev,
655	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
656
657	return (0);
658}
659
660static void
661et_get_eaddr(device_t dev, uint8_t eaddr[])
662{
663	uint32_t val;
664	int i;
665
666	val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4);
667	for (i = 0; i < 4; ++i)
668		eaddr[i] = (val >> (8 * i)) & 0xff;
669
670	val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2);
671	for (; i < ETHER_ADDR_LEN; ++i)
672		eaddr[i] = (val >> (8 * (i - 4))) & 0xff;
673}
674
675static void
676et_reset(struct et_softc *sc)
677{
678	CSR_WRITE_4(sc, ET_MAC_CFG1,
679		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
680		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
681		    ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
682
683	CSR_WRITE_4(sc, ET_SWRST,
684		    ET_SWRST_TXDMA | ET_SWRST_RXDMA |
685		    ET_SWRST_TXMAC | ET_SWRST_RXMAC |
686		    ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC);
687
688	CSR_WRITE_4(sc, ET_MAC_CFG1,
689		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
690		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC);
691	CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
692}
693
694static void
695et_disable_intrs(struct et_softc *sc)
696{
697	CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
698}
699
700static void
701et_enable_intrs(struct et_softc *sc, uint32_t intrs)
702{
703	CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs);
704}
705
706static int
707et_dma_alloc(device_t dev)
708{
709	struct et_softc *sc = device_get_softc(dev);
710	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
711	struct et_txstatus_data *txsd = &sc->sc_tx_status;
712	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
713	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
714	int i, error;
715
716	/*
717	 * Create top level DMA tag
718	 */
719	error = bus_dma_tag_create(NULL, 1, 0,
720				   BUS_SPACE_MAXADDR_32BIT,
721				   BUS_SPACE_MAXADDR,
722				   NULL, NULL,
723				   MAXBSIZE,
724				   BUS_SPACE_UNRESTRICTED,
725				   BUS_SPACE_MAXSIZE_32BIT,
726				   0, NULL, NULL, &sc->sc_dtag);
727	if (error) {
728		device_printf(dev, "can't create DMA tag\n");
729		return (error);
730	}
731
732	/*
733	 * Create TX ring DMA stuffs
734	 */
735	error = et_dma_mem_create(dev, ET_TX_RING_SIZE, &tx_ring->tr_dtag,
736				  (void **)&tx_ring->tr_desc,
737				  &tx_ring->tr_paddr, &tx_ring->tr_dmap);
738	if (error) {
739		device_printf(dev, "can't create TX ring DMA stuffs\n");
740		return (error);
741	}
742
743	/*
744	 * Create TX status DMA stuffs
745	 */
746	error = et_dma_mem_create(dev, sizeof(uint32_t), &txsd->txsd_dtag,
747				  (void **)&txsd->txsd_status,
748				  &txsd->txsd_paddr, &txsd->txsd_dmap);
749	if (error) {
750		device_printf(dev, "can't create TX status DMA stuffs\n");
751		return (error);
752	}
753
754	/*
755	 * Create DMA stuffs for RX rings
756	 */
757	for (i = 0; i < ET_RX_NRING; ++i) {
758		static const uint32_t rx_ring_posreg[ET_RX_NRING] =
759		{ ET_RX_RING0_POS, ET_RX_RING1_POS };
760
761		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
762
763		error = et_dma_mem_create(dev, ET_RX_RING_SIZE,
764					  &rx_ring->rr_dtag,
765					  (void **)&rx_ring->rr_desc,
766					  &rx_ring->rr_paddr,
767					  &rx_ring->rr_dmap);
768		if (error) {
769			device_printf(dev, "can't create DMA stuffs for "
770				      "the %d RX ring\n", i);
771			return (error);
772		}
773		rx_ring->rr_posreg = rx_ring_posreg[i];
774	}
775
776	/*
777	 * Create RX stat ring DMA stuffs
778	 */
779	error = et_dma_mem_create(dev, ET_RXSTAT_RING_SIZE,
780				  &rxst_ring->rsr_dtag,
781				  (void **)&rxst_ring->rsr_stat,
782				  &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap);
783	if (error) {
784		device_printf(dev, "can't create RX stat ring DMA stuffs\n");
785		return (error);
786	}
787
788	/*
789	 * Create RX status DMA stuffs
790	 */
791	error = et_dma_mem_create(dev, sizeof(struct et_rxstatus),
792				  &rxsd->rxsd_dtag,
793				  (void **)&rxsd->rxsd_status,
794				  &rxsd->rxsd_paddr, &rxsd->rxsd_dmap);
795	if (error) {
796		device_printf(dev, "can't create RX status DMA stuffs\n");
797		return (error);
798	}
799
800	/*
801	 * Create mbuf DMA stuffs
802	 */
803	error = et_dma_mbuf_create(dev);
804	if (error)
805		return (error);
806
807	return (0);
808}
809
810static void
811et_dma_free(device_t dev)
812{
813	struct et_softc *sc = device_get_softc(dev);
814	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
815	struct et_txstatus_data *txsd = &sc->sc_tx_status;
816	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
817	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
818	int i, rx_done[ET_RX_NRING];
819
820	/*
821	 * Destroy TX ring DMA stuffs
822	 */
823	et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc,
824			   tx_ring->tr_dmap);
825
826	/*
827	 * Destroy TX status DMA stuffs
828	 */
829	et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status,
830			   txsd->txsd_dmap);
831
832	/*
833	 * Destroy DMA stuffs for RX rings
834	 */
835	for (i = 0; i < ET_RX_NRING; ++i) {
836		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
837
838		et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc,
839				   rx_ring->rr_dmap);
840	}
841
842	/*
843	 * Destroy RX stat ring DMA stuffs
844	 */
845	et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat,
846			   rxst_ring->rsr_dmap);
847
848	/*
849	 * Destroy RX status DMA stuffs
850	 */
851	et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status,
852			   rxsd->rxsd_dmap);
853
854	/*
855	 * Destroy mbuf DMA stuffs
856	 */
857	for (i = 0; i < ET_RX_NRING; ++i)
858		rx_done[i] = ET_RX_NDESC;
859	et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done);
860
861	/*
862	 * Destroy top level DMA tag
863	 */
864	if (sc->sc_dtag != NULL)
865		bus_dma_tag_destroy(sc->sc_dtag);
866}
867
868static int
869et_dma_mbuf_create(device_t dev)
870{
871	struct et_softc *sc = device_get_softc(dev);
872	struct et_txbuf_data *tbd = &sc->sc_tx_data;
873	int i, error, rx_done[ET_RX_NRING];
874
875	/*
876	 * Create mbuf DMA tag
877	 */
878	error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
879				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
880				   NULL, NULL,
881				   ET_JUMBO_FRAMELEN, ET_NSEG_MAX,
882				   BUS_SPACE_MAXSIZE_32BIT,
883				   BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_mbuf_dtag);
884	if (error) {
885		device_printf(dev, "can't create mbuf DMA tag\n");
886		return (error);
887	}
888
889	/*
890	 * Create spare DMA map for RX mbufs
891	 */
892	error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, &sc->sc_mbuf_tmp_dmap);
893	if (error) {
894		device_printf(dev, "can't create spare mbuf DMA map\n");
895		bus_dma_tag_destroy(sc->sc_mbuf_dtag);
896		sc->sc_mbuf_dtag = NULL;
897		return (error);
898	}
899
900	/*
901	 * Create DMA maps for RX mbufs
902	 */
903	bzero(rx_done, sizeof(rx_done));
904	for (i = 0; i < ET_RX_NRING; ++i) {
905		struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
906		int j;
907
908		for (j = 0; j < ET_RX_NDESC; ++j) {
909			error = bus_dmamap_create(sc->sc_mbuf_dtag, 0,
910				&rbd->rbd_buf[j].rb_dmap);
911			if (error) {
912				device_printf(dev, "can't create %d RX mbuf "
913					      "for %d RX ring\n", j, i);
914				rx_done[i] = j;
915				et_dma_mbuf_destroy(dev, 0, rx_done);
916				return (error);
917			}
918		}
919		rx_done[i] = ET_RX_NDESC;
920
921		rbd->rbd_softc = sc;
922		rbd->rbd_ring = &sc->sc_rx_ring[i];
923	}
924
925	/*
926	 * Create DMA maps for TX mbufs
927	 */
928	for (i = 0; i < ET_TX_NDESC; ++i) {
929		error = bus_dmamap_create(sc->sc_mbuf_dtag, 0,
930					  &tbd->tbd_buf[i].tb_dmap);
931		if (error) {
932			device_printf(dev, "can't create %d TX mbuf "
933				      "DMA map\n", i);
934			et_dma_mbuf_destroy(dev, i, rx_done);
935			return (error);
936		}
937	}
938
939	return (0);
940}
941
942static void
943et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[])
944{
945	struct et_softc *sc = device_get_softc(dev);
946	struct et_txbuf_data *tbd = &sc->sc_tx_data;
947	int i;
948
949	if (sc->sc_mbuf_dtag == NULL)
950		return;
951
952	/*
953	 * Destroy DMA maps for RX mbufs
954	 */
955	for (i = 0; i < ET_RX_NRING; ++i) {
956		struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
957		int j;
958
959		for (j = 0; j < rx_done[i]; ++j) {
960			struct et_rxbuf *rb = &rbd->rbd_buf[j];
961
962			KASSERT(rb->rb_mbuf == NULL,
963			    ("RX mbuf in %d RX ring is not freed yet\n", i));
964			bus_dmamap_destroy(sc->sc_mbuf_dtag, rb->rb_dmap);
965		}
966	}
967
968	/*
969	 * Destroy DMA maps for TX mbufs
970	 */
971	for (i = 0; i < tx_done; ++i) {
972		struct et_txbuf *tb = &tbd->tbd_buf[i];
973
974		KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n"));
975		bus_dmamap_destroy(sc->sc_mbuf_dtag, tb->tb_dmap);
976	}
977
978	/*
979	 * Destroy spare mbuf DMA map
980	 */
981	bus_dmamap_destroy(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap);
982
983	/*
984	 * Destroy mbuf DMA tag
985	 */
986	bus_dma_tag_destroy(sc->sc_mbuf_dtag);
987	sc->sc_mbuf_dtag = NULL;
988}
989
990static int
991et_dma_mem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag,
992		  void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap)
993{
994	struct et_softc *sc = device_get_softc(dev);
995	int error;
996
997	error = bus_dma_tag_create(sc->sc_dtag, ET_ALIGN, 0,
998				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
999				   NULL, NULL,
1000				   size, 1, BUS_SPACE_MAXSIZE_32BIT,
1001				   0, NULL, NULL, dtag);
1002	if (error) {
1003		device_printf(dev, "can't create DMA tag\n");
1004		return (error);
1005	}
1006
1007	error = bus_dmamem_alloc(*dtag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1008				 dmap);
1009	if (error) {
1010		device_printf(dev, "can't allocate DMA mem\n");
1011		bus_dma_tag_destroy(*dtag);
1012		*dtag = NULL;
1013		return (error);
1014	}
1015
1016	error = bus_dmamap_load(*dtag, *dmap, *addr, size,
1017				et_dma_ring_addr, paddr, BUS_DMA_WAITOK);
1018	if (error) {
1019		device_printf(dev, "can't load DMA mem\n");
1020		bus_dmamem_free(*dtag, *addr, *dmap);
1021		bus_dma_tag_destroy(*dtag);
1022		*dtag = NULL;
1023		return (error);
1024	}
1025	return (0);
1026}
1027
1028static void
1029et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
1030{
1031	if (dtag != NULL) {
1032		bus_dmamap_unload(dtag, dmap);
1033		bus_dmamem_free(dtag, addr, dmap);
1034		bus_dma_tag_destroy(dtag);
1035	}
1036}
1037
1038static void
1039et_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
1040{
1041	KASSERT(nseg == 1, ("too many segments\n"));
1042	*((bus_addr_t *)arg) = seg->ds_addr;
1043}
1044
1045static void
1046et_chip_attach(struct et_softc *sc)
1047{
1048	uint32_t val;
1049
1050	/*
1051	 * Perform minimal initialization
1052	 */
1053
1054	/* Disable loopback */
1055	CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1056
1057	/* Reset MAC */
1058	CSR_WRITE_4(sc, ET_MAC_CFG1,
1059		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1060		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1061		    ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1062
1063	/*
1064	 * Setup half duplex mode
1065	 */
1066	val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) |
1067	    (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) |
1068	    (55 << ET_MAC_HDX_COLLWIN_SHIFT) |
1069	    ET_MAC_HDX_EXC_DEFER;
1070	CSR_WRITE_4(sc, ET_MAC_HDX, val);
1071
1072	/* Clear MAC control */
1073	CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1074
1075	/* Reset MII */
1076	CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1077
1078	/* Bring MAC out of reset state */
1079	CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1080
1081	/* Enable memory controllers */
1082	CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1083}
1084
1085static void
1086et_intr(void *xsc)
1087{
1088	struct et_softc *sc = xsc;
1089	struct ifnet *ifp;
1090	uint32_t intrs;
1091
1092	ET_LOCK(sc);
1093	ifp = sc->ifp;
1094	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1095		ET_UNLOCK(sc);
1096		return;
1097	}
1098
1099	et_disable_intrs(sc);
1100
1101	intrs = CSR_READ_4(sc, ET_INTR_STATUS);
1102	intrs &= ET_INTRS;
1103	if (intrs == 0)	/* Not interested */
1104		goto back;
1105
1106	if (intrs & ET_INTR_RXEOF)
1107		et_rxeof(sc);
1108	if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER))
1109		et_txeof(sc);
1110	if (intrs & ET_INTR_TIMER)
1111		CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1112back:
1113	et_enable_intrs(sc, ET_INTRS);
1114	ET_UNLOCK(sc);
1115}
1116
1117static void
1118et_init_locked(struct et_softc *sc)
1119{
1120	struct ifnet *ifp = sc->ifp;
1121	const struct et_bsize *arr;
1122	int error, i;
1123
1124	ET_LOCK_ASSERT(sc);
1125
1126	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1127		return;
1128
1129	et_stop(sc);
1130
1131	arr = et_bufsize_std;
1132	for (i = 0; i < ET_RX_NRING; ++i) {
1133		sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize;
1134		sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf;
1135	}
1136
1137	error = et_init_tx_ring(sc);
1138	if (error)
1139		goto back;
1140
1141	error = et_init_rx_ring(sc);
1142	if (error)
1143		goto back;
1144
1145	error = et_chip_init(sc);
1146	if (error)
1147		goto back;
1148
1149	error = et_enable_txrx(sc, 1);
1150	if (error)
1151		goto back;
1152
1153	et_enable_intrs(sc, ET_INTRS);
1154
1155	callout_reset(&sc->sc_tick, hz, et_tick, sc);
1156
1157	CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1158
1159	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1160	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1161back:
1162	if (error)
1163		et_stop(sc);
1164}
1165
1166static void
1167et_init(void *xsc)
1168{
1169	struct et_softc *sc = xsc;
1170
1171	ET_LOCK(sc);
1172	et_init_locked(sc);
1173	ET_UNLOCK(sc);
1174}
1175
1176static int
1177et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1178{
1179	struct et_softc *sc = ifp->if_softc;
1180	struct mii_data *mii = device_get_softc(sc->sc_miibus);
1181	struct ifreq *ifr = (struct ifreq *)data;
1182	int error = 0, mask, max_framelen;
1183
1184/* XXX LOCKSUSED */
1185	switch (cmd) {
1186	case SIOCSIFFLAGS:
1187		ET_LOCK(sc);
1188		if (ifp->if_flags & IFF_UP) {
1189			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1190				if ((ifp->if_flags ^ sc->sc_if_flags) &
1191				(IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST))
1192					et_setmulti(sc);
1193			} else {
1194				et_init_locked(sc);
1195			}
1196		} else {
1197			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1198				et_stop(sc);
1199		}
1200		sc->sc_if_flags = ifp->if_flags;
1201		ET_UNLOCK(sc);
1202		break;
1203
1204	case SIOCSIFMEDIA:
1205	case SIOCGIFMEDIA:
1206		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1207		break;
1208
1209	case SIOCADDMULTI:
1210	case SIOCDELMULTI:
1211		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1212			ET_LOCK(sc);
1213			et_setmulti(sc);
1214			ET_UNLOCK(sc);
1215			error = 0;
1216		}
1217		break;
1218
1219	case SIOCSIFMTU:
1220#if 0
1221		if (sc->sc_flags & ET_FLAG_JUMBO)
1222			max_framelen = ET_JUMBO_FRAMELEN;
1223		else
1224#endif
1225			max_framelen = MCLBYTES - 1;
1226
1227		if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) {
1228			error = EOPNOTSUPP;
1229			break;
1230		}
1231
1232		if (ifp->if_mtu != ifr->ifr_mtu) {
1233			ifp->if_mtu = ifr->ifr_mtu;
1234			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1235			et_init(sc);
1236		}
1237		break;
1238
1239	case SIOCSIFCAP:
1240		ET_LOCK(sc);
1241		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1242		if ((mask & IFCAP_TXCSUM) != 0 &&
1243		    (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1244			ifp->if_capenable ^= IFCAP_TXCSUM;
1245			if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1246				ifp->if_hwassist |= ET_CSUM_FEATURES;
1247			else
1248				ifp->if_hwassist &= ~ET_CSUM_FEATURES;
1249		}
1250		ET_UNLOCK(sc);
1251		break;
1252
1253	default:
1254		error = ether_ioctl(ifp, cmd, data);
1255		break;
1256	}
1257	return (error);
1258}
1259
1260static void
1261et_start_locked(struct ifnet *ifp)
1262{
1263	struct et_softc *sc = ifp->if_softc;
1264	struct et_txbuf_data *tbd;
1265	int trans;
1266
1267	ET_LOCK_ASSERT(sc);
1268	tbd = &sc->sc_tx_data;
1269
1270	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
1271		return;
1272
1273	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
1274		return;
1275
1276	trans = 0;
1277	for (;;) {
1278		struct mbuf *m;
1279
1280		if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) {
1281			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1282			break;
1283		}
1284
1285		IFQ_DEQUEUE(&ifp->if_snd, m);
1286		if (m == NULL)
1287			break;
1288
1289		if (et_encap(sc, &m)) {
1290			ifp->if_oerrors++;
1291			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1292			break;
1293		}
1294		trans = 1;
1295
1296		BPF_MTAP(ifp, m);
1297	}
1298
1299	if (trans)
1300		sc->watchdog_timer = 5;
1301}
1302
1303static void
1304et_start(struct ifnet *ifp)
1305{
1306	struct et_softc *sc = ifp->if_softc;
1307
1308	ET_LOCK(sc);
1309	et_start_locked(ifp);
1310	ET_UNLOCK(sc);
1311}
1312
1313static void
1314et_watchdog(struct et_softc *sc)
1315{
1316	ET_LOCK_ASSERT(sc);
1317
1318	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
1319		return;
1320
1321	if_printf(sc->ifp, "watchdog timed out\n");
1322
1323	sc->ifp->if_oerrors++;
1324	sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1325	et_init_locked(sc);
1326	et_start_locked(sc->ifp);
1327}
1328
1329static int
1330et_stop_rxdma(struct et_softc *sc)
1331{
1332	CSR_WRITE_4(sc, ET_RXDMA_CTRL,
1333		    ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE);
1334
1335	DELAY(5);
1336	if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {
1337		if_printf(sc->ifp, "can't stop RX DMA engine\n");
1338		return (ETIMEDOUT);
1339	}
1340	return (0);
1341}
1342
1343static int
1344et_stop_txdma(struct et_softc *sc)
1345{
1346	CSR_WRITE_4(sc, ET_TXDMA_CTRL,
1347		    ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT);
1348	return (0);
1349}
1350
1351static void
1352et_free_tx_ring(struct et_softc *sc)
1353{
1354	struct et_txbuf_data *tbd = &sc->sc_tx_data;
1355	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1356	int i;
1357
1358	for (i = 0; i < ET_TX_NDESC; ++i) {
1359		struct et_txbuf *tb = &tbd->tbd_buf[i];
1360
1361		if (tb->tb_mbuf != NULL) {
1362			bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap);
1363			m_freem(tb->tb_mbuf);
1364			tb->tb_mbuf = NULL;
1365		}
1366	}
1367
1368	bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1369	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
1370			BUS_DMASYNC_PREWRITE);
1371}
1372
1373static void
1374et_free_rx_ring(struct et_softc *sc)
1375{
1376	int n;
1377
1378	for (n = 0; n < ET_RX_NRING; ++n) {
1379		struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1380		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n];
1381		int i;
1382
1383		for (i = 0; i < ET_RX_NDESC; ++i) {
1384			struct et_rxbuf *rb = &rbd->rbd_buf[i];
1385
1386			if (rb->rb_mbuf != NULL) {
1387				bus_dmamap_unload(sc->sc_mbuf_dtag,
1388			  	    rb->rb_dmap);
1389				m_freem(rb->rb_mbuf);
1390				rb->rb_mbuf = NULL;
1391			}
1392		}
1393
1394		bzero(rx_ring->rr_desc, ET_RX_RING_SIZE);
1395		bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap,
1396				BUS_DMASYNC_PREWRITE);
1397	}
1398}
1399
1400static void
1401et_setmulti(struct et_softc *sc)
1402{
1403	struct ifnet *ifp;
1404	uint32_t hash[4] = { 0, 0, 0, 0 };
1405	uint32_t rxmac_ctrl, pktfilt;
1406	struct ifmultiaddr *ifma;
1407	int i, count;
1408
1409	ET_LOCK_ASSERT(sc);
1410	ifp = sc->ifp;
1411
1412	pktfilt = CSR_READ_4(sc, ET_PKTFILT);
1413	rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);
1414
1415	pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST);
1416	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1417		rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT;
1418		goto back;
1419	}
1420
1421	count = 0;
1422	if_maddr_rlock(ifp);
1423	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1424		uint32_t *hp, h;
1425
1426		if (ifma->ifma_addr->sa_family != AF_LINK)
1427			continue;
1428
1429		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1430				   ifma->ifma_addr), ETHER_ADDR_LEN);
1431		h = (h & 0x3f800000) >> 23;
1432
1433		hp = &hash[0];
1434		if (h >= 32 && h < 64) {
1435			h -= 32;
1436			hp = &hash[1];
1437		} else if (h >= 64 && h < 96) {
1438			h -= 64;
1439			hp = &hash[2];
1440		} else if (h >= 96) {
1441			h -= 96;
1442			hp = &hash[3];
1443		}
1444		*hp |= (1 << h);
1445
1446		++count;
1447	}
1448	if_maddr_runlock(ifp);
1449
1450	for (i = 0; i < 4; ++i)
1451		CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]);
1452
1453	if (count > 0)
1454		pktfilt |= ET_PKTFILT_MCAST;
1455	rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT;
1456back:
1457	CSR_WRITE_4(sc, ET_PKTFILT, pktfilt);
1458	CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl);
1459}
1460
1461static int
1462et_chip_init(struct et_softc *sc)
1463{
1464	struct ifnet *ifp = sc->ifp;
1465	uint32_t rxq_end;
1466	int error, frame_len, rxmem_size;
1467
1468	/*
1469	 * Split 16Kbytes internal memory between TX and RX
1470	 * according to frame length.
1471	 */
1472	frame_len = ET_FRAMELEN(ifp->if_mtu);
1473	if (frame_len < 2048) {
1474		rxmem_size = ET_MEM_RXSIZE_DEFAULT;
1475	} else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) {
1476		rxmem_size = ET_MEM_SIZE / 2;
1477	} else {
1478		rxmem_size = ET_MEM_SIZE -
1479		roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT);
1480	}
1481	rxq_end = ET_QUEUE_ADDR(rxmem_size);
1482
1483	CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START);
1484	CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end);
1485	CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1);
1486	CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END);
1487
1488	/* No loopback */
1489	CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1490
1491	/* Clear MSI configure */
1492	if ((sc->sc_flags & ET_FLAG_MSI) == 0)
1493		CSR_WRITE_4(sc, ET_MSI_CFG, 0);
1494
1495	/* Disable timer */
1496	CSR_WRITE_4(sc, ET_TIMER, 0);
1497
1498	/* Initialize MAC */
1499	et_init_mac(sc);
1500
1501	/* Enable memory controllers */
1502	CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1503
1504	/* Initialize RX MAC */
1505	et_init_rxmac(sc);
1506
1507	/* Initialize TX MAC */
1508	et_init_txmac(sc);
1509
1510	/* Initialize RX DMA engine */
1511	error = et_init_rxdma(sc);
1512	if (error)
1513		return (error);
1514
1515	/* Initialize TX DMA engine */
1516	error = et_init_txdma(sc);
1517	if (error)
1518		return (error);
1519
1520	return (0);
1521}
1522
1523static int
1524et_init_tx_ring(struct et_softc *sc)
1525{
1526	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1527	struct et_txstatus_data *txsd = &sc->sc_tx_status;
1528	struct et_txbuf_data *tbd = &sc->sc_tx_data;
1529
1530	bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1531	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
1532			BUS_DMASYNC_PREWRITE);
1533
1534	tbd->tbd_start_index = 0;
1535	tbd->tbd_start_wrap = 0;
1536	tbd->tbd_used = 0;
1537
1538	bzero(txsd->txsd_status, sizeof(uint32_t));
1539	bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap,
1540			BUS_DMASYNC_PREWRITE);
1541	return (0);
1542}
1543
1544static int
1545et_init_rx_ring(struct et_softc *sc)
1546{
1547	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1548	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1549	int n;
1550
1551	for (n = 0; n < ET_RX_NRING; ++n) {
1552		struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1553		int i, error;
1554
1555		for (i = 0; i < ET_RX_NDESC; ++i) {
1556			error = rbd->rbd_newbuf(rbd, i, 1);
1557			if (error) {
1558				if_printf(sc->ifp, "%d ring %d buf, "
1559					  "newbuf failed: %d\n", n, i, error);
1560				return (error);
1561			}
1562		}
1563	}
1564
1565	bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus));
1566	bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap,
1567			BUS_DMASYNC_PREWRITE);
1568
1569	bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE);
1570	bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap,
1571			BUS_DMASYNC_PREWRITE);
1572
1573	return (0);
1574}
1575
1576static void
1577et_dma_buf_addr(void *xctx, bus_dma_segment_t *segs, int nsegs,
1578		bus_size_t mapsz __unused, int error)
1579{
1580	struct et_dmamap_ctx *ctx = xctx;
1581	int i;
1582
1583	if (error)
1584		return;
1585
1586	if (nsegs > ctx->nsegs) {
1587		ctx->nsegs = 0;
1588		return;
1589	}
1590
1591	ctx->nsegs = nsegs;
1592	for (i = 0; i < nsegs; ++i)
1593		ctx->segs[i] = segs[i];
1594}
1595
1596static int
1597et_init_rxdma(struct et_softc *sc)
1598{
1599	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1600	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1601	struct et_rxdesc_ring *rx_ring;
1602	int error;
1603
1604	error = et_stop_rxdma(sc);
1605	if (error) {
1606		if_printf(sc->ifp, "can't init RX DMA engine\n");
1607		return (error);
1608	}
1609
1610	/*
1611	 * Install RX status
1612	 */
1613	CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr));
1614	CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr));
1615
1616	/*
1617	 * Install RX stat ring
1618	 */
1619	CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr));
1620	CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr));
1621	CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1);
1622	CSR_WRITE_4(sc, ET_RXSTAT_POS, 0);
1623	CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1);
1624
1625	/* Match ET_RXSTAT_POS */
1626	rxst_ring->rsr_index = 0;
1627	rxst_ring->rsr_wrap = 0;
1628
1629	/*
1630	 * Install the 2nd RX descriptor ring
1631	 */
1632	rx_ring = &sc->sc_rx_ring[1];
1633	CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1634	CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1635	CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1);
1636	CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP);
1637	CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1638
1639	/* Match ET_RX_RING1_POS */
1640	rx_ring->rr_index = 0;
1641	rx_ring->rr_wrap = 1;
1642
1643	/*
1644	 * Install the 1st RX descriptor ring
1645	 */
1646	rx_ring = &sc->sc_rx_ring[0];
1647	CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1648	CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1649	CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1);
1650	CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP);
1651	CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1652
1653	/* Match ET_RX_RING0_POS */
1654	rx_ring->rr_index = 0;
1655	rx_ring->rr_wrap = 1;
1656
1657	/*
1658	 * RX intr moderation
1659	 */
1660	CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts);
1661	CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay);
1662
1663	return (0);
1664}
1665
1666static int
1667et_init_txdma(struct et_softc *sc)
1668{
1669	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1670	struct et_txstatus_data *txsd = &sc->sc_tx_status;
1671	int error;
1672
1673	error = et_stop_txdma(sc);
1674	if (error) {
1675		if_printf(sc->ifp, "can't init TX DMA engine\n");
1676		return (error);
1677	}
1678
1679	/*
1680	 * Install TX descriptor ring
1681	 */
1682	CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr));
1683	CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr));
1684	CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1);
1685
1686	/*
1687	 * Install TX status
1688	 */
1689	CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr));
1690	CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr));
1691
1692	CSR_WRITE_4(sc, ET_TX_READY_POS, 0);
1693
1694	/* Match ET_TX_READY_POS */
1695	tx_ring->tr_ready_index = 0;
1696	tx_ring->tr_ready_wrap = 0;
1697
1698	return (0);
1699}
1700
1701static void
1702et_init_mac(struct et_softc *sc)
1703{
1704	struct ifnet *ifp = sc->ifp;
1705	const uint8_t *eaddr = IF_LLADDR(ifp);
1706	uint32_t val;
1707
1708	/* Reset MAC */
1709	CSR_WRITE_4(sc, ET_MAC_CFG1,
1710		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1711		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1712		    ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1713
1714	/*
1715	 * Setup inter packet gap
1716	 */
1717	val = (56 << ET_IPG_NONB2B_1_SHIFT) |
1718	    (88 << ET_IPG_NONB2B_2_SHIFT) |
1719	    (80 << ET_IPG_MINIFG_SHIFT) |
1720	    (96 << ET_IPG_B2B_SHIFT);
1721	CSR_WRITE_4(sc, ET_IPG, val);
1722
1723	/*
1724	 * Setup half duplex mode
1725	 */
1726	val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) |
1727	    (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) |
1728	    (55 << ET_MAC_HDX_COLLWIN_SHIFT) |
1729	    ET_MAC_HDX_EXC_DEFER;
1730	CSR_WRITE_4(sc, ET_MAC_HDX, val);
1731
1732	/* Clear MAC control */
1733	CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1734
1735	/* Reset MII */
1736	CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1737
1738	/*
1739	 * Set MAC address
1740	 */
1741	val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24);
1742	CSR_WRITE_4(sc, ET_MAC_ADDR1, val);
1743	val = (eaddr[0] << 16) | (eaddr[1] << 24);
1744	CSR_WRITE_4(sc, ET_MAC_ADDR2, val);
1745
1746	/* Set max frame length */
1747	CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu));
1748
1749	/* Bring MAC out of reset state */
1750	CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1751}
1752
1753static void
1754et_init_rxmac(struct et_softc *sc)
1755{
1756	struct ifnet *ifp = sc->ifp;
1757	const uint8_t *eaddr = IF_LLADDR(ifp);
1758	uint32_t val;
1759	int i;
1760
1761	/* Disable RX MAC and WOL */
1762	CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE);
1763
1764	/*
1765	 * Clear all WOL related registers
1766	 */
1767	for (i = 0; i < 3; ++i)
1768		CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0);
1769	for (i = 0; i < 20; ++i)
1770		CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0);
1771
1772	/*
1773	 * Set WOL source address.  XXX is this necessary?
1774	 */
1775	val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5];
1776	CSR_WRITE_4(sc, ET_WOL_SA_LO, val);
1777	val = (eaddr[0] << 8) | eaddr[1];
1778	CSR_WRITE_4(sc, ET_WOL_SA_HI, val);
1779
1780	/* Clear packet filters */
1781	CSR_WRITE_4(sc, ET_PKTFILT, 0);
1782
1783	/* No ucast filtering */
1784	CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0);
1785	CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0);
1786	CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0);
1787
1788	if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) {
1789		/*
1790		 * In order to transmit jumbo packets greater than
1791		 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between
1792		 * RX MAC and RX DMA needs to be reduced in size to
1793		 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen).  In
1794		 * order to implement this, we must use "cut through"
1795		 * mode in the RX MAC, which chops packets down into
1796		 * segments.  In this case we selected 256 bytes,
1797		 * since this is the size of the PCI-Express TLP's
1798		 * that the ET1310 uses.
1799		 */
1800		val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) |
1801		      ET_RXMAC_MC_SEGSZ_ENABLE;
1802	} else {
1803		val = 0;
1804	}
1805	CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val);
1806
1807	CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0);
1808
1809	/* Initialize RX MAC management register */
1810	CSR_WRITE_4(sc, ET_RXMAC_MGT, 0);
1811
1812	CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0);
1813
1814	CSR_WRITE_4(sc, ET_RXMAC_MGT,
1815		    ET_RXMAC_MGT_PASS_ECRC |
1816		    ET_RXMAC_MGT_PASS_ELEN |
1817		    ET_RXMAC_MGT_PASS_ETRUNC |
1818		    ET_RXMAC_MGT_CHECK_PKT);
1819
1820	/*
1821	 * Configure runt filtering (may not work on certain chip generation)
1822	 */
1823	val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) &
1824	    ET_PKTFILT_MINLEN_MASK;
1825	val |= ET_PKTFILT_FRAG;
1826	CSR_WRITE_4(sc, ET_PKTFILT, val);
1827
1828	/* Enable RX MAC but leave WOL disabled */
1829	CSR_WRITE_4(sc, ET_RXMAC_CTRL,
1830		    ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE);
1831
1832	/*
1833	 * Setup multicast hash and allmulti/promisc mode
1834	 */
1835	et_setmulti(sc);
1836}
1837
1838static void
1839et_init_txmac(struct et_softc *sc)
1840{
1841	/* Disable TX MAC and FC(?) */
1842	CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
1843
1844	/* No flow control yet */
1845	CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
1846
1847	/* Enable TX MAC but leave FC(?) diabled */
1848	CSR_WRITE_4(sc, ET_TXMAC_CTRL,
1849		    ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE);
1850}
1851
1852static int
1853et_start_rxdma(struct et_softc *sc)
1854{
1855	uint32_t val = 0;
1856
1857	val |= (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) |
1858	       ET_RXDMA_CTRL_RING0_ENABLE;
1859	val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) |
1860	       ET_RXDMA_CTRL_RING1_ENABLE;
1861
1862	CSR_WRITE_4(sc, ET_RXDMA_CTRL, val);
1863
1864	DELAY(5);
1865
1866	if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {
1867		if_printf(sc->ifp, "can't start RX DMA engine\n");
1868		return (ETIMEDOUT);
1869	}
1870	return (0);
1871}
1872
1873static int
1874et_start_txdma(struct et_softc *sc)
1875{
1876	CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT);
1877	return (0);
1878}
1879
1880static int
1881et_enable_txrx(struct et_softc *sc, int media_upd)
1882{
1883	struct ifnet *ifp = sc->ifp;
1884	uint32_t val;
1885	int i, error;
1886
1887	val = CSR_READ_4(sc, ET_MAC_CFG1);
1888	val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
1889	val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
1890		 ET_MAC_CFG1_LOOPBACK);
1891	CSR_WRITE_4(sc, ET_MAC_CFG1, val);
1892
1893	if (media_upd)
1894		et_ifmedia_upd_locked(ifp);
1895	else
1896		et_setmedia(sc);
1897
1898#define NRETRY	50
1899
1900	for (i = 0; i < NRETRY; ++i) {
1901		val = CSR_READ_4(sc, ET_MAC_CFG1);
1902		if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
1903		    (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
1904			break;
1905
1906		DELAY(100);
1907	}
1908	if (i == NRETRY) {
1909		if_printf(ifp, "can't enable RX/TX\n");
1910		return (0);
1911	}
1912	sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
1913
1914#undef NRETRY
1915
1916	/*
1917	 * Start TX/RX DMA engine
1918	 */
1919	error = et_start_rxdma(sc);
1920	if (error)
1921		return (error);
1922
1923	error = et_start_txdma(sc);
1924	if (error)
1925		return (error);
1926
1927	return (0);
1928}
1929
1930static void
1931et_rxeof(struct et_softc *sc)
1932{
1933	struct ifnet *ifp;
1934	struct et_rxstatus_data *rxsd;
1935	struct et_rxstat_ring *rxst_ring;
1936	uint32_t rxs_stat_ring, rxst_info2;
1937	int rxst_wrap, rxst_index;
1938
1939	ET_LOCK_ASSERT(sc);
1940	ifp = sc->ifp;
1941	rxsd = &sc->sc_rx_status;
1942	rxst_ring = &sc->sc_rxstat_ring;
1943
1944	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
1945		return;
1946
1947	bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap,
1948			BUS_DMASYNC_POSTREAD);
1949	bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap,
1950			BUS_DMASYNC_POSTREAD);
1951
1952	rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring);
1953	rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0;
1954	rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >>
1955	    ET_RXS_STATRING_INDEX_SHIFT;
1956
1957	while (rxst_index != rxst_ring->rsr_index ||
1958	       rxst_wrap != rxst_ring->rsr_wrap) {
1959		struct et_rxbuf_data *rbd;
1960		struct et_rxdesc_ring *rx_ring;
1961		struct et_rxstat *st;
1962		struct mbuf *m;
1963		int buflen, buf_idx, ring_idx;
1964		uint32_t rxstat_pos, rxring_pos;
1965
1966		MPASS(rxst_ring->rsr_index < ET_RX_NSTAT);
1967		st = &rxst_ring->rsr_stat[rxst_ring->rsr_index];
1968		rxst_info2 = le32toh(st->rxst_info2);
1969		buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >>
1970		    ET_RXST_INFO2_LEN_SHIFT;
1971		buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >>
1972		    ET_RXST_INFO2_BUFIDX_SHIFT;
1973		ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >>
1974		    ET_RXST_INFO2_RINGIDX_SHIFT;
1975
1976		if (++rxst_ring->rsr_index == ET_RX_NSTAT) {
1977			rxst_ring->rsr_index = 0;
1978			rxst_ring->rsr_wrap ^= 1;
1979		}
1980		rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK;
1981		if (rxst_ring->rsr_wrap)
1982			rxstat_pos |= ET_RXSTAT_POS_WRAP;
1983		CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos);
1984
1985		if (ring_idx >= ET_RX_NRING) {
1986			ifp->if_ierrors++;
1987			if_printf(ifp, "invalid ring index %d\n", ring_idx);
1988			continue;
1989		}
1990		if (buf_idx >= ET_RX_NDESC) {
1991			ifp->if_ierrors++;
1992			if_printf(ifp, "invalid buf index %d\n", buf_idx);
1993			continue;
1994		}
1995
1996		rbd = &sc->sc_rx_data[ring_idx];
1997		m = rbd->rbd_buf[buf_idx].rb_mbuf;
1998
1999		if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) {
2000			if (buflen < ETHER_CRC_LEN) {
2001				m_freem(m);
2002				m = NULL;
2003				ifp->if_ierrors++;
2004			} else {
2005				m->m_pkthdr.len = m->m_len =
2006				    buflen - ETHER_CRC_LEN;
2007				m->m_pkthdr.rcvif = ifp;
2008				ifp->if_ipackets++;
2009				ET_UNLOCK(sc);
2010				ifp->if_input(ifp, m);
2011				ET_LOCK(sc);
2012			}
2013		} else {
2014			ifp->if_ierrors++;
2015		}
2016		m = NULL;	/* Catch invalid reference */
2017
2018		rx_ring = &sc->sc_rx_ring[ring_idx];
2019
2020		if (buf_idx != rx_ring->rr_index) {
2021			if_printf(ifp, "WARNING!! ring %d, "
2022				  "buf_idx %d, rr_idx %d\n",
2023				  ring_idx, buf_idx, rx_ring->rr_index);
2024		}
2025
2026		MPASS(rx_ring->rr_index < ET_RX_NDESC);
2027		if (++rx_ring->rr_index == ET_RX_NDESC) {
2028			rx_ring->rr_index = 0;
2029			rx_ring->rr_wrap ^= 1;
2030		}
2031		rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK;
2032		if (rx_ring->rr_wrap)
2033			rxring_pos |= ET_RX_RING_POS_WRAP;
2034		CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos);
2035	}
2036}
2037
2038static int
2039et_encap(struct et_softc *sc, struct mbuf **m0)
2040{
2041	struct mbuf *m = *m0;
2042	bus_dma_segment_t segs[ET_NSEG_MAX];
2043	struct et_dmamap_ctx ctx;
2044	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
2045	struct et_txbuf_data *tbd = &sc->sc_tx_data;
2046	struct et_txdesc *td;
2047	bus_dmamap_t map;
2048	int error, maxsegs, first_idx, last_idx, i;
2049	uint32_t csum_flags, tx_ready_pos, last_td_ctrl2;
2050
2051	maxsegs = ET_TX_NDESC - tbd->tbd_used;
2052	if (maxsegs > ET_NSEG_MAX)
2053		maxsegs = ET_NSEG_MAX;
2054	KASSERT(maxsegs >= ET_NSEG_SPARE,
2055		("not enough spare TX desc (%d)\n", maxsegs));
2056
2057	MPASS(tx_ring->tr_ready_index < ET_TX_NDESC);
2058	first_idx = tx_ring->tr_ready_index;
2059	map = tbd->tbd_buf[first_idx].tb_dmap;
2060
2061	ctx.nsegs = maxsegs;
2062	ctx.segs = segs;
2063	error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m,
2064				     et_dma_buf_addr, &ctx, BUS_DMA_NOWAIT);
2065	if (!error && ctx.nsegs == 0) {
2066		bus_dmamap_unload(sc->sc_mbuf_dtag, map);
2067		error = EFBIG;
2068	}
2069	if (error && error != EFBIG) {
2070		if_printf(sc->ifp, "can't load TX mbuf, error %d\n",
2071			  error);
2072		goto back;
2073	}
2074	if (error) {	/* error == EFBIG */
2075		struct mbuf *m_new;
2076
2077		m_new = m_defrag(m, M_DONTWAIT);
2078		if (m_new == NULL) {
2079			if_printf(sc->ifp, "can't defrag TX mbuf\n");
2080			error = ENOBUFS;
2081			goto back;
2082		} else {
2083			*m0 = m = m_new;
2084		}
2085
2086		ctx.nsegs = maxsegs;
2087		ctx.segs = segs;
2088		error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m,
2089					     et_dma_buf_addr, &ctx,
2090					     BUS_DMA_NOWAIT);
2091		if (error || ctx.nsegs == 0) {
2092			if (ctx.nsegs == 0) {
2093				bus_dmamap_unload(sc->sc_mbuf_dtag, map);
2094				error = EFBIG;
2095			}
2096			if_printf(sc->ifp,
2097				  "can't load defraged TX mbuf\n");
2098			goto back;
2099		}
2100	}
2101
2102	bus_dmamap_sync(sc->sc_mbuf_dtag, map, BUS_DMASYNC_PREWRITE);
2103
2104	last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG;
2105	sc->sc_tx += ctx.nsegs;
2106	if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) {
2107		sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs;
2108		last_td_ctrl2 |= ET_TDCTRL2_INTR;
2109	}
2110
2111	csum_flags = 0;
2112	if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) {
2113		if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2114			csum_flags |= ET_TDCTRL2_CSUM_IP;
2115		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2116			csum_flags |= ET_TDCTRL2_CSUM_UDP;
2117		else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2118			csum_flags |= ET_TDCTRL2_CSUM_TCP;
2119	}
2120	last_idx = -1;
2121	for (i = 0; i < ctx.nsegs; ++i) {
2122		int idx;
2123
2124		idx = (first_idx + i) % ET_TX_NDESC;
2125		td = &tx_ring->tr_desc[idx];
2126		td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr));
2127		td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr));
2128		td->td_ctrl1 =  htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK);
2129		if (i == ctx.nsegs - 1) {	/* Last frag */
2130			td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags);
2131			last_idx = idx;
2132		} else
2133			td->td_ctrl2 = htole32(csum_flags);
2134
2135		MPASS(tx_ring->tr_ready_index < ET_TX_NDESC);
2136		if (++tx_ring->tr_ready_index == ET_TX_NDESC) {
2137			tx_ring->tr_ready_index = 0;
2138			tx_ring->tr_ready_wrap ^= 1;
2139		}
2140	}
2141	td = &tx_ring->tr_desc[first_idx];
2142	td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG);	/* First frag */
2143
2144	MPASS(last_idx >= 0);
2145	tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap;
2146	tbd->tbd_buf[last_idx].tb_dmap = map;
2147	tbd->tbd_buf[last_idx].tb_mbuf = m;
2148
2149	tbd->tbd_used += ctx.nsegs;
2150	MPASS(tbd->tbd_used <= ET_TX_NDESC);
2151
2152	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
2153			BUS_DMASYNC_PREWRITE);
2154
2155	tx_ready_pos = tx_ring->tr_ready_index & ET_TX_READY_POS_INDEX_MASK;
2156	if (tx_ring->tr_ready_wrap)
2157		tx_ready_pos |= ET_TX_READY_POS_WRAP;
2158	CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
2159
2160	error = 0;
2161back:
2162	if (error) {
2163		m_freem(m);
2164		*m0 = NULL;
2165	}
2166	return (error);
2167}
2168
2169static void
2170et_txeof(struct et_softc *sc)
2171{
2172	struct ifnet *ifp;
2173	struct et_txdesc_ring *tx_ring;
2174	struct et_txbuf_data *tbd;
2175	uint32_t tx_done;
2176	int end, wrap;
2177
2178	ET_LOCK_ASSERT(sc);
2179	ifp = sc->ifp;
2180	tx_ring = &sc->sc_tx_ring;
2181	tbd = &sc->sc_tx_data;
2182
2183	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
2184		return;
2185
2186	if (tbd->tbd_used == 0)
2187		return;
2188
2189	tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);
2190	end = tx_done & ET_TX_DONE_POS_INDEX_MASK;
2191	wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0;
2192
2193	while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) {
2194		struct et_txbuf *tb;
2195
2196		MPASS(tbd->tbd_start_index < ET_TX_NDESC);
2197		tb = &tbd->tbd_buf[tbd->tbd_start_index];
2198
2199		bzero(&tx_ring->tr_desc[tbd->tbd_start_index],
2200		      sizeof(struct et_txdesc));
2201		bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
2202				BUS_DMASYNC_PREWRITE);
2203
2204		if (tb->tb_mbuf != NULL) {
2205			bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap);
2206			m_freem(tb->tb_mbuf);
2207			tb->tb_mbuf = NULL;
2208			ifp->if_opackets++;
2209		}
2210
2211		if (++tbd->tbd_start_index == ET_TX_NDESC) {
2212			tbd->tbd_start_index = 0;
2213			tbd->tbd_start_wrap ^= 1;
2214		}
2215
2216		MPASS(tbd->tbd_used > 0);
2217		tbd->tbd_used--;
2218	}
2219
2220	if (tbd->tbd_used == 0)
2221		sc->watchdog_timer = 0;
2222	if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC)
2223		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2224
2225	et_start_locked(ifp);
2226}
2227
2228static void
2229et_tick(void *xsc)
2230{
2231	struct et_softc *sc = xsc;
2232	struct ifnet *ifp;
2233	struct mii_data *mii;
2234
2235	ET_LOCK_ASSERT(sc);
2236	ifp = sc->ifp;
2237	mii = device_get_softc(sc->sc_miibus);
2238
2239	mii_tick(mii);
2240	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 &&
2241	    (mii->mii_media_status & IFM_ACTIVE) &&
2242	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2243		if_printf(ifp, "Link up, enable TX/RX\n");
2244		if (et_enable_txrx(sc, 0) == 0)
2245			et_start_locked(ifp);
2246	}
2247	et_watchdog(sc);
2248	callout_reset(&sc->sc_tick, hz, et_tick, sc);
2249}
2250
2251static int
2252et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init)
2253{
2254	return (et_newbuf(rbd, buf_idx, init, MCLBYTES));
2255}
2256
2257static int
2258et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init)
2259{
2260	return (et_newbuf(rbd, buf_idx, init, MHLEN));
2261}
2262
2263static int
2264et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0)
2265{
2266	struct et_softc *sc = rbd->rbd_softc;
2267	struct et_rxbuf *rb;
2268	struct mbuf *m;
2269	struct et_dmamap_ctx ctx;
2270	bus_dma_segment_t seg;
2271	bus_dmamap_t dmap;
2272	int error, len;
2273
2274	MPASS(buf_idx < ET_RX_NDESC);
2275	rb = &rbd->rbd_buf[buf_idx];
2276
2277	m = m_getl(len0, /* init ? M_WAIT :*/ M_DONTWAIT, MT_DATA, M_PKTHDR, &len);
2278	if (m == NULL) {
2279		error = ENOBUFS;
2280
2281		if (init) {
2282			if_printf(sc->ifp,
2283				  "m_getl failed, size %d\n", len0);
2284			return (error);
2285		} else {
2286			goto back;
2287		}
2288	}
2289	m->m_len = m->m_pkthdr.len = len;
2290
2291	/*
2292	 * Try load RX mbuf into temporary DMA tag
2293	 */
2294	ctx.nsegs = 1;
2295	ctx.segs = &seg;
2296	error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap, m,
2297				     et_dma_buf_addr, &ctx,
2298				     init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2299	if (error || ctx.nsegs == 0) {
2300		if (!error) {
2301			bus_dmamap_unload(sc->sc_mbuf_dtag,
2302					  sc->sc_mbuf_tmp_dmap);
2303			error = EFBIG;
2304			if_printf(sc->ifp, "too many segments?!\n");
2305		}
2306		m_freem(m);
2307		m = NULL;
2308
2309		if (init) {
2310			if_printf(sc->ifp, "can't load RX mbuf\n");
2311			return (error);
2312		} else {
2313			goto back;
2314		}
2315	}
2316
2317	if (!init) {
2318		bus_dmamap_sync(sc->sc_mbuf_dtag, rb->rb_dmap,
2319				BUS_DMASYNC_POSTREAD);
2320		bus_dmamap_unload(sc->sc_mbuf_dtag, rb->rb_dmap);
2321	}
2322	rb->rb_mbuf = m;
2323	rb->rb_paddr = seg.ds_addr;
2324
2325	/*
2326	 * Swap RX buf's DMA map with the loaded temporary one
2327	 */
2328	dmap = rb->rb_dmap;
2329	rb->rb_dmap = sc->sc_mbuf_tmp_dmap;
2330	sc->sc_mbuf_tmp_dmap = dmap;
2331
2332	error = 0;
2333back:
2334	et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2335	return (error);
2336}
2337
2338/*
2339 * Create sysctl tree
2340 */
2341static void
2342et_add_sysctls(struct et_softc * sc)
2343{
2344	struct sysctl_ctx_list *ctx;
2345	struct sysctl_oid_list *children;
2346
2347	ctx = device_get_sysctl_ctx(sc->dev);
2348	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
2349
2350	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts",
2351	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I",
2352	    "RX IM, # packets per RX interrupt");
2353	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay",
2354	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I",
2355	    "RX IM, RX interrupt delay (x10 usec)");
2356	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs",
2357	    CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0,
2358	    "TX IM, # segments per TX interrupt");
2359	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer",
2360	    CTLFLAG_RW, &sc->sc_timer, 0, "TX timer");
2361}
2362
2363static int
2364et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS)
2365{
2366	struct et_softc *sc = arg1;
2367	struct ifnet *ifp = sc->ifp;
2368	int error = 0, v;
2369
2370	v = sc->sc_rx_intr_npkts;
2371	error = sysctl_handle_int(oidp, &v, 0, req);
2372	if (error || req->newptr == NULL)
2373		goto back;
2374	if (v <= 0) {
2375		error = EINVAL;
2376		goto back;
2377	}
2378
2379	if (sc->sc_rx_intr_npkts != v) {
2380		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2381			CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v);
2382		sc->sc_rx_intr_npkts = v;
2383	}
2384back:
2385	return (error);
2386}
2387
2388static int
2389et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS)
2390{
2391	struct et_softc *sc = arg1;
2392	struct ifnet *ifp = sc->ifp;
2393	int error = 0, v;
2394
2395	v = sc->sc_rx_intr_delay;
2396	error = sysctl_handle_int(oidp, &v, 0, req);
2397	if (error || req->newptr == NULL)
2398		goto back;
2399	if (v <= 0) {
2400		error = EINVAL;
2401		goto back;
2402	}
2403
2404	if (sc->sc_rx_intr_delay != v) {
2405		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2406			CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v);
2407		sc->sc_rx_intr_delay = v;
2408	}
2409back:
2410	return (error);
2411}
2412
2413static void
2414et_setmedia(struct et_softc *sc)
2415{
2416	struct mii_data *mii = device_get_softc(sc->sc_miibus);
2417	uint32_t cfg2, ctrl;
2418
2419	cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
2420	cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
2421		  ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
2422	cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
2423	    ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) &
2424	    ET_MAC_CFG2_PREAMBLE_LEN_MASK);
2425
2426	ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
2427	ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
2428
2429	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
2430		cfg2 |= ET_MAC_CFG2_MODE_GMII;
2431	} else {
2432		cfg2 |= ET_MAC_CFG2_MODE_MII;
2433		ctrl |= ET_MAC_CTRL_MODE_MII;
2434	}
2435
2436	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
2437		cfg2 |= ET_MAC_CFG2_FDX;
2438	else
2439		ctrl |= ET_MAC_CTRL_GHDX;
2440
2441	CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
2442	CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
2443}
2444
2445static void
2446et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr)
2447{
2448	struct et_rxdesc_ring *rx_ring = rbd->rbd_ring;
2449	struct et_rxdesc *desc;
2450
2451	MPASS(buf_idx < ET_RX_NDESC);
2452	desc = &rx_ring->rr_desc[buf_idx];
2453
2454	desc->rd_addr_hi = htole32(ET_ADDR_HI(paddr));
2455	desc->rd_addr_lo = htole32(ET_ADDR_LO(paddr));
2456	desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK);
2457
2458	bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap,
2459			BUS_DMASYNC_PREWRITE);
2460}
2461