if_et.c revision 199611
150476Speter/*- 22337Scsgr * Copyright (c) 2007 The DragonFly Project. All rights reserved. 32337Scsgr * 42337Scsgr * This code is derived from software contributed to The DragonFly Project 574814Sru * by Sepherosa Ziehau <sepherosa@gmail.com> 62337Scsgr * 7202210Sed * Redistribution and use in source and binary forms, with or without 8202210Sed * modification, are permitted provided that the following conditions 92337Scsgr * are met: 1019416Sjkh * 1119404Storstenb * 1. Redistributions of source code must retain the above copyright 1219416Sjkh * notice, this list of conditions and the following disclaimer. 1319404Storstenb * 2. Redistributions in binary form must reproduce the above copyright 142337Scsgr * notice, this list of conditions and the following disclaimer in 152337Scsgr * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 35 * $FreeBSD: head/sys/dev/et/if_et.c 199611 2009-11-20 20:33:59Z yongari $ 36 */ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/endian.h> 41#include <sys/kernel.h> 42#include <sys/bus.h> 43#include <sys/malloc.h> 44#include <sys/mbuf.h> 45#include <sys/proc.h> 46#include <sys/rman.h> 47#include <sys/module.h> 48#include <sys/socket.h> 49#include <sys/sockio.h> 50#include <sys/sysctl.h> 51 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_dl.h> 55#include <net/if_types.h> 56#include <net/bpf.h> 57#include <net/if_arp.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_vlan_var.h> 61 62#include <machine/bus.h> 63 64#include <dev/mii/miivar.h> 65#include <dev/mii/truephyreg.h> 66 67#include <dev/pci/pcireg.h> 68#include <dev/pci/pcivar.h> 69 70#include <dev/et/if_etreg.h> 71#include <dev/et/if_etvar.h> 72 73#include "miibus_if.h" 74 75MODULE_DEPEND(et, pci, 1, 1, 1); 76MODULE_DEPEND(et, ether, 1, 1, 1); 77MODULE_DEPEND(et, miibus, 1, 1, 1); 78 79/* Tunables. */ 80static int msi_disable = 0; 81TUNABLE_INT("hw.et.msi_disable", &msi_disable); 82 83#define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 84 85static int et_probe(device_t); 86static int et_attach(device_t); 87static int et_detach(device_t); 88static int et_shutdown(device_t); 89 90static int et_miibus_readreg(device_t, int, int); 91static int et_miibus_writereg(device_t, int, int, int); 92static void et_miibus_statchg(device_t); 93 94static void et_init_locked(struct et_softc *); 95static void et_init(void *); 96static int et_ioctl(struct ifnet *, u_long, caddr_t); 97static void et_start_locked(struct ifnet *); 98static void et_start(struct ifnet *); 99static void et_watchdog(struct et_softc *); 100static int et_ifmedia_upd_locked(struct ifnet *); 101static int et_ifmedia_upd(struct ifnet *); 102static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 103 104static void et_add_sysctls(struct et_softc *); 105static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 106static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 107 108static void et_intr(void *); 109static void et_enable_intrs(struct et_softc *, uint32_t); 110static void et_disable_intrs(struct et_softc *); 111static void et_rxeof(struct et_softc *); 112static void et_txeof(struct et_softc *); 113 114static int et_dma_alloc(device_t); 115static void et_dma_free(device_t); 116static int et_dma_mem_create(device_t, bus_size_t, bus_dma_tag_t *, 117 void **, bus_addr_t *, bus_dmamap_t *); 118static void et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t); 119static int et_dma_mbuf_create(device_t); 120static void et_dma_mbuf_destroy(device_t, int, const int[]); 121static void et_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 122static void et_dma_buf_addr(void *, bus_dma_segment_t *, int, 123 bus_size_t, int); 124static int et_init_tx_ring(struct et_softc *); 125static int et_init_rx_ring(struct et_softc *); 126static void et_free_tx_ring(struct et_softc *); 127static void et_free_rx_ring(struct et_softc *); 128static int et_encap(struct et_softc *, struct mbuf **); 129static int et_newbuf(struct et_rxbuf_data *, int, int, int); 130static int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 131static int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 132 133static void et_stop(struct et_softc *); 134static int et_chip_init(struct et_softc *); 135static void et_chip_attach(struct et_softc *); 136static void et_init_mac(struct et_softc *); 137static void et_init_rxmac(struct et_softc *); 138static void et_init_txmac(struct et_softc *); 139static int et_init_rxdma(struct et_softc *); 140static int et_init_txdma(struct et_softc *); 141static int et_start_rxdma(struct et_softc *); 142static int et_start_txdma(struct et_softc *); 143static int et_stop_rxdma(struct et_softc *); 144static int et_stop_txdma(struct et_softc *); 145static int et_enable_txrx(struct et_softc *, int); 146static void et_reset(struct et_softc *); 147static int et_bus_config(struct et_softc *); 148static void et_get_eaddr(device_t, uint8_t[]); 149static void et_setmulti(struct et_softc *); 150static void et_tick(void *); 151static void et_setmedia(struct et_softc *); 152static void et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t); 153 154static const struct et_dev { 155 uint16_t vid; 156 uint16_t did; 157 const char *desc; 158} et_devices[] = { 159 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 160 "Agere ET1310 Gigabit Ethernet" }, 161 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 162 "Agere ET1310 Fast Ethernet" }, 163 { 0, 0, NULL } 164}; 165 166static device_method_t et_methods[] = { 167 DEVMETHOD(device_probe, et_probe), 168 DEVMETHOD(device_attach, et_attach), 169 DEVMETHOD(device_detach, et_detach), 170 DEVMETHOD(device_shutdown, et_shutdown), 171 172 DEVMETHOD(bus_print_child, bus_generic_print_child), 173 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 174 175 DEVMETHOD(miibus_readreg, et_miibus_readreg), 176 DEVMETHOD(miibus_writereg, et_miibus_writereg), 177 DEVMETHOD(miibus_statchg, et_miibus_statchg), 178 179 { 0, 0 } 180}; 181 182static driver_t et_driver = { 183 "et", 184 et_methods, 185 sizeof(struct et_softc) 186}; 187 188static devclass_t et_devclass; 189 190DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 191DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 192 193static int et_rx_intr_npkts = 32; 194static int et_rx_intr_delay = 20; /* x10 usec */ 195static int et_tx_intr_nsegs = 126; 196static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 197 198TUNABLE_INT("hw.et.timer", &et_timer); 199TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 200TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 201TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 202 203struct et_bsize { 204 int bufsize; 205 et_newbuf_t newbuf; 206}; 207 208static const struct et_bsize et_bufsize_std[ET_RX_NRING] = { 209 { .bufsize = ET_RXDMA_CTRL_RING0_128, 210 .newbuf = et_newbuf_hdr }, 211 { .bufsize = ET_RXDMA_CTRL_RING1_2048, 212 .newbuf = et_newbuf_cluster }, 213}; 214 215static int 216et_probe(device_t dev) 217{ 218 const struct et_dev *d; 219 uint16_t did, vid; 220 221 vid = pci_get_vendor(dev); 222 did = pci_get_device(dev); 223 224 for (d = et_devices; d->desc != NULL; ++d) { 225 if (vid == d->vid && did == d->did) { 226 device_set_desc(dev, d->desc); 227 return (0); 228 } 229 } 230 return (ENXIO); 231} 232 233static int 234et_attach(device_t dev) 235{ 236 struct et_softc *sc; 237 struct ifnet *ifp; 238 uint8_t eaddr[ETHER_ADDR_LEN]; 239 int cap, error, msic; 240 241 sc = device_get_softc(dev); 242 sc->dev = dev; 243 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 244 MTX_DEF); 245 246 ifp = sc->ifp = if_alloc(IFT_ETHER); 247 if (ifp == NULL) { 248 device_printf(dev, "can not if_alloc()\n"); 249 error = ENOSPC; 250 goto fail; 251 } 252 253 /* 254 * Initialize tunables 255 */ 256 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 257 sc->sc_rx_intr_delay = et_rx_intr_delay; 258 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 259 sc->sc_timer = et_timer; 260 261 /* Enable bus mastering */ 262 pci_enable_busmaster(dev); 263 264 /* 265 * Allocate IO memory 266 */ 267 sc->sc_mem_rid = ET_PCIR_BAR; 268 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 269 &sc->sc_mem_rid, RF_ACTIVE); 270 if (sc->sc_mem_res == NULL) { 271 device_printf(dev, "can't allocate IO memory\n"); 272 return (ENXIO); 273 } 274 275 msic = 0; 276 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { 277 sc->sc_expcap = cap; 278 sc->sc_flags |= ET_FLAG_PCIE; 279 msic = pci_msi_count(dev); 280 if (bootverbose) 281 device_printf(dev, "MSI count: %d\n", msic); 282 } 283 if (msic > 0 && msi_disable == 0) { 284 msic = 1; 285 if (pci_alloc_msi(dev, &msic) == 0) { 286 if (msic == 1) { 287 device_printf(dev, "Using %d MSI message\n", 288 msic); 289 sc->sc_flags |= ET_FLAG_MSI; 290 } else 291 pci_release_msi(dev); 292 } 293 } 294 295 /* 296 * Allocate IRQ 297 */ 298 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 299 sc->sc_irq_rid = 0; 300 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 301 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 302 } else { 303 sc->sc_irq_rid = 1; 304 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 305 &sc->sc_irq_rid, RF_ACTIVE); 306 } 307 if (sc->sc_irq_res == NULL) { 308 device_printf(dev, "can't allocate irq\n"); 309 error = ENXIO; 310 goto fail; 311 } 312 313 error = et_bus_config(sc); 314 if (error) 315 goto fail; 316 317 et_get_eaddr(dev, eaddr); 318 319 CSR_WRITE_4(sc, ET_PM, 320 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 321 322 et_reset(sc); 323 324 et_disable_intrs(sc); 325 326 error = et_dma_alloc(dev); 327 if (error) 328 goto fail; 329 330 ifp->if_softc = sc; 331 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 332 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 333 ifp->if_init = et_init; 334 ifp->if_ioctl = et_ioctl; 335 ifp->if_start = et_start; 336 ifp->if_mtu = ETHERMTU; 337 ifp->if_capabilities = /*IFCAP_TXCSUM*/IFCAP_HWCSUM | IFCAP_VLAN_MTU; 338 ifp->if_capenable = ifp->if_capabilities; 339 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 340 IFQ_SET_READY(&ifp->if_snd); 341 342 et_chip_attach(sc); 343 344 error = mii_phy_probe(dev, &sc->sc_miibus, 345 et_ifmedia_upd, et_ifmedia_sts); 346 if (error) { 347 device_printf(dev, "can't probe any PHY\n"); 348 goto fail; 349 } 350 351 ether_ifattach(ifp, eaddr); 352 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 353 354 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 355 NULL, et_intr, sc, &sc->sc_irq_handle); 356 if (error) { 357 ether_ifdetach(ifp); 358 device_printf(dev, "can't setup intr\n"); 359 goto fail; 360 } 361 362 et_add_sysctls(sc); 363 364 return (0); 365fail: 366 et_detach(dev); 367 return (error); 368} 369 370static int 371et_detach(device_t dev) 372{ 373 struct et_softc *sc = device_get_softc(dev); 374 375 if (device_is_attached(dev)) { 376 struct ifnet *ifp = sc->ifp; 377 378 ET_LOCK(sc); 379 et_stop(sc); 380 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 381 ET_UNLOCK(sc); 382 383 ether_ifdetach(ifp); 384 } 385 386 if (sc->sc_miibus != NULL) 387 device_delete_child(dev, sc->sc_miibus); 388 bus_generic_detach(dev); 389 390 if (sc->sc_irq_res != NULL) { 391 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 392 sc->sc_irq_res); 393 } 394 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 395 pci_release_msi(dev); 396 397 if (sc->sc_mem_res != NULL) { 398 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 399 sc->sc_mem_res); 400 } 401 402 if (sc->ifp != NULL) 403 if_free(sc->ifp); 404 405 et_dma_free(dev); 406 407 mtx_destroy(&sc->sc_mtx); 408 409 return (0); 410} 411 412static int 413et_shutdown(device_t dev) 414{ 415 struct et_softc *sc = device_get_softc(dev); 416 417 ET_LOCK(sc); 418 et_stop(sc); 419 ET_UNLOCK(sc); 420 return (0); 421} 422 423static int 424et_miibus_readreg(device_t dev, int phy, int reg) 425{ 426 struct et_softc *sc = device_get_softc(dev); 427 uint32_t val; 428 int i, ret; 429 430 /* Stop any pending operations */ 431 CSR_WRITE_4(sc, ET_MII_CMD, 0); 432 433 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 434 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 435 CSR_WRITE_4(sc, ET_MII_ADDR, val); 436 437 /* Start reading */ 438 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 439 440#define NRETRY 50 441 442 for (i = 0; i < NRETRY; ++i) { 443 val = CSR_READ_4(sc, ET_MII_IND); 444 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 445 break; 446 DELAY(50); 447 } 448 if (i == NRETRY) { 449 if_printf(sc->ifp, 450 "read phy %d, reg %d timed out\n", phy, reg); 451 ret = 0; 452 goto back; 453 } 454 455#undef NRETRY 456 457 val = CSR_READ_4(sc, ET_MII_STAT); 458 ret = val & ET_MII_STAT_VALUE_MASK; 459 460back: 461 /* Make sure that the current operation is stopped */ 462 CSR_WRITE_4(sc, ET_MII_CMD, 0); 463 return (ret); 464} 465 466static int 467et_miibus_writereg(device_t dev, int phy, int reg, int val0) 468{ 469 struct et_softc *sc = device_get_softc(dev); 470 uint32_t val; 471 int i; 472 473 /* Stop any pending operations */ 474 CSR_WRITE_4(sc, ET_MII_CMD, 0); 475 476 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 477 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 478 CSR_WRITE_4(sc, ET_MII_ADDR, val); 479 480 /* Start writing */ 481 CSR_WRITE_4(sc, ET_MII_CTRL, 482 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 483 484#define NRETRY 100 485 486 for (i = 0; i < NRETRY; ++i) { 487 val = CSR_READ_4(sc, ET_MII_IND); 488 if ((val & ET_MII_IND_BUSY) == 0) 489 break; 490 DELAY(50); 491 } 492 if (i == NRETRY) { 493 if_printf(sc->ifp, 494 "write phy %d, reg %d timed out\n", phy, reg); 495 et_miibus_readreg(dev, phy, reg); 496 } 497 498#undef NRETRY 499 500 /* Make sure that the current operation is stopped */ 501 CSR_WRITE_4(sc, ET_MII_CMD, 0); 502 return (0); 503} 504 505static void 506et_miibus_statchg(device_t dev) 507{ 508 et_setmedia(device_get_softc(dev)); 509} 510 511static int 512et_ifmedia_upd_locked(struct ifnet *ifp) 513{ 514 struct et_softc *sc = ifp->if_softc; 515 struct mii_data *mii = device_get_softc(sc->sc_miibus); 516 517 if (mii->mii_instance != 0) { 518 struct mii_softc *miisc; 519 520 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 521 mii_phy_reset(miisc); 522 } 523 mii_mediachg(mii); 524 525 return (0); 526} 527 528static int 529et_ifmedia_upd(struct ifnet *ifp) 530{ 531 struct et_softc *sc = ifp->if_softc; 532 int res; 533 534 ET_LOCK(sc); 535 res = et_ifmedia_upd_locked(ifp); 536 ET_UNLOCK(sc); 537 538 return (res); 539} 540 541static void 542et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 543{ 544 struct et_softc *sc = ifp->if_softc; 545 struct mii_data *mii = device_get_softc(sc->sc_miibus); 546 547 mii_pollstat(mii); 548 ifmr->ifm_active = mii->mii_media_active; 549 ifmr->ifm_status = mii->mii_media_status; 550} 551 552static void 553et_stop(struct et_softc *sc) 554{ 555 struct ifnet *ifp = sc->ifp; 556 557 ET_LOCK_ASSERT(sc); 558 559 callout_stop(&sc->sc_tick); 560 561 et_stop_rxdma(sc); 562 et_stop_txdma(sc); 563 564 et_disable_intrs(sc); 565 566 et_free_tx_ring(sc); 567 et_free_rx_ring(sc); 568 569 et_reset(sc); 570 571 sc->sc_tx = 0; 572 sc->sc_tx_intr = 0; 573 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 574 575 sc->watchdog_timer = 0; 576 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 577} 578 579static int 580et_bus_config(struct et_softc *sc) 581{ 582 uint32_t val, max_plsz; 583 uint16_t ack_latency, replay_timer; 584 585 /* 586 * Test whether EEPROM is valid 587 * NOTE: Read twice to get the correct value 588 */ 589 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 590 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 591 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 592 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 593 return (ENXIO); 594 } 595 596 /* TODO: LED */ 597 598 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 599 return (0); 600 601 /* 602 * Configure ACK latency and replay timer according to 603 * max playload size 604 */ 605 val = pci_read_config(sc->dev, 606 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4); 607 max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD; 608 609 switch (max_plsz) { 610 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 611 ack_latency = ET_PCIV_ACK_LATENCY_128; 612 replay_timer = ET_PCIV_REPLAY_TIMER_128; 613 break; 614 615 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 616 ack_latency = ET_PCIV_ACK_LATENCY_256; 617 replay_timer = ET_PCIV_REPLAY_TIMER_256; 618 break; 619 620 default: 621 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 622 replay_timer = pci_read_config(sc->dev, 623 ET_PCIR_REPLAY_TIMER, 2); 624 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 625 ack_latency, replay_timer); 626 break; 627 } 628 if (ack_latency != 0) { 629 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 630 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 631 2); 632 } 633 634 /* 635 * Set L0s and L1 latency timer to 2us 636 */ 637 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 638 val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT); 639 /* L0s exit latency : 2us */ 640 val |= 0x00005000; 641 /* L1 exit latency : 2us */ 642 val |= 0x00028000; 643 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 644 645 /* 646 * Set max read request size to 2048 bytes 647 */ 648 val = pci_read_config(sc->dev, 649 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 650 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 651 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 652 pci_write_config(sc->dev, 653 sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2); 654 655 return (0); 656} 657 658static void 659et_get_eaddr(device_t dev, uint8_t eaddr[]) 660{ 661 uint32_t val; 662 int i; 663 664 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 665 for (i = 0; i < 4; ++i) 666 eaddr[i] = (val >> (8 * i)) & 0xff; 667 668 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 669 for (; i < ETHER_ADDR_LEN; ++i) 670 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 671} 672 673static void 674et_reset(struct et_softc *sc) 675{ 676 CSR_WRITE_4(sc, ET_MAC_CFG1, 677 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 678 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 679 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 680 681 CSR_WRITE_4(sc, ET_SWRST, 682 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 683 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 684 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 685 686 CSR_WRITE_4(sc, ET_MAC_CFG1, 687 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 688 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 689 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 690} 691 692static void 693et_disable_intrs(struct et_softc *sc) 694{ 695 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 696} 697 698static void 699et_enable_intrs(struct et_softc *sc, uint32_t intrs) 700{ 701 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 702} 703 704static int 705et_dma_alloc(device_t dev) 706{ 707 struct et_softc *sc = device_get_softc(dev); 708 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 709 struct et_txstatus_data *txsd = &sc->sc_tx_status; 710 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 711 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 712 int i, error; 713 714 /* 715 * Create top level DMA tag 716 */ 717 error = bus_dma_tag_create(NULL, 1, 0, 718 BUS_SPACE_MAXADDR_32BIT, 719 BUS_SPACE_MAXADDR, 720 NULL, NULL, 721 MAXBSIZE, 722 BUS_SPACE_UNRESTRICTED, 723 BUS_SPACE_MAXSIZE_32BIT, 724 0, NULL, NULL, &sc->sc_dtag); 725 if (error) { 726 device_printf(dev, "can't create DMA tag\n"); 727 return (error); 728 } 729 730 /* 731 * Create TX ring DMA stuffs 732 */ 733 error = et_dma_mem_create(dev, ET_TX_RING_SIZE, &tx_ring->tr_dtag, 734 (void **)&tx_ring->tr_desc, 735 &tx_ring->tr_paddr, &tx_ring->tr_dmap); 736 if (error) { 737 device_printf(dev, "can't create TX ring DMA stuffs\n"); 738 return (error); 739 } 740 741 /* 742 * Create TX status DMA stuffs 743 */ 744 error = et_dma_mem_create(dev, sizeof(uint32_t), &txsd->txsd_dtag, 745 (void **)&txsd->txsd_status, 746 &txsd->txsd_paddr, &txsd->txsd_dmap); 747 if (error) { 748 device_printf(dev, "can't create TX status DMA stuffs\n"); 749 return (error); 750 } 751 752 /* 753 * Create DMA stuffs for RX rings 754 */ 755 for (i = 0; i < ET_RX_NRING; ++i) { 756 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 757 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 758 759 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 760 761 error = et_dma_mem_create(dev, ET_RX_RING_SIZE, 762 &rx_ring->rr_dtag, 763 (void **)&rx_ring->rr_desc, 764 &rx_ring->rr_paddr, 765 &rx_ring->rr_dmap); 766 if (error) { 767 device_printf(dev, "can't create DMA stuffs for " 768 "the %d RX ring\n", i); 769 return (error); 770 } 771 rx_ring->rr_posreg = rx_ring_posreg[i]; 772 } 773 774 /* 775 * Create RX stat ring DMA stuffs 776 */ 777 error = et_dma_mem_create(dev, ET_RXSTAT_RING_SIZE, 778 &rxst_ring->rsr_dtag, 779 (void **)&rxst_ring->rsr_stat, 780 &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap); 781 if (error) { 782 device_printf(dev, "can't create RX stat ring DMA stuffs\n"); 783 return (error); 784 } 785 786 /* 787 * Create RX status DMA stuffs 788 */ 789 error = et_dma_mem_create(dev, sizeof(struct et_rxstatus), 790 &rxsd->rxsd_dtag, 791 (void **)&rxsd->rxsd_status, 792 &rxsd->rxsd_paddr, &rxsd->rxsd_dmap); 793 if (error) { 794 device_printf(dev, "can't create RX status DMA stuffs\n"); 795 return (error); 796 } 797 798 /* 799 * Create mbuf DMA stuffs 800 */ 801 error = et_dma_mbuf_create(dev); 802 if (error) 803 return (error); 804 805 return (0); 806} 807 808static void 809et_dma_free(device_t dev) 810{ 811 struct et_softc *sc = device_get_softc(dev); 812 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 813 struct et_txstatus_data *txsd = &sc->sc_tx_status; 814 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 815 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 816 int i, rx_done[ET_RX_NRING]; 817 818 /* 819 * Destroy TX ring DMA stuffs 820 */ 821 et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc, 822 tx_ring->tr_dmap); 823 824 /* 825 * Destroy TX status DMA stuffs 826 */ 827 et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status, 828 txsd->txsd_dmap); 829 830 /* 831 * Destroy DMA stuffs for RX rings 832 */ 833 for (i = 0; i < ET_RX_NRING; ++i) { 834 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 835 836 et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc, 837 rx_ring->rr_dmap); 838 } 839 840 /* 841 * Destroy RX stat ring DMA stuffs 842 */ 843 et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat, 844 rxst_ring->rsr_dmap); 845 846 /* 847 * Destroy RX status DMA stuffs 848 */ 849 et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status, 850 rxsd->rxsd_dmap); 851 852 /* 853 * Destroy mbuf DMA stuffs 854 */ 855 for (i = 0; i < ET_RX_NRING; ++i) 856 rx_done[i] = ET_RX_NDESC; 857 et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done); 858 859 /* 860 * Destroy top level DMA tag 861 */ 862 if (sc->sc_dtag != NULL) 863 bus_dma_tag_destroy(sc->sc_dtag); 864} 865 866static int 867et_dma_mbuf_create(device_t dev) 868{ 869 struct et_softc *sc = device_get_softc(dev); 870 struct et_txbuf_data *tbd = &sc->sc_tx_data; 871 int i, error, rx_done[ET_RX_NRING]; 872 873 /* 874 * Create mbuf DMA tag 875 */ 876 error = bus_dma_tag_create(sc->sc_dtag, 1, 0, 877 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 878 NULL, NULL, 879 ET_JUMBO_FRAMELEN, ET_NSEG_MAX, 880 BUS_SPACE_MAXSIZE_32BIT, 881 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_mbuf_dtag); 882 if (error) { 883 device_printf(dev, "can't create mbuf DMA tag\n"); 884 return (error); 885 } 886 887 /* 888 * Create spare DMA map for RX mbufs 889 */ 890 error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, &sc->sc_mbuf_tmp_dmap); 891 if (error) { 892 device_printf(dev, "can't create spare mbuf DMA map\n"); 893 bus_dma_tag_destroy(sc->sc_mbuf_dtag); 894 sc->sc_mbuf_dtag = NULL; 895 return (error); 896 } 897 898 /* 899 * Create DMA maps for RX mbufs 900 */ 901 bzero(rx_done, sizeof(rx_done)); 902 for (i = 0; i < ET_RX_NRING; ++i) { 903 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 904 int j; 905 906 for (j = 0; j < ET_RX_NDESC; ++j) { 907 error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, 908 &rbd->rbd_buf[j].rb_dmap); 909 if (error) { 910 device_printf(dev, "can't create %d RX mbuf " 911 "for %d RX ring\n", j, i); 912 rx_done[i] = j; 913 et_dma_mbuf_destroy(dev, 0, rx_done); 914 return (error); 915 } 916 } 917 rx_done[i] = ET_RX_NDESC; 918 919 rbd->rbd_softc = sc; 920 rbd->rbd_ring = &sc->sc_rx_ring[i]; 921 } 922 923 /* 924 * Create DMA maps for TX mbufs 925 */ 926 for (i = 0; i < ET_TX_NDESC; ++i) { 927 error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, 928 &tbd->tbd_buf[i].tb_dmap); 929 if (error) { 930 device_printf(dev, "can't create %d TX mbuf " 931 "DMA map\n", i); 932 et_dma_mbuf_destroy(dev, i, rx_done); 933 return (error); 934 } 935 } 936 937 return (0); 938} 939 940static void 941et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[]) 942{ 943 struct et_softc *sc = device_get_softc(dev); 944 struct et_txbuf_data *tbd = &sc->sc_tx_data; 945 int i; 946 947 if (sc->sc_mbuf_dtag == NULL) 948 return; 949 950 /* 951 * Destroy DMA maps for RX mbufs 952 */ 953 for (i = 0; i < ET_RX_NRING; ++i) { 954 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 955 int j; 956 957 for (j = 0; j < rx_done[i]; ++j) { 958 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 959 960 KASSERT(rb->rb_mbuf == NULL, 961 ("RX mbuf in %d RX ring is not freed yet\n", i)); 962 bus_dmamap_destroy(sc->sc_mbuf_dtag, rb->rb_dmap); 963 } 964 } 965 966 /* 967 * Destroy DMA maps for TX mbufs 968 */ 969 for (i = 0; i < tx_done; ++i) { 970 struct et_txbuf *tb = &tbd->tbd_buf[i]; 971 972 KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n")); 973 bus_dmamap_destroy(sc->sc_mbuf_dtag, tb->tb_dmap); 974 } 975 976 /* 977 * Destroy spare mbuf DMA map 978 */ 979 bus_dmamap_destroy(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap); 980 981 /* 982 * Destroy mbuf DMA tag 983 */ 984 bus_dma_tag_destroy(sc->sc_mbuf_dtag); 985 sc->sc_mbuf_dtag = NULL; 986} 987 988static int 989et_dma_mem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag, 990 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap) 991{ 992 struct et_softc *sc = device_get_softc(dev); 993 int error; 994 995 error = bus_dma_tag_create(sc->sc_dtag, ET_ALIGN, 0, 996 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 997 NULL, NULL, 998 size, 1, BUS_SPACE_MAXSIZE_32BIT, 999 0, NULL, NULL, dtag); 1000 if (error) { 1001 device_printf(dev, "can't create DMA tag\n"); 1002 return (error); 1003 } 1004 1005 error = bus_dmamem_alloc(*dtag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO, 1006 dmap); 1007 if (error) { 1008 device_printf(dev, "can't allocate DMA mem\n"); 1009 bus_dma_tag_destroy(*dtag); 1010 *dtag = NULL; 1011 return (error); 1012 } 1013 1014 error = bus_dmamap_load(*dtag, *dmap, *addr, size, 1015 et_dma_ring_addr, paddr, BUS_DMA_WAITOK); 1016 if (error) { 1017 device_printf(dev, "can't load DMA mem\n"); 1018 bus_dmamem_free(*dtag, *addr, *dmap); 1019 bus_dma_tag_destroy(*dtag); 1020 *dtag = NULL; 1021 return (error); 1022 } 1023 return (0); 1024} 1025 1026static void 1027et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap) 1028{ 1029 if (dtag != NULL) { 1030 bus_dmamap_unload(dtag, dmap); 1031 bus_dmamem_free(dtag, addr, dmap); 1032 bus_dma_tag_destroy(dtag); 1033 } 1034} 1035 1036static void 1037et_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 1038{ 1039 KASSERT(nseg == 1, ("too many segments\n")); 1040 *((bus_addr_t *)arg) = seg->ds_addr; 1041} 1042 1043static void 1044et_chip_attach(struct et_softc *sc) 1045{ 1046 uint32_t val; 1047 1048 /* 1049 * Perform minimal initialization 1050 */ 1051 1052 /* Disable loopback */ 1053 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1054 1055 /* Reset MAC */ 1056 CSR_WRITE_4(sc, ET_MAC_CFG1, 1057 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1058 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1059 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1060 1061 /* 1062 * Setup half duplex mode 1063 */ 1064 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1065 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1066 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1067 ET_MAC_HDX_EXC_DEFER; 1068 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1069 1070 /* Clear MAC control */ 1071 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1072 1073 /* Reset MII */ 1074 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1075 1076 /* Bring MAC out of reset state */ 1077 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1078 1079 /* Enable memory controllers */ 1080 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1081} 1082 1083static void 1084et_intr(void *xsc) 1085{ 1086 struct et_softc *sc = xsc; 1087 struct ifnet *ifp; 1088 uint32_t intrs; 1089 1090 ET_LOCK(sc); 1091 ifp = sc->ifp; 1092 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1093 ET_UNLOCK(sc); 1094 return; 1095 } 1096 1097 et_disable_intrs(sc); 1098 1099 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 1100 intrs &= ET_INTRS; 1101 if (intrs == 0) /* Not interested */ 1102 goto back; 1103 1104 if (intrs & ET_INTR_RXEOF) 1105 et_rxeof(sc); 1106 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 1107 et_txeof(sc); 1108 if (intrs & ET_INTR_TIMER) 1109 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1110back: 1111 et_enable_intrs(sc, ET_INTRS); 1112 ET_UNLOCK(sc); 1113} 1114 1115static void 1116et_init_locked(struct et_softc *sc) 1117{ 1118 struct ifnet *ifp = sc->ifp; 1119 const struct et_bsize *arr; 1120 int error, i; 1121 1122 ET_LOCK_ASSERT(sc); 1123 1124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1125 return; 1126 1127 et_stop(sc); 1128 1129 arr = et_bufsize_std; 1130 for (i = 0; i < ET_RX_NRING; ++i) { 1131 sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize; 1132 sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf; 1133 } 1134 1135 error = et_init_tx_ring(sc); 1136 if (error) 1137 goto back; 1138 1139 error = et_init_rx_ring(sc); 1140 if (error) 1141 goto back; 1142 1143 error = et_chip_init(sc); 1144 if (error) 1145 goto back; 1146 1147 error = et_enable_txrx(sc, 1); 1148 if (error) 1149 goto back; 1150 1151 et_enable_intrs(sc, ET_INTRS); 1152 1153 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1154 1155 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1156 1157 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1159back: 1160 if (error) 1161 et_stop(sc); 1162} 1163 1164static void 1165et_init(void *xsc) 1166{ 1167 struct et_softc *sc = xsc; 1168 1169 ET_LOCK(sc); 1170 et_init_locked(sc); 1171 ET_UNLOCK(sc); 1172} 1173 1174static int 1175et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1176{ 1177 struct et_softc *sc = ifp->if_softc; 1178 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1179 struct ifreq *ifr = (struct ifreq *)data; 1180 int error = 0, mask, max_framelen; 1181 1182/* XXX LOCKSUSED */ 1183 switch (cmd) { 1184 case SIOCSIFFLAGS: 1185 ET_LOCK(sc); 1186 if (ifp->if_flags & IFF_UP) { 1187 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1188 if ((ifp->if_flags ^ sc->sc_if_flags) & 1189 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1190 et_setmulti(sc); 1191 } else { 1192 et_init_locked(sc); 1193 } 1194 } else { 1195 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1196 et_stop(sc); 1197 } 1198 sc->sc_if_flags = ifp->if_flags; 1199 ET_UNLOCK(sc); 1200 break; 1201 1202 case SIOCSIFMEDIA: 1203 case SIOCGIFMEDIA: 1204 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1205 break; 1206 1207 case SIOCADDMULTI: 1208 case SIOCDELMULTI: 1209 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1210 ET_LOCK(sc); 1211 et_setmulti(sc); 1212 ET_UNLOCK(sc); 1213 error = 0; 1214 } 1215 break; 1216 1217 case SIOCSIFMTU: 1218#if 0 1219 if (sc->sc_flags & ET_FLAG_JUMBO) 1220 max_framelen = ET_JUMBO_FRAMELEN; 1221 else 1222#endif 1223 max_framelen = MCLBYTES - 1; 1224 1225 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1226 error = EOPNOTSUPP; 1227 break; 1228 } 1229 1230 if (ifp->if_mtu != ifr->ifr_mtu) { 1231 ifp->if_mtu = ifr->ifr_mtu; 1232 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1233 et_init(sc); 1234 } 1235 break; 1236 1237 case SIOCSIFCAP: 1238 ET_LOCK(sc); 1239 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1240 if ((mask & IFCAP_TXCSUM) != 0 && 1241 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1242 ifp->if_capenable ^= IFCAP_TXCSUM; 1243 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1244 ifp->if_hwassist |= ET_CSUM_FEATURES; 1245 else 1246 ifp->if_hwassist &= ~ET_CSUM_FEATURES; 1247 } 1248 ET_UNLOCK(sc); 1249 break; 1250 1251 default: 1252 error = ether_ioctl(ifp, cmd, data); 1253 break; 1254 } 1255 return (error); 1256} 1257 1258static void 1259et_start_locked(struct ifnet *ifp) 1260{ 1261 struct et_softc *sc = ifp->if_softc; 1262 struct et_txbuf_data *tbd; 1263 int trans; 1264 1265 ET_LOCK_ASSERT(sc); 1266 tbd = &sc->sc_tx_data; 1267 1268 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 1269 return; 1270 1271 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) 1272 return; 1273 1274 trans = 0; 1275 for (;;) { 1276 struct mbuf *m; 1277 1278 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1279 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1280 break; 1281 } 1282 1283 IFQ_DEQUEUE(&ifp->if_snd, m); 1284 if (m == NULL) 1285 break; 1286 1287 if (et_encap(sc, &m)) { 1288 ifp->if_oerrors++; 1289 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1290 break; 1291 } 1292 trans = 1; 1293 1294 BPF_MTAP(ifp, m); 1295 } 1296 1297 if (trans) 1298 sc->watchdog_timer = 5; 1299} 1300 1301static void 1302et_start(struct ifnet *ifp) 1303{ 1304 struct et_softc *sc = ifp->if_softc; 1305 1306 ET_LOCK(sc); 1307 et_start_locked(ifp); 1308 ET_UNLOCK(sc); 1309} 1310 1311static void 1312et_watchdog(struct et_softc *sc) 1313{ 1314 ET_LOCK_ASSERT(sc); 1315 1316 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1317 return; 1318 1319 if_printf(sc->ifp, "watchdog timed out\n"); 1320 1321 et_init_locked(sc); 1322 et_start_locked(sc->ifp); 1323} 1324 1325static int 1326et_stop_rxdma(struct et_softc *sc) 1327{ 1328 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1329 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1330 1331 DELAY(5); 1332 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1333 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1334 return (ETIMEDOUT); 1335 } 1336 return (0); 1337} 1338 1339static int 1340et_stop_txdma(struct et_softc *sc) 1341{ 1342 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1343 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1344 return (0); 1345} 1346 1347static void 1348et_free_tx_ring(struct et_softc *sc) 1349{ 1350 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1351 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1352 int i; 1353 1354 for (i = 0; i < ET_TX_NDESC; ++i) { 1355 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1356 1357 if (tb->tb_mbuf != NULL) { 1358 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1359 m_freem(tb->tb_mbuf); 1360 tb->tb_mbuf = NULL; 1361 } 1362 } 1363 1364 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1365 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1366 BUS_DMASYNC_PREWRITE); 1367} 1368 1369static void 1370et_free_rx_ring(struct et_softc *sc) 1371{ 1372 int n; 1373 1374 for (n = 0; n < ET_RX_NRING; ++n) { 1375 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1376 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1377 int i; 1378 1379 for (i = 0; i < ET_RX_NDESC; ++i) { 1380 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1381 1382 if (rb->rb_mbuf != NULL) { 1383 bus_dmamap_unload(sc->sc_mbuf_dtag, 1384 rb->rb_dmap); 1385 m_freem(rb->rb_mbuf); 1386 rb->rb_mbuf = NULL; 1387 } 1388 } 1389 1390 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1391 bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap, 1392 BUS_DMASYNC_PREWRITE); 1393 } 1394} 1395 1396static void 1397et_setmulti(struct et_softc *sc) 1398{ 1399 struct ifnet *ifp; 1400 uint32_t hash[4] = { 0, 0, 0, 0 }; 1401 uint32_t rxmac_ctrl, pktfilt; 1402 struct ifmultiaddr *ifma; 1403 int i, count; 1404 1405 ET_LOCK_ASSERT(sc); 1406 ifp = sc->ifp; 1407 1408 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1409 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1410 1411 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1412 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1413 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1414 goto back; 1415 } 1416 1417 count = 0; 1418 if_maddr_rlock(ifp); 1419 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1420 uint32_t *hp, h; 1421 1422 if (ifma->ifma_addr->sa_family != AF_LINK) 1423 continue; 1424 1425 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1426 ifma->ifma_addr), ETHER_ADDR_LEN); 1427 h = (h & 0x3f800000) >> 23; 1428 1429 hp = &hash[0]; 1430 if (h >= 32 && h < 64) { 1431 h -= 32; 1432 hp = &hash[1]; 1433 } else if (h >= 64 && h < 96) { 1434 h -= 64; 1435 hp = &hash[2]; 1436 } else if (h >= 96) { 1437 h -= 96; 1438 hp = &hash[3]; 1439 } 1440 *hp |= (1 << h); 1441 1442 ++count; 1443 } 1444 if_maddr_runlock(ifp); 1445 1446 for (i = 0; i < 4; ++i) 1447 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1448 1449 if (count > 0) 1450 pktfilt |= ET_PKTFILT_MCAST; 1451 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1452back: 1453 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1454 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1455} 1456 1457static int 1458et_chip_init(struct et_softc *sc) 1459{ 1460 struct ifnet *ifp = sc->ifp; 1461 uint32_t rxq_end; 1462 int error, frame_len, rxmem_size; 1463 1464 /* 1465 * Split 16Kbytes internal memory between TX and RX 1466 * according to frame length. 1467 */ 1468 frame_len = ET_FRAMELEN(ifp->if_mtu); 1469 if (frame_len < 2048) { 1470 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1471 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1472 rxmem_size = ET_MEM_SIZE / 2; 1473 } else { 1474 rxmem_size = ET_MEM_SIZE - 1475 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1476 } 1477 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1478 1479 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1480 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1481 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1482 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1483 1484 /* No loopback */ 1485 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1486 1487 /* Clear MSI configure */ 1488 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1489 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1490 1491 /* Disable timer */ 1492 CSR_WRITE_4(sc, ET_TIMER, 0); 1493 1494 /* Initialize MAC */ 1495 et_init_mac(sc); 1496 1497 /* Enable memory controllers */ 1498 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1499 1500 /* Initialize RX MAC */ 1501 et_init_rxmac(sc); 1502 1503 /* Initialize TX MAC */ 1504 et_init_txmac(sc); 1505 1506 /* Initialize RX DMA engine */ 1507 error = et_init_rxdma(sc); 1508 if (error) 1509 return (error); 1510 1511 /* Initialize TX DMA engine */ 1512 error = et_init_txdma(sc); 1513 if (error) 1514 return (error); 1515 1516 return (0); 1517} 1518 1519static int 1520et_init_tx_ring(struct et_softc *sc) 1521{ 1522 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1523 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1524 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1525 1526 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1527 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1528 BUS_DMASYNC_PREWRITE); 1529 1530 tbd->tbd_start_index = 0; 1531 tbd->tbd_start_wrap = 0; 1532 tbd->tbd_used = 0; 1533 1534 bzero(txsd->txsd_status, sizeof(uint32_t)); 1535 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1536 BUS_DMASYNC_PREWRITE); 1537 return (0); 1538} 1539 1540static int 1541et_init_rx_ring(struct et_softc *sc) 1542{ 1543 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1544 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1545 int n; 1546 1547 for (n = 0; n < ET_RX_NRING; ++n) { 1548 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1549 int i, error; 1550 1551 for (i = 0; i < ET_RX_NDESC; ++i) { 1552 error = rbd->rbd_newbuf(rbd, i, 1); 1553 if (error) { 1554 if_printf(sc->ifp, "%d ring %d buf, " 1555 "newbuf failed: %d\n", n, i, error); 1556 return (error); 1557 } 1558 } 1559 } 1560 1561 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1562 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1563 BUS_DMASYNC_PREWRITE); 1564 1565 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1566 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1567 BUS_DMASYNC_PREWRITE); 1568 1569 return (0); 1570} 1571 1572static void 1573et_dma_buf_addr(void *xctx, bus_dma_segment_t *segs, int nsegs, 1574 bus_size_t mapsz __unused, int error) 1575{ 1576 struct et_dmamap_ctx *ctx = xctx; 1577 int i; 1578 1579 if (error) 1580 return; 1581 1582 if (nsegs > ctx->nsegs) { 1583 ctx->nsegs = 0; 1584 return; 1585 } 1586 1587 ctx->nsegs = nsegs; 1588 for (i = 0; i < nsegs; ++i) 1589 ctx->segs[i] = segs[i]; 1590} 1591 1592static int 1593et_init_rxdma(struct et_softc *sc) 1594{ 1595 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1596 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1597 struct et_rxdesc_ring *rx_ring; 1598 int error; 1599 1600 error = et_stop_rxdma(sc); 1601 if (error) { 1602 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1603 return (error); 1604 } 1605 1606 /* 1607 * Install RX status 1608 */ 1609 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1610 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1611 1612 /* 1613 * Install RX stat ring 1614 */ 1615 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1616 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1617 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1618 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1619 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1620 1621 /* Match ET_RXSTAT_POS */ 1622 rxst_ring->rsr_index = 0; 1623 rxst_ring->rsr_wrap = 0; 1624 1625 /* 1626 * Install the 2nd RX descriptor ring 1627 */ 1628 rx_ring = &sc->sc_rx_ring[1]; 1629 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1630 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1631 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1632 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1633 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1634 1635 /* Match ET_RX_RING1_POS */ 1636 rx_ring->rr_index = 0; 1637 rx_ring->rr_wrap = 1; 1638 1639 /* 1640 * Install the 1st RX descriptor ring 1641 */ 1642 rx_ring = &sc->sc_rx_ring[0]; 1643 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1644 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1645 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1646 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1647 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1648 1649 /* Match ET_RX_RING0_POS */ 1650 rx_ring->rr_index = 0; 1651 rx_ring->rr_wrap = 1; 1652 1653 /* 1654 * RX intr moderation 1655 */ 1656 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1657 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1658 1659 return (0); 1660} 1661 1662static int 1663et_init_txdma(struct et_softc *sc) 1664{ 1665 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1666 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1667 int error; 1668 1669 error = et_stop_txdma(sc); 1670 if (error) { 1671 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1672 return (error); 1673 } 1674 1675 /* 1676 * Install TX descriptor ring 1677 */ 1678 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1679 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1680 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1681 1682 /* 1683 * Install TX status 1684 */ 1685 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1686 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1687 1688 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1689 1690 /* Match ET_TX_READY_POS */ 1691 tx_ring->tr_ready_index = 0; 1692 tx_ring->tr_ready_wrap = 0; 1693 1694 return (0); 1695} 1696 1697static void 1698et_init_mac(struct et_softc *sc) 1699{ 1700 struct ifnet *ifp = sc->ifp; 1701 const uint8_t *eaddr = IF_LLADDR(ifp); 1702 uint32_t val; 1703 1704 /* Reset MAC */ 1705 CSR_WRITE_4(sc, ET_MAC_CFG1, 1706 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1707 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1708 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1709 1710 /* 1711 * Setup inter packet gap 1712 */ 1713 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1714 (88 << ET_IPG_NONB2B_2_SHIFT) | 1715 (80 << ET_IPG_MINIFG_SHIFT) | 1716 (96 << ET_IPG_B2B_SHIFT); 1717 CSR_WRITE_4(sc, ET_IPG, val); 1718 1719 /* 1720 * Setup half duplex mode 1721 */ 1722 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1723 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1724 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1725 ET_MAC_HDX_EXC_DEFER; 1726 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1727 1728 /* Clear MAC control */ 1729 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1730 1731 /* Reset MII */ 1732 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1733 1734 /* 1735 * Set MAC address 1736 */ 1737 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1738 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1739 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1740 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1741 1742 /* Set max frame length */ 1743 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1744 1745 /* Bring MAC out of reset state */ 1746 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1747} 1748 1749static void 1750et_init_rxmac(struct et_softc *sc) 1751{ 1752 struct ifnet *ifp = sc->ifp; 1753 const uint8_t *eaddr = IF_LLADDR(ifp); 1754 uint32_t val; 1755 int i; 1756 1757 /* Disable RX MAC and WOL */ 1758 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1759 1760 /* 1761 * Clear all WOL related registers 1762 */ 1763 for (i = 0; i < 3; ++i) 1764 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1765 for (i = 0; i < 20; ++i) 1766 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1767 1768 /* 1769 * Set WOL source address. XXX is this necessary? 1770 */ 1771 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1772 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1773 val = (eaddr[0] << 8) | eaddr[1]; 1774 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1775 1776 /* Clear packet filters */ 1777 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1778 1779 /* No ucast filtering */ 1780 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1781 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1782 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1783 1784 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1785 /* 1786 * In order to transmit jumbo packets greater than 1787 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1788 * RX MAC and RX DMA needs to be reduced in size to 1789 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1790 * order to implement this, we must use "cut through" 1791 * mode in the RX MAC, which chops packets down into 1792 * segments. In this case we selected 256 bytes, 1793 * since this is the size of the PCI-Express TLP's 1794 * that the ET1310 uses. 1795 */ 1796 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1797 ET_RXMAC_MC_SEGSZ_ENABLE; 1798 } else { 1799 val = 0; 1800 } 1801 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1802 1803 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1804 1805 /* Initialize RX MAC management register */ 1806 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1807 1808 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1809 1810 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1811 ET_RXMAC_MGT_PASS_ECRC | 1812 ET_RXMAC_MGT_PASS_ELEN | 1813 ET_RXMAC_MGT_PASS_ETRUNC | 1814 ET_RXMAC_MGT_CHECK_PKT); 1815 1816 /* 1817 * Configure runt filtering (may not work on certain chip generation) 1818 */ 1819 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1820 ET_PKTFILT_MINLEN_MASK; 1821 val |= ET_PKTFILT_FRAG; 1822 CSR_WRITE_4(sc, ET_PKTFILT, val); 1823 1824 /* Enable RX MAC but leave WOL disabled */ 1825 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1826 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1827 1828 /* 1829 * Setup multicast hash and allmulti/promisc mode 1830 */ 1831 et_setmulti(sc); 1832} 1833 1834static void 1835et_init_txmac(struct et_softc *sc) 1836{ 1837 /* Disable TX MAC and FC(?) */ 1838 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1839 1840 /* No flow control yet */ 1841 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1842 1843 /* Enable TX MAC but leave FC(?) diabled */ 1844 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1845 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1846} 1847 1848static int 1849et_start_rxdma(struct et_softc *sc) 1850{ 1851 uint32_t val = 0; 1852 1853 val |= (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 1854 ET_RXDMA_CTRL_RING0_ENABLE; 1855 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 1856 ET_RXDMA_CTRL_RING1_ENABLE; 1857 1858 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1859 1860 DELAY(5); 1861 1862 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1863 if_printf(sc->ifp, "can't start RX DMA engine\n"); 1864 return (ETIMEDOUT); 1865 } 1866 return (0); 1867} 1868 1869static int 1870et_start_txdma(struct et_softc *sc) 1871{ 1872 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1873 return (0); 1874} 1875 1876static int 1877et_enable_txrx(struct et_softc *sc, int media_upd) 1878{ 1879 struct ifnet *ifp = sc->ifp; 1880 uint32_t val; 1881 int i, error; 1882 1883 val = CSR_READ_4(sc, ET_MAC_CFG1); 1884 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1885 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1886 ET_MAC_CFG1_LOOPBACK); 1887 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1888 1889 if (media_upd) 1890 et_ifmedia_upd_locked(ifp); 1891 else 1892 et_setmedia(sc); 1893 1894#define NRETRY 50 1895 1896 for (i = 0; i < NRETRY; ++i) { 1897 val = CSR_READ_4(sc, ET_MAC_CFG1); 1898 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1899 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1900 break; 1901 1902 DELAY(100); 1903 } 1904 if (i == NRETRY) { 1905 if_printf(ifp, "can't enable RX/TX\n"); 1906 return (0); 1907 } 1908 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 1909 1910#undef NRETRY 1911 1912 /* 1913 * Start TX/RX DMA engine 1914 */ 1915 error = et_start_rxdma(sc); 1916 if (error) 1917 return (error); 1918 1919 error = et_start_txdma(sc); 1920 if (error) 1921 return (error); 1922 1923 return (0); 1924} 1925 1926static void 1927et_rxeof(struct et_softc *sc) 1928{ 1929 struct ifnet *ifp; 1930 struct et_rxstatus_data *rxsd; 1931 struct et_rxstat_ring *rxst_ring; 1932 uint32_t rxs_stat_ring, rxst_info2; 1933 int rxst_wrap, rxst_index; 1934 1935 ET_LOCK_ASSERT(sc); 1936 ifp = sc->ifp; 1937 rxsd = &sc->sc_rx_status; 1938 rxst_ring = &sc->sc_rxstat_ring; 1939 1940 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 1941 return; 1942 1943 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1944 BUS_DMASYNC_POSTREAD); 1945 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1946 BUS_DMASYNC_POSTREAD); 1947 1948 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 1949 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1950 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 1951 ET_RXS_STATRING_INDEX_SHIFT; 1952 1953 while (rxst_index != rxst_ring->rsr_index || 1954 rxst_wrap != rxst_ring->rsr_wrap) { 1955 struct et_rxbuf_data *rbd; 1956 struct et_rxdesc_ring *rx_ring; 1957 struct et_rxstat *st; 1958 struct mbuf *m; 1959 int buflen, buf_idx, ring_idx; 1960 uint32_t rxstat_pos, rxring_pos; 1961 1962 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 1963 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1964 rxst_info2 = le32toh(st->rxst_info2); 1965 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 1966 ET_RXST_INFO2_LEN_SHIFT; 1967 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 1968 ET_RXST_INFO2_BUFIDX_SHIFT; 1969 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 1970 ET_RXST_INFO2_RINGIDX_SHIFT; 1971 1972 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1973 rxst_ring->rsr_index = 0; 1974 rxst_ring->rsr_wrap ^= 1; 1975 } 1976 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 1977 if (rxst_ring->rsr_wrap) 1978 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1979 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1980 1981 if (ring_idx >= ET_RX_NRING) { 1982 ifp->if_ierrors++; 1983 if_printf(ifp, "invalid ring index %d\n", ring_idx); 1984 continue; 1985 } 1986 if (buf_idx >= ET_RX_NDESC) { 1987 ifp->if_ierrors++; 1988 if_printf(ifp, "invalid buf index %d\n", buf_idx); 1989 continue; 1990 } 1991 1992 rbd = &sc->sc_rx_data[ring_idx]; 1993 m = rbd->rbd_buf[buf_idx].rb_mbuf; 1994 1995 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1996 if (buflen < ETHER_CRC_LEN) { 1997 m_freem(m); 1998 m = NULL; 1999 ifp->if_ierrors++; 2000 } else { 2001 m->m_pkthdr.len = m->m_len = 2002 buflen - ETHER_CRC_LEN; 2003 m->m_pkthdr.rcvif = ifp; 2004 ifp->if_ipackets++; 2005 ET_UNLOCK(sc); 2006 ifp->if_input(ifp, m); 2007 ET_LOCK(sc); 2008 } 2009 } else { 2010 ifp->if_ierrors++; 2011 } 2012 m = NULL; /* Catch invalid reference */ 2013 2014 rx_ring = &sc->sc_rx_ring[ring_idx]; 2015 2016 if (buf_idx != rx_ring->rr_index) { 2017 if_printf(ifp, "WARNING!! ring %d, " 2018 "buf_idx %d, rr_idx %d\n", 2019 ring_idx, buf_idx, rx_ring->rr_index); 2020 } 2021 2022 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2023 if (++rx_ring->rr_index == ET_RX_NDESC) { 2024 rx_ring->rr_index = 0; 2025 rx_ring->rr_wrap ^= 1; 2026 } 2027 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2028 if (rx_ring->rr_wrap) 2029 rxring_pos |= ET_RX_RING_POS_WRAP; 2030 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2031 } 2032} 2033 2034static int 2035et_encap(struct et_softc *sc, struct mbuf **m0) 2036{ 2037 struct mbuf *m = *m0; 2038 bus_dma_segment_t segs[ET_NSEG_MAX]; 2039 struct et_dmamap_ctx ctx; 2040 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 2041 struct et_txbuf_data *tbd = &sc->sc_tx_data; 2042 struct et_txdesc *td; 2043 bus_dmamap_t map; 2044 int error, maxsegs, first_idx, last_idx, i; 2045 uint32_t csum_flags, tx_ready_pos, last_td_ctrl2; 2046 2047 maxsegs = ET_TX_NDESC - tbd->tbd_used; 2048 if (maxsegs > ET_NSEG_MAX) 2049 maxsegs = ET_NSEG_MAX; 2050 KASSERT(maxsegs >= ET_NSEG_SPARE, 2051 ("not enough spare TX desc (%d)\n", maxsegs)); 2052 2053 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2054 first_idx = tx_ring->tr_ready_index; 2055 map = tbd->tbd_buf[first_idx].tb_dmap; 2056 2057 ctx.nsegs = maxsegs; 2058 ctx.segs = segs; 2059 error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m, 2060 et_dma_buf_addr, &ctx, BUS_DMA_NOWAIT); 2061 if (!error && ctx.nsegs == 0) { 2062 bus_dmamap_unload(sc->sc_mbuf_dtag, map); 2063 error = EFBIG; 2064 } 2065 if (error && error != EFBIG) { 2066 if_printf(sc->ifp, "can't load TX mbuf, error %d\n", 2067 error); 2068 goto back; 2069 } 2070 if (error) { /* error == EFBIG */ 2071 struct mbuf *m_new; 2072 2073 m_new = m_defrag(m, M_DONTWAIT); 2074 if (m_new == NULL) { 2075 if_printf(sc->ifp, "can't defrag TX mbuf\n"); 2076 error = ENOBUFS; 2077 goto back; 2078 } else { 2079 *m0 = m = m_new; 2080 } 2081 2082 ctx.nsegs = maxsegs; 2083 ctx.segs = segs; 2084 error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m, 2085 et_dma_buf_addr, &ctx, 2086 BUS_DMA_NOWAIT); 2087 if (error || ctx.nsegs == 0) { 2088 if (ctx.nsegs == 0) { 2089 bus_dmamap_unload(sc->sc_mbuf_dtag, map); 2090 error = EFBIG; 2091 } 2092 if_printf(sc->ifp, 2093 "can't load defraged TX mbuf\n"); 2094 goto back; 2095 } 2096 } 2097 2098 bus_dmamap_sync(sc->sc_mbuf_dtag, map, BUS_DMASYNC_PREWRITE); 2099 2100 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2101 sc->sc_tx += ctx.nsegs; 2102 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2103 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2104 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2105 } 2106 2107 csum_flags = 0; 2108 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2109 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2110 csum_flags |= ET_TDCTRL2_CSUM_IP; 2111 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2112 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2113 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2114 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2115 } 2116 last_idx = -1; 2117 for (i = 0; i < ctx.nsegs; ++i) { 2118 int idx; 2119 2120 idx = (first_idx + i) % ET_TX_NDESC; 2121 td = &tx_ring->tr_desc[idx]; 2122 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2123 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2124 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2125 if (i == ctx.nsegs - 1) { /* Last frag */ 2126 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2127 last_idx = idx; 2128 } else 2129 td->td_ctrl2 = htole32(csum_flags); 2130 2131 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2132 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2133 tx_ring->tr_ready_index = 0; 2134 tx_ring->tr_ready_wrap ^= 1; 2135 } 2136 } 2137 td = &tx_ring->tr_desc[first_idx]; 2138 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); /* First frag */ 2139 2140 MPASS(last_idx >= 0); 2141 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2142 tbd->tbd_buf[last_idx].tb_dmap = map; 2143 tbd->tbd_buf[last_idx].tb_mbuf = m; 2144 2145 tbd->tbd_used += ctx.nsegs; 2146 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2147 2148 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2149 BUS_DMASYNC_PREWRITE); 2150 2151 tx_ready_pos = tx_ring->tr_ready_index & ET_TX_READY_POS_INDEX_MASK; 2152 if (tx_ring->tr_ready_wrap) 2153 tx_ready_pos |= ET_TX_READY_POS_WRAP; 2154 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 2155 2156 error = 0; 2157back: 2158 if (error) { 2159 m_freem(m); 2160 *m0 = NULL; 2161 } 2162 return (error); 2163} 2164 2165static void 2166et_txeof(struct et_softc *sc) 2167{ 2168 struct ifnet *ifp; 2169 struct et_txdesc_ring *tx_ring; 2170 struct et_txbuf_data *tbd; 2171 uint32_t tx_done; 2172 int end, wrap; 2173 2174 ET_LOCK_ASSERT(sc); 2175 ifp = sc->ifp; 2176 tx_ring = &sc->sc_tx_ring; 2177 tbd = &sc->sc_tx_data; 2178 2179 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2180 return; 2181 2182 if (tbd->tbd_used == 0) 2183 return; 2184 2185 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2186 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2187 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2188 2189 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2190 struct et_txbuf *tb; 2191 2192 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2193 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2194 2195 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 2196 sizeof(struct et_txdesc)); 2197 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2198 BUS_DMASYNC_PREWRITE); 2199 2200 if (tb->tb_mbuf != NULL) { 2201 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 2202 m_freem(tb->tb_mbuf); 2203 tb->tb_mbuf = NULL; 2204 ifp->if_opackets++; 2205 } 2206 2207 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2208 tbd->tbd_start_index = 0; 2209 tbd->tbd_start_wrap ^= 1; 2210 } 2211 2212 MPASS(tbd->tbd_used > 0); 2213 tbd->tbd_used--; 2214 } 2215 2216 if (tbd->tbd_used == 0) 2217 sc->watchdog_timer = 0; 2218 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 2219 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2220 2221 et_start_locked(ifp); 2222} 2223 2224static void 2225et_tick(void *xsc) 2226{ 2227 struct et_softc *sc = xsc; 2228 struct ifnet *ifp; 2229 struct mii_data *mii; 2230 2231 ET_LOCK_ASSERT(sc); 2232 ifp = sc->ifp; 2233 mii = device_get_softc(sc->sc_miibus); 2234 2235 mii_tick(mii); 2236 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 && 2237 (mii->mii_media_status & IFM_ACTIVE) && 2238 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2239 if_printf(ifp, "Link up, enable TX/RX\n"); 2240 if (et_enable_txrx(sc, 0) == 0) 2241 et_start_locked(ifp); 2242 } 2243 et_watchdog(sc); 2244 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2245} 2246 2247static int 2248et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 2249{ 2250 return (et_newbuf(rbd, buf_idx, init, MCLBYTES)); 2251} 2252 2253static int 2254et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 2255{ 2256 return (et_newbuf(rbd, buf_idx, init, MHLEN)); 2257} 2258 2259static int 2260et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 2261{ 2262 struct et_softc *sc = rbd->rbd_softc; 2263 struct et_rxbuf *rb; 2264 struct mbuf *m; 2265 struct et_dmamap_ctx ctx; 2266 bus_dma_segment_t seg; 2267 bus_dmamap_t dmap; 2268 int error, len; 2269 2270 MPASS(buf_idx < ET_RX_NDESC); 2271 rb = &rbd->rbd_buf[buf_idx]; 2272 2273 m = m_getl(len0, /* init ? M_WAIT :*/ M_DONTWAIT, MT_DATA, M_PKTHDR, &len); 2274 if (m == NULL) { 2275 error = ENOBUFS; 2276 2277 if (init) { 2278 if_printf(sc->ifp, 2279 "m_getl failed, size %d\n", len0); 2280 return (error); 2281 } else { 2282 goto back; 2283 } 2284 } 2285 m->m_len = m->m_pkthdr.len = len; 2286 2287 /* 2288 * Try load RX mbuf into temporary DMA tag 2289 */ 2290 ctx.nsegs = 1; 2291 ctx.segs = &seg; 2292 error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap, m, 2293 et_dma_buf_addr, &ctx, 2294 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 2295 if (error || ctx.nsegs == 0) { 2296 if (!error) { 2297 bus_dmamap_unload(sc->sc_mbuf_dtag, 2298 sc->sc_mbuf_tmp_dmap); 2299 error = EFBIG; 2300 if_printf(sc->ifp, "too many segments?!\n"); 2301 } 2302 m_freem(m); 2303 m = NULL; 2304 2305 if (init) { 2306 if_printf(sc->ifp, "can't load RX mbuf\n"); 2307 return (error); 2308 } else { 2309 goto back; 2310 } 2311 } 2312 2313 if (!init) { 2314 bus_dmamap_sync(sc->sc_mbuf_dtag, rb->rb_dmap, 2315 BUS_DMASYNC_POSTREAD); 2316 bus_dmamap_unload(sc->sc_mbuf_dtag, rb->rb_dmap); 2317 } 2318 rb->rb_mbuf = m; 2319 rb->rb_paddr = seg.ds_addr; 2320 2321 /* 2322 * Swap RX buf's DMA map with the loaded temporary one 2323 */ 2324 dmap = rb->rb_dmap; 2325 rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 2326 sc->sc_mbuf_tmp_dmap = dmap; 2327 2328 error = 0; 2329back: 2330 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr); 2331 return (error); 2332} 2333 2334/* 2335 * Create sysctl tree 2336 */ 2337static void 2338et_add_sysctls(struct et_softc * sc) 2339{ 2340 struct sysctl_ctx_list *ctx; 2341 struct sysctl_oid_list *children; 2342 2343 ctx = device_get_sysctl_ctx(sc->dev); 2344 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2345 2346 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2347 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I", 2348 "RX IM, # packets per RX interrupt"); 2349 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2350 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I", 2351 "RX IM, RX interrupt delay (x10 usec)"); 2352 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2353 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2354 "TX IM, # segments per TX interrupt"); 2355 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2356 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2357} 2358 2359static int 2360et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2361{ 2362 struct et_softc *sc = arg1; 2363 struct ifnet *ifp = sc->ifp; 2364 int error = 0, v; 2365 2366 v = sc->sc_rx_intr_npkts; 2367 error = sysctl_handle_int(oidp, &v, 0, req); 2368 if (error || req->newptr == NULL) 2369 goto back; 2370 if (v <= 0) { 2371 error = EINVAL; 2372 goto back; 2373 } 2374 2375 if (sc->sc_rx_intr_npkts != v) { 2376 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2377 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2378 sc->sc_rx_intr_npkts = v; 2379 } 2380back: 2381 return (error); 2382} 2383 2384static int 2385et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2386{ 2387 struct et_softc *sc = arg1; 2388 struct ifnet *ifp = sc->ifp; 2389 int error = 0, v; 2390 2391 v = sc->sc_rx_intr_delay; 2392 error = sysctl_handle_int(oidp, &v, 0, req); 2393 if (error || req->newptr == NULL) 2394 goto back; 2395 if (v <= 0) { 2396 error = EINVAL; 2397 goto back; 2398 } 2399 2400 if (sc->sc_rx_intr_delay != v) { 2401 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2402 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2403 sc->sc_rx_intr_delay = v; 2404 } 2405back: 2406 return (error); 2407} 2408 2409static void 2410et_setmedia(struct et_softc *sc) 2411{ 2412 struct mii_data *mii = device_get_softc(sc->sc_miibus); 2413 uint32_t cfg2, ctrl; 2414 2415 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 2416 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 2417 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 2418 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 2419 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 2420 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 2421 2422 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 2423 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 2424 2425 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 2426 cfg2 |= ET_MAC_CFG2_MODE_GMII; 2427 } else { 2428 cfg2 |= ET_MAC_CFG2_MODE_MII; 2429 ctrl |= ET_MAC_CTRL_MODE_MII; 2430 } 2431 2432 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 2433 cfg2 |= ET_MAC_CFG2_FDX; 2434 else 2435 ctrl |= ET_MAC_CTRL_GHDX; 2436 2437 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 2438 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 2439} 2440 2441static void 2442et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr) 2443{ 2444 struct et_rxdesc_ring *rx_ring = rbd->rbd_ring; 2445 struct et_rxdesc *desc; 2446 2447 MPASS(buf_idx < ET_RX_NDESC); 2448 desc = &rx_ring->rr_desc[buf_idx]; 2449 2450 desc->rd_addr_hi = htole32(ET_ADDR_HI(paddr)); 2451 desc->rd_addr_lo = htole32(ET_ADDR_LO(paddr)); 2452 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2453 2454 bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap, 2455 BUS_DMASYNC_PREWRITE); 2456} 2457