esp_sbus.c revision 145201
1/*- 2 * Copyright (c) 2004 Scott Long 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28/* $NetBSD: esp_sbus.c,v 1.31 2005/02/27 00:27:48 perry Exp $ */ 29 30/*- 31 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 36 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67#include <sys/cdefs.h> 68__FBSDID("$FreeBSD: head/sys/dev/esp/esp_sbus.c 145201 2005-04-17 17:42:36Z marius $"); 69 70#include <sys/param.h> 71#include <sys/systm.h> 72#include <sys/bus.h> 73#include <sys/kernel.h> 74#include <sys/module.h> 75#include <sys/resource.h> 76 77#include <dev/ofw/ofw_bus.h> 78#include <dev/ofw/openfirm.h> 79#include <machine/bus.h> 80#include <machine/resource.h> 81#include <sys/rman.h> 82 83#include <cam/cam.h> 84#include <cam/cam_ccb.h> 85#include <cam/scsi/scsi_all.h> 86 87#include <sparc64/sbus/lsi64854reg.h> 88#include <sparc64/sbus/lsi64854var.h> 89#include <sparc64/sbus/sbusvar.h> 90 91#include <dev/esp/ncr53c9xreg.h> 92#include <dev/esp/ncr53c9xvar.h> 93 94/* #define ESP_SBUS_DEBUG */ 95 96struct esp_softc { 97 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 98 struct device *sc_dev; 99 100 int sc_rid; 101 struct resource *sc_res; 102 bus_space_handle_t sc_regh; 103 bus_space_tag_t sc_regt; 104 105 int sc_irqrid; 106 struct resource *sc_irqres; 107 void *sc_irq; 108 109 struct lsi64854_softc *sc_dma; /* pointer to my DMA */ 110}; 111 112static int esp_sbus_probe(device_t); 113static int esp_sbus_attach(device_t); 114static int esp_sbus_detach(device_t); 115static int esp_sbus_suspend(device_t); 116static int esp_sbus_resume(device_t); 117 118static device_method_t esp_sbus_methods[] = { 119 DEVMETHOD(device_probe, esp_sbus_probe), 120 DEVMETHOD(device_attach, esp_sbus_attach), 121 DEVMETHOD(device_detach, esp_sbus_detach), 122 DEVMETHOD(device_suspend, esp_sbus_suspend), 123 DEVMETHOD(device_resume, esp_sbus_resume), 124 {0, 0} 125}; 126 127static driver_t esp_sbus_driver = { 128 "esp", 129 esp_sbus_methods, 130 sizeof(struct esp_softc) 131}; 132 133static devclass_t esp_devclass; 134DRIVER_MODULE(esp, sbus, esp_sbus_driver, esp_devclass, 0, 0); 135 136/* 137 * Functions and the switch for the MI code. 138 */ 139static u_char esp_read_reg(struct ncr53c9x_softc *, int); 140static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 141static int esp_dma_isintr(struct ncr53c9x_softc *); 142static void esp_dma_reset(struct ncr53c9x_softc *); 143static int esp_dma_intr(struct ncr53c9x_softc *); 144static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, 145 int, size_t *); 146static void esp_dma_go(struct ncr53c9x_softc *); 147static void esp_dma_stop(struct ncr53c9x_softc *); 148static int esp_dma_isactive(struct ncr53c9x_softc *); 149static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 150 151static struct ncr53c9x_glue esp_sbus_glue = { 152 esp_read_reg, 153 esp_write_reg, 154 esp_dma_isintr, 155 esp_dma_reset, 156 esp_dma_intr, 157 esp_dma_setup, 158 esp_dma_go, 159 esp_dma_stop, 160 esp_dma_isactive, 161 NULL, /* gl_clear_latched_intr */ 162}; 163 164static int 165esp_sbus_probe(device_t dev) 166{ 167 const char *name; 168 169 name = ofw_bus_get_name(dev); 170 if (strcmp("SUNW,fas", name) == 0) { 171 device_set_desc(dev, "Sun FAS366 Fast-Wide SCSI"); 172 return (BUS_PROBE_DEFAULT); 173 } 174 175 return (ENXIO); 176} 177 178static int 179esp_sbus_attach(device_t dev) 180{ 181 struct esp_softc *esc; 182 struct ncr53c9x_softc *sc; 183 struct lsi64854_softc *lsc; 184 phandle_t node; 185 int burst; 186 187 esc = device_get_softc(dev); 188 bzero(esc, sizeof(struct esp_softc)); 189 sc = &esc->sc_ncr53c9x; 190 191 esc->sc_dev = dev; 192 node = ofw_bus_get_node(dev); 193 if (OF_getprop(node, "initiator-id", &sc->sc_id, 194 sizeof(sc->sc_id)) == -1) 195 sc->sc_id = 7; 196 if (OF_getprop(node, "clock-frequency", &sc->sc_freq, 197 sizeof(sc->sc_freq)) == -1) { 198 printf("failed to query OFW for clock-frequency\n"); 199 sc->sc_freq = sbus_get_clockfreq(dev); 200 } 201 202#ifdef ESP_SBUS_DEBUG 203 device_printf(dev, "%s: sc_id %d, freq %d\n", __func__, sc->sc_id, 204 sc->sc_freq); 205#endif 206 207 /* 208 * allocate space for DMA, in SUNW,fas there are no separate 209 * DMA devices 210 */ 211 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, 212 M_NOWAIT | M_ZERO); 213 if (lsc == NULL) { 214 device_printf(dev, "out of memory (lsi64854_softc)\n"); 215 return (ENOMEM); 216 } 217 esc->sc_dma = lsc; 218 219 /* 220 * fas has 2 register spaces: DMA (lsi64854) and SCSI core (ncr53c9x) 221 */ 222 223 /* allocate DMA registers */ 224 lsc->sc_rid = 0; 225 if ((lsc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 226 &lsc->sc_rid, RF_ACTIVE)) == NULL) { 227 device_printf(dev, "cannot allocate DMA registers\n"); 228 free(lsc, M_DEVBUF); 229 return (ENXIO); 230 } 231 lsc->sc_regt = rman_get_bustag(lsc->sc_res); 232 lsc->sc_regh = rman_get_bushandle(lsc->sc_res); 233 234 /* Create a parent DMA tag based on this bus */ 235 if (bus_dma_tag_create( 236 NULL, /* parent */ 237 PAGE_SIZE, 0, /* alignment, boundary */ 238 BUS_SPACE_MAXADDR, /* lowaddr */ 239 BUS_SPACE_MAXADDR, /* highaddr */ 240 NULL, NULL, /* filter, filterarg */ 241 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 242 0, /* nsegments */ 243 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 244 0, /* flags */ 245 NULL, NULL, /* no locking */ 246 &lsc->sc_parent_dmat)) { 247 device_printf(dev, "cannot allocate parent DMA tag\n"); 248 free(lsc, M_DEVBUF); 249 return (ENOMEM); 250 } 251 burst = sbus_get_burstsz(dev); 252 253#ifdef ESP_SBUS_DEBUG 254 printf("%s: burst 0x%x\n", __func__, burst); 255#endif 256 257 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 258 (burst & SBUS_BURST_16) ? 16 : 0; 259 260 lsc->sc_channel = L64854_CHANNEL_SCSI; 261 lsc->sc_client = sc; 262 lsc->sc_dev = dev; 263 264 lsi64854_attach(lsc); 265 266 /* 267 * allocate SCSI core registers 268 */ 269 esc->sc_rid = 1; 270 if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 271 &esc->sc_rid, RF_ACTIVE)) == NULL) { 272 device_printf(dev, "cannot allocate SCSI core registers\n"); 273 free(lsc, M_DEVBUF); 274 return (ENXIO); 275 } 276 esc->sc_regt = rman_get_bustag(esc->sc_res); 277 esc->sc_regh = rman_get_bushandle(esc->sc_res); 278 279 espattach(esc, &esp_sbus_glue); 280 281 return (0); 282} 283 284static int 285esp_sbus_detach(device_t dev) 286{ 287 struct ncr53c9x_softc *sc; 288 struct esp_softc *esc; 289 290 esc = device_get_softc(dev); 291 sc = &esc->sc_ncr53c9x; 292 return (ncr53c9x_detach(sc, 0)); 293} 294 295static int 296esp_sbus_suspend(device_t dev) 297{ 298 299 return (ENXIO); 300} 301 302static int 303esp_sbus_resume(device_t dev) 304{ 305 306 return (ENXIO); 307} 308 309/* 310 * Attach this instance, and then all the sub-devices 311 */ 312static void 313espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 314{ 315 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 316 unsigned int uid = 0; 317 318 /* 319 * Set up glue for MI code early; we use some of it here. 320 */ 321 sc->sc_glue = gluep; 322 323 /* gimme MHz */ 324 sc->sc_freq /= 1000000; 325 326 /* 327 * XXX More of this should be in ncr53c9x_attach(), but 328 * XXX should we really poke around the chip that much in 329 * XXX the MI code? Think about this more... 330 */ 331 332 /* 333 * It is necessary to try to load the 2nd config register here, 334 * to find out what rev the esp chip is, else the ncr53c9x_reset 335 * will not set up the defaults correctly. 336 */ 337 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 338 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 339 sc->sc_cfg3 = NCRCFG3_CDB; 340 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 341 342 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 343 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 344 sc->sc_rev = NCR_VARIANT_ESP100; 345 } else { 346 sc->sc_cfg2 = NCRCFG2_SCSI2; 347 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 348 sc->sc_cfg3 = 0; 349 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 350 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 351 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 352 if (NCR_READ_REG(sc, NCR_CFG3) != 353 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 354 sc->sc_rev = NCR_VARIANT_ESP100A; 355 } else { 356 /* NCRCFG2_FE enables > 64K transfers */ 357 sc->sc_cfg2 |= NCRCFG2_FE; 358 sc->sc_cfg3 = 0; 359 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 360 sc->sc_rev = NCR_VARIANT_ESP200; 361 362 /* 363 * XXX spec says it's valid after power up or chip 364 * reset. 365 */ 366 uid = NCR_READ_REG(sc, NCR_UID); 367 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 368 sc->sc_rev = NCR_VARIANT_FAS366; 369 } 370 } 371 372#ifdef ESP_SBUS_DEBUG 373 printf("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid); 374#endif 375 376 /* 377 * XXX minsync and maxxfer _should_ be set up in MI code, 378 * XXX but it appears to have some dependency on what sort 379 * XXX of DMA we're hooked up to, etc. 380 */ 381 382 /* 383 * This is the value used to start sync negotiations 384 * Note that the NCR register "SYNCTP" is programmed 385 * in "clocks per byte", and has a minimum value of 4. 386 * The SCSI period used in negotiation is one-fourth 387 * of the time (in nanoseconds) needed to transfer one byte. 388 * Since the chip's clock is given in MHz, we have the following 389 * formula: 4 * period = (1000 / freq) * 4 390 */ 391 sc->sc_minsync = 1000 / sc->sc_freq; 392 393 /* limit minsync due to unsolved performance issues */ 394 sc->sc_maxsync = sc->sc_minsync; 395 sc->sc_maxoffset = 15; 396 397 sc->sc_extended_geom = 1; 398 399 /* 400 * Alas, we must now modify the value a bit, because it's 401 * only valid when can switch on FASTCLK and FASTSCSI bits 402 * in config register 3... 403 */ 404 switch (sc->sc_rev) { 405 case NCR_VARIANT_ESP100: 406 sc->sc_maxwidth = 0; 407 sc->sc_maxxfer = 64 * 1024; 408 sc->sc_minsync = 0; /* No synch on old chip? */ 409 break; 410 411 case NCR_VARIANT_ESP100A: 412 sc->sc_maxwidth = 1; 413 sc->sc_maxxfer = 64 * 1024; 414 /* Min clocks/byte is 5 */ 415 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 416 break; 417 418 case NCR_VARIANT_ESP200: 419 case NCR_VARIANT_FAS366: 420 sc->sc_maxwidth = 1; 421 sc->sc_maxxfer = 16 * 1024 * 1024; 422 /* XXX - do actually set FAST* bits */ 423 break; 424 } 425 426 /* Establish interrupt channel */ 427 esc->sc_irqrid = 0; 428 if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ, 429 &esc->sc_irqrid, RF_SHAREABLE|RF_ACTIVE)) == NULL) { 430 device_printf(esc->sc_dev, "Cannot allocate interrupt\n"); 431 return; 432 } 433 if (bus_setup_intr(esc->sc_dev, esc->sc_irqres, 434 INTR_TYPE_BIO|INTR_MPSAFE, ncr53c9x_intr, sc, &esc->sc_irq)) { 435 device_printf(esc->sc_dev, "Cannot set up interrupt\n"); 436 return; 437 } 438 439 /* Turn on target selection using the `DMA' method */ 440 if (sc->sc_rev != NCR_VARIANT_FAS366) 441 sc->sc_features |= NCR_F_DMASELECT; 442 443 /* Do the common parts of attachment. */ 444 sc->sc_dev = esc->sc_dev; 445 ncr53c9x_attach(sc); 446} 447 448/* 449 * Glue functions. 450 */ 451 452#ifdef ESP_SBUS_DEBUG 453int esp_sbus_debug = 0; 454 455static struct { 456 char *r_name; 457 int r_flag; 458} esp__read_regnames [] = { 459 { "TCL", 0}, /* 0/00 */ 460 { "TCM", 0}, /* 1/04 */ 461 { "FIFO", 0}, /* 2/08 */ 462 { "CMD", 0}, /* 3/0c */ 463 { "STAT", 0}, /* 4/10 */ 464 { "INTR", 0}, /* 5/14 */ 465 { "STEP", 0}, /* 6/18 */ 466 { "FFLAGS", 1}, /* 7/1c */ 467 { "CFG1", 1}, /* 8/20 */ 468 { "STAT2", 0}, /* 9/24 */ 469 { "CFG4", 1}, /* a/28 */ 470 { "CFG2", 1}, /* b/2c */ 471 { "CFG3", 1}, /* c/30 */ 472 { "-none", 1}, /* d/34 */ 473 { "TCH", 1}, /* e/38 */ 474 { "TCX", 1}, /* f/3c */ 475}; 476 477static struct { 478 char *r_name; 479 int r_flag; 480} esp__write_regnames[] = { 481 { "TCL", 1}, /* 0/00 */ 482 { "TCM", 1}, /* 1/04 */ 483 { "FIFO", 0}, /* 2/08 */ 484 { "CMD", 0}, /* 3/0c */ 485 { "SELID", 1}, /* 4/10 */ 486 { "TIMEOUT", 1}, /* 5/14 */ 487 { "SYNCTP", 1}, /* 6/18 */ 488 { "SYNCOFF", 1}, /* 7/1c */ 489 { "CFG1", 1}, /* 8/20 */ 490 { "CCF", 1}, /* 9/24 */ 491 { "TEST", 1}, /* a/28 */ 492 { "CFG2", 1}, /* b/2c */ 493 { "CFG3", 1}, /* c/30 */ 494 { "-none", 1}, /* d/34 */ 495 { "TCH", 1}, /* e/38 */ 496 { "TCX", 1}, /* f/3c */ 497}; 498#endif 499 500static u_char 501esp_read_reg(struct ncr53c9x_softc *sc, int reg) 502{ 503 struct esp_softc *esc = (struct esp_softc *)sc; 504 u_char v; 505 506 v = bus_space_read_1(esc->sc_regt, esc->sc_regh, reg * 4); 507#ifdef ESP_SBUS_DEBUG 508 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 509 printf("RD:%x <%s> %x\n", reg * 4, 510 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 511#endif 512 return v; 513} 514 515static void 516esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 517{ 518 struct esp_softc *esc = (struct esp_softc *)sc; 519 520#ifdef ESP_SBUS_DEBUG 521 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 522 printf("WR:%x <%s> %x\n", reg * 4, 523 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 524#endif 525 bus_space_write_1(esc->sc_regt, esc->sc_regh, reg * 4, v); 526} 527 528static int 529esp_dma_isintr(struct ncr53c9x_softc *sc) 530{ 531 struct esp_softc *esc = (struct esp_softc *)sc; 532 533 return (DMA_ISINTR(esc->sc_dma)); 534} 535 536static void 537esp_dma_reset(struct ncr53c9x_softc *sc) 538{ 539 struct esp_softc *esc = (struct esp_softc *)sc; 540 541 DMA_RESET(esc->sc_dma); 542} 543 544static int 545esp_dma_intr(struct ncr53c9x_softc *sc) 546{ 547 struct esp_softc *esc = (struct esp_softc *)sc; 548 549 return (DMA_INTR(esc->sc_dma)); 550} 551 552static int 553esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 554 int datain, size_t *dmasize) 555{ 556 struct esp_softc *esc = (struct esp_softc *)sc; 557 558 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 559} 560 561static void 562esp_dma_go(struct ncr53c9x_softc *sc) 563{ 564 struct esp_softc *esc = (struct esp_softc *)sc; 565 566 DMA_GO(esc->sc_dma); 567} 568 569static void 570esp_dma_stop(struct ncr53c9x_softc *sc) 571{ 572 struct esp_softc *esc = (struct esp_softc *)sc; 573 uint32_t csr; 574 575 csr = L64854_GCSR(esc->sc_dma); 576 csr &= ~D_EN_DMA; 577 L64854_SCSR(esc->sc_dma, csr); 578} 579 580static int 581esp_dma_isactive(struct ncr53c9x_softc *sc) 582{ 583 struct esp_softc *esc = (struct esp_softc *)sc; 584 585 return (DMA_ISACTIVE(esc->sc_dma)); 586} 587