esp_sbus.c revision 135152
1/*- 2 * Copyright (c) 2004 Scott Long 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28/* $NetBSD: esp_sbus.c,v 1.27 2002/12/10 13:44:47 pk Exp $ */ 29 30/*- 31 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 36 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67#include <sys/cdefs.h> 68__FBSDID("$FreeBSD: head/sys/dev/esp/esp_sbus.c 135152 2004-09-13 15:15:38Z scottl $"); 69 70#include <sys/param.h> 71#include <sys/systm.h> 72#include <sys/bus.h> 73#include <sys/kernel.h> 74#include <sys/module.h> 75#include <sys/resource.h> 76#include <sys/lock.h> 77#include <sys/mutex.h> 78 79#include <dev/ofw/ofw_bus.h> 80#include <dev/ofw/openfirm.h> 81#include <machine/bus.h> 82#include <machine/ofw_machdep.h> 83#include <machine/resource.h> 84#include <sys/rman.h> 85#include <sparc64/sbus/sbusvar.h> 86 87#include <cam/cam.h> 88#include <cam/cam_ccb.h> 89#include <cam/scsi/scsi_all.h> 90 91#include <dev/esp/lsi64854reg.h> 92#include <dev/esp/lsi64854var.h> 93 94#include <dev/esp/ncr53c9xreg.h> 95#include <dev/esp/ncr53c9xvar.h> 96 97/* #define ESP_SBUS_DEBUG */ 98 99struct esp_softc { 100 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 101 struct device *sc_dev; 102 103 int sc_rid; 104 struct resource *sc_res; 105 bus_space_handle_t sc_regh; 106 bus_space_tag_t sc_regt; 107 108 int sc_irqrid; 109 struct resource *sc_irqres; 110 void *sc_irq; 111 112 struct lsi64854_softc *sc_dma; /* pointer to my DMA */ 113 114 int sc_pri; /* SBUS priority */ 115}; 116 117static int esp_sbus_probe(device_t); 118static int esp_sbus_attach(device_t); 119static int esp_sbus_detach(device_t); 120static int esp_sbus_suspend(device_t); 121static int esp_sbus_resume(device_t); 122 123static device_method_t esp_sbus_methods[] = { 124 DEVMETHOD(device_probe, esp_sbus_probe), 125 DEVMETHOD(device_attach, esp_sbus_attach), 126 DEVMETHOD(device_detach, esp_sbus_detach), 127 DEVMETHOD(device_suspend, esp_sbus_suspend), 128 DEVMETHOD(device_resume, esp_sbus_resume), 129 {0, 0} 130}; 131 132static driver_t esp_sbus_driver = { 133 "esp", 134 esp_sbus_methods, 135 sizeof(struct esp_softc) 136}; 137 138static devclass_t esp_devclass; 139DRIVER_MODULE(esp, sbus, esp_sbus_driver, esp_devclass, 0, 0); 140 141/* 142 * Functions and the switch for the MI code. 143 */ 144static u_char esp_read_reg(struct ncr53c9x_softc *, int); 145static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 146static int esp_dma_isintr(struct ncr53c9x_softc *); 147static void esp_dma_reset(struct ncr53c9x_softc *); 148static int esp_dma_intr(struct ncr53c9x_softc *); 149static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, 150 int, size_t *); 151static void esp_dma_go(struct ncr53c9x_softc *); 152static void esp_dma_stop(struct ncr53c9x_softc *); 153static int esp_dma_isactive(struct ncr53c9x_softc *); 154static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 155 156static struct ncr53c9x_glue esp_sbus_glue = { 157 esp_read_reg, 158 esp_write_reg, 159 esp_dma_isintr, 160 esp_dma_reset, 161 esp_dma_intr, 162 esp_dma_setup, 163 esp_dma_go, 164 esp_dma_stop, 165 esp_dma_isactive, 166 NULL, /* gl_clear_latched_intr */ 167}; 168 169static int 170esp_sbus_probe(device_t dev) 171{ 172 const char *name; 173 174 name = ofw_bus_get_name(dev); 175 if (strcmp("SUNW,fas", name) == 0) { 176 device_set_desc(dev, "Sun FAS366 Fast-Wide SCSI"); 177 return (-10); 178 } 179 180 return (ENXIO); 181} 182 183static int 184esp_sbus_attach(device_t dev) 185{ 186 struct esp_softc *esc = device_get_softc(dev); 187 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 188 struct lsi64854_softc *lsc; 189 phandle_t node; 190 int burst; 191 192 esc->sc_dev = dev; 193 node = ofw_bus_get_node(dev); 194 if (OF_getprop(node, "initiator-id", &sc->sc_id, 195 sizeof(sc->sc_id)) == -1) 196 sc->sc_id = 7; 197 if (OF_getprop(node, "clock-frequency", &sc->sc_freq, 198 sizeof(sc->sc_freq)) == -1) { 199 printf("failed to query OFW for clock-frequency\n"); 200 sc->sc_freq = sbus_get_clockfreq(dev); 201 } 202 203#ifdef ESP_SBUS_DEBUG 204 device_printf(dev, "espattach_sbus: sc_id %d, freq %d\n", 205 sc->sc_id, sc->sc_freq); 206#endif 207 208 /* 209 * allocate space for dma, in SUNW,fas there are no separate 210 * dma devices 211 */ 212 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 213 214 if (lsc == NULL) { 215 device_printf(dev, "out of memory (lsi64854_softc)\n"); 216 return (ENOMEM); 217 } 218 esc->sc_dma = lsc; 219 220 /* 221 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 222 */ 223 224 /* Map dma registers */ 225 lsc->sc_rid = 0; 226 if ((lsc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 227 &lsc->sc_rid, RF_ACTIVE)) == NULL) { 228 device_printf(dev, "cannot map dma registers\n"); 229 free(lsc, M_DEVBUF); 230 return (ENXIO); 231 } 232 lsc->sc_regt = rman_get_bustag(lsc->sc_res); 233 lsc->sc_regh = rman_get_bushandle(lsc->sc_res); 234 235 /* Create a parent DMA tag based on this bus */ 236 if (bus_dma_tag_create(NULL, /* parent */ 237 PAGE_SIZE, 0, /* algnmnt, boundary */ 238 BUS_SPACE_MAXADDR, /* lowaddr */ 239 BUS_SPACE_MAXADDR, /* highaddr */ 240 NULL, NULL, /* filter, filterarg */ 241 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 242 0, /* nsegments */ 243 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 244 0, /* flags */ 245 NULL, NULL, /* No locking */ 246 &lsc->sc_parent_dmat)) { 247 device_printf(dev, "cannot allocate parent DMA tag\n"); 248 free(lsc, M_DEVBUF); 249 return (ENOMEM); 250 } 251 burst = sbus_get_burstsz(dev); 252 253#ifdef ESP_SBUS_DEBUG 254 printf("espattach_sbus: burst 0x%x\n", burst); 255#endif 256 257 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 258 (burst & SBUS_BURST_16) ? 16 : 0; 259 260 lsc->sc_channel = L64854_CHANNEL_SCSI; 261 lsc->sc_client = sc; 262 lsc->sc_dev = dev; 263 264 lsi64854_attach(lsc); 265 266 /* 267 * map SCSI core registers 268 */ 269 esc->sc_rid = 1; 270 if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 271 &esc->sc_rid, RF_ACTIVE)) == NULL) { 272 device_printf(dev, "cannot map scsi core registers\n"); 273 free(lsc, M_DEVBUF); 274 return (ENXIO); 275 } 276 esc->sc_regt = rman_get_bustag(esc->sc_res); 277 esc->sc_regh = rman_get_bushandle(esc->sc_res); 278 279#if 0 280 esc->sc_pri = sa->sa_pri; 281 282 /* add me to the sbus structures */ 283 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 284 sbus_establish(&esc->sc_sd, &sc->sc_dev); 285#endif 286 287 espattach(esc, &esp_sbus_glue); 288 289 return (0); 290} 291 292static int 293esp_sbus_detach(device_t dev) 294{ 295 struct ncr53c9x_softc *sc; 296 struct esp_softc *esc; 297 298 esc = device_get_softc(dev); 299 sc = &esc->sc_ncr53c9x; 300 return (ncr53c9x_detach(sc, 0)); 301} 302 303static int 304esp_sbus_suspend(device_t dev) 305{ 306 return (ENXIO); 307} 308 309static int 310esp_sbus_resume(device_t dev) 311{ 312 return (ENXIO); 313} 314 315/* 316 * Attach this instance, and then all the sub-devices 317 */ 318void 319espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 320{ 321 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 322 unsigned int uid = 0; 323 324 /* 325 * Set up glue for MI code early; we use some of it here. 326 */ 327 sc->sc_glue = gluep; 328 329 /* gimme MHz */ 330 sc->sc_freq /= 1000000; 331 332 /* 333 * XXX More of this should be in ncr53c9x_attach(), but 334 * XXX should we really poke around the chip that much in 335 * XXX the MI code? Think about this more... 336 */ 337 338 /* 339 * It is necessary to try to load the 2nd config register here, 340 * to find out what rev the esp chip is, else the ncr53c9x_reset 341 * will not set up the defaults correctly. 342 */ 343 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 344 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 345 sc->sc_cfg3 = NCRCFG3_CDB; 346 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 347 348 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 349 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 350 sc->sc_rev = NCR_VARIANT_ESP100; 351 } else { 352 sc->sc_cfg2 = NCRCFG2_SCSI2; 353 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 354 sc->sc_cfg3 = 0; 355 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 356 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 357 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 358 if (NCR_READ_REG(sc, NCR_CFG3) != 359 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 360 sc->sc_rev = NCR_VARIANT_ESP100A; 361 } else { 362 /* NCRCFG2_FE enables > 64K transfers */ 363 sc->sc_cfg2 |= NCRCFG2_FE; 364 sc->sc_cfg3 = 0; 365 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 366 sc->sc_rev = NCR_VARIANT_ESP200; 367 368 /* XXX spec says it's valid after power up or chip reset */ 369 uid = NCR_READ_REG(sc, NCR_UID); 370 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 371 sc->sc_rev = NCR_VARIANT_FAS366; 372 } 373 } 374 375#ifdef ESP_SBUS_DEBUG 376 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 377#endif 378 379 /* 380 * XXX minsync and maxxfer _should_ be set up in MI code, 381 * XXX but it appears to have some dependency on what sort 382 * XXX of DMA we're hooked up to, etc. 383 */ 384 385 /* 386 * This is the value used to start sync negotiations 387 * Note that the NCR register "SYNCTP" is programmed 388 * in "clocks per byte", and has a minimum value of 4. 389 * The SCSI period used in negotiation is one-fourth 390 * of the time (in nanoseconds) needed to transfer one byte. 391 * Since the chip's clock is given in MHz, we have the following 392 * formula: 4 * period = (1000 / freq) * 4 393 */ 394 sc->sc_minsync = 1000 / sc->sc_freq; 395 396 /* limit minsync due to unsolved performance issues */ 397 sc->sc_maxsync = sc->sc_minsync; 398 sc->sc_maxoffset = 15; 399 400 sc->sc_extended_geom = 1; 401 402 /* 403 * Alas, we must now modify the value a bit, because it's 404 * only valid when can switch on FASTCLK and FASTSCSI bits 405 * in config register 3... 406 */ 407 switch (sc->sc_rev) { 408 case NCR_VARIANT_ESP100: 409 sc->sc_maxwidth = 0; 410 sc->sc_maxxfer = 64 * 1024; 411 sc->sc_minsync = 0; /* No synch on old chip? */ 412 break; 413 414 case NCR_VARIANT_ESP100A: 415 sc->sc_maxwidth = 1; 416 sc->sc_maxxfer = 64 * 1024; 417 /* Min clocks/byte is 5 */ 418 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 419 break; 420 421 case NCR_VARIANT_ESP200: 422 case NCR_VARIANT_FAS366: 423 sc->sc_maxwidth = 1; 424 sc->sc_maxxfer = 16 * 1024 * 1024; 425 /* XXX - do actually set FAST* bits */ 426 break; 427 } 428 429 /* Establish interrupt channel */ 430 esc->sc_irqrid = 0; 431 if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ, 432 &esc->sc_irqrid, RF_SHAREABLE|RF_ACTIVE)) == NULL) { 433 device_printf(esc->sc_dev, "Cannot allocate interrupt\n"); 434 return; 435 } 436 if (bus_setup_intr(esc->sc_dev, esc->sc_irqres, 437 INTR_TYPE_BIO|INTR_ENTROPY, ncr53c9x_intr, sc, &esc->sc_irq)) { 438 device_printf(esc->sc_dev, "Cannot set up interrupt\n"); 439 return; 440 } 441 442 /* Turn on target selection using the `dma' method */ 443 if (sc->sc_rev != NCR_VARIANT_FAS366) 444 sc->sc_features |= NCR_F_DMASELECT; 445 446 /* Do the common parts of attachment. */ 447 sc->sc_dev = esc->sc_dev; 448 ncr53c9x_attach(sc); 449} 450 451/* 452 * Glue functions. 453 */ 454 455#ifdef ESP_SBUS_DEBUG 456int esp_sbus_debug = 0; 457 458static struct { 459 char *r_name; 460 int r_flag; 461} esp__read_regnames [] = { 462 { "TCL", 0}, /* 0/00 */ 463 { "TCM", 0}, /* 1/04 */ 464 { "FIFO", 0}, /* 2/08 */ 465 { "CMD", 0}, /* 3/0c */ 466 { "STAT", 0}, /* 4/10 */ 467 { "INTR", 0}, /* 5/14 */ 468 { "STEP", 0}, /* 6/18 */ 469 { "FFLAGS", 1}, /* 7/1c */ 470 { "CFG1", 1}, /* 8/20 */ 471 { "STAT2", 0}, /* 9/24 */ 472 { "CFG4", 1}, /* a/28 */ 473 { "CFG2", 1}, /* b/2c */ 474 { "CFG3", 1}, /* c/30 */ 475 { "-none", 1}, /* d/34 */ 476 { "TCH", 1}, /* e/38 */ 477 { "TCX", 1}, /* f/3c */ 478}; 479 480static struct { 481 char *r_name; 482 int r_flag; 483} esp__write_regnames[] = { 484 { "TCL", 1}, /* 0/00 */ 485 { "TCM", 1}, /* 1/04 */ 486 { "FIFO", 0}, /* 2/08 */ 487 { "CMD", 0}, /* 3/0c */ 488 { "SELID", 1}, /* 4/10 */ 489 { "TIMEOUT", 1}, /* 5/14 */ 490 { "SYNCTP", 1}, /* 6/18 */ 491 { "SYNCOFF", 1}, /* 7/1c */ 492 { "CFG1", 1}, /* 8/20 */ 493 { "CCF", 1}, /* 9/24 */ 494 { "TEST", 1}, /* a/28 */ 495 { "CFG2", 1}, /* b/2c */ 496 { "CFG3", 1}, /* c/30 */ 497 { "-none", 1}, /* d/34 */ 498 { "TCH", 1}, /* e/38 */ 499 { "TCX", 1}, /* f/3c */ 500}; 501#endif 502 503u_char 504esp_read_reg(struct ncr53c9x_softc *sc, int reg) 505{ 506 struct esp_softc *esc = (struct esp_softc *)sc; 507 u_char v; 508 509 v = bus_space_read_1(esc->sc_regt, esc->sc_regh, reg * 4); 510#ifdef ESP_SBUS_DEBUG 511 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 512 printf("RD:%x <%s> %x\n", reg * 4, 513 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 514#endif 515 return v; 516} 517 518void 519esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 520{ 521 struct esp_softc *esc = (struct esp_softc *)sc; 522 523#ifdef ESP_SBUS_DEBUG 524 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 525 printf("WR:%x <%s> %x\n", reg * 4, 526 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 527#endif 528 bus_space_write_1(esc->sc_regt, esc->sc_regh, reg * 4, v); 529} 530 531int 532esp_dma_isintr(struct ncr53c9x_softc *sc) 533{ 534 struct esp_softc *esc = (struct esp_softc *)sc; 535 536 return (DMA_ISINTR(esc->sc_dma)); 537} 538 539void 540esp_dma_reset(struct ncr53c9x_softc *sc) 541{ 542 struct esp_softc *esc = (struct esp_softc *)sc; 543 544 DMA_RESET(esc->sc_dma); 545} 546 547int 548esp_dma_intr(struct ncr53c9x_softc *sc) 549{ 550 struct esp_softc *esc = (struct esp_softc *)sc; 551 552 return (DMA_INTR(esc->sc_dma)); 553} 554 555int 556esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 557 int datain, size_t *dmasize) 558{ 559 struct esp_softc *esc = (struct esp_softc *)sc; 560 561 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 562} 563 564void 565esp_dma_go(struct ncr53c9x_softc *sc) 566{ 567 struct esp_softc *esc = (struct esp_softc *)sc; 568 569 DMA_GO(esc->sc_dma); 570} 571 572void 573esp_dma_stop(struct ncr53c9x_softc *sc) 574{ 575 struct esp_softc *esc = (struct esp_softc *)sc; 576 uint32_t csr; 577 578 csr = L64854_GCSR(esc->sc_dma); 579 csr &= ~D_EN_DMA; 580 L64854_SCSR(esc->sc_dma, csr); 581} 582 583int 584esp_dma_isactive(struct ncr53c9x_softc *sc) 585{ 586 struct esp_softc *esc = (struct esp_softc *)sc; 587 588 return (DMA_ISACTIVE(esc->sc_dma)); 589} 590