if_epreg.h revision 8876
1135446Strhodes/* 2218384Sdougb * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3135446Strhodes * 4135446Strhodes * Redistribution and use in source and binary forms, with or without 5193149Sdougb * modification, are permitted provided that the following conditions are 6135446Strhodes * met: 1. Redistributions of source code must retain the above copyright 7135446Strhodes * notice, this list of conditions and the following disclaimer. 2. The name 8135446Strhodes * of the author may not be used to endorse or promote products derived from 9135446Strhodes * this software withough specific prior written permission 10135446Strhodes * 11135446Strhodes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 12135446Strhodes * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13135446Strhodes * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 14135446Strhodes * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15135446Strhodes * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16135446Strhodes * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17135446Strhodes * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18218384Sdougb * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19135446Strhodes * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20135446Strhodes * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21135446Strhodes * 22135446Strhodes * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by: 23193149Sdougb * 24170222Sdougb October 2, 1994 25135446Strhodes 26135446Strhodes Modified by: Andres Vega Garcia 27135446Strhodes 28135446Strhodes INRIA - Sophia Antipolis, France 29135446Strhodes e-mail: avega@sophia.inria.fr 30135446Strhodes finger: avega@pax.inria.fr 31135446Strhodes 32135446Strhodes */ 33135446Strhodes/* 34135446Strhodes * $Id: if_epreg.h,v 1.7 1995/04/10 21:25:06 jkh Exp $ 35135446Strhodes * 36135446Strhodes * Promiscuous mode added and interrupt logic slightly changed 37135446Strhodes * to reduce the number of adapter failures. Transceiver select 38135446Strhodes * logic changed to use value from EEPROM. Autoconfiguration 39135446Strhodes * features added. 40135446Strhodes * Done by: 41135446Strhodes * Serge Babkin 42135446Strhodes * Chelindbank (Chelyabinsk, Russia) 43135446Strhodes * babkin@hq.icb.chel.su 44170222Sdougb */ 45170222Sdougb 46170222Sdougb/* 47170222Sdougb * Ethernet software status per interface. 48170222Sdougb */ 49170222Sdougbstruct ep_softc { 50170222Sdougb struct arpcom arpcom; /* Ethernet common part */ 51170222Sdougb short ep_io_addr; /* i/o bus address */ 52170222Sdougb#define MAX_MBS 8 /* # of mbufs we keep around */ 53170222Sdougb struct mbuf *mb[MAX_MBS]; /* spare mbuf storage. */ 54135446Strhodes int next_mb; /* Which mbuf to use next. */ 55170222Sdougb int last_mb; /* Last mbuf. */ 56135446Strhodes struct mbuf *top, *mcur; 57135446Strhodes short tx_start_thresh; /* Current TX_start_thresh. */ 58135446Strhodes short tx_rate; 59135446Strhodes short tx_counter; 60135446Strhodes short rx_early_thresh; /* Current RX_early_thresh. */ 61135446Strhodes short rx_latency; 62193149Sdougb short rx_avg_pkt; 63135446Strhodes short cur_len; 64135446Strhodes caddr_t bpf; /* BPF "magic cookie" */ 65218384Sdougb u_short ep_connectors; /* Connectors on this card. */ 66218384Sdougb int stat; /* some flags */ 67218384Sdougb#define F_RX_FIRST 0x1 68218384Sdougb#define F_WAIT_TRAIL 0x2 69218384Sdougb#define F_RX_TRAILER 0x4 70218384Sdougb#define F_PROMISC 0x8 71218384Sdougb 72135446Strhodes#define F_ACCESS_32_BITS 0x100 73135446Strhodes 74135446Strhodes#ifdef EP_LOCAL_STATS 75135446Strhodes short tx_underrun; 76170222Sdougb short rx_no_first; 77135446Strhodes short rx_no_mbuf; 78170222Sdougb short rx_bpf_disc; 79170222Sdougb short rx_overrunf; 80170222Sdougb short rx_overrunl; 81170222Sdougb#endif 82170222Sdougb}; 83170222Sdougb 84170222Sdougb/* 85170222Sdougb * Some global constants 86170222Sdougb */ 87218384Sdougb#define ETHER_MIN_LEN 64 88135446Strhodes#define ETHER_MAX_LEN 1518 89135446Strhodes#define ETHER_ADDR_LEN 6 90135446Strhodes 91193149Sdougb#define TX_INIT_RATE 16 92218384Sdougb#define TX_INIT_MAX_RATE 64 93218384Sdougb#define RX_INIT_LATENCY 64 94135446Strhodes#define RX_INIT_EARLY_THRESH 64 95135446Strhodes#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 96135446Strhodes#define MIN_RX_EARLY_THRESHL 4 97135446Strhodes 98135446Strhodes#define EEPROMSIZE 0x40 99135446Strhodes#define MAX_EEPROMBUSY 1000 100135446Strhodes#define EP_LAST_TAG 0xd7 101135446Strhodes#define EP_MAX_BOARDS 16 102135446Strhodes#define EP_ID_PORT 0x100 103135446Strhodes 104135446Strhodes/* 105135446Strhodes * some macros to acces long named fields 106135446Strhodes */ 107135446Strhodes#define IS_BASE (is->id_iobase) 108135446Strhodes#define BASE (sc->ep_io_addr) 109135446Strhodes 110170222Sdougb/* 111135446Strhodes * Commands to read/write EEPROM trough EEPROM command register (Window 0, 112135446Strhodes * Offset 0xa) 113135446Strhodes */ 114135446Strhodes#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 115135446Strhodes#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 116135446Strhodes#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 117135446Strhodes#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 118135446Strhodes 119135446Strhodes#define EEPROM_BUSY (1<<15) 120218384Sdougb#define EEPROM_TST_MODE (1<<14) 121218384Sdougb 122218384Sdougb/* 123135446Strhodes * Some short functions, worth to let them be a macro 124170222Sdougb */ 125170222Sdougb#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 126170222Sdougb#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x)) 127170222Sdougb 128218384Sdougb/************************************************************************** 129170222Sdougb * * 130170222Sdougb * These define the EEPROM data structure. They are used in the probe 131170222Sdougb * function to verify the existance of the adapter after having sent 132170222Sdougb * the ID_Sequence. 133135446Strhodes * 134135446Strhodes * There are others but only the ones we use are defined here. 135170222Sdougb * 136170222Sdougb **************************************************************************/ 137170222Sdougb 138170222Sdougb#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 139135446Strhodes#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 140135446Strhodes#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 141135446Strhodes#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 142135446Strhodes#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 143170222Sdougb#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 144135446Strhodes#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 145135446Strhodes 146135446Strhodes/************************************************************************** 147170222Sdougb * * 148135446Strhodes * These are the registers for the 3Com 3c509 and their bit patterns when * 149135446Strhodes * applicable. They have been taken out the the "EtherLink III Parallel * 150170222Sdougb * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 151135446Strhodes * from 3com. * 152135446Strhodes * * 153135446Strhodes **************************************************************************/ 154135446Strhodes 155170222Sdougb#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a 156135446Strhodes * command reg. */ 157135446Strhodes#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status 158135446Strhodes * reg. */ 159170222Sdougb#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window 160135446Strhodes * reg. */ 161135446Strhodes/* 162170222Sdougb * Window 0 registers. Setup. 163135446Strhodes */ 164135446Strhodes/* Write */ 165135446Strhodes#define EP_W0_EEPROM_DATA 0x0c 166135446Strhodes#define EP_W0_EEPROM_COMMAND 0x0a 167170222Sdougb#define EP_W0_RESOURCE_CFG 0x08 168135446Strhodes#define EP_W0_ADDRESS_CFG 0x06 169135446Strhodes#define EP_W0_CONFIG_CTRL 0x04 170135446Strhodes/* Read */ 171135446Strhodes#define EP_W0_PRODUCT_ID 0x02 172170222Sdougb#define EP_W0_MFG_ID 0x00 173135446Strhodes 174135446Strhodes/* 175135446Strhodes * Window 1 registers. Operating Set. 176135446Strhodes */ 177170222Sdougb/* Write */ 178135446Strhodes#define EP_W1_TX_PIO_WR_2 0x02 179135446Strhodes#define EP_W1_TX_PIO_WR_1 0x00 180135446Strhodes/* Read */ 181170222Sdougb#define EP_W1_FREE_TX 0x0c 182170222Sdougb#define EP_W1_TX_STATUS 0x0b /* byte */ 183170222Sdougb#define EP_W1_TIMER 0x0a /* byte */ 184135446Strhodes#define EP_W1_RX_STATUS 0x08 185135446Strhodes#define EP_W1_RX_PIO_RD_2 0x02 186170222Sdougb#define EP_W1_RX_PIO_RD_1 0x00 187170222Sdougb 188170222Sdougb/* 189170222Sdougb * Window 2 registers. Station Address Setup/Read 190135446Strhodes */ 191135446Strhodes/* Read/Write */ 192135446Strhodes#define EP_W2_ADDR_5 0x05 193135446Strhodes#define EP_W2_ADDR_4 0x04 194135446Strhodes#define EP_W2_ADDR_3 0x03 195135446Strhodes#define EP_W2_ADDR_2 0x02 196170222Sdougb#define EP_W2_ADDR_1 0x01 197135446Strhodes#define EP_W2_ADDR_0 0x00 198135446Strhodes 199135446Strhodes/* 200170222Sdougb * Window 3 registers. FIFO Management. 201170222Sdougb */ 202170222Sdougb/* Read */ 203170222Sdougb#define EP_W3_FREE_TX 0x0c 204170222Sdougb#define EP_W3_FREE_RX 0x0a 205170222Sdougb 206135446Strhodes/* 207135446Strhodes * Window 4 registers. Diagnostics. 208170222Sdougb */ 209170222Sdougb/* Read/Write */ 210170222Sdougb#define EP_W4_MEDIA_TYPE 0x0a 211170222Sdougb#define EP_W4_CTRLR_STATUS 0x08 212170222Sdougb#define EP_W4_NET_DIAG 0x06 213135446Strhodes#define EP_W4_FIFO_DIAG 0x04 214170222Sdougb#define EP_W4_HOST_DIAG 0x02 215135446Strhodes#define EP_W4_TX_DIAG 0x00 216170222Sdougb 217170222Sdougb/* 218135446Strhodes * Window 5 Registers. Results and Internal status. 219135446Strhodes */ 220135446Strhodes/* Read */ 221135446Strhodes#define EP_W5_READ_0_MASK 0x0c 222135446Strhodes#define EP_W5_INTR_MASK 0x0a 223135446Strhodes#define EP_W5_RX_FILTER 0x08 224135446Strhodes#define EP_W5_RX_EARLY_THRESH 0x06 225170222Sdougb#define EP_W5_TX_AVAIL_THRESH 0x02 226135446Strhodes#define EP_W5_TX_START_THRESH 0x00 227135446Strhodes 228135446Strhodes/* 229135446Strhodes * Window 6 registers. Statistics. 230170222Sdougb */ 231170222Sdougb/* Read/Write */ 232170222Sdougb#define TX_TOTAL_OK 0x0c 233170222Sdougb#define RX_TOTAL_OK 0x0a 234170222Sdougb#define TX_DEFERRALS 0x08 235135446Strhodes#define RX_FRAMES_OK 0x07 236135446Strhodes#define TX_FRAMES_OK 0x06 237170222Sdougb#define RX_OVERRUNS 0x05 238170222Sdougb#define TX_COLLISIONS 0x04 239135446Strhodes#define TX_AFTER_1_COLLISION 0x03 240135446Strhodes#define TX_AFTER_X_COLLISIONS 0x02 241135446Strhodes#define TX_NO_SQE 0x01 242135446Strhodes#define TX_CD_LOST 0x00 243135446Strhodes 244170222Sdougb/**************************************** 245135446Strhodes * 246135446Strhodes * Register definitions. 247135446Strhodes * 248170222Sdougb ****************************************/ 249170222Sdougb 250135446Strhodes/* 251135446Strhodes * Command register. All windows. 252170222Sdougb * 253170222Sdougb * 16 bit register. 254135446Strhodes * 15-11: 5-bit code for command to be executed. 255135446Strhodes * 10-0: 11-bit arg if any. For commands with no args; 256135446Strhodes * this can be set to anything. 257135446Strhodes */ 258135446Strhodes#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 259170222Sdougb * after issuing */ 260135446Strhodes#define WINDOW_SELECT (u_short) (0x1<<11) 261135446Strhodes#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 262135446Strhodes * determine whether 263170222Sdougb * this is needed. If 264135446Strhodes * so; wait 800 uSec 265135446Strhodes * before using trans- 266135446Strhodes * ceiver. */ 267135446Strhodes#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 268135446Strhodes * power-up */ 269#define RX_ENABLE (u_short) (0x4<<11) 270#define RX_RESET (u_short) (0x5<<11) 271#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 272#define TX_ENABLE (u_short) (0x9<<11) 273#define TX_DISABLE (u_short) (0xa<<11) 274#define TX_RESET (u_short) (0xb<<11) 275#define REQ_INTR (u_short) (0xc<<11) 276#define SET_INTR_MASK (u_short) (0xe<<11) 277#define SET_RD_0_MASK (u_short) (0xf<<11) 278#define SET_RX_FILTER (u_short) (0x10<<11) 279#define FIL_INDIVIDUAL (u_short) (0x1) 280#define FIL_GROUP (u_short) (0x2) 281#define FIL_BRDCST (u_short) (0x4) 282#define FIL_ALL (u_short) (0x8) 283#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 284#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 285#define SET_TX_START_THRESH (u_short) (0x13<<11) 286#define STATS_ENABLE (u_short) (0x15<<11) 287#define STATS_DISABLE (u_short) (0x16<<11) 288#define STOP_TRANSCEIVER (u_short) (0x17<<11) 289/* 290 * The following C_* acknowledge the various interrupts. Some of them don't 291 * do anything. See the manual. 292 */ 293#define ACK_INTR (u_short) (0x6800) 294#define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 295#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 296#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 297#define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 298#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 299#define C_RX_EARLY (u_short) (ACK_INTR|0x20) 300#define C_INT_RQD (u_short) (ACK_INTR|0x40) 301#define C_UPD_STATS (u_short) (ACK_INTR|0x80) 302#define C_MASK (u_short) 0xFF /* mask of C_* */ 303 304/* 305 * Status register. All windows. 306 * 307 * 15-13: Window number(0-7). 308 * 12: Command_in_progress. 309 * 11: reserved. 310 * 10: reserved. 311 * 9: reserved. 312 * 8: reserved. 313 * 7: Update Statistics. 314 * 6: Interrupt Requested. 315 * 5: RX Early. 316 * 4: RX Complete. 317 * 3: TX Available. 318 * 2: TX Complete. 319 * 1: Adapter Failure. 320 * 0: Interrupt Latch. 321 */ 322#define S_INTR_LATCH (u_short) (0x1) 323#define S_CARD_FAILURE (u_short) (0x2) 324#define S_TX_COMPLETE (u_short) (0x4) 325#define S_TX_AVAIL (u_short) (0x8) 326#define S_RX_COMPLETE (u_short) (0x10) 327#define S_RX_EARLY (u_short) (0x20) 328#define S_INT_RQD (u_short) (0x40) 329#define S_UPD_STATS (u_short) (0x80) 330#define S_MASK (u_short) 0xFF /* mask of S_* */ 331#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ 332 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 333#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 334 335/* Address Config. Register. 336 * Window 0/Port 06 337 */ 338 339#define ACF_CONNECTOR_BITS 14 340#define ACF_CONNECTOR_UTP 0 341#define ACF_CONNECTOR_AUI 1 342#define ACF_CONNECTOR_BNC 3 343 344/* Resource configuration register. 345 * Window 0/Port 08 346 * 347 */ 348 349#define SET_IRQ(i) (((i)<<12) | 0xF00) /* set IRQ i */ 350 351/* 352 * FIFO Registers. 353 * RX Status. Window 1/Port 08 354 * 355 * 15: Incomplete or FIFO empty. 356 * 14: 1: Error in RX Packet 0: Incomplete or no error. 357 * 13-11: Type of error. 358 * 1000 = Overrun. 359 * 1011 = Run Packet Error. 360 * 1100 = Alignment Error. 361 * 1101 = CRC Error. 362 * 1001 = Oversize Packet Error (>1514 bytes) 363 * 0010 = Dribble Bits. 364 * (all other error codes, no errors.) 365 * 366 * 10-0: RX Bytes (0-1514) 367 */ 368#define ERR_RX_INCOMPLETE (u_short) (0x1<<15) 369#define ERR_RX (u_short) (0x1<<14) 370#define ERR_RX_OVERRUN (u_short) (0x8<<11) 371#define ERR_RX_RUN_PKT (u_short) (0xb<<11) 372#define ERR_RX_ALIGN (u_short) (0xc<<11) 373#define ERR_RX_CRC (u_short) (0xd<<11) 374#define ERR_RX_OVERSIZE (u_short) (0x9<<11) 375#define ERR_RX_DRIBBLE (u_short) (0x2<<11) 376 377/* 378 * FIFO Registers. 379 * TX Status. Window 1/Port 0B 380 * 381 * Reports the transmit status of a completed transmission. Writing this 382 * register pops the transmit completion stack. 383 * 384 * Window 1/Port 0x0b. 385 * 386 * 7: Complete 387 * 6: Interrupt on successful transmission requested. 388 * 5: Jabber Error (TP Only, TX Reset required. ) 389 * 4: Underrun (TX Reset required. ) 390 * 3: Maximum Collisions. 391 * 2: TX Status Overflow. 392 * 1-0: Undefined. 393 * 394 */ 395#define TXS_COMPLETE 0x80 396#define TXS_SUCCES_INTR_REQ 0x40 397#define TXS_JABBER 0x20 398#define TXS_UNDERRUN 0x10 399#define TXS_MAX_COLLISION 0x8 400#define TXS_STATUS_OVERFLOW 0x4 401 402/* 403 * Configuration control register. 404 * Window 0/Port 04 405 */ 406/* Read */ 407#define IS_AUI (1<<13) 408#define IS_BNC (1<<12) 409#define IS_UTP (1<<9) 410/* Write */ 411#define ENABLE_DRQ_IRQ 0x0001 412#define W0_P4_CMD_RESET_ADAPTER 0x4 413#define W0_P4_CMD_ENABLE_ADAPTER 0x1 414/* 415 * Media type and status. 416 * Window 4/Port 0A 417 */ 418#define ENABLE_UTP 0xc0 419#define DISABLE_UTP 0x0 420 421/* 422 * Misc defines for various things. 423 */ 424#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ 425#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ 426#define PROD_ID 0x9150 427 428#define AUI 0x1 429#define BNC 0x2 430#define UTP 0x4 431 432#define ETHER_ADDR_LEN 6 433#define ETHER_MAX 1536 434#define RX_BYTES_MASK (u_short) (0x07ff) 435 436 /* EISA support */ 437#define EP_EISA_START 0x1000 438#define EP_EISA_W0 0x0c80 439