if_epreg.h revision 51673
1963Sats/* 24435Sgibbs * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 38876Srgrimes * 4963Sats * Redistribution and use in source and binary forms, with or without 54435Sgibbs * modification, are permitted provided that the following conditions are 64435Sgibbs * met: 1. Redistributions of source code must retain the above copyright 74435Sgibbs * notice, this list of conditions and the following disclaimer. 2. The name 84435Sgibbs * of the author may not be used to endorse or promote products derived from 913765Smpp * this software without specific prior written permission 108876Srgrimes * 114435Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 124435Sgibbs * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 134435Sgibbs * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 144435Sgibbs * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 154435Sgibbs * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 164435Sgibbs * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 174435Sgibbs * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 184435Sgibbs * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 194435Sgibbs * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 204435Sgibbs * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 218876Srgrimes * 2250477Speter * $FreeBSD: head/sys/dev/ep/if_epreg.h 51673 1999-09-26 06:42:36Z mdodd $ 237510Sjkh */ 244435Sgibbs 254435Sgibbs/* 2651673Smdodd * DELAY_MULTIPLE: How much to boost "base" delays, except 2751673Smdodd * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this. 2816374Snate */ 2951673Smdodd#define DELAY_MULTIPLE 10 3051673Smdodd#define BIT_DELAY_MULTIPLE 10 3116374Snate 3216374Snate/* 334435Sgibbs * Some global constants 344435Sgibbs */ 354435Sgibbs#define TX_INIT_RATE 16 364435Sgibbs#define TX_INIT_MAX_RATE 64 374435Sgibbs#define RX_INIT_LATENCY 64 3830398Sitojun#define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */ 3930398Sitojun#define RX_NEXT_EARLY_THRESH 500 404435Sgibbs 414435Sgibbs#define EEPROMSIZE 0x40 424435Sgibbs#define MAX_EEPROMBUSY 1000 434435Sgibbs#define EP_LAST_TAG 0xd7 444435Sgibbs#define EP_MAX_BOARDS 16 4530760Sjoerg/* 4630760Sjoerg * This `ID' port is a mere hack. There's currently no chance to register 4730760Sjoerg * it with config's idea of the ports that are in use. 4830760Sjoerg * 4935256Sdes * "After the automatic configuration is completed, the IDS is in its initial 5030760Sjoerg * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where 5130760Sjoerg * 'x' is any hex digit. If a zero is written to any one of these ports, then 5230760Sjoerg * that address is remembered and becomes the ID port. A second zero written 5330760Sjoerg * to that port resets the ID sequence to its initial state. The IDS watches 5430760Sjoerg * for the ID sequence to be written to the ID port." 5530760Sjoerg * 5630760Sjoerg * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray 5730760Sjoerg * ports. 5830760Sjoerg */ 5930760Sjoerg#define EP_ID_PORT 0x110 6014259Sgibbs#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */ 614435Sgibbs 624435Sgibbs/* 634435Sgibbs * some macros to acces long named fields 644435Sgibbs */ 654435Sgibbs#define IS_BASE (is->id_iobase) 664435Sgibbs#define BASE (sc->ep_io_addr) 674435Sgibbs 684435Sgibbs/* 694435Sgibbs * Commands to read/write EEPROM trough EEPROM command register (Window 0, 704435Sgibbs * Offset 0xa) 714435Sgibbs */ 724435Sgibbs#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 734435Sgibbs#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 744435Sgibbs#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 754435Sgibbs#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 764435Sgibbs 774435Sgibbs#define EEPROM_BUSY (1<<15) 784435Sgibbs#define EEPROM_TST_MODE (1<<14) 794435Sgibbs 804435Sgibbs/* 814435Sgibbs * Some short functions, worth to let them be a macro 824435Sgibbs */ 834435Sgibbs#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 844435Sgibbs#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x)) 854435Sgibbs 86963Sats/************************************************************************** 874435Sgibbs * * 88963Sats * These define the EEPROM data structure. They are used in the probe 8913765Smpp * function to verify the existence of the adapter after having sent 90963Sats * the ID_Sequence. 91963Sats * 92963Sats * There are others but only the ones we use are defined here. 93963Sats * 94963Sats **************************************************************************/ 95963Sats 96963Sats#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 97963Sats#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 98963Sats#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 99963Sats#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 100963Sats#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 101963Sats#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 1024435Sgibbs#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 103963Sats 104963Sats/************************************************************************** 105963Sats * * 106963Sats * These are the registers for the 3Com 3c509 and their bit patterns when * 107963Sats * applicable. They have been taken out the the "EtherLink III Parallel * 108963Sats * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 109963Sats * from 3com. * 110963Sats * * 111963Sats **************************************************************************/ 112963Sats 1134435Sgibbs#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a 1144435Sgibbs * command reg. */ 1154435Sgibbs#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status 1164435Sgibbs * reg. */ 1174435Sgibbs#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window 1184435Sgibbs * reg. */ 119963Sats/* 120963Sats * Window 0 registers. Setup. 121963Sats */ 1224435Sgibbs/* Write */ 123963Sats#define EP_W0_EEPROM_DATA 0x0c 124963Sats#define EP_W0_EEPROM_COMMAND 0x0a 125963Sats#define EP_W0_RESOURCE_CFG 0x08 126963Sats#define EP_W0_ADDRESS_CFG 0x06 127963Sats#define EP_W0_CONFIG_CTRL 0x04 1284435Sgibbs/* Read */ 129963Sats#define EP_W0_PRODUCT_ID 0x02 130963Sats#define EP_W0_MFG_ID 0x00 131963Sats 132963Sats/* 133963Sats * Window 1 registers. Operating Set. 134963Sats */ 1354435Sgibbs/* Write */ 136963Sats#define EP_W1_TX_PIO_WR_2 0x02 137963Sats#define EP_W1_TX_PIO_WR_1 0x00 1384435Sgibbs/* Read */ 139963Sats#define EP_W1_FREE_TX 0x0c 1404435Sgibbs#define EP_W1_TX_STATUS 0x0b /* byte */ 1414435Sgibbs#define EP_W1_TIMER 0x0a /* byte */ 142963Sats#define EP_W1_RX_STATUS 0x08 143963Sats#define EP_W1_RX_PIO_RD_2 0x02 144963Sats#define EP_W1_RX_PIO_RD_1 0x00 145963Sats 146963Sats/* 147963Sats * Window 2 registers. Station Address Setup/Read 148963Sats */ 1494435Sgibbs/* Read/Write */ 150963Sats#define EP_W2_ADDR_5 0x05 151963Sats#define EP_W2_ADDR_4 0x04 152963Sats#define EP_W2_ADDR_3 0x03 153963Sats#define EP_W2_ADDR_2 0x02 154963Sats#define EP_W2_ADDR_1 0x01 155963Sats#define EP_W2_ADDR_0 0x00 156963Sats 1574435Sgibbs/* 158963Sats * Window 3 registers. FIFO Management. 159963Sats */ 1604435Sgibbs/* Read */ 161963Sats#define EP_W3_FREE_TX 0x0c 162963Sats#define EP_W3_FREE_RX 0x0a 16349070Shosokawa#define EP_W3_OPTIONS 0x08 164963Sats 165963Sats/* 166963Sats * Window 4 registers. Diagnostics. 167963Sats */ 1684435Sgibbs/* Read/Write */ 169963Sats#define EP_W4_MEDIA_TYPE 0x0a 170963Sats#define EP_W4_CTRLR_STATUS 0x08 171963Sats#define EP_W4_NET_DIAG 0x06 172963Sats#define EP_W4_FIFO_DIAG 0x04 173963Sats#define EP_W4_HOST_DIAG 0x02 174963Sats#define EP_W4_TX_DIAG 0x00 175963Sats 176963Sats/* 177963Sats * Window 5 Registers. Results and Internal status. 178963Sats */ 1794435Sgibbs/* Read */ 180963Sats#define EP_W5_READ_0_MASK 0x0c 181963Sats#define EP_W5_INTR_MASK 0x0a 182963Sats#define EP_W5_RX_FILTER 0x08 183963Sats#define EP_W5_RX_EARLY_THRESH 0x06 184963Sats#define EP_W5_TX_AVAIL_THRESH 0x02 185963Sats#define EP_W5_TX_START_THRESH 0x00 186963Sats 187963Sats/* 188963Sats * Window 6 registers. Statistics. 189963Sats */ 1904435Sgibbs/* Read/Write */ 191963Sats#define TX_TOTAL_OK 0x0c 192963Sats#define RX_TOTAL_OK 0x0a 193963Sats#define TX_DEFERRALS 0x08 194963Sats#define RX_FRAMES_OK 0x07 195963Sats#define TX_FRAMES_OK 0x06 196963Sats#define RX_OVERRUNS 0x05 197963Sats#define TX_COLLISIONS 0x04 198963Sats#define TX_AFTER_1_COLLISION 0x03 199963Sats#define TX_AFTER_X_COLLISIONS 0x02 200963Sats#define TX_NO_SQE 0x01 201963Sats#define TX_CD_LOST 0x00 202963Sats 203963Sats/**************************************** 204963Sats * 205963Sats * Register definitions. 206963Sats * 207963Sats ****************************************/ 208963Sats 209963Sats/* 210963Sats * Command register. All windows. 211963Sats * 212963Sats * 16 bit register. 213963Sats * 15-11: 5-bit code for command to be executed. 214963Sats * 10-0: 11-bit arg if any. For commands with no args; 215963Sats * this can be set to anything. 216963Sats */ 2174435Sgibbs#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 2184435Sgibbs * after issuing */ 219963Sats#define WINDOW_SELECT (u_short) (0x1<<11) 2204435Sgibbs#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 2214435Sgibbs * determine whether 2224435Sgibbs * this is needed. If 2234435Sgibbs * so; wait 800 uSec 2244435Sgibbs * before using trans- 2254435Sgibbs * ceiver. */ 2264435Sgibbs#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 2274435Sgibbs * power-up */ 228963Sats#define RX_ENABLE (u_short) (0x4<<11) 229963Sats#define RX_RESET (u_short) (0x5<<11) 230963Sats#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 231963Sats#define TX_ENABLE (u_short) (0x9<<11) 232963Sats#define TX_DISABLE (u_short) (0xa<<11) 233963Sats#define TX_RESET (u_short) (0xb<<11) 234963Sats#define REQ_INTR (u_short) (0xc<<11) 235963Sats#define SET_INTR_MASK (u_short) (0xe<<11) 236963Sats#define SET_RD_0_MASK (u_short) (0xf<<11) 237963Sats#define SET_RX_FILTER (u_short) (0x10<<11) 2384435Sgibbs#define FIL_INDIVIDUAL (u_short) (0x1) 2394435Sgibbs#define FIL_GROUP (u_short) (0x2) 2404435Sgibbs#define FIL_BRDCST (u_short) (0x4) 2414435Sgibbs#define FIL_ALL (u_short) (0x8) 242963Sats#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 243963Sats#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 244963Sats#define SET_TX_START_THRESH (u_short) (0x13<<11) 245963Sats#define STATS_ENABLE (u_short) (0x15<<11) 246963Sats#define STATS_DISABLE (u_short) (0x16<<11) 247963Sats#define STOP_TRANSCEIVER (u_short) (0x17<<11) 2484435Sgibbs/* 2494435Sgibbs * The following C_* acknowledge the various interrupts. Some of them don't 2504435Sgibbs * do anything. See the manual. 2514435Sgibbs */ 2524435Sgibbs#define ACK_INTR (u_short) (0x6800) 2534435Sgibbs#define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 2544435Sgibbs#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 2554435Sgibbs#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 2564435Sgibbs#define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 2574435Sgibbs#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 2584435Sgibbs#define C_RX_EARLY (u_short) (ACK_INTR|0x20) 2594435Sgibbs#define C_INT_RQD (u_short) (ACK_INTR|0x40) 2604435Sgibbs#define C_UPD_STATS (u_short) (ACK_INTR|0x80) 2617510Sjkh#define C_MASK (u_short) 0xFF /* mask of C_* */ 262963Sats 263963Sats/* 264963Sats * Status register. All windows. 265963Sats * 266963Sats * 15-13: Window number(0-7). 267963Sats * 12: Command_in_progress. 268963Sats * 11: reserved. 269963Sats * 10: reserved. 270963Sats * 9: reserved. 271963Sats * 8: reserved. 272963Sats * 7: Update Statistics. 273963Sats * 6: Interrupt Requested. 274963Sats * 5: RX Early. 275963Sats * 4: RX Complete. 276963Sats * 3: TX Available. 277963Sats * 2: TX Complete. 278963Sats * 1: Adapter Failure. 279963Sats * 0: Interrupt Latch. 280963Sats */ 281963Sats#define S_INTR_LATCH (u_short) (0x1) 282963Sats#define S_CARD_FAILURE (u_short) (0x2) 283963Sats#define S_TX_COMPLETE (u_short) (0x4) 284963Sats#define S_TX_AVAIL (u_short) (0x8) 285963Sats#define S_RX_COMPLETE (u_short) (0x10) 286963Sats#define S_RX_EARLY (u_short) (0x20) 287963Sats#define S_INT_RQD (u_short) (0x40) 288963Sats#define S_UPD_STATS (u_short) (0x80) 2897510Sjkh#define S_MASK (u_short) 0xFF /* mask of S_* */ 2904435Sgibbs#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ 2914435Sgibbs S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 292963Sats#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 293963Sats 2947510Sjkh/* Address Config. Register. 2957510Sjkh * Window 0/Port 06 2967510Sjkh */ 2977510Sjkh 2987510Sjkh#define ACF_CONNECTOR_BITS 14 2997510Sjkh#define ACF_CONNECTOR_UTP 0 3007510Sjkh#define ACF_CONNECTOR_AUI 1 3017510Sjkh#define ACF_CONNECTOR_BNC 3 3027510Sjkh 3037510Sjkh/* Resource configuration register. 3047510Sjkh * Window 0/Port 08 3057510Sjkh * 3067510Sjkh */ 3077510Sjkh 30817223Samurai#define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \ 30917223Samurai ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \ 31017223Samurai ((u_short)(irq)<<12)) ) /* set IRQ i */ 3117510Sjkh 312963Sats/* 3138876Srgrimes * FIFO Registers. 3144435Sgibbs * RX Status. Window 1/Port 08 315963Sats * 316963Sats * 15: Incomplete or FIFO empty. 317963Sats * 14: 1: Error in RX Packet 0: Incomplete or no error. 318963Sats * 13-11: Type of error. 319963Sats * 1000 = Overrun. 320963Sats * 1011 = Run Packet Error. 321963Sats * 1100 = Alignment Error. 322963Sats * 1101 = CRC Error. 323963Sats * 1001 = Oversize Packet Error (>1514 bytes) 324963Sats * 0010 = Dribble Bits. 325963Sats * (all other error codes, no errors.) 326963Sats * 327963Sats * 10-0: RX Bytes (0-1514) 328963Sats */ 3294435Sgibbs#define ERR_RX_INCOMPLETE (u_short) (0x1<<15) 3304435Sgibbs#define ERR_RX (u_short) (0x1<<14) 3314435Sgibbs#define ERR_RX_OVERRUN (u_short) (0x8<<11) 3324435Sgibbs#define ERR_RX_RUN_PKT (u_short) (0xb<<11) 3334435Sgibbs#define ERR_RX_ALIGN (u_short) (0xc<<11) 3344435Sgibbs#define ERR_RX_CRC (u_short) (0xd<<11) 3354435Sgibbs#define ERR_RX_OVERSIZE (u_short) (0x9<<11) 3364435Sgibbs#define ERR_RX_DRIBBLE (u_short) (0x2<<11) 337963Sats 338963Sats/* 3398876Srgrimes * FIFO Registers. 3404435Sgibbs * TX Status. Window 1/Port 0B 341963Sats * 342963Sats * Reports the transmit status of a completed transmission. Writing this 343963Sats * register pops the transmit completion stack. 344963Sats * 345963Sats * Window 1/Port 0x0b. 346963Sats * 347963Sats * 7: Complete 348963Sats * 6: Interrupt on successful transmission requested. 349963Sats * 5: Jabber Error (TP Only, TX Reset required. ) 350963Sats * 4: Underrun (TX Reset required. ) 351963Sats * 3: Maximum Collisions. 352963Sats * 2: TX Status Overflow. 353963Sats * 1-0: Undefined. 354963Sats * 355963Sats */ 356963Sats#define TXS_COMPLETE 0x80 3574435Sgibbs#define TXS_SUCCES_INTR_REQ 0x40 358963Sats#define TXS_JABBER 0x20 359963Sats#define TXS_UNDERRUN 0x10 360963Sats#define TXS_MAX_COLLISION 0x8 361963Sats#define TXS_STATUS_OVERFLOW 0x4 362963Sats 363963Sats/* 3648876Srgrimes * Configuration control register. 3654435Sgibbs * Window 0/Port 04 3664435Sgibbs */ 3674435Sgibbs/* Read */ 3684435Sgibbs#define IS_AUI (1<<13) 3694435Sgibbs#define IS_BNC (1<<12) 3704435Sgibbs#define IS_UTP (1<<9) 3714435Sgibbs/* Write */ 3724435Sgibbs#define ENABLE_DRQ_IRQ 0x0001 3734435Sgibbs#define W0_P4_CMD_RESET_ADAPTER 0x4 3744435Sgibbs#define W0_P4_CMD_ENABLE_ADAPTER 0x1 3758876Srgrimes/* 3764435Sgibbs * Media type and status. 3774435Sgibbs * Window 4/Port 0A 3784435Sgibbs */ 3794435Sgibbs#define ENABLE_UTP 0xc0 3804435Sgibbs#define DISABLE_UTP 0x0 3814435Sgibbs 3824435Sgibbs/* 383963Sats * Misc defines for various things. 384963Sats */ 3854435Sgibbs#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ 3864435Sgibbs#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ 3874435Sgibbs#define PROD_ID 0x9150 3884435Sgibbs 389963Sats#define AUI 0x1 390963Sats#define BNC 0x2 391963Sats#define UTP 0x4 3924435Sgibbs 393963Sats#define RX_BYTES_MASK (u_short) (0x07ff) 3942478Sats 39549070Shosokawa/* 39649070Shosokawa * Config flags 39749070Shosokawa */ 39849070Shosokawa#define EP_FLAGS_100TX 0x1 399