if_epreg.h revision 50477 
1/*
2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: 1. Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer. 2. The name
8 * of the author may not be used to endorse or promote products derived from
9 * this software without specific prior written permission
10 *
11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
23 *
24 October 2, 1994
25
26 Modified by: Andres Vega Garcia
27
28 INRIA - Sophia Antipolis, France
29 e-mail: avega@sophia.inria.fr
30 finger: avega@pax.inria.fr
31
32 */
33/*
34 * $FreeBSD: head/sys/dev/ep/if_epreg.h 50477 1999-08-28 01:08:13Z peter $
35 *
36 *  Promiscuous mode added and interrupt logic slightly changed
37 *  to reduce the number of adapter failures. Transceiver select
38 *  logic changed to use value from EEPROM. Autoconfiguration
39 *  features added.
40 *  Done by:
41 *          Serge Babkin
42 *          Chelindbank (Chelyabinsk, Russia)
43 *          babkin@hq.icb.chel.su
44 */
45
46/*
47 * Pccard support for 3C589 by:
48 *		HAMADA Naoki
49 *		nao@tom-yam.or.jp
50 */
51
52/*
53 * Ethernet software status per interface.
54 */
55struct ep_softc {
56    struct arpcom arpcom;	/* Ethernet common part		 */
57    int ep_io_addr;		/* i/o bus address		 */
58    struct mbuf *top, *mcur;
59    short cur_len;
60    u_short ep_connectors;	/* Connectors on this card.	 */
61    u_char ep_connector;	/* Configured connector.	 */
62    int stat;			/* some flags */
63    int gone;			/* adapter is not present (for PCCARD) */
64#define         F_RX_FIRST   0x1
65#define		F_PROMISC    0x8
66
67#define         F_ACCESS_32_BITS 0x100
68
69    struct ep_board *epb;
70
71    int unit;
72
73#ifdef  EP_LOCAL_STATS
74    short tx_underrun;
75    short rx_no_first;
76    short rx_no_mbuf;
77    short rx_bpf_disc;
78    short rx_overrunf;
79    short rx_overrunl;
80#endif
81};
82
83struct ep_board {
84	int epb_addr;	/* address of this board */
85	char epb_used;	/* was this entry already used for configuring ? */
86				/* data from EEPROM for later use */
87	u_short eth_addr[3];	/* Ethernet address */
88	u_short prod_id;	/* product ID */
89	int	cmd_off;	/* command offset (bit shift) */
90	int	mii_trans;	/* activate MII transiever */
91	u_short res_cfg;	/* resource configuration */
92};
93
94
95/*
96 * Some global constants
97 */
98#define TX_INIT_RATE         16
99#define TX_INIT_MAX_RATE     64
100#define RX_INIT_LATENCY      64
101#define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */
102#define RX_NEXT_EARLY_THRESH 500
103
104#define EEPROMSIZE      0x40
105#define MAX_EEPROMBUSY  1000
106#define EP_LAST_TAG     0xd7
107#define EP_MAX_BOARDS   16
108/*
109 * This `ID' port is a mere hack.  There's currently no chance to register
110 * it with config's idea of the ports that are in use.
111 *
112 * "After the automatic configuration is completed, the IDS is in its initial
113 * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where
114 * 'x' is any hex digit.  If a zero is written to any one of these ports, then
115 * that address is remembered and becomes the ID port.  A second zero written
116 * to that port resets the ID sequence to its initial state.  The IDS watches
117 * for the ID sequence to be written to the ID port."
118 *
119 * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray
120 * ports.
121 */
122#define EP_ID_PORT      0x110
123#define EP_IOSIZE	16	/* 16 bytes of I/O space used. */
124
125/*
126 * some macros to acces long named fields
127 */
128#define IS_BASE (is->id_iobase)
129#define BASE 	(sc->ep_io_addr)
130
131/*
132 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
133 * Offset 0xa)
134 */
135#define EEPROM_CMD_RD    0x0080	/* Read:  Address required (5 bits) */
136#define EEPROM_CMD_WR    0x0040	/* Write: Address required (5 bits) */
137#define EEPROM_CMD_ERASE 0x00c0	/* Erase: Address required (5 bits) */
138#define EEPROM_CMD_EWEN  0x0030	/* Erase/Write Enable: No data required */
139
140#define EEPROM_BUSY		(1<<15)
141#define EEPROM_TST_MODE		(1<<14)
142
143/*
144 * Some short functions, worth to let them be a macro
145 */
146#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
147#define GO_WINDOW(x)      outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
148
149/**************************************************************************
150 *									  *
151 * These define the EEPROM data structure.  They are used in the probe
152 * function to verify the existence of the adapter after having sent
153 * the ID_Sequence.
154 *
155 * There are others but only the ones we use are defined here.
156 *
157 **************************************************************************/
158
159#define EEPROM_NODE_ADDR_0	0x0	/* Word */
160#define EEPROM_NODE_ADDR_1	0x1	/* Word */
161#define EEPROM_NODE_ADDR_2	0x2	/* Word */
162#define EEPROM_PROD_ID		0x3	/* 0x9[0-f]50 */
163#define EEPROM_MFG_ID		0x7	/* 0x6d50 */
164#define EEPROM_ADDR_CFG		0x8	/* Base addr */
165#define EEPROM_RESOURCE_CFG	0x9	/* IRQ. Bits 12-15 */
166
167/**************************************************************************
168 *										  *
169 * These are the registers for the 3Com 3c509 and their bit patterns when *
170 * applicable.  They have been taken out the the "EtherLink III Parallel  *
171 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
172 * from 3com.								  *
173 *										  *
174 **************************************************************************/
175
176#define EP_COMMAND		0x0e	/* Write. BASE+0x0e is always a
177					 * command reg. */
178#define EP_STATUS		0x0e	/* Read. BASE+0x0e is always status
179					 * reg. */
180#define EP_WINDOW		0x0f	/* Read. BASE+0x0f is always window
181					 * reg. */
182/*
183 * Window 0 registers. Setup.
184 */
185/* Write */
186#define EP_W0_EEPROM_DATA	0x0c
187#define EP_W0_EEPROM_COMMAND	0x0a
188#define EP_W0_RESOURCE_CFG	0x08
189#define EP_W0_ADDRESS_CFG	0x06
190#define EP_W0_CONFIG_CTRL	0x04
191/* Read */
192#define EP_W0_PRODUCT_ID	0x02
193#define EP_W0_MFG_ID		0x00
194
195/*
196 * Window 1 registers. Operating Set.
197 */
198/* Write */
199#define EP_W1_TX_PIO_WR_2	0x02
200#define EP_W1_TX_PIO_WR_1	0x00
201/* Read */
202#define EP_W1_FREE_TX		0x0c
203#define EP_W1_TX_STATUS		0x0b	/* byte */
204#define EP_W1_TIMER		0x0a	/* byte */
205#define EP_W1_RX_STATUS		0x08
206#define EP_W1_RX_PIO_RD_2	0x02
207#define EP_W1_RX_PIO_RD_1	0x00
208
209/*
210 * Window 2 registers. Station Address Setup/Read
211 */
212/* Read/Write */
213#define EP_W2_ADDR_5		0x05
214#define EP_W2_ADDR_4		0x04
215#define EP_W2_ADDR_3		0x03
216#define EP_W2_ADDR_2		0x02
217#define EP_W2_ADDR_1		0x01
218#define EP_W2_ADDR_0		0x00
219
220/*
221 * Window 3 registers.  FIFO Management.
222 */
223/* Read */
224#define EP_W3_FREE_TX		0x0c
225#define EP_W3_FREE_RX		0x0a
226#define EP_W3_OPTIONS		0x08
227
228/*
229 * Window 4 registers. Diagnostics.
230 */
231/* Read/Write */
232#define EP_W4_MEDIA_TYPE	0x0a
233#define EP_W4_CTRLR_STATUS	0x08
234#define EP_W4_NET_DIAG		0x06
235#define EP_W4_FIFO_DIAG		0x04
236#define EP_W4_HOST_DIAG		0x02
237#define EP_W4_TX_DIAG		0x00
238
239/*
240 * Window 5 Registers.  Results and Internal status.
241 */
242/* Read */
243#define EP_W5_READ_0_MASK	0x0c
244#define EP_W5_INTR_MASK		0x0a
245#define EP_W5_RX_FILTER		0x08
246#define EP_W5_RX_EARLY_THRESH	0x06
247#define EP_W5_TX_AVAIL_THRESH	0x02
248#define EP_W5_TX_START_THRESH	0x00
249
250/*
251 * Window 6 registers. Statistics.
252 */
253/* Read/Write */
254#define TX_TOTAL_OK		0x0c
255#define RX_TOTAL_OK		0x0a
256#define TX_DEFERRALS		0x08
257#define RX_FRAMES_OK		0x07
258#define TX_FRAMES_OK		0x06
259#define RX_OVERRUNS		0x05
260#define TX_COLLISIONS		0x04
261#define TX_AFTER_1_COLLISION	0x03
262#define TX_AFTER_X_COLLISIONS	0x02
263#define TX_NO_SQE		0x01
264#define TX_CD_LOST		0x00
265
266/****************************************
267 *
268 * Register definitions.
269 *
270 ****************************************/
271
272/*
273 * Command register. All windows.
274 *
275 * 16 bit register.
276 *     15-11:  5-bit code for command to be executed.
277 *     10-0:   11-bit arg if any. For commands with no args;
278 *	      this can be set to anything.
279 */
280#define GLOBAL_RESET		(u_short) 0x0000	/* Wait at least 1ms
281							 * after issuing */
282#define WINDOW_SELECT		(u_short) (0x1<<11)
283#define START_TRANSCEIVER	(u_short) (0x2<<11)	/* Read ADDR_CFG reg to
284							 * determine whether
285							 * this is needed. If
286							 * so; wait 800 uSec
287							 * before using trans-
288							 * ceiver. */
289#define RX_DISABLE		(u_short) (0x3<<11)	/* state disabled on
290							 * power-up */
291#define RX_ENABLE		(u_short) (0x4<<11)
292#define RX_RESET		(u_short) (0x5<<11)
293#define RX_DISCARD_TOP_PACK	(u_short) (0x8<<11)
294#define TX_ENABLE		(u_short) (0x9<<11)
295#define TX_DISABLE		(u_short) (0xa<<11)
296#define TX_RESET		(u_short) (0xb<<11)
297#define REQ_INTR		(u_short) (0xc<<11)
298#define SET_INTR_MASK		(u_short) (0xe<<11)
299#define SET_RD_0_MASK		(u_short) (0xf<<11)
300#define SET_RX_FILTER		(u_short) (0x10<<11)
301#define FIL_INDIVIDUAL	(u_short) (0x1)
302#define FIL_GROUP		(u_short) (0x2)
303#define FIL_BRDCST	(u_short) (0x4)
304#define FIL_ALL		(u_short) (0x8)
305#define SET_RX_EARLY_THRESH	(u_short) (0x11<<11)
306#define SET_TX_AVAIL_THRESH	(u_short) (0x12<<11)
307#define SET_TX_START_THRESH	(u_short) (0x13<<11)
308#define STATS_ENABLE		(u_short) (0x15<<11)
309#define STATS_DISABLE		(u_short) (0x16<<11)
310#define STOP_TRANSCEIVER	(u_short) (0x17<<11)
311/*
312 * The following C_* acknowledge the various interrupts. Some of them don't
313 * do anything.  See the manual.
314 */
315#define ACK_INTR		(u_short) (0x6800)
316#define C_INTR_LATCH	(u_short) (ACK_INTR|0x1)
317#define C_CARD_FAILURE	(u_short) (ACK_INTR|0x2)
318#define C_TX_COMPLETE	(u_short) (ACK_INTR|0x4)
319#define C_TX_AVAIL	(u_short) (ACK_INTR|0x8)
320#define C_RX_COMPLETE	(u_short) (ACK_INTR|0x10)
321#define C_RX_EARLY	(u_short) (ACK_INTR|0x20)
322#define C_INT_RQD		(u_short) (ACK_INTR|0x40)
323#define C_UPD_STATS	(u_short) (ACK_INTR|0x80)
324#define C_MASK	(u_short) 0xFF /* mask of C_* */
325
326/*
327 * Status register. All windows.
328 *
329 *     15-13:  Window number(0-7).
330 *     12:     Command_in_progress.
331 *     11:     reserved.
332 *     10:     reserved.
333 *     9:      reserved.
334 *     8:      reserved.
335 *     7:      Update Statistics.
336 *     6:      Interrupt Requested.
337 *     5:      RX Early.
338 *     4:      RX Complete.
339 *     3:      TX Available.
340 *     2:      TX Complete.
341 *     1:      Adapter Failure.
342 *     0:      Interrupt Latch.
343 */
344#define S_INTR_LATCH		(u_short) (0x1)
345#define S_CARD_FAILURE		(u_short) (0x2)
346#define S_TX_COMPLETE		(u_short) (0x4)
347#define S_TX_AVAIL		(u_short) (0x8)
348#define S_RX_COMPLETE		(u_short) (0x10)
349#define S_RX_EARLY		(u_short) (0x20)
350#define S_INT_RQD		(u_short) (0x40)
351#define S_UPD_STATS		(u_short) (0x80)
352#define S_MASK	(u_short) 0xFF /* mask of S_* */
353#define S_5_INTS                (S_CARD_FAILURE|S_TX_COMPLETE|\
354				 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
355#define S_COMMAND_IN_PROGRESS	(u_short) (0x1000)
356
357/* Address Config. Register.
358 * Window 0/Port 06
359 */
360
361#define ACF_CONNECTOR_BITS	14
362#define ACF_CONNECTOR_UTP	0
363#define ACF_CONNECTOR_AUI	1
364#define ACF_CONNECTOR_BNC	3
365
366/* Resource configuration register.
367 * Window 0/Port 08
368 *
369 */
370
371#define SET_IRQ(base,irq)     outw((base) + EP_W0_RESOURCE_CFG, \
372                              ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
373                              ((u_short)(irq)<<12))  ) /* set IRQ i */
374
375/*
376 * FIFO Registers.
377 * RX Status. Window 1/Port 08
378 *
379 *     15:     Incomplete or FIFO empty.
380 *     14:     1: Error in RX Packet   0: Incomplete or no error.
381 *     13-11:  Type of error.
382 *	      1000 = Overrun.
383 *	      1011 = Run Packet Error.
384 *	      1100 = Alignment Error.
385 *	      1101 = CRC Error.
386 *	      1001 = Oversize Packet Error (>1514 bytes)
387 *	      0010 = Dribble Bits.
388 *	      (all other error codes, no errors.)
389 *
390 *     10-0:   RX Bytes (0-1514)
391 */
392#define ERR_RX_INCOMPLETE  (u_short) (0x1<<15)
393#define ERR_RX		   (u_short) (0x1<<14)
394#define ERR_RX_OVERRUN 	   (u_short) (0x8<<11)
395#define ERR_RX_RUN_PKT	   (u_short) (0xb<<11)
396#define ERR_RX_ALIGN	   (u_short) (0xc<<11)
397#define ERR_RX_CRC	   (u_short) (0xd<<11)
398#define ERR_RX_OVERSIZE	   (u_short) (0x9<<11)
399#define ERR_RX_DRIBBLE	   (u_short) (0x2<<11)
400
401/*
402 * FIFO Registers.
403 * TX Status. Window 1/Port 0B
404 *
405 *   Reports the transmit status of a completed transmission. Writing this
406 *   register pops the transmit completion stack.
407 *
408 *   Window 1/Port 0x0b.
409 *
410 *     7:      Complete
411 *     6:      Interrupt on successful transmission requested.
412 *     5:      Jabber Error (TP Only, TX Reset required. )
413 *     4:      Underrun (TX Reset required. )
414 *     3:      Maximum Collisions.
415 *     2:      TX Status Overflow.
416 *     1-0:    Undefined.
417 *
418 */
419#define TXS_COMPLETE		0x80
420#define TXS_SUCCES_INTR_REQ		0x40
421#define TXS_JABBER		0x20
422#define TXS_UNDERRUN		0x10
423#define TXS_MAX_COLLISION	0x8
424#define TXS_STATUS_OVERFLOW	0x4
425
426/*
427 * Configuration control register.
428 * Window 0/Port 04
429 */
430/* Read */
431#define IS_AUI 				(1<<13)
432#define IS_BNC 				(1<<12)
433#define IS_UTP 				(1<<9)
434/* Write */
435#define ENABLE_DRQ_IRQ			0x0001
436#define W0_P4_CMD_RESET_ADAPTER       0x4
437#define W0_P4_CMD_ENABLE_ADAPTER      0x1
438/*
439 * Media type and status.
440 * Window 4/Port 0A
441 */
442#define ENABLE_UTP			0xc0
443#define DISABLE_UTP			0x0
444
445/*
446 * Misc defines for various things.
447 */
448#define ACTIVATE_ADAPTER_TO_CONFIG 	0xff /* to the id_port */
449#define MFG_ID 				0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
450#define PROD_ID 			0x9150
451
452#define AUI 				0x1
453#define BNC 				0x2
454#define UTP 				0x4
455
456#define RX_BYTES_MASK			(u_short) (0x07ff)
457
458extern	struct ep_board ep_board[];
459extern	int ep_boards;
460extern	u_long ep_unit;
461extern	struct ep_softc *ep_alloc __P((int unit, struct ep_board *epb));
462extern	void ep_free __P((struct ep_softc *sc));
463extern	void  ep_intr __P((void *sc));
464extern 	int ep_attach __P((struct ep_softc *sc));
465
466extern	u_int16_t get_e __P((struct ep_softc *sc, int offset));
467
468/*
469 * Config flags
470 */
471#define EP_FLAGS_100TX			0x1
472