if_epreg.h revision 30398
1963Sats/* 24435Sgibbs * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 38876Srgrimes * 4963Sats * Redistribution and use in source and binary forms, with or without 54435Sgibbs * modification, are permitted provided that the following conditions are 64435Sgibbs * met: 1. Redistributions of source code must retain the above copyright 74435Sgibbs * notice, this list of conditions and the following disclaimer. 2. The name 84435Sgibbs * of the author may not be used to endorse or promote products derived from 913765Smpp * this software without specific prior written permission 108876Srgrimes * 114435Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 124435Sgibbs * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 134435Sgibbs * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 144435Sgibbs * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 154435Sgibbs * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 164435Sgibbs * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 174435Sgibbs * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 184435Sgibbs * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 194435Sgibbs * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 204435Sgibbs * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 218876Srgrimes * 227510Sjkh * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by: 238876Srgrimes * 244435Sgibbs October 2, 1994 254435Sgibbs 268876Srgrimes Modified by: Andres Vega Garcia 278876Srgrimes 288876Srgrimes INRIA - Sophia Antipolis, France 298876Srgrimes e-mail: avega@sophia.inria.fr 304435Sgibbs finger: avega@pax.inria.fr 314435Sgibbs 32963Sats */ 337510Sjkh/* 3430398Sitojun * $Id: if_epreg.h,v 1.20 1997/02/22 09:36:26 peter Exp $ 357510Sjkh * 367510Sjkh * Promiscuous mode added and interrupt logic slightly changed 377510Sjkh * to reduce the number of adapter failures. Transceiver select 387510Sjkh * logic changed to use value from EEPROM. Autoconfiguration 397510Sjkh * features added. 407510Sjkh * Done by: 417510Sjkh * Serge Babkin 427510Sjkh * Chelindbank (Chelyabinsk, Russia) 437510Sjkh * babkin@hq.icb.chel.su 447510Sjkh */ 454435Sgibbs 464435Sgibbs/* 4716374Snate * Pccard support for 3C589 by: 4816374Snate * HAMADA Naoki 4916374Snate * nao@tom-yam.or.jp 5016374Snate */ 5116374Snate 5216374Snate/* 534435Sgibbs * Ethernet software status per interface. 544435Sgibbs */ 554435Sgibbsstruct ep_softc { 564435Sgibbs struct arpcom arpcom; /* Ethernet common part */ 5719650Sbde int ep_io_addr; /* i/o bus address */ 584435Sgibbs struct mbuf *top, *mcur; 594435Sgibbs short cur_len; 604435Sgibbs u_short ep_connectors; /* Connectors on this card. */ 6114297Sgibbs u_char ep_connector; /* Configured connector. */ 624435Sgibbs int stat; /* some flags */ 6316374Snate int gone; /* adapter is not present (for PCCARD) */ 644435Sgibbs#define F_RX_FIRST 0x1 657267Sdg#define F_PROMISC 0x8 664435Sgibbs 674435Sgibbs#define F_ACCESS_32_BITS 0x100 684435Sgibbs 6913692Sgibbs struct ep_board *epb; 7013692Sgibbs 7114259Sgibbs int unit; 7214259Sgibbs 734435Sgibbs#ifdef EP_LOCAL_STATS 744435Sgibbs short tx_underrun; 754435Sgibbs short rx_no_first; 764435Sgibbs short rx_no_mbuf; 774435Sgibbs short rx_bpf_disc; 784435Sgibbs short rx_overrunf; 794435Sgibbs short rx_overrunl; 804435Sgibbs#endif 814435Sgibbs}; 824435Sgibbs 8313692Sgibbsstruct ep_board { 8413692Sgibbs int epb_addr; /* address of this board */ 8513692Sgibbs char epb_used; /* was this entry already used for configuring ? */ 8613692Sgibbs /* data from EEPROM for later use */ 8713692Sgibbs u_short eth_addr[3]; /* Ethernet address */ 8813692Sgibbs u_short prod_id; /* product ID */ 8913692Sgibbs u_short res_cfg; /* resource configuration */ 9014259Sgibbs}; 9113692Sgibbs 9213692Sgibbs 934435Sgibbs/* 944435Sgibbs * Some global constants 954435Sgibbs */ 964435Sgibbs#define TX_INIT_RATE 16 974435Sgibbs#define TX_INIT_MAX_RATE 64 984435Sgibbs#define RX_INIT_LATENCY 64 9930398Sitojun#define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */ 10030398Sitojun#define RX_NEXT_EARLY_THRESH 500 1014435Sgibbs 1024435Sgibbs#define EEPROMSIZE 0x40 1034435Sgibbs#define MAX_EEPROMBUSY 1000 1044435Sgibbs#define EP_LAST_TAG 0xd7 1054435Sgibbs#define EP_MAX_BOARDS 16 1064435Sgibbs#define EP_ID_PORT 0x100 10714259Sgibbs#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */ 1084435Sgibbs 1094435Sgibbs/* 1104435Sgibbs * some macros to acces long named fields 1114435Sgibbs */ 1124435Sgibbs#define IS_BASE (is->id_iobase) 1134435Sgibbs#define BASE (sc->ep_io_addr) 1144435Sgibbs 1154435Sgibbs/* 1164435Sgibbs * Commands to read/write EEPROM trough EEPROM command register (Window 0, 1174435Sgibbs * Offset 0xa) 1184435Sgibbs */ 1194435Sgibbs#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 1204435Sgibbs#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 1214435Sgibbs#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 1224435Sgibbs#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 1234435Sgibbs 1244435Sgibbs#define EEPROM_BUSY (1<<15) 1254435Sgibbs#define EEPROM_TST_MODE (1<<14) 1264435Sgibbs 1274435Sgibbs/* 1284435Sgibbs * Some short functions, worth to let them be a macro 1294435Sgibbs */ 1304435Sgibbs#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 1314435Sgibbs#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x)) 1324435Sgibbs 133963Sats/************************************************************************** 1344435Sgibbs * * 135963Sats * These define the EEPROM data structure. They are used in the probe 13613765Smpp * function to verify the existence of the adapter after having sent 137963Sats * the ID_Sequence. 138963Sats * 139963Sats * There are others but only the ones we use are defined here. 140963Sats * 141963Sats **************************************************************************/ 142963Sats 143963Sats#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 144963Sats#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 145963Sats#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 146963Sats#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 147963Sats#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 148963Sats#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 1494435Sgibbs#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 150963Sats 151963Sats/************************************************************************** 152963Sats * * 153963Sats * These are the registers for the 3Com 3c509 and their bit patterns when * 154963Sats * applicable. They have been taken out the the "EtherLink III Parallel * 155963Sats * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 156963Sats * from 3com. * 157963Sats * * 158963Sats **************************************************************************/ 159963Sats 1604435Sgibbs#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a 1614435Sgibbs * command reg. */ 1624435Sgibbs#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status 1634435Sgibbs * reg. */ 1644435Sgibbs#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window 1654435Sgibbs * reg. */ 166963Sats/* 167963Sats * Window 0 registers. Setup. 168963Sats */ 1694435Sgibbs/* Write */ 170963Sats#define EP_W0_EEPROM_DATA 0x0c 171963Sats#define EP_W0_EEPROM_COMMAND 0x0a 172963Sats#define EP_W0_RESOURCE_CFG 0x08 173963Sats#define EP_W0_ADDRESS_CFG 0x06 174963Sats#define EP_W0_CONFIG_CTRL 0x04 1754435Sgibbs/* Read */ 176963Sats#define EP_W0_PRODUCT_ID 0x02 177963Sats#define EP_W0_MFG_ID 0x00 178963Sats 179963Sats/* 180963Sats * Window 1 registers. Operating Set. 181963Sats */ 1824435Sgibbs/* Write */ 183963Sats#define EP_W1_TX_PIO_WR_2 0x02 184963Sats#define EP_W1_TX_PIO_WR_1 0x00 1854435Sgibbs/* Read */ 186963Sats#define EP_W1_FREE_TX 0x0c 1874435Sgibbs#define EP_W1_TX_STATUS 0x0b /* byte */ 1884435Sgibbs#define EP_W1_TIMER 0x0a /* byte */ 189963Sats#define EP_W1_RX_STATUS 0x08 190963Sats#define EP_W1_RX_PIO_RD_2 0x02 191963Sats#define EP_W1_RX_PIO_RD_1 0x00 192963Sats 193963Sats/* 194963Sats * Window 2 registers. Station Address Setup/Read 195963Sats */ 1964435Sgibbs/* Read/Write */ 197963Sats#define EP_W2_ADDR_5 0x05 198963Sats#define EP_W2_ADDR_4 0x04 199963Sats#define EP_W2_ADDR_3 0x03 200963Sats#define EP_W2_ADDR_2 0x02 201963Sats#define EP_W2_ADDR_1 0x01 202963Sats#define EP_W2_ADDR_0 0x00 203963Sats 2044435Sgibbs/* 205963Sats * Window 3 registers. FIFO Management. 206963Sats */ 2074435Sgibbs/* Read */ 208963Sats#define EP_W3_FREE_TX 0x0c 209963Sats#define EP_W3_FREE_RX 0x0a 210963Sats 211963Sats/* 212963Sats * Window 4 registers. Diagnostics. 213963Sats */ 2144435Sgibbs/* Read/Write */ 215963Sats#define EP_W4_MEDIA_TYPE 0x0a 216963Sats#define EP_W4_CTRLR_STATUS 0x08 217963Sats#define EP_W4_NET_DIAG 0x06 218963Sats#define EP_W4_FIFO_DIAG 0x04 219963Sats#define EP_W4_HOST_DIAG 0x02 220963Sats#define EP_W4_TX_DIAG 0x00 221963Sats 222963Sats/* 223963Sats * Window 5 Registers. Results and Internal status. 224963Sats */ 2254435Sgibbs/* Read */ 226963Sats#define EP_W5_READ_0_MASK 0x0c 227963Sats#define EP_W5_INTR_MASK 0x0a 228963Sats#define EP_W5_RX_FILTER 0x08 229963Sats#define EP_W5_RX_EARLY_THRESH 0x06 230963Sats#define EP_W5_TX_AVAIL_THRESH 0x02 231963Sats#define EP_W5_TX_START_THRESH 0x00 232963Sats 233963Sats/* 234963Sats * Window 6 registers. Statistics. 235963Sats */ 2364435Sgibbs/* Read/Write */ 237963Sats#define TX_TOTAL_OK 0x0c 238963Sats#define RX_TOTAL_OK 0x0a 239963Sats#define TX_DEFERRALS 0x08 240963Sats#define RX_FRAMES_OK 0x07 241963Sats#define TX_FRAMES_OK 0x06 242963Sats#define RX_OVERRUNS 0x05 243963Sats#define TX_COLLISIONS 0x04 244963Sats#define TX_AFTER_1_COLLISION 0x03 245963Sats#define TX_AFTER_X_COLLISIONS 0x02 246963Sats#define TX_NO_SQE 0x01 247963Sats#define TX_CD_LOST 0x00 248963Sats 249963Sats/**************************************** 250963Sats * 251963Sats * Register definitions. 252963Sats * 253963Sats ****************************************/ 254963Sats 255963Sats/* 256963Sats * Command register. All windows. 257963Sats * 258963Sats * 16 bit register. 259963Sats * 15-11: 5-bit code for command to be executed. 260963Sats * 10-0: 11-bit arg if any. For commands with no args; 261963Sats * this can be set to anything. 262963Sats */ 2634435Sgibbs#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 2644435Sgibbs * after issuing */ 265963Sats#define WINDOW_SELECT (u_short) (0x1<<11) 2664435Sgibbs#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 2674435Sgibbs * determine whether 2684435Sgibbs * this is needed. If 2694435Sgibbs * so; wait 800 uSec 2704435Sgibbs * before using trans- 2714435Sgibbs * ceiver. */ 2724435Sgibbs#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 2734435Sgibbs * power-up */ 274963Sats#define RX_ENABLE (u_short) (0x4<<11) 275963Sats#define RX_RESET (u_short) (0x5<<11) 276963Sats#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 277963Sats#define TX_ENABLE (u_short) (0x9<<11) 278963Sats#define TX_DISABLE (u_short) (0xa<<11) 279963Sats#define TX_RESET (u_short) (0xb<<11) 280963Sats#define REQ_INTR (u_short) (0xc<<11) 281963Sats#define SET_INTR_MASK (u_short) (0xe<<11) 282963Sats#define SET_RD_0_MASK (u_short) (0xf<<11) 283963Sats#define SET_RX_FILTER (u_short) (0x10<<11) 2844435Sgibbs#define FIL_INDIVIDUAL (u_short) (0x1) 2854435Sgibbs#define FIL_GROUP (u_short) (0x2) 2864435Sgibbs#define FIL_BRDCST (u_short) (0x4) 2874435Sgibbs#define FIL_ALL (u_short) (0x8) 288963Sats#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 289963Sats#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 290963Sats#define SET_TX_START_THRESH (u_short) (0x13<<11) 291963Sats#define STATS_ENABLE (u_short) (0x15<<11) 292963Sats#define STATS_DISABLE (u_short) (0x16<<11) 293963Sats#define STOP_TRANSCEIVER (u_short) (0x17<<11) 2944435Sgibbs/* 2954435Sgibbs * The following C_* acknowledge the various interrupts. Some of them don't 2964435Sgibbs * do anything. See the manual. 2974435Sgibbs */ 2984435Sgibbs#define ACK_INTR (u_short) (0x6800) 2994435Sgibbs#define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 3004435Sgibbs#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 3014435Sgibbs#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 3024435Sgibbs#define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 3034435Sgibbs#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 3044435Sgibbs#define C_RX_EARLY (u_short) (ACK_INTR|0x20) 3054435Sgibbs#define C_INT_RQD (u_short) (ACK_INTR|0x40) 3064435Sgibbs#define C_UPD_STATS (u_short) (ACK_INTR|0x80) 3077510Sjkh#define C_MASK (u_short) 0xFF /* mask of C_* */ 308963Sats 309963Sats/* 310963Sats * Status register. All windows. 311963Sats * 312963Sats * 15-13: Window number(0-7). 313963Sats * 12: Command_in_progress. 314963Sats * 11: reserved. 315963Sats * 10: reserved. 316963Sats * 9: reserved. 317963Sats * 8: reserved. 318963Sats * 7: Update Statistics. 319963Sats * 6: Interrupt Requested. 320963Sats * 5: RX Early. 321963Sats * 4: RX Complete. 322963Sats * 3: TX Available. 323963Sats * 2: TX Complete. 324963Sats * 1: Adapter Failure. 325963Sats * 0: Interrupt Latch. 326963Sats */ 327963Sats#define S_INTR_LATCH (u_short) (0x1) 328963Sats#define S_CARD_FAILURE (u_short) (0x2) 329963Sats#define S_TX_COMPLETE (u_short) (0x4) 330963Sats#define S_TX_AVAIL (u_short) (0x8) 331963Sats#define S_RX_COMPLETE (u_short) (0x10) 332963Sats#define S_RX_EARLY (u_short) (0x20) 333963Sats#define S_INT_RQD (u_short) (0x40) 334963Sats#define S_UPD_STATS (u_short) (0x80) 3357510Sjkh#define S_MASK (u_short) 0xFF /* mask of S_* */ 3364435Sgibbs#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ 3374435Sgibbs S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 338963Sats#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 339963Sats 3407510Sjkh/* Address Config. Register. 3417510Sjkh * Window 0/Port 06 3427510Sjkh */ 3437510Sjkh 3447510Sjkh#define ACF_CONNECTOR_BITS 14 3457510Sjkh#define ACF_CONNECTOR_UTP 0 3467510Sjkh#define ACF_CONNECTOR_AUI 1 3477510Sjkh#define ACF_CONNECTOR_BNC 3 3487510Sjkh 3497510Sjkh/* Resource configuration register. 3507510Sjkh * Window 0/Port 08 3517510Sjkh * 3527510Sjkh */ 3537510Sjkh 35417223Samurai#define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \ 35517223Samurai ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \ 35617223Samurai ((u_short)(irq)<<12)) ) /* set IRQ i */ 3577510Sjkh 358963Sats/* 3598876Srgrimes * FIFO Registers. 3604435Sgibbs * RX Status. Window 1/Port 08 361963Sats * 362963Sats * 15: Incomplete or FIFO empty. 363963Sats * 14: 1: Error in RX Packet 0: Incomplete or no error. 364963Sats * 13-11: Type of error. 365963Sats * 1000 = Overrun. 366963Sats * 1011 = Run Packet Error. 367963Sats * 1100 = Alignment Error. 368963Sats * 1101 = CRC Error. 369963Sats * 1001 = Oversize Packet Error (>1514 bytes) 370963Sats * 0010 = Dribble Bits. 371963Sats * (all other error codes, no errors.) 372963Sats * 373963Sats * 10-0: RX Bytes (0-1514) 374963Sats */ 3754435Sgibbs#define ERR_RX_INCOMPLETE (u_short) (0x1<<15) 3764435Sgibbs#define ERR_RX (u_short) (0x1<<14) 3774435Sgibbs#define ERR_RX_OVERRUN (u_short) (0x8<<11) 3784435Sgibbs#define ERR_RX_RUN_PKT (u_short) (0xb<<11) 3794435Sgibbs#define ERR_RX_ALIGN (u_short) (0xc<<11) 3804435Sgibbs#define ERR_RX_CRC (u_short) (0xd<<11) 3814435Sgibbs#define ERR_RX_OVERSIZE (u_short) (0x9<<11) 3824435Sgibbs#define ERR_RX_DRIBBLE (u_short) (0x2<<11) 383963Sats 384963Sats/* 3858876Srgrimes * FIFO Registers. 3864435Sgibbs * TX Status. Window 1/Port 0B 387963Sats * 388963Sats * Reports the transmit status of a completed transmission. Writing this 389963Sats * register pops the transmit completion stack. 390963Sats * 391963Sats * Window 1/Port 0x0b. 392963Sats * 393963Sats * 7: Complete 394963Sats * 6: Interrupt on successful transmission requested. 395963Sats * 5: Jabber Error (TP Only, TX Reset required. ) 396963Sats * 4: Underrun (TX Reset required. ) 397963Sats * 3: Maximum Collisions. 398963Sats * 2: TX Status Overflow. 399963Sats * 1-0: Undefined. 400963Sats * 401963Sats */ 402963Sats#define TXS_COMPLETE 0x80 4034435Sgibbs#define TXS_SUCCES_INTR_REQ 0x40 404963Sats#define TXS_JABBER 0x20 405963Sats#define TXS_UNDERRUN 0x10 406963Sats#define TXS_MAX_COLLISION 0x8 407963Sats#define TXS_STATUS_OVERFLOW 0x4 408963Sats 409963Sats/* 4108876Srgrimes * Configuration control register. 4114435Sgibbs * Window 0/Port 04 4124435Sgibbs */ 4134435Sgibbs/* Read */ 4144435Sgibbs#define IS_AUI (1<<13) 4154435Sgibbs#define IS_BNC (1<<12) 4164435Sgibbs#define IS_UTP (1<<9) 4174435Sgibbs/* Write */ 4184435Sgibbs#define ENABLE_DRQ_IRQ 0x0001 4194435Sgibbs#define W0_P4_CMD_RESET_ADAPTER 0x4 4204435Sgibbs#define W0_P4_CMD_ENABLE_ADAPTER 0x1 4218876Srgrimes/* 4224435Sgibbs * Media type and status. 4234435Sgibbs * Window 4/Port 0A 4244435Sgibbs */ 4254435Sgibbs#define ENABLE_UTP 0xc0 4264435Sgibbs#define DISABLE_UTP 0x0 4274435Sgibbs 4284435Sgibbs/* 429963Sats * Misc defines for various things. 430963Sats */ 4314435Sgibbs#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ 4324435Sgibbs#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ 4334435Sgibbs#define PROD_ID 0x9150 4344435Sgibbs 435963Sats#define AUI 0x1 436963Sats#define BNC 0x2 437963Sats#define UTP 0x4 4384435Sgibbs 439963Sats#define RX_BYTES_MASK (u_short) (0x07ff) 4402478Sats 44114259Sgibbsextern struct ep_board ep_board[]; 44214259Sgibbsextern int ep_boards; 44314259Sgibbsextern u_long ep_unit; 44414259Sgibbsextern struct ep_softc *ep_alloc __P((int unit, struct ep_board *epb)); 44514259Sgibbsextern void ep_free __P((struct ep_softc *sc)); 44614259Sgibbsextern void ep_intr __P((void *sc)); 44714259Sgibbsextern int ep_attach __P((struct ep_softc *sc)); 44814259Sgibbs 44914259Sgibbsextern u_int16_t get_e __P((struct ep_softc *sc, int offset)); 450