if_epreg.h revision 14259
1963Sats/* 24435Sgibbs * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 38876Srgrimes * 4963Sats * Redistribution and use in source and binary forms, with or without 54435Sgibbs * modification, are permitted provided that the following conditions are 64435Sgibbs * met: 1. Redistributions of source code must retain the above copyright 74435Sgibbs * notice, this list of conditions and the following disclaimer. 2. The name 84435Sgibbs * of the author may not be used to endorse or promote products derived from 913765Smpp * this software without specific prior written permission 108876Srgrimes * 114435Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 124435Sgibbs * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 134435Sgibbs * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 144435Sgibbs * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 154435Sgibbs * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 164435Sgibbs * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 174435Sgibbs * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 184435Sgibbs * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 194435Sgibbs * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 204435Sgibbs * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 218876Srgrimes * 227510Sjkh * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by: 238876Srgrimes * 244435Sgibbs October 2, 1994 254435Sgibbs 268876Srgrimes Modified by: Andres Vega Garcia 278876Srgrimes 288876Srgrimes INRIA - Sophia Antipolis, France 298876Srgrimes e-mail: avega@sophia.inria.fr 304435Sgibbs finger: avega@pax.inria.fr 314435Sgibbs 32963Sats */ 337510Sjkh/* 3414259Sgibbs * $Id: if_epreg.h,v 1.11 1996/02/06 18:50:42 wollman Exp $ 357510Sjkh * 367510Sjkh * Promiscuous mode added and interrupt logic slightly changed 377510Sjkh * to reduce the number of adapter failures. Transceiver select 387510Sjkh * logic changed to use value from EEPROM. Autoconfiguration 397510Sjkh * features added. 407510Sjkh * Done by: 417510Sjkh * Serge Babkin 427510Sjkh * Chelindbank (Chelyabinsk, Russia) 437510Sjkh * babkin@hq.icb.chel.su 447510Sjkh */ 454435Sgibbs 464435Sgibbs/* 474435Sgibbs * Ethernet software status per interface. 484435Sgibbs */ 494435Sgibbsstruct ep_softc { 504435Sgibbs struct arpcom arpcom; /* Ethernet common part */ 514435Sgibbs short ep_io_addr; /* i/o bus address */ 524435Sgibbs#define MAX_MBS 8 /* # of mbufs we keep around */ 534435Sgibbs struct mbuf *mb[MAX_MBS]; /* spare mbuf storage. */ 544435Sgibbs int next_mb; /* Which mbuf to use next. */ 554435Sgibbs int last_mb; /* Last mbuf. */ 564435Sgibbs struct mbuf *top, *mcur; 574435Sgibbs short tx_start_thresh; /* Current TX_start_thresh. */ 584435Sgibbs short tx_rate; 594435Sgibbs short tx_counter; 604435Sgibbs short rx_early_thresh; /* Current RX_early_thresh. */ 614435Sgibbs short rx_latency; 624435Sgibbs short rx_avg_pkt; 634435Sgibbs short cur_len; 644435Sgibbs u_short ep_connectors; /* Connectors on this card. */ 6514259Sgibbs u_short ep_connector; /* Configured connector. */ 664435Sgibbs int stat; /* some flags */ 674435Sgibbs#define F_RX_FIRST 0x1 684435Sgibbs#define F_WAIT_TRAIL 0x2 694435Sgibbs#define F_RX_TRAILER 0x4 707267Sdg#define F_PROMISC 0x8 714435Sgibbs 724435Sgibbs#define F_ACCESS_32_BITS 0x100 734435Sgibbs 7413692Sgibbs struct ep_board *epb; 7513692Sgibbs 7614259Sgibbs int unit; 7714259Sgibbs 7814259Sgibbs struct kern_devconf* kdc; 7914259Sgibbs 804435Sgibbs#ifdef EP_LOCAL_STATS 814435Sgibbs short tx_underrun; 824435Sgibbs short rx_no_first; 834435Sgibbs short rx_no_mbuf; 844435Sgibbs short rx_bpf_disc; 854435Sgibbs short rx_overrunf; 864435Sgibbs short rx_overrunl; 874435Sgibbs#endif 884435Sgibbs}; 894435Sgibbs 9013692Sgibbsstruct ep_board { 9113692Sgibbs int epb_addr; /* address of this board */ 9213692Sgibbs char epb_used; /* was this entry already used for configuring ? */ 9313692Sgibbs /* data from EEPROM for later use */ 9413692Sgibbs u_short eth_addr[3]; /* Ethernet address */ 9513692Sgibbs u_short prod_id; /* product ID */ 9613692Sgibbs u_short res_cfg; /* resource configuration */ 9714259Sgibbs}; 9813692Sgibbs 9913692Sgibbs 1004435Sgibbs/* 1014435Sgibbs * Some global constants 1024435Sgibbs */ 1034435Sgibbs#define ETHER_MIN_LEN 64 1044435Sgibbs#define ETHER_MAX_LEN 1518 1054435Sgibbs#define ETHER_ADDR_LEN 6 1064435Sgibbs 1074435Sgibbs#define TX_INIT_RATE 16 1084435Sgibbs#define TX_INIT_MAX_RATE 64 1094435Sgibbs#define RX_INIT_LATENCY 64 1104435Sgibbs#define RX_INIT_EARLY_THRESH 64 1114435Sgibbs#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 1124435Sgibbs#define MIN_RX_EARLY_THRESHL 4 1134435Sgibbs 1144435Sgibbs#define EEPROMSIZE 0x40 1154435Sgibbs#define MAX_EEPROMBUSY 1000 1164435Sgibbs#define EP_LAST_TAG 0xd7 1174435Sgibbs#define EP_MAX_BOARDS 16 1184435Sgibbs#define EP_ID_PORT 0x100 11914259Sgibbs#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */ 1204435Sgibbs 1214435Sgibbs/* 1224435Sgibbs * some macros to acces long named fields 1234435Sgibbs */ 1244435Sgibbs#define IS_BASE (is->id_iobase) 1254435Sgibbs#define BASE (sc->ep_io_addr) 1264435Sgibbs 1274435Sgibbs/* 1284435Sgibbs * Commands to read/write EEPROM trough EEPROM command register (Window 0, 1294435Sgibbs * Offset 0xa) 1304435Sgibbs */ 1314435Sgibbs#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 1324435Sgibbs#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 1334435Sgibbs#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 1344435Sgibbs#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 1354435Sgibbs 1364435Sgibbs#define EEPROM_BUSY (1<<15) 1374435Sgibbs#define EEPROM_TST_MODE (1<<14) 1384435Sgibbs 1394435Sgibbs/* 1404435Sgibbs * Some short functions, worth to let them be a macro 1414435Sgibbs */ 1424435Sgibbs#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 1434435Sgibbs#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x)) 1444435Sgibbs 145963Sats/************************************************************************** 1464435Sgibbs * * 147963Sats * These define the EEPROM data structure. They are used in the probe 14813765Smpp * function to verify the existence of the adapter after having sent 149963Sats * the ID_Sequence. 150963Sats * 151963Sats * There are others but only the ones we use are defined here. 152963Sats * 153963Sats **************************************************************************/ 154963Sats 155963Sats#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 156963Sats#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 157963Sats#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 158963Sats#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 159963Sats#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 160963Sats#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 1614435Sgibbs#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 162963Sats 163963Sats/************************************************************************** 164963Sats * * 165963Sats * These are the registers for the 3Com 3c509 and their bit patterns when * 166963Sats * applicable. They have been taken out the the "EtherLink III Parallel * 167963Sats * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 168963Sats * from 3com. * 169963Sats * * 170963Sats **************************************************************************/ 171963Sats 1724435Sgibbs#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a 1734435Sgibbs * command reg. */ 1744435Sgibbs#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status 1754435Sgibbs * reg. */ 1764435Sgibbs#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window 1774435Sgibbs * reg. */ 178963Sats/* 179963Sats * Window 0 registers. Setup. 180963Sats */ 1814435Sgibbs/* Write */ 182963Sats#define EP_W0_EEPROM_DATA 0x0c 183963Sats#define EP_W0_EEPROM_COMMAND 0x0a 184963Sats#define EP_W0_RESOURCE_CFG 0x08 185963Sats#define EP_W0_ADDRESS_CFG 0x06 186963Sats#define EP_W0_CONFIG_CTRL 0x04 1874435Sgibbs/* Read */ 188963Sats#define EP_W0_PRODUCT_ID 0x02 189963Sats#define EP_W0_MFG_ID 0x00 190963Sats 191963Sats/* 192963Sats * Window 1 registers. Operating Set. 193963Sats */ 1944435Sgibbs/* Write */ 195963Sats#define EP_W1_TX_PIO_WR_2 0x02 196963Sats#define EP_W1_TX_PIO_WR_1 0x00 1974435Sgibbs/* Read */ 198963Sats#define EP_W1_FREE_TX 0x0c 1994435Sgibbs#define EP_W1_TX_STATUS 0x0b /* byte */ 2004435Sgibbs#define EP_W1_TIMER 0x0a /* byte */ 201963Sats#define EP_W1_RX_STATUS 0x08 202963Sats#define EP_W1_RX_PIO_RD_2 0x02 203963Sats#define EP_W1_RX_PIO_RD_1 0x00 204963Sats 205963Sats/* 206963Sats * Window 2 registers. Station Address Setup/Read 207963Sats */ 2084435Sgibbs/* Read/Write */ 209963Sats#define EP_W2_ADDR_5 0x05 210963Sats#define EP_W2_ADDR_4 0x04 211963Sats#define EP_W2_ADDR_3 0x03 212963Sats#define EP_W2_ADDR_2 0x02 213963Sats#define EP_W2_ADDR_1 0x01 214963Sats#define EP_W2_ADDR_0 0x00 215963Sats 2164435Sgibbs/* 217963Sats * Window 3 registers. FIFO Management. 218963Sats */ 2194435Sgibbs/* Read */ 220963Sats#define EP_W3_FREE_TX 0x0c 221963Sats#define EP_W3_FREE_RX 0x0a 222963Sats 223963Sats/* 224963Sats * Window 4 registers. Diagnostics. 225963Sats */ 2264435Sgibbs/* Read/Write */ 227963Sats#define EP_W4_MEDIA_TYPE 0x0a 228963Sats#define EP_W4_CTRLR_STATUS 0x08 229963Sats#define EP_W4_NET_DIAG 0x06 230963Sats#define EP_W4_FIFO_DIAG 0x04 231963Sats#define EP_W4_HOST_DIAG 0x02 232963Sats#define EP_W4_TX_DIAG 0x00 233963Sats 234963Sats/* 235963Sats * Window 5 Registers. Results and Internal status. 236963Sats */ 2374435Sgibbs/* Read */ 238963Sats#define EP_W5_READ_0_MASK 0x0c 239963Sats#define EP_W5_INTR_MASK 0x0a 240963Sats#define EP_W5_RX_FILTER 0x08 241963Sats#define EP_W5_RX_EARLY_THRESH 0x06 242963Sats#define EP_W5_TX_AVAIL_THRESH 0x02 243963Sats#define EP_W5_TX_START_THRESH 0x00 244963Sats 245963Sats/* 246963Sats * Window 6 registers. Statistics. 247963Sats */ 2484435Sgibbs/* Read/Write */ 249963Sats#define TX_TOTAL_OK 0x0c 250963Sats#define RX_TOTAL_OK 0x0a 251963Sats#define TX_DEFERRALS 0x08 252963Sats#define RX_FRAMES_OK 0x07 253963Sats#define TX_FRAMES_OK 0x06 254963Sats#define RX_OVERRUNS 0x05 255963Sats#define TX_COLLISIONS 0x04 256963Sats#define TX_AFTER_1_COLLISION 0x03 257963Sats#define TX_AFTER_X_COLLISIONS 0x02 258963Sats#define TX_NO_SQE 0x01 259963Sats#define TX_CD_LOST 0x00 260963Sats 261963Sats/**************************************** 262963Sats * 263963Sats * Register definitions. 264963Sats * 265963Sats ****************************************/ 266963Sats 267963Sats/* 268963Sats * Command register. All windows. 269963Sats * 270963Sats * 16 bit register. 271963Sats * 15-11: 5-bit code for command to be executed. 272963Sats * 10-0: 11-bit arg if any. For commands with no args; 273963Sats * this can be set to anything. 274963Sats */ 2754435Sgibbs#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 2764435Sgibbs * after issuing */ 277963Sats#define WINDOW_SELECT (u_short) (0x1<<11) 2784435Sgibbs#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 2794435Sgibbs * determine whether 2804435Sgibbs * this is needed. If 2814435Sgibbs * so; wait 800 uSec 2824435Sgibbs * before using trans- 2834435Sgibbs * ceiver. */ 2844435Sgibbs#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 2854435Sgibbs * power-up */ 286963Sats#define RX_ENABLE (u_short) (0x4<<11) 287963Sats#define RX_RESET (u_short) (0x5<<11) 288963Sats#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 289963Sats#define TX_ENABLE (u_short) (0x9<<11) 290963Sats#define TX_DISABLE (u_short) (0xa<<11) 291963Sats#define TX_RESET (u_short) (0xb<<11) 292963Sats#define REQ_INTR (u_short) (0xc<<11) 293963Sats#define SET_INTR_MASK (u_short) (0xe<<11) 294963Sats#define SET_RD_0_MASK (u_short) (0xf<<11) 295963Sats#define SET_RX_FILTER (u_short) (0x10<<11) 2964435Sgibbs#define FIL_INDIVIDUAL (u_short) (0x1) 2974435Sgibbs#define FIL_GROUP (u_short) (0x2) 2984435Sgibbs#define FIL_BRDCST (u_short) (0x4) 2994435Sgibbs#define FIL_ALL (u_short) (0x8) 300963Sats#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 301963Sats#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 302963Sats#define SET_TX_START_THRESH (u_short) (0x13<<11) 303963Sats#define STATS_ENABLE (u_short) (0x15<<11) 304963Sats#define STATS_DISABLE (u_short) (0x16<<11) 305963Sats#define STOP_TRANSCEIVER (u_short) (0x17<<11) 3064435Sgibbs/* 3074435Sgibbs * The following C_* acknowledge the various interrupts. Some of them don't 3084435Sgibbs * do anything. See the manual. 3094435Sgibbs */ 3104435Sgibbs#define ACK_INTR (u_short) (0x6800) 3114435Sgibbs#define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 3124435Sgibbs#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 3134435Sgibbs#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 3144435Sgibbs#define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 3154435Sgibbs#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 3164435Sgibbs#define C_RX_EARLY (u_short) (ACK_INTR|0x20) 3174435Sgibbs#define C_INT_RQD (u_short) (ACK_INTR|0x40) 3184435Sgibbs#define C_UPD_STATS (u_short) (ACK_INTR|0x80) 3197510Sjkh#define C_MASK (u_short) 0xFF /* mask of C_* */ 320963Sats 321963Sats/* 322963Sats * Status register. All windows. 323963Sats * 324963Sats * 15-13: Window number(0-7). 325963Sats * 12: Command_in_progress. 326963Sats * 11: reserved. 327963Sats * 10: reserved. 328963Sats * 9: reserved. 329963Sats * 8: reserved. 330963Sats * 7: Update Statistics. 331963Sats * 6: Interrupt Requested. 332963Sats * 5: RX Early. 333963Sats * 4: RX Complete. 334963Sats * 3: TX Available. 335963Sats * 2: TX Complete. 336963Sats * 1: Adapter Failure. 337963Sats * 0: Interrupt Latch. 338963Sats */ 339963Sats#define S_INTR_LATCH (u_short) (0x1) 340963Sats#define S_CARD_FAILURE (u_short) (0x2) 341963Sats#define S_TX_COMPLETE (u_short) (0x4) 342963Sats#define S_TX_AVAIL (u_short) (0x8) 343963Sats#define S_RX_COMPLETE (u_short) (0x10) 344963Sats#define S_RX_EARLY (u_short) (0x20) 345963Sats#define S_INT_RQD (u_short) (0x40) 346963Sats#define S_UPD_STATS (u_short) (0x80) 3477510Sjkh#define S_MASK (u_short) 0xFF /* mask of S_* */ 3484435Sgibbs#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ 3494435Sgibbs S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 350963Sats#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 351963Sats 3527510Sjkh/* Address Config. Register. 3537510Sjkh * Window 0/Port 06 3547510Sjkh */ 3557510Sjkh 3567510Sjkh#define ACF_CONNECTOR_BITS 14 3577510Sjkh#define ACF_CONNECTOR_UTP 0 3587510Sjkh#define ACF_CONNECTOR_AUI 1 3597510Sjkh#define ACF_CONNECTOR_BNC 3 3607510Sjkh 3617510Sjkh/* Resource configuration register. 3627510Sjkh * Window 0/Port 08 3637510Sjkh * 3647510Sjkh */ 3657510Sjkh 3667510Sjkh#define SET_IRQ(i) (((i)<<12) | 0xF00) /* set IRQ i */ 3677510Sjkh 368963Sats/* 3698876Srgrimes * FIFO Registers. 3704435Sgibbs * RX Status. Window 1/Port 08 371963Sats * 372963Sats * 15: Incomplete or FIFO empty. 373963Sats * 14: 1: Error in RX Packet 0: Incomplete or no error. 374963Sats * 13-11: Type of error. 375963Sats * 1000 = Overrun. 376963Sats * 1011 = Run Packet Error. 377963Sats * 1100 = Alignment Error. 378963Sats * 1101 = CRC Error. 379963Sats * 1001 = Oversize Packet Error (>1514 bytes) 380963Sats * 0010 = Dribble Bits. 381963Sats * (all other error codes, no errors.) 382963Sats * 383963Sats * 10-0: RX Bytes (0-1514) 384963Sats */ 3854435Sgibbs#define ERR_RX_INCOMPLETE (u_short) (0x1<<15) 3864435Sgibbs#define ERR_RX (u_short) (0x1<<14) 3874435Sgibbs#define ERR_RX_OVERRUN (u_short) (0x8<<11) 3884435Sgibbs#define ERR_RX_RUN_PKT (u_short) (0xb<<11) 3894435Sgibbs#define ERR_RX_ALIGN (u_short) (0xc<<11) 3904435Sgibbs#define ERR_RX_CRC (u_short) (0xd<<11) 3914435Sgibbs#define ERR_RX_OVERSIZE (u_short) (0x9<<11) 3924435Sgibbs#define ERR_RX_DRIBBLE (u_short) (0x2<<11) 393963Sats 394963Sats/* 3958876Srgrimes * FIFO Registers. 3964435Sgibbs * TX Status. Window 1/Port 0B 397963Sats * 398963Sats * Reports the transmit status of a completed transmission. Writing this 399963Sats * register pops the transmit completion stack. 400963Sats * 401963Sats * Window 1/Port 0x0b. 402963Sats * 403963Sats * 7: Complete 404963Sats * 6: Interrupt on successful transmission requested. 405963Sats * 5: Jabber Error (TP Only, TX Reset required. ) 406963Sats * 4: Underrun (TX Reset required. ) 407963Sats * 3: Maximum Collisions. 408963Sats * 2: TX Status Overflow. 409963Sats * 1-0: Undefined. 410963Sats * 411963Sats */ 412963Sats#define TXS_COMPLETE 0x80 4134435Sgibbs#define TXS_SUCCES_INTR_REQ 0x40 414963Sats#define TXS_JABBER 0x20 415963Sats#define TXS_UNDERRUN 0x10 416963Sats#define TXS_MAX_COLLISION 0x8 417963Sats#define TXS_STATUS_OVERFLOW 0x4 418963Sats 419963Sats/* 4208876Srgrimes * Configuration control register. 4214435Sgibbs * Window 0/Port 04 4224435Sgibbs */ 4234435Sgibbs/* Read */ 4244435Sgibbs#define IS_AUI (1<<13) 4254435Sgibbs#define IS_BNC (1<<12) 4264435Sgibbs#define IS_UTP (1<<9) 4274435Sgibbs/* Write */ 4284435Sgibbs#define ENABLE_DRQ_IRQ 0x0001 4294435Sgibbs#define W0_P4_CMD_RESET_ADAPTER 0x4 4304435Sgibbs#define W0_P4_CMD_ENABLE_ADAPTER 0x1 4318876Srgrimes/* 4324435Sgibbs * Media type and status. 4334435Sgibbs * Window 4/Port 0A 4344435Sgibbs */ 4354435Sgibbs#define ENABLE_UTP 0xc0 4364435Sgibbs#define DISABLE_UTP 0x0 4374435Sgibbs 4384435Sgibbs/* 439963Sats * Misc defines for various things. 440963Sats */ 4414435Sgibbs#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ 4424435Sgibbs#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ 4434435Sgibbs#define PROD_ID 0x9150 4444435Sgibbs 445963Sats#define AUI 0x1 446963Sats#define BNC 0x2 447963Sats#define UTP 0x4 4484435Sgibbs 449963Sats#define ETHER_ADDR_LEN 6 450963Sats#define ETHER_MAX 1536 451963Sats#define RX_BYTES_MASK (u_short) (0x07ff) 4522478Sats 45314259Sgibbsextern struct ep_board ep_board[]; 45414259Sgibbsextern int ep_boards; 45514259Sgibbsextern u_long ep_unit; 45614259Sgibbsextern struct ep_softc *ep_alloc __P((int unit, struct ep_board *epb)); 45714259Sgibbsextern void ep_free __P((struct ep_softc *sc)); 45814259Sgibbsextern void ep_intr __P((void *sc)); 45914259Sgibbsextern int ep_attach __P((struct ep_softc *sc)); 46014259Sgibbs 46114259Sgibbsextern u_int16_t get_e __P((struct ep_softc *sc, int offset)); 462