if_epreg.h revision 117700
1/* 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from 9 * this software without specific prior written permission 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 * 22 * $FreeBSD: head/sys/dev/ep/if_epreg.h 117700 2003-07-17 19:37:56Z markm $ 23 */ 24 25/* 26 * DELAY_MULTIPLE: How much to boost "base" delays, except 27 * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this. 28 */ 29#define DELAY_MULTIPLE 10 30#define BIT_DELAY_MULTIPLE 10 31 32/* 33 * Some global constants 34 */ 35#define TX_INIT_RATE 16 36#define TX_INIT_MAX_RATE 64 37#define RX_INIT_LATENCY 64 38#define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */ 39#define RX_NEXT_EARLY_THRESH 500 40 41#define EEPROMSIZE 0x40 42#define MAX_EEPROMBUSY 1000 43#define EP_LAST_TAG 0xd7 44#define EP_MAX_BOARDS 16 45/* 46 * This `ID' port is a mere hack. There's currently no chance to register 47 * it with config's idea of the ports that are in use. 48 * 49 * "After the automatic configuration is completed, the IDS is in its initial 50 * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where 51 * 'x' is any hex digit. If a zero is written to any one of these ports, then 52 * that address is remembered and becomes the ID port. A second zero written 53 * to that port resets the ID sequence to its initial state. The IDS watches 54 * for the ID sequence to be written to the ID port." 55 * 56 * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray 57 * ports. 58 */ 59#define EP_ID_PORT 0x110 60#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */ 61 62/* 63 * some macros to acces long named fields 64 */ 65#define BASE (sc->ep_io_addr) 66 67/* 68 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 69 * Offset 0xa) 70 */ 71#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 72#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 73#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 74#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 75 76#define EEPROM_BUSY (1<<15) 77#define EEPROM_TST_MODE (1<<14) 78 79/* 80 * Some short functions, worth to let them be a macro 81 */ 82#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 83#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x)) 84 85/************************************************************************** 86 * * 87 * These define the EEPROM data structure. They are used in the probe 88 * function to verify the existence of the adapter after having sent 89 * the ID_Sequence. 90 * 91 **************************************************************************/ 92 93#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 94#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 95#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 96#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 97#define EEPROM_MFG_DATE 0x4 /* Manufacturing date */ 98#define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */ 99#define EEPROM_MFG_PRODUCT 0x6 /* Product code */ 100#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 101#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 102#define ADDR_CFG_EISA 0x1f 103#define ADDR_CFG_MASK 0x1f 104#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 105#define EEPROM_OEM_ADDR0 0xa 106#define EEPROM_OEM_ADDR1 0xb 107#define EEPROM_OEM_ADDR2 0xc 108#define EEPROM_SOFTINFO 0xd 109#define EEPROM_COMPAT 0xe 110#define EEPROM_SOFTINFO2 0xf 111#define EEPROM_CAP 0x10 112#define CAP_ISA 0x2083 113#define CAP_PCMCIA 0x2082 114#define EEPROM_INT_CONFIG_0 0x12 115#define EEPROM_INT_CONFIG_1 0x13 116/* RAM Partition TX FIFO/RX FIFO */ 117#define ICW1_RAM_PART_MASK 0x03 118#define ICW1_RAM_PART_35 0x00 /* 2:5 (only legal if RAM size == 000b 119 * default power-up/reset */ 120#define ICW1_RAM_PART_13 0x01 /* 1:3 (only legal if RAM size == 121 * 000b) */ 122#define ICW1_RAM_PART_11 0x10 /* 1:1 */ 123#define ICW1_RAM_PART_RESV 0x11 /* Reserved */ 124/* ISA Adapter Selection */ 125#define ICW1_IAS_MASK 0x0c 126#define ICW1_IAS_DIS 0x00 /* Both mechanisms disabled (default) */ 127#define ICW1_IAS_ISA 0x04 /* ISA contention only */ 128#define ICW1_IAS_PNP 0x08 /* ISA Plug and Play only */ 129#define ICW1_IAS_BOTH 0x0c /* Both mechanisms enabled */ 130 131#define EEPROM_CHECKSUM_EL3 0x17 132 133/************************************************************************** 134 * * 135 * These are the registers for the 3Com 3c509 and their bit patterns when * 136 * applicable. They have been taken out the the "EtherLink III Parallel * 137 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 138 * from 3com. * 139 * * 140 **************************************************************************/ 141 142#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a 143 * command reg. */ 144#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status 145 * reg. */ 146#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window 147 * reg. */ 148/* 149 * Window 0 registers. Setup. 150 */ 151/* Write */ 152#define EP_W0_EEPROM_DATA 0x0c 153#define EP_W0_EEPROM_COMMAND 0x0a 154#define EP_W0_RESOURCE_CFG 0x08 155#define EP_W0_ADDRESS_CFG 0x06 156#define EP_W0_CONFIG_CTRL 0x04 157/* Read */ 158#define EP_W0_PRODUCT_ID 0x02 159#define EP_W0_MFG_ID 0x00 160 161/* 162 * Window 1 registers. Operating Set. 163 */ 164/* Write */ 165#define EP_W1_TX_PIO_WR_2 0x02 166#define EP_W1_TX_PIO_WR_1 0x00 167/* Read */ 168#define EP_W1_FREE_TX 0x0c 169#define EP_W1_TX_STATUS 0x0b /* byte */ 170#define EP_W1_TIMER 0x0a /* byte */ 171#define EP_W1_RX_STATUS 0x08 172#define EP_W1_RX_PIO_RD_2 0x02 173#define EP_W1_RX_PIO_RD_1 0x00 174 175/* 176 * Window 2 registers. Station Address Setup/Read 177 */ 178/* Read/Write */ 179#define EP_W2_ADDR_5 0x05 180#define EP_W2_ADDR_4 0x04 181#define EP_W2_ADDR_3 0x03 182#define EP_W2_ADDR_2 0x02 183#define EP_W2_ADDR_1 0x01 184#define EP_W2_ADDR_0 0x00 185 186/* 187 * Window 3 registers. FIFO Management. 188 */ 189/* Read */ 190#define EP_W3_FREE_TX 0x0c 191#define EP_W3_FREE_RX 0x0a 192#define EP_W3_OPTIONS 0x08 193 194/* 195 * Window 4 registers. Diagnostics. 196 */ 197/* Read/Write */ 198#define EP_W4_MEDIA_TYPE 0x0a 199#define EP_W4_CTRLR_STATUS 0x08 200#define EP_W4_NET_DIAG 0x06 201#define EP_W4_FIFO_DIAG 0x04 202#define EP_W4_HOST_DIAG 0x02 203#define EP_W4_TX_DIAG 0x00 204 205/* 206 * Window 5 Registers. Results and Internal status. 207 */ 208/* Read */ 209#define EP_W5_READ_0_MASK 0x0c 210#define EP_W5_INTR_MASK 0x0a 211#define EP_W5_RX_FILTER 0x08 212#define EP_W5_RX_EARLY_THRESH 0x06 213#define EP_W5_TX_AVAIL_THRESH 0x02 214#define EP_W5_TX_START_THRESH 0x00 215 216/* 217 * Window 6 registers. Statistics. 218 */ 219/* Read/Write */ 220#define TX_TOTAL_OK 0x0c 221#define RX_TOTAL_OK 0x0a 222#define TX_DEFERRALS 0x08 223#define RX_FRAMES_OK 0x07 224#define TX_FRAMES_OK 0x06 225#define RX_OVERRUNS 0x05 226#define TX_COLLISIONS 0x04 227#define TX_AFTER_1_COLLISION 0x03 228#define TX_AFTER_X_COLLISIONS 0x02 229#define TX_NO_SQE 0x01 230#define TX_CD_LOST 0x00 231 232/**************************************** 233 * 234 * Register definitions. 235 * 236 ****************************************/ 237 238/* 239 * Command parameter that disables threshold interrupts 240 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. 241 * "busmastering" cards need 8188. 242 * The implicit two-bit upshift done by busmastering cards means 243 * a value of 2047 disables threshold interrupts on both. 244 */ 245#define EP_THRESH_DISABLE 2047 246 247/* 248 * Command register. All windows. 249 * 250 * 16 bit register. 251 * 15-11: 5-bit code for command to be executed. 252 * 10-0: 11-bit arg if any. For commands with no args; 253 * this can be set to anything. 254 */ 255#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 256 * after issuing */ 257#define WINDOW_SELECT (u_short) (0x1<<11) 258#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 259 * determine whether 260 * this is needed. If 261 * so; wait 800 uSec 262 * before using trans- 263 * ceiver. */ 264#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 265 * power-up */ 266#define RX_ENABLE (u_short) (0x4<<11) 267#define RX_RESET (u_short) (0x5<<11) 268#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 269#define TX_ENABLE (u_short) (0x9<<11) 270#define TX_DISABLE (u_short) (0xa<<11) 271#define TX_RESET (u_short) (0xb<<11) 272#define REQ_INTR (u_short) (0xc<<11) 273#define SET_INTR_MASK (u_short) (0xe<<11) 274#define SET_RD_0_MASK (u_short) (0xf<<11) 275#define SET_RX_FILTER (u_short) (0x10<<11) 276#define FIL_INDIVIDUAL (u_short) (0x1) 277#define FIL_GROUP (u_short) (0x2) 278#define FIL_BRDCST (u_short) (0x4) 279#define FIL_ALL (u_short) (0x8) 280#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 281#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 282#define SET_TX_START_THRESH (u_short) (0x13<<11) 283#define STATS_ENABLE (u_short) (0x15<<11) 284#define STATS_DISABLE (u_short) (0x16<<11) 285#define STOP_TRANSCEIVER (u_short) (0x17<<11) 286/* 287 * The following C_* acknowledge the various interrupts. Some of them don't 288 * do anything. See the manual. 289 */ 290#define ACK_INTR (u_short) (0x6800) 291#define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 292#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 293#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 294#define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 295#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 296#define C_RX_EARLY (u_short) (ACK_INTR|0x20) 297#define C_INT_RQD (u_short) (ACK_INTR|0x40) 298#define C_UPD_STATS (u_short) (ACK_INTR|0x80) 299#define C_MASK (u_short) 0xFF /* mask of C_* */ 300 301/* 302 * Status register. All windows. 303 * 304 * 15-13: Window number(0-7). 305 * 12: Command_in_progress. 306 * 11: reserved. 307 * 10: reserved. 308 * 9: reserved. 309 * 8: reserved. 310 * 7: Update Statistics. 311 * 6: Interrupt Requested. 312 * 5: RX Early. 313 * 4: RX Complete. 314 * 3: TX Available. 315 * 2: TX Complete. 316 * 1: Adapter Failure. 317 * 0: Interrupt Latch. 318 */ 319#define S_INTR_LATCH (u_short) (0x1) 320#define S_CARD_FAILURE (u_short) (0x2) 321#define S_TX_COMPLETE (u_short) (0x4) 322#define S_TX_AVAIL (u_short) (0x8) 323#define S_RX_COMPLETE (u_short) (0x10) 324#define S_RX_EARLY (u_short) (0x20) 325#define S_INT_RQD (u_short) (0x40) 326#define S_UPD_STATS (u_short) (0x80) 327#define S_MASK (u_short) 0xFF /* mask of S_* */ 328#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ 329 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 330#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 331 332/* Address Config. Register. 333 * Window 0/Port 06 334 */ 335 336#define ACF_CONNECTOR_BITS 14 337#define ACF_CONNECTOR_UTP 0 338#define ACF_CONNECTOR_AUI 1 339#define ACF_CONNECTOR_BNC 3 340 341/* Resource configuration register. 342 * Window 0/Port 08 343 * 344 */ 345 346#define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \ 347 ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \ 348 ((u_short)(irq)<<12)) ) /* set IRQ i */ 349 350/* 351 * FIFO Registers. 352 * RX Status. Window 1/Port 08 353 * 354 * 15: Incomplete or FIFO empty. 355 * 14: 1: Error in RX Packet 0: Incomplete or no error. 356 * 13-11: Type of error. 357 * 1000 = Overrun. 358 * 1011 = Run Packet Error. 359 * 1100 = Alignment Error. 360 * 1101 = CRC Error. 361 * 1001 = Oversize Packet Error (>1514 bytes) 362 * 0010 = Dribble Bits. 363 * (all other error codes, no errors.) 364 * 365 * 10-0: RX Bytes (0-1514) 366 */ 367#define ERR_RX_INCOMPLETE (u_short) (0x1<<15) 368#define ERR_RX (u_short) (0x1<<14) 369#define ERR_RX_OVERRUN (u_short) (0x8<<11) 370#define ERR_RX_RUN_PKT (u_short) (0xb<<11) 371#define ERR_RX_ALIGN (u_short) (0xc<<11) 372#define ERR_RX_CRC (u_short) (0xd<<11) 373#define ERR_RX_OVERSIZE (u_short) (0x9<<11) 374#define ERR_RX_DRIBBLE (u_short) (0x2<<11) 375 376/* 377 * FIFO Registers. 378 * TX Status. Window 1/Port 0B 379 * 380 * Reports the transmit status of a completed transmission. Writing this 381 * register pops the transmit completion stack. 382 * 383 * Window 1/Port 0x0b. 384 * 385 * 7: Complete 386 * 6: Interrupt on successful transmission requested. 387 * 5: Jabber Error (TP Only, TX Reset required. ) 388 * 4: Underrun (TX Reset required. ) 389 * 3: Maximum Collisions. 390 * 2: TX Status Overflow. 391 * 1-0: Undefined. 392 * 393 */ 394#define TXS_COMPLETE 0x80 395#define TXS_SUCCES_INTR_REQ 0x40 396#define TXS_JABBER 0x20 397#define TXS_UNDERRUN 0x10 398#define TXS_MAX_COLLISION 0x8 399#define TXS_STATUS_OVERFLOW 0x4 400 401/* 402 * Configuration control register. 403 * Window 0/Port 04 404 */ 405/* Read */ 406#define IS_AUI (1<<13) 407#define IS_BNC (1<<12) 408#define IS_UTP (1<<9) 409/* Write */ 410#define ENABLE_DRQ_IRQ 0x0001 411#define W0_P4_CMD_RESET_ADAPTER 0x4 412#define W0_P4_CMD_ENABLE_ADAPTER 0x1 413/* 414 * Media type and status. 415 * Window 4/Port 0A 416 */ 417#define ENABLE_UTP 0xc0 418#define DISABLE_UTP 0x0 419 420/* 421 * Misc defines for various things. 422 */ 423#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ 424#define MFG_ID 0x6d50 /* in EEPROM and W0 425 * ADDR_CONFIG */ 426#define PROD_ID 0x9150 427 428#define AUI 0x1 429#define BNC 0x2 430#define UTP 0x4 431 432#define RX_BYTES_MASK (u_short) (0x07ff) 433 434/* 435 * Config flags 436 */ 437#define EP_FLAGS_100TX 0x1 438