1320731Szbb/*- 2368013Smw * SPDX-License-Identifier: BSD-2-Clause 3320731Szbb * 4361534Smw * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5320731Szbb * All rights reserved. 6320731Szbb * 7320731Szbb * Redistribution and use in source and binary forms, with or without 8320731Szbb * modification, are permitted provided that the following conditions 9320731Szbb * are met: 10320731Szbb * 11320731Szbb * 1. Redistributions of source code must retain the above copyright 12320731Szbb * notice, this list of conditions and the following disclaimer. 13320731Szbb * 14320731Szbb * 2. Redistributions in binary form must reproduce the above copyright 15320731Szbb * notice, this list of conditions and the following disclaimer in the 16320731Szbb * documentation and/or other materials provided with the distribution. 17320731Szbb * 18320731Szbb * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19320731Szbb * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20320731Szbb * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21320731Szbb * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22320731Szbb * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23320731Szbb * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24320731Szbb * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25320731Szbb * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26320731Szbb * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27320731Szbb * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28320731Szbb * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29320731Szbb * 30320731Szbb * $FreeBSD: stable/11/sys/dev/ena/ena.h 369337 2021-02-22 20:47:05Z mw $ 31320731Szbb * 32320731Szbb */ 33320731Szbb 34320731Szbb#ifndef ENA_H 35320731Szbb#define ENA_H 36320731Szbb 37320731Szbb#include <sys/types.h> 38320731Szbb 39320731Szbb#include "ena-com/ena_com.h" 40320731Szbb#include "ena-com/ena_eth_com.h" 41320731Szbb 42361467Smw#define DRV_MODULE_VER_MAJOR 2 43368013Smw#define DRV_MODULE_VER_MINOR 3 44369337Smw#define DRV_MODULE_VER_SUBMINOR 1 45320731Szbb 46320731Szbb#define DRV_MODULE_NAME "ena" 47320731Szbb 48320731Szbb#ifndef DRV_MODULE_VERSION 49320731Szbb#define DRV_MODULE_VERSION \ 50320731Szbb __XSTRING(DRV_MODULE_VER_MAJOR) "." \ 51320731Szbb __XSTRING(DRV_MODULE_VER_MINOR) "." \ 52320731Szbb __XSTRING(DRV_MODULE_VER_SUBMINOR) 53320731Szbb#endif 54320731Szbb#define DEVICE_NAME "Elastic Network Adapter (ENA)" 55320731Szbb#define DEVICE_DESC "ENA adapter" 56320731Szbb 57320731Szbb/* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */ 58320731Szbb#define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL) 59320731Szbb 60320731Szbb/* 1 for AENQ + ADMIN */ 61343398Smw#define ENA_ADMIN_MSIX_VEC 1 62343398Smw#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 63320731Szbb 64320731Szbb#define ENA_REG_BAR 0 65320731Szbb#define ENA_MEM_BAR 2 66320731Szbb 67320731Szbb#define ENA_BUS_DMA_SEGS 32 68320731Szbb 69361467Smw#define ENA_DEFAULT_BUF_RING_SIZE 4096 70361467Smw 71320731Szbb#define ENA_DEFAULT_RING_SIZE 1024 72361534Smw#define ENA_MIN_RING_SIZE 256 73320731Szbb 74361467Smw/* 75361467Smw * Refill Rx queue when number of required descriptors is above 76361467Smw * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 77361467Smw */ 78343398Smw#define ENA_RX_REFILL_THRESH_DIVIDER 8 79361467Smw#define ENA_RX_REFILL_THRESH_PACKET 256 80320731Szbb 81320731Szbb#define ENA_IRQNAME_SIZE 40 82320731Szbb 83343397Smw#define ENA_PKT_MAX_BUFS 19 84320731Szbb 85320731Szbb#define ENA_RX_RSS_TABLE_LOG_SIZE 7 86320731Szbb#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 87320731Szbb 88320731Szbb#define ENA_HASH_KEY_SIZE 40 89320731Szbb 90320731Szbb#define ENA_MAX_FRAME_LEN 10000 91343397Smw#define ENA_MIN_FRAME_LEN 60 92320731Szbb 93361467Smw#define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2) 94320731Szbb 95320731Szbb#define DB_THRESHOLD 64 96320731Szbb 97320731Szbb#define TX_COMMIT 32 98320731Szbb /* 99320731Szbb * TX budget for cleaning. It should be half of the RX budget to reduce amount 100320731Szbb * of TCP retransmissions. 101320731Szbb */ 102320731Szbb#define TX_BUDGET 128 103320731Szbb/* RX cleanup budget. -1 stands for infinity. */ 104320731Szbb#define RX_BUDGET 256 105320731Szbb/* 106320731Szbb * How many times we can repeat cleanup in the io irq handling routine if the 107320731Szbb * RX or TX budget was depleted. 108320731Szbb */ 109320731Szbb#define CLEAN_BUDGET 8 110320731Szbb 111320731Szbb#define RX_IRQ_INTERVAL 20 112320731Szbb#define TX_IRQ_INTERVAL 50 113320731Szbb 114343398Smw#define ENA_MIN_MTU 128 115343398Smw 116320731Szbb#define ENA_TSO_MAXSIZE 65536 117320731Szbb 118320731Szbb#define ENA_MMIO_DISABLE_REG_READ BIT(0) 119320731Szbb 120320731Szbb#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 121320731Szbb 122320731Szbb#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 123320731Szbb 124320731Szbb#define ENA_IO_TXQ_IDX(q) (2 * (q)) 125320731Szbb#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 126320731Szbb 127320731Szbb#define ENA_MGMNT_IRQ_IDX 0 128320731Szbb#define ENA_IO_IRQ_FIRST_IDX 1 129320731Szbb#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 130320731Szbb 131361467Smw#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 132361467Smw 133320731Szbb/* 134320731Szbb * ENA device should send keep alive msg every 1 sec. 135320731Szbb * We wait for 6 sec just to be on the safe side. 136320731Szbb */ 137320731Szbb#define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6) 138320731Szbb 139320731Szbb/* Time in jiffies before concluding the transmitter is hung. */ 140320731Szbb#define DEFAULT_TX_CMP_TO (SBT_1S * 5) 141320731Szbb 142320731Szbb/* Number of queues to check for missing queues per timer tick */ 143320731Szbb#define DEFAULT_TX_MONITORED_QUEUES (4) 144320731Szbb 145320731Szbb/* Max number of timeouted packets before device reset */ 146320731Szbb#define DEFAULT_TX_CMP_THRESHOLD (128) 147320731Szbb 148320731Szbb/* 149320731Szbb * Supported PCI vendor and devices IDs 150320731Szbb */ 151320731Szbb#define PCI_VENDOR_ID_AMAZON 0x1d0f 152320731Szbb 153368013Smw#define PCI_DEV_ID_ENA_PF 0x0ec2 154368013Smw#define PCI_DEV_ID_ENA_PF_RSERV0 0x1ec2 155368013Smw#define PCI_DEV_ID_ENA_VF 0xec20 156368013Smw#define PCI_DEV_ID_ENA_VF_RSERV0 0xec21 157320731Szbb 158361467Smw/* 159361467Smw * Flags indicating current ENA driver state 160361467Smw */ 161361467Smwenum ena_flags_t { 162361467Smw ENA_FLAG_DEVICE_RUNNING, 163361467Smw ENA_FLAG_DEV_UP, 164361467Smw ENA_FLAG_LINK_UP, 165361467Smw ENA_FLAG_MSIX_ENABLED, 166361467Smw ENA_FLAG_TRIGGER_RESET, 167361467Smw ENA_FLAG_ONGOING_RESET, 168361467Smw ENA_FLAG_DEV_UP_BEFORE_RESET, 169361467Smw ENA_FLAG_RSS_ACTIVE, 170361467Smw ENA_FLAGS_NUMBER = ENA_FLAG_RSS_ACTIVE 171361467Smw}; 172361467Smw 173361467SmwBITSET_DEFINE(_ena_state, ENA_FLAGS_NUMBER); 174361467Smwtypedef struct _ena_state ena_state_t; 175361467Smw 176361467Smw#define ENA_FLAG_ZERO(adapter) \ 177361467Smw BIT_ZERO(ENA_FLAGS_NUMBER, &(adapter)->flags) 178361467Smw#define ENA_FLAG_ISSET(bit, adapter) \ 179361467Smw BIT_ISSET(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 180361467Smw#define ENA_FLAG_SET_ATOMIC(bit, adapter) \ 181361467Smw BIT_SET_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 182361467Smw#define ENA_FLAG_CLEAR_ATOMIC(bit, adapter) \ 183361467Smw BIT_CLR_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 184361467Smw 185320731Szbbstruct msix_entry { 186320731Szbb int entry; 187320731Szbb int vector; 188320731Szbb}; 189320731Szbb 190320731Szbbtypedef struct _ena_vendor_info_t { 191343398Smw uint16_t vendor_id; 192343398Smw uint16_t device_id; 193320731Szbb unsigned int index; 194320731Szbb} ena_vendor_info_t; 195320731Szbb 196320731Szbbstruct ena_irq { 197320731Szbb /* Interrupt resources */ 198320731Szbb struct resource *res; 199361467Smw driver_filter_t *handler; 200320731Szbb void *data; 201320731Szbb void *cookie; 202320731Szbb unsigned int vector; 203320731Szbb bool requested; 204320731Szbb int cpu; 205320731Szbb char name[ENA_IRQNAME_SIZE]; 206320731Szbb}; 207320731Szbb 208320731Szbbstruct ena_que { 209320731Szbb struct ena_adapter *adapter; 210320731Szbb struct ena_ring *tx_ring; 211320731Szbb struct ena_ring *rx_ring; 212361467Smw 213361467Smw struct task cleanup_task; 214361467Smw struct taskqueue *cleanup_tq; 215361467Smw 216320731Szbb uint32_t id; 217320731Szbb int cpu; 218320731Szbb}; 219320731Szbb 220361467Smwstruct ena_calc_queue_size_ctx { 221361467Smw struct ena_com_dev_get_features_ctx *get_feat_ctx; 222361467Smw struct ena_com_dev *ena_dev; 223361467Smw device_t pdev; 224361534Smw uint32_t tx_queue_size; 225361534Smw uint32_t rx_queue_size; 226361534Smw uint32_t max_tx_queue_size; 227361534Smw uint32_t max_rx_queue_size; 228361467Smw uint16_t max_tx_sgl_size; 229361467Smw uint16_t max_rx_sgl_size; 230361467Smw}; 231361467Smw 232361468Smw#ifdef DEV_NETMAP 233361468Smwstruct ena_netmap_tx_info { 234361468Smw uint32_t socket_buf_idx[ENA_PKT_MAX_BUFS]; 235361468Smw bus_dmamap_t map_seg[ENA_PKT_MAX_BUFS]; 236361468Smw unsigned int sockets_used; 237361468Smw}; 238361468Smw#endif 239361468Smw 240320731Szbbstruct ena_tx_buffer { 241320731Szbb struct mbuf *mbuf; 242320731Szbb /* # of ena desc for this specific mbuf 243320731Szbb * (includes data desc and metadata desc) */ 244320731Szbb unsigned int tx_descs; 245320731Szbb /* # of buffers used by this mbuf */ 246320731Szbb unsigned int num_of_bufs; 247320731Szbb 248361468Smw bus_dmamap_t dmamap; 249361467Smw 250320731Szbb /* Used to detect missing tx packets */ 251320731Szbb struct bintime timestamp; 252320731Szbb bool print_once; 253320731Szbb 254361468Smw#ifdef DEV_NETMAP 255361468Smw struct ena_netmap_tx_info nm_info; 256361468Smw#endif /* DEV_NETMAP */ 257361468Smw 258320731Szbb struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 259320731Szbb} __aligned(CACHE_LINE_SIZE); 260320731Szbb 261320731Szbbstruct ena_rx_buffer { 262320731Szbb struct mbuf *mbuf; 263320731Szbb bus_dmamap_t map; 264320731Szbb struct ena_com_buf ena_buf; 265361468Smw#ifdef DEV_NETMAP 266361468Smw uint32_t netmap_buf_idx; 267361468Smw#endif /* DEV_NETMAP */ 268320731Szbb} __aligned(CACHE_LINE_SIZE); 269320731Szbb 270320731Szbbstruct ena_stats_tx { 271320731Szbb counter_u64_t cnt; 272320731Szbb counter_u64_t bytes; 273320731Szbb counter_u64_t prepare_ctx_err; 274320731Szbb counter_u64_t dma_mapping_err; 275320731Szbb counter_u64_t doorbells; 276320731Szbb counter_u64_t missing_tx_comp; 277320731Szbb counter_u64_t bad_req_id; 278320731Szbb counter_u64_t collapse; 279320731Szbb counter_u64_t collapse_err; 280361467Smw counter_u64_t queue_wakeup; 281361467Smw counter_u64_t queue_stop; 282361467Smw counter_u64_t llq_buffer_copy; 283320731Szbb}; 284320731Szbb 285320731Szbbstruct ena_stats_rx { 286320731Szbb counter_u64_t cnt; 287320731Szbb counter_u64_t bytes; 288320731Szbb counter_u64_t refil_partial; 289320731Szbb counter_u64_t bad_csum; 290343398Smw counter_u64_t mjum_alloc_fail; 291320731Szbb counter_u64_t mbuf_alloc_fail; 292320731Szbb counter_u64_t dma_mapping_err; 293320731Szbb counter_u64_t bad_desc_num; 294343397Smw counter_u64_t bad_req_id; 295343397Smw counter_u64_t empty_rx_ring; 296320731Szbb}; 297320731Szbb 298320731Szbbstruct ena_ring { 299343397Smw /* Holds the empty requests for TX/RX out of order completions */ 300343397Smw union { 301343397Smw uint16_t *free_tx_ids; 302343397Smw uint16_t *free_rx_ids; 303343397Smw }; 304320731Szbb struct ena_com_dev *ena_dev; 305320731Szbb struct ena_adapter *adapter; 306320731Szbb struct ena_com_io_cq *ena_com_io_cq; 307320731Szbb struct ena_com_io_sq *ena_com_io_sq; 308320731Szbb 309343398Smw uint16_t qid; 310343398Smw 311343398Smw /* Determines if device will use LLQ or normal mode for TX */ 312343398Smw enum ena_admin_placement_policy_type tx_mem_queue_type; 313361468Smw union { 314361468Smw /* The maximum length the driver can push to the device (For LLQ) */ 315361468Smw uint8_t tx_max_header_size; 316361468Smw /* The maximum (and default) mbuf size for the Rx descriptor. */ 317361468Smw uint16_t rx_mbuf_sz; 318320731Szbb 319361468Smw }; 320361468Smw 321361467Smw bool first_interrupt; 322361467Smw uint16_t no_interrupt_event_cnt; 323361467Smw 324320731Szbb struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 325343398Smw 326320731Szbb struct ena_que *que; 327320731Szbb struct lro_ctrl lro; 328320731Szbb 329320731Szbb uint16_t next_to_use; 330320731Szbb uint16_t next_to_clean; 331320731Szbb 332320731Szbb union { 333320731Szbb struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 334320731Szbb struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */ 335320731Szbb }; 336320731Szbb int ring_size; /* number of tx/rx_buffer_info's entries */ 337320731Szbb 338320731Szbb struct buf_ring *br; /* only for TX */ 339361467Smw uint32_t buf_ring_size; 340343398Smw 341320731Szbb struct mtx ring_mtx; 342320731Szbb char mtx_name[16]; 343343398Smw 344361467Smw struct { 345361467Smw struct task enqueue_task; 346361467Smw struct taskqueue *enqueue_tq; 347343397Smw }; 348320731Szbb 349320731Szbb union { 350320731Szbb struct ena_stats_tx tx_stats; 351320731Szbb struct ena_stats_rx rx_stats; 352320731Szbb }; 353320731Szbb 354361467Smw union { 355361467Smw int empty_rx_queue; 356361467Smw /* For Tx ring to indicate if it's running or not */ 357361467Smw bool running; 358361467Smw }; 359361467Smw 360361467Smw /* How many packets are sent in one Tx loop, used for doorbells */ 361361467Smw uint32_t acum_pkts; 362361467Smw 363361467Smw /* Used for LLQ */ 364361467Smw uint8_t *push_buf_intermediate_buf; 365361468Smw 366361468Smw#ifdef DEV_NETMAP 367361468Smw bool initialized; 368361468Smw#endif /* DEV_NETMAP */ 369320731Szbb} __aligned(CACHE_LINE_SIZE); 370320731Szbb 371320731Szbbstruct ena_stats_dev { 372320731Szbb counter_u64_t wd_expired; 373320731Szbb counter_u64_t interface_up; 374320731Szbb counter_u64_t interface_down; 375320731Szbb counter_u64_t admin_q_pause; 376320731Szbb}; 377320731Szbb 378320731Szbbstruct ena_hw_stats { 379343397Smw counter_u64_t rx_packets; 380343397Smw counter_u64_t tx_packets; 381320731Szbb 382343397Smw counter_u64_t rx_bytes; 383343397Smw counter_u64_t tx_bytes; 384320731Szbb 385343397Smw counter_u64_t rx_drops; 386361534Smw counter_u64_t tx_drops; 387320731Szbb}; 388320731Szbb 389320731Szbb/* Board specific private data structure */ 390320731Szbbstruct ena_adapter { 391320731Szbb struct ena_com_dev *ena_dev; 392320731Szbb 393320731Szbb /* OS defined structs */ 394320731Szbb if_t ifp; 395320731Szbb device_t pdev; 396320731Szbb struct ifmedia media; 397320731Szbb 398320731Szbb /* OS resources */ 399343398Smw struct resource *memory; 400343398Smw struct resource *registers; 401369337Smw struct resource *msix; 402369337Smw int msix_rid; 403320731Szbb 404361534Smw struct sx global_lock; 405320731Szbb 406320731Szbb /* MSI-X */ 407320731Szbb struct msix_entry *msix_entries; 408320731Szbb int msix_vecs; 409320731Szbb 410320731Szbb /* DMA tags used throughout the driver adapter for Tx and Rx */ 411320731Szbb bus_dma_tag_t tx_buf_tag; 412320731Szbb bus_dma_tag_t rx_buf_tag; 413320731Szbb int dma_width; 414320731Szbb 415343398Smw uint32_t max_mtu; 416343398Smw 417361534Smw uint32_t num_io_queues; 418361534Smw uint32_t max_num_io_queues; 419361534Smw 420361534Smw uint32_t requested_tx_ring_size; 421361534Smw uint32_t requested_rx_ring_size; 422361534Smw 423361534Smw uint32_t max_tx_ring_size; 424361534Smw uint32_t max_rx_ring_size; 425361534Smw 426320731Szbb uint16_t max_tx_sgl_size; 427320731Szbb uint16_t max_rx_sgl_size; 428320731Szbb 429320731Szbb uint32_t tx_offload_cap; 430320731Szbb 431361534Smw uint32_t buf_ring_size; 432320731Szbb 433320731Szbb /* RSS*/ 434343398Smw uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE]; 435320731Szbb 436320731Szbb uint8_t mac_addr[ETHER_ADDR_LEN]; 437320731Szbb /* mdio and phy*/ 438320731Szbb 439361467Smw ena_state_t flags; 440320731Szbb 441320731Szbb /* Queue will represent one TX and one RX ring */ 442320731Szbb struct ena_que que[ENA_MAX_NUM_IO_QUEUES] 443320731Szbb __aligned(CACHE_LINE_SIZE); 444320731Szbb 445320731Szbb /* TX */ 446320731Szbb struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 447320731Szbb __aligned(CACHE_LINE_SIZE); 448320731Szbb 449320731Szbb /* RX */ 450320731Szbb struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 451320731Szbb __aligned(CACHE_LINE_SIZE); 452320731Szbb 453320731Szbb struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 454320731Szbb 455320731Szbb /* Timer service */ 456320731Szbb struct callout timer_service; 457320731Szbb sbintime_t keep_alive_timestamp; 458320731Szbb uint32_t next_monitored_tx_qid; 459320731Szbb struct task reset_task; 460320731Szbb struct taskqueue *reset_tq; 461320731Szbb int wd_active; 462320731Szbb sbintime_t keep_alive_timeout; 463320731Szbb sbintime_t missing_tx_timeout; 464320731Szbb uint32_t missing_tx_max_queues; 465320731Szbb uint32_t missing_tx_threshold; 466361534Smw bool disable_meta_caching; 467320731Szbb 468368013Smw uint16_t eni_metrics_sample_interval; 469368013Smw uint16_t eni_metrics_sample_interval_cnt; 470368013Smw 471320731Szbb /* Statistics */ 472320731Szbb struct ena_stats_dev dev_stats; 473320731Szbb struct ena_hw_stats hw_stats; 474368013Smw struct ena_admin_eni_stats eni_metrics; 475343397Smw 476343397Smw enum ena_regs_reset_reason_types reset_reason; 477320731Szbb}; 478320731Szbb 479320731Szbb#define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx) 480320731Szbb#define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx) 481320731Szbb#define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx) 482320731Szbb 483361534Smw#define ENA_LOCK_INIT(adapter) \ 484361534Smw sx_init(&(adapter)->global_lock, "ENA global lock") 485361534Smw#define ENA_LOCK_DESTROY(adapter) sx_destroy(&(adapter)->global_lock) 486361534Smw#define ENA_LOCK_LOCK(adapter) sx_xlock(&(adapter)->global_lock) 487361534Smw#define ENA_LOCK_UNLOCK(adapter) sx_unlock(&(adapter)->global_lock) 488361534Smw 489361534Smw#define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 490361534Smw#define clamp_val(val, lo, hi) clamp_t(__typeof(val), val, lo, hi) 491361534Smw 492320731Szbbstatic inline int ena_mbuf_count(struct mbuf *mbuf) 493320731Szbb{ 494320731Szbb int count = 1; 495320731Szbb 496320731Szbb while ((mbuf = mbuf->m_next) != NULL) 497320731Szbb ++count; 498320731Szbb 499320731Szbb return count; 500320731Szbb} 501320731Szbb 502361534Smwint ena_up(struct ena_adapter *adapter); 503361534Smwvoid ena_down(struct ena_adapter *adapter); 504361534Smwint ena_restore_device(struct ena_adapter *adapter); 505361534Smwvoid ena_destroy_device(struct ena_adapter *adapter, bool graceful); 506361534Smwint ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num); 507361534Smwint ena_update_buf_ring_size(struct ena_adapter *adapter, 508361534Smw uint32_t new_buf_ring_size); 509361534Smwint ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size, 510361534Smw uint32_t new_rx_size); 511361534Smwint ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num); 512361468Smw 513361534Smwstatic inline void 514361534Smwena_trigger_reset(struct ena_adapter *adapter, 515361534Smw enum ena_regs_reset_reason_types reset_reason) 516361534Smw{ 517361534Smw if (likely(!ENA_FLAG_ISSET(ENA_FLAG_TRIGGER_RESET, adapter))) { 518361534Smw adapter->reset_reason = reset_reason; 519361534Smw ENA_FLAG_SET_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter); 520361534Smw } 521361534Smw} 522361534Smw 523320731Szbb#endif /* !(ENA_H) */ 524