ena.c revision 344575
1/*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/dev/ena/ena.c 344575 2019-02-26 12:26:25Z mw $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/kthread.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/smp.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47#include <sys/taskqueue.h> 48#include <sys/time.h> 49#include <sys/eventhandler.h> 50 51#include <machine/bus.h> 52#include <machine/resource.h> 53#include <machine/in_cksum.h> 54 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if.h> 58#include <net/if_var.h> 59#include <net/if_arp.h> 60#include <net/if_dl.h> 61#include <net/if_media.h> 62#include <net/rss_config.h> 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#include <netinet/in_rss.h> 67#include <netinet/in_systm.h> 68#include <netinet/in.h> 69#include <netinet/if_ether.h> 70#include <netinet/ip.h> 71#include <netinet/ip6.h> 72#include <netinet/tcp.h> 73#include <netinet/udp.h> 74 75#include <dev/pci/pcivar.h> 76#include <dev/pci/pcireg.h> 77 78#include "ena.h" 79#include "ena_sysctl.h" 80 81/********************************************************* 82 * Function prototypes 83 *********************************************************/ 84static int ena_probe(device_t); 85static void ena_intr_msix_mgmnt(void *); 86static int ena_allocate_pci_resources(struct ena_adapter*); 87static void ena_free_pci_resources(struct ena_adapter *); 88static int ena_change_mtu(if_t, int); 89static inline void ena_alloc_counters(counter_u64_t *, int); 90static inline void ena_free_counters(counter_u64_t *, int); 91static inline void ena_reset_counters(counter_u64_t *, int); 92static void ena_init_io_rings_common(struct ena_adapter *, 93 struct ena_ring *, uint16_t); 94static void ena_init_io_rings(struct ena_adapter *); 95static void ena_free_io_ring_resources(struct ena_adapter *, unsigned int); 96static void ena_free_all_io_rings_resources(struct ena_adapter *); 97static int ena_setup_tx_dma_tag(struct ena_adapter *); 98static int ena_free_tx_dma_tag(struct ena_adapter *); 99static int ena_setup_rx_dma_tag(struct ena_adapter *); 100static int ena_free_rx_dma_tag(struct ena_adapter *); 101static int ena_setup_tx_resources(struct ena_adapter *, int); 102static void ena_free_tx_resources(struct ena_adapter *, int); 103static int ena_setup_all_tx_resources(struct ena_adapter *); 104static void ena_free_all_tx_resources(struct ena_adapter *); 105static inline int validate_rx_req_id(struct ena_ring *, uint16_t); 106static int ena_setup_rx_resources(struct ena_adapter *, unsigned int); 107static void ena_free_rx_resources(struct ena_adapter *, unsigned int); 108static int ena_setup_all_rx_resources(struct ena_adapter *); 109static void ena_free_all_rx_resources(struct ena_adapter *); 110static inline int ena_alloc_rx_mbuf(struct ena_adapter *, struct ena_ring *, 111 struct ena_rx_buffer *); 112static void ena_free_rx_mbuf(struct ena_adapter *, struct ena_ring *, 113 struct ena_rx_buffer *); 114static int ena_refill_rx_bufs(struct ena_ring *, uint32_t); 115static void ena_free_rx_bufs(struct ena_adapter *, unsigned int); 116static void ena_refill_all_rx_bufs(struct ena_adapter *); 117static void ena_free_all_rx_bufs(struct ena_adapter *); 118static void ena_free_tx_bufs(struct ena_adapter *, unsigned int); 119static void ena_free_all_tx_bufs(struct ena_adapter *); 120static void ena_destroy_all_tx_queues(struct ena_adapter *); 121static void ena_destroy_all_rx_queues(struct ena_adapter *); 122static void ena_destroy_all_io_queues(struct ena_adapter *); 123static int ena_create_io_queues(struct ena_adapter *); 124static int ena_tx_cleanup(struct ena_ring *); 125static void ena_deferred_rx_cleanup(void *, int); 126static int ena_rx_cleanup(struct ena_ring *); 127static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 128static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 129 struct mbuf *); 130static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 131 struct ena_com_rx_ctx *, uint16_t *); 132static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 133 struct mbuf *); 134static void ena_handle_msix(void *); 135static int ena_enable_msix(struct ena_adapter *); 136static void ena_setup_mgmnt_intr(struct ena_adapter *); 137static void ena_setup_io_intr(struct ena_adapter *); 138static int ena_request_mgmnt_irq(struct ena_adapter *); 139static int ena_request_io_irq(struct ena_adapter *); 140static void ena_free_mgmnt_irq(struct ena_adapter *); 141static void ena_free_io_irq(struct ena_adapter *); 142static void ena_free_irqs(struct ena_adapter*); 143static void ena_disable_msix(struct ena_adapter *); 144static void ena_unmask_all_io_irqs(struct ena_adapter *); 145static int ena_rss_configure(struct ena_adapter *); 146static int ena_up_complete(struct ena_adapter *); 147static int ena_up(struct ena_adapter *); 148static void ena_down(struct ena_adapter *); 149static uint64_t ena_get_counter(if_t, ift_counter); 150static int ena_media_change(if_t); 151static void ena_media_status(if_t, struct ifmediareq *); 152static void ena_init(void *); 153static int ena_ioctl(if_t, u_long, caddr_t); 154static int ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *); 155static void ena_update_host_info(struct ena_admin_host_info *, if_t); 156static void ena_update_hwassist(struct ena_adapter *); 157static int ena_setup_ifnet(device_t, struct ena_adapter *, 158 struct ena_com_dev_get_features_ctx *); 159static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *); 160static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 161 struct mbuf **mbuf); 162static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 163static void ena_start_xmit(struct ena_ring *); 164static int ena_mq_start(if_t, struct mbuf *); 165static void ena_deferred_mq_start(void *, int); 166static void ena_qflush(if_t); 167static int ena_calc_io_queue_num(struct ena_adapter *, 168 struct ena_com_dev_get_features_ctx *); 169static int ena_calc_queue_size(struct ena_adapter *, uint16_t *, 170 uint16_t *, struct ena_com_dev_get_features_ctx *); 171static int ena_rss_init_default(struct ena_adapter *); 172static void ena_rss_init_default_deferred(void *); 173static void ena_config_host_info(struct ena_com_dev *); 174static int ena_attach(device_t); 175static int ena_detach(device_t); 176static int ena_device_init(struct ena_adapter *, device_t, 177 struct ena_com_dev_get_features_ctx *, int *); 178static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *, 179 int); 180static void ena_update_on_link_change(void *, struct ena_admin_aenq_entry *); 181static void unimplemented_aenq_handler(void *, 182 struct ena_admin_aenq_entry *); 183static void ena_timer_service(void *); 184 185static char ena_version[] = DEVICE_NAME DRV_MODULE_NAME " v" DRV_MODULE_VERSION; 186 187static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD, 0, "ENA driver parameters"); 188 189/* 190 * Tuneable number of buffers in the buf-ring (drbr) 191 */ 192static int ena_buf_ring_size = 4096; 193SYSCTL_INT(_hw_ena, OID_AUTO, buf_ring_size, CTLFLAG_RWTUN, 194 &ena_buf_ring_size, 0, "Size of the bufring"); 195 196/* 197 * Logging level for changing verbosity of the output 198 */ 199int ena_log_level = ENA_ALERT | ENA_WARNING; 200SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, 201 &ena_log_level, 0, "Logging level indicating verbosity of the logs"); 202 203static ena_vendor_info_t ena_vendor_info_array[] = { 204 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_PF, 0}, 205 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_PF, 0}, 206 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_VF, 0}, 207 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_VF, 0}, 208 /* Last entry */ 209 { 0, 0, 0 } 210}; 211 212/* 213 * Contains pointers to event handlers, e.g. link state chage. 214 */ 215static struct ena_aenq_handlers aenq_handlers; 216 217void 218ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 219{ 220 if (error != 0) 221 return; 222 *(bus_addr_t *) arg = segs[0].ds_addr; 223} 224 225int 226ena_dma_alloc(device_t dmadev, bus_size_t size, 227 ena_mem_handle_t *dma , int mapflags) 228{ 229 struct ena_adapter* adapter = device_get_softc(dmadev); 230 uint32_t maxsize; 231 uint64_t dma_space_addr; 232 int error; 233 234 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; 235 236 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); 237 if (unlikely(dma_space_addr == 0)) 238 dma_space_addr = BUS_SPACE_MAXADDR; 239 240 error = bus_dma_tag_create(bus_get_dma_tag(dmadev), /* parent */ 241 8, 0, /* alignment, bounds */ 242 dma_space_addr, /* lowaddr of exclusion window */ 243 BUS_SPACE_MAXADDR,/* highaddr of exclusion window */ 244 NULL, NULL, /* filter, filterarg */ 245 maxsize, /* maxsize */ 246 1, /* nsegments */ 247 maxsize, /* maxsegsize */ 248 BUS_DMA_ALLOCNOW, /* flags */ 249 NULL, /* lockfunc */ 250 NULL, /* lockarg */ 251 &dma->tag); 252 if (unlikely(error != 0)) { 253 ena_trace(ENA_ALERT, "bus_dma_tag_create failed: %d\n", error); 254 goto fail_tag; 255 } 256 257 error = bus_dmamem_alloc(dma->tag, (void**) &dma->vaddr, 258 BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->map); 259 if (unlikely(error != 0)) { 260 ena_trace(ENA_ALERT, "bus_dmamem_alloc(%ju) failed: %d\n", 261 (uintmax_t)size, error); 262 goto fail_map_create; 263 } 264 265 dma->paddr = 0; 266 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 267 size, ena_dmamap_callback, &dma->paddr, mapflags); 268 if (unlikely((error != 0) || (dma->paddr == 0))) { 269 ena_trace(ENA_ALERT, ": bus_dmamap_load failed: %d\n", error); 270 goto fail_map_load; 271 } 272 273 return (0); 274 275fail_map_load: 276 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 277fail_map_create: 278 bus_dma_tag_destroy(dma->tag); 279fail_tag: 280 dma->tag = NULL; 281 282 return (error); 283} 284 285static int 286ena_allocate_pci_resources(struct ena_adapter* adapter) 287{ 288 device_t pdev = adapter->pdev; 289 int rid; 290 291 rid = PCIR_BAR(ENA_REG_BAR); 292 adapter->memory = NULL; 293 adapter->registers = bus_alloc_resource_any(pdev, SYS_RES_MEMORY, 294 &rid, RF_ACTIVE); 295 if (unlikely(adapter->registers == NULL)) { 296 device_printf(pdev, "Unable to allocate bus resource: " 297 "registers\n"); 298 return (ENXIO); 299 } 300 301 return (0); 302} 303 304static void 305ena_free_pci_resources(struct ena_adapter *adapter) 306{ 307 device_t pdev = adapter->pdev; 308 309 if (adapter->memory != NULL) { 310 bus_release_resource(pdev, SYS_RES_MEMORY, 311 PCIR_BAR(ENA_MEM_BAR), adapter->memory); 312 } 313 314 if (adapter->registers != NULL) { 315 bus_release_resource(pdev, SYS_RES_MEMORY, 316 PCIR_BAR(ENA_REG_BAR), adapter->registers); 317 } 318} 319 320static int 321ena_probe(device_t dev) 322{ 323 ena_vendor_info_t *ent; 324 char adapter_name[60]; 325 uint16_t pci_vendor_id = 0; 326 uint16_t pci_device_id = 0; 327 328 pci_vendor_id = pci_get_vendor(dev); 329 pci_device_id = pci_get_device(dev); 330 331 ent = ena_vendor_info_array; 332 while (ent->vendor_id != 0) { 333 if ((pci_vendor_id == ent->vendor_id) && 334 (pci_device_id == ent->device_id)) { 335 ena_trace(ENA_DBG, "vendor=%x device=%x ", 336 pci_vendor_id, pci_device_id); 337 338 sprintf(adapter_name, DEVICE_DESC); 339 device_set_desc_copy(dev, adapter_name); 340 return (BUS_PROBE_DEFAULT); 341 } 342 343 ent++; 344 345 } 346 347 return (ENXIO); 348} 349 350static int 351ena_change_mtu(if_t ifp, int new_mtu) 352{ 353 struct ena_adapter *adapter = if_getsoftc(ifp); 354 int rc; 355 356 if ((new_mtu > adapter->max_mtu) || (new_mtu < ENA_MIN_MTU)) { 357 device_printf(adapter->pdev, "Invalid MTU setting. " 358 "new_mtu: %d max mtu: %d min mtu: %d\n", 359 new_mtu, adapter->max_mtu, ENA_MIN_MTU); 360 return (EINVAL); 361 } 362 363 rc = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 364 if (likely(rc == 0)) { 365 ena_trace(ENA_DBG, "set MTU to %d\n", new_mtu); 366 if_setmtu(ifp, new_mtu); 367 } else { 368 device_printf(adapter->pdev, "Failed to set MTU to %d\n", 369 new_mtu); 370 } 371 372 return (rc); 373} 374 375static inline void 376ena_alloc_counters(counter_u64_t *begin, int size) 377{ 378 counter_u64_t *end = (counter_u64_t *)((char *)begin + size); 379 380 for (; begin < end; ++begin) 381 *begin = counter_u64_alloc(M_WAITOK); 382} 383 384static inline void 385ena_free_counters(counter_u64_t *begin, int size) 386{ 387 counter_u64_t *end = (counter_u64_t *)((char *)begin + size); 388 389 for (; begin < end; ++begin) 390 counter_u64_free(*begin); 391} 392 393static inline void 394ena_reset_counters(counter_u64_t *begin, int size) 395{ 396 counter_u64_t *end = (counter_u64_t *)((char *)begin + size); 397 398 for (; begin < end; ++begin) 399 counter_u64_zero(*begin); 400} 401 402static void 403ena_init_io_rings_common(struct ena_adapter *adapter, struct ena_ring *ring, 404 uint16_t qid) 405{ 406 407 ring->qid = qid; 408 ring->adapter = adapter; 409 ring->ena_dev = adapter->ena_dev; 410} 411 412static void 413ena_init_io_rings(struct ena_adapter *adapter) 414{ 415 struct ena_com_dev *ena_dev; 416 struct ena_ring *txr, *rxr; 417 struct ena_que *que; 418 int i; 419 420 ena_dev = adapter->ena_dev; 421 422 for (i = 0; i < adapter->num_queues; i++) { 423 txr = &adapter->tx_ring[i]; 424 rxr = &adapter->rx_ring[i]; 425 426 /* TX/RX common ring state */ 427 ena_init_io_rings_common(adapter, txr, i); 428 ena_init_io_rings_common(adapter, rxr, i); 429 430 /* TX specific ring state */ 431 txr->ring_size = adapter->tx_ring_size; 432 txr->tx_max_header_size = ena_dev->tx_max_header_size; 433 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 434 txr->smoothed_interval = 435 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 436 437 /* Allocate a buf ring */ 438 txr->br = buf_ring_alloc(ena_buf_ring_size, M_DEVBUF, 439 M_WAITOK, &txr->ring_mtx); 440 441 /* Alloc TX statistics. */ 442 ena_alloc_counters((counter_u64_t *)&txr->tx_stats, 443 sizeof(txr->tx_stats)); 444 445 /* RX specific ring state */ 446 rxr->ring_size = adapter->rx_ring_size; 447 rxr->smoothed_interval = 448 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 449 450 /* Alloc RX statistics. */ 451 ena_alloc_counters((counter_u64_t *)&rxr->rx_stats, 452 sizeof(rxr->rx_stats)); 453 454 /* Initialize locks */ 455 snprintf(txr->mtx_name, nitems(txr->mtx_name), "%s:tx(%d)", 456 device_get_nameunit(adapter->pdev), i); 457 snprintf(rxr->mtx_name, nitems(rxr->mtx_name), "%s:rx(%d)", 458 device_get_nameunit(adapter->pdev), i); 459 460 mtx_init(&txr->ring_mtx, txr->mtx_name, NULL, MTX_DEF); 461 mtx_init(&rxr->ring_mtx, rxr->mtx_name, NULL, MTX_DEF); 462 463 que = &adapter->que[i]; 464 que->adapter = adapter; 465 que->id = i; 466 que->tx_ring = txr; 467 que->rx_ring = rxr; 468 469 txr->que = que; 470 rxr->que = que; 471 472 rxr->empty_rx_queue = 0; 473 } 474} 475 476static void 477ena_free_io_ring_resources(struct ena_adapter *adapter, unsigned int qid) 478{ 479 struct ena_ring *txr = &adapter->tx_ring[qid]; 480 struct ena_ring *rxr = &adapter->rx_ring[qid]; 481 482 ena_free_counters((counter_u64_t *)&txr->tx_stats, 483 sizeof(txr->tx_stats)); 484 ena_free_counters((counter_u64_t *)&rxr->rx_stats, 485 sizeof(rxr->rx_stats)); 486 487 ENA_RING_MTX_LOCK(txr); 488 drbr_free(txr->br, M_DEVBUF); 489 ENA_RING_MTX_UNLOCK(txr); 490 491 mtx_destroy(&txr->ring_mtx); 492 mtx_destroy(&rxr->ring_mtx); 493} 494 495static void 496ena_free_all_io_rings_resources(struct ena_adapter *adapter) 497{ 498 int i; 499 500 for (i = 0; i < adapter->num_queues; i++) 501 ena_free_io_ring_resources(adapter, i); 502 503} 504 505static int 506ena_setup_tx_dma_tag(struct ena_adapter *adapter) 507{ 508 int ret; 509 510 /* Create DMA tag for Tx buffers */ 511 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), 512 1, 0, /* alignment, bounds */ 513 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 514 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 515 NULL, NULL, /* filter, filterarg */ 516 ENA_TSO_MAXSIZE, /* maxsize */ 517 adapter->max_tx_sgl_size - 1, /* nsegments */ 518 ENA_TSO_MAXSIZE, /* maxsegsize */ 519 0, /* flags */ 520 NULL, /* lockfunc */ 521 NULL, /* lockfuncarg */ 522 &adapter->tx_buf_tag); 523 524 return (ret); 525} 526 527static int 528ena_free_tx_dma_tag(struct ena_adapter *adapter) 529{ 530 int ret; 531 532 ret = bus_dma_tag_destroy(adapter->tx_buf_tag); 533 534 if (likely(ret == 0)) 535 adapter->tx_buf_tag = NULL; 536 537 return (ret); 538} 539 540static int 541ena_setup_rx_dma_tag(struct ena_adapter *adapter) 542{ 543 int ret; 544 545 /* Create DMA tag for Rx buffers*/ 546 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */ 547 1, 0, /* alignment, bounds */ 548 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 549 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 550 NULL, NULL, /* filter, filterarg */ 551 MJUM16BYTES, /* maxsize */ 552 adapter->max_rx_sgl_size, /* nsegments */ 553 MJUM16BYTES, /* maxsegsize */ 554 0, /* flags */ 555 NULL, /* lockfunc */ 556 NULL, /* lockarg */ 557 &adapter->rx_buf_tag); 558 559 return (ret); 560} 561 562static int 563ena_free_rx_dma_tag(struct ena_adapter *adapter) 564{ 565 int ret; 566 567 ret = bus_dma_tag_destroy(adapter->rx_buf_tag); 568 569 if (likely(ret == 0)) 570 adapter->rx_buf_tag = NULL; 571 572 return (ret); 573} 574 575/** 576 * ena_setup_tx_resources - allocate Tx resources (Descriptors) 577 * @adapter: network interface device structure 578 * @qid: queue index 579 * 580 * Returns 0 on success, otherwise on failure. 581 **/ 582static int 583ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 584{ 585 struct ena_que *que = &adapter->que[qid]; 586 struct ena_ring *tx_ring = que->tx_ring; 587 int size, i, err; 588#ifdef RSS 589 cpuset_t cpu_mask; 590#endif 591 592 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 593 594 tx_ring->tx_buffer_info = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 595 if (unlikely(tx_ring->tx_buffer_info == NULL)) 596 return (ENOMEM); 597 598 size = sizeof(uint16_t) * tx_ring->ring_size; 599 tx_ring->free_tx_ids = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 600 if (unlikely(tx_ring->free_tx_ids == NULL)) 601 goto err_buf_info_free; 602 603 /* Req id stack for TX OOO completions */ 604 for (i = 0; i < tx_ring->ring_size; i++) 605 tx_ring->free_tx_ids[i] = i; 606 607 /* Reset TX statistics. */ 608 ena_reset_counters((counter_u64_t *)&tx_ring->tx_stats, 609 sizeof(tx_ring->tx_stats)); 610 611 tx_ring->next_to_use = 0; 612 tx_ring->next_to_clean = 0; 613 614 /* Make sure that drbr is empty */ 615 ENA_RING_MTX_LOCK(tx_ring); 616 drbr_flush(adapter->ifp, tx_ring->br); 617 ENA_RING_MTX_UNLOCK(tx_ring); 618 619 /* ... and create the buffer DMA maps */ 620 for (i = 0; i < tx_ring->ring_size; i++) { 621 err = bus_dmamap_create(adapter->tx_buf_tag, 0, 622 &tx_ring->tx_buffer_info[i].map); 623 if (unlikely(err != 0)) { 624 ena_trace(ENA_ALERT, 625 "Unable to create Tx DMA map for buffer %d\n", i); 626 goto err_buf_info_unmap; 627 } 628 } 629 630 /* Allocate taskqueues */ 631 TASK_INIT(&tx_ring->enqueue_task, 0, ena_deferred_mq_start, tx_ring); 632 tx_ring->enqueue_tq = taskqueue_create_fast("ena_tx_enque", M_NOWAIT, 633 taskqueue_thread_enqueue, &tx_ring->enqueue_tq); 634 if (unlikely(tx_ring->enqueue_tq == NULL)) { 635 ena_trace(ENA_ALERT, 636 "Unable to create taskqueue for enqueue task\n"); 637 i = tx_ring->ring_size; 638 goto err_buf_info_unmap; 639 } 640 641 /* RSS set cpu for thread */ 642#ifdef RSS 643 CPU_SETOF(que->cpu, &cpu_mask); 644 taskqueue_start_threads_cpuset(&tx_ring->enqueue_tq, 1, PI_NET, 645 &cpu_mask, "%s tx_ring enq (bucket %d)", 646 device_get_nameunit(adapter->pdev), que->cpu); 647#else /* RSS */ 648 taskqueue_start_threads(&tx_ring->enqueue_tq, 1, PI_NET, 649 "%s txeq %d", device_get_nameunit(adapter->pdev), que->cpu); 650#endif /* RSS */ 651 652 return (0); 653 654err_buf_info_unmap: 655 while (i--) { 656 bus_dmamap_destroy(adapter->tx_buf_tag, 657 tx_ring->tx_buffer_info[i].map); 658 } 659 free(tx_ring->free_tx_ids, M_DEVBUF); 660 tx_ring->free_tx_ids = NULL; 661err_buf_info_free: 662 free(tx_ring->tx_buffer_info, M_DEVBUF); 663 tx_ring->tx_buffer_info = NULL; 664 665 return (ENOMEM); 666} 667 668/** 669 * ena_free_tx_resources - Free Tx Resources per Queue 670 * @adapter: network interface device structure 671 * @qid: queue index 672 * 673 * Free all transmit software resources 674 **/ 675static void 676ena_free_tx_resources(struct ena_adapter *adapter, int qid) 677{ 678 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 679 680 while (taskqueue_cancel(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 681 NULL)) 682 taskqueue_drain(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 683 684 taskqueue_free(tx_ring->enqueue_tq); 685 686 ENA_RING_MTX_LOCK(tx_ring); 687 /* Flush buffer ring, */ 688 drbr_flush(adapter->ifp, tx_ring->br); 689 690 /* Free buffer DMA maps, */ 691 for (int i = 0; i < tx_ring->ring_size; i++) { 692 m_freem(tx_ring->tx_buffer_info[i].mbuf); 693 tx_ring->tx_buffer_info[i].mbuf = NULL; 694 bus_dmamap_unload(adapter->tx_buf_tag, 695 tx_ring->tx_buffer_info[i].map); 696 bus_dmamap_destroy(adapter->tx_buf_tag, 697 tx_ring->tx_buffer_info[i].map); 698 } 699 ENA_RING_MTX_UNLOCK(tx_ring); 700 701 /* And free allocated memory. */ 702 free(tx_ring->tx_buffer_info, M_DEVBUF); 703 tx_ring->tx_buffer_info = NULL; 704 705 free(tx_ring->free_tx_ids, M_DEVBUF); 706 tx_ring->free_tx_ids = NULL; 707} 708 709/** 710 * ena_setup_all_tx_resources - allocate all queues Tx resources 711 * @adapter: network interface device structure 712 * 713 * Returns 0 on success, otherwise on failure. 714 **/ 715static int 716ena_setup_all_tx_resources(struct ena_adapter *adapter) 717{ 718 int i, rc; 719 720 for (i = 0; i < adapter->num_queues; i++) { 721 rc = ena_setup_tx_resources(adapter, i); 722 if (rc != 0) { 723 device_printf(adapter->pdev, 724 "Allocation for Tx Queue %u failed\n", i); 725 goto err_setup_tx; 726 } 727 } 728 729 return (0); 730 731err_setup_tx: 732 /* Rewind the index freeing the rings as we go */ 733 while (i--) 734 ena_free_tx_resources(adapter, i); 735 return (rc); 736} 737 738/** 739 * ena_free_all_tx_resources - Free Tx Resources for All Queues 740 * @adapter: network interface device structure 741 * 742 * Free all transmit software resources 743 **/ 744static void 745ena_free_all_tx_resources(struct ena_adapter *adapter) 746{ 747 int i; 748 749 for (i = 0; i < adapter->num_queues; i++) 750 ena_free_tx_resources(adapter, i); 751} 752 753static inline int 754validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 755{ 756 if (likely(req_id < rx_ring->ring_size)) 757 return (0); 758 759 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 760 req_id); 761 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 762 763 /* Trigger device reset */ 764 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 765 rx_ring->adapter->trigger_reset = true; 766 767 return (EFAULT); 768} 769 770/** 771 * ena_setup_rx_resources - allocate Rx resources (Descriptors) 772 * @adapter: network interface device structure 773 * @qid: queue index 774 * 775 * Returns 0 on success, otherwise on failure. 776 **/ 777static int 778ena_setup_rx_resources(struct ena_adapter *adapter, unsigned int qid) 779{ 780 struct ena_que *que = &adapter->que[qid]; 781 struct ena_ring *rx_ring = que->rx_ring; 782 int size, err, i; 783#ifdef RSS 784 cpuset_t cpu_mask; 785#endif 786 787 size = sizeof(struct ena_rx_buffer) * rx_ring->ring_size; 788 789 /* 790 * Alloc extra element so in rx path 791 * we can always prefetch rx_info + 1 792 */ 793 size += sizeof(struct ena_rx_buffer); 794 795 rx_ring->rx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 796 797 size = sizeof(uint16_t) * rx_ring->ring_size; 798 rx_ring->free_rx_ids = malloc(size, M_DEVBUF, M_WAITOK); 799 800 for (i = 0; i < rx_ring->ring_size; i++) 801 rx_ring->free_rx_ids[i] = i; 802 803 /* Reset RX statistics. */ 804 ena_reset_counters((counter_u64_t *)&rx_ring->rx_stats, 805 sizeof(rx_ring->rx_stats)); 806 807 rx_ring->next_to_clean = 0; 808 rx_ring->next_to_use = 0; 809 810 /* ... and create the buffer DMA maps */ 811 for (i = 0; i < rx_ring->ring_size; i++) { 812 err = bus_dmamap_create(adapter->rx_buf_tag, 0, 813 &(rx_ring->rx_buffer_info[i].map)); 814 if (err != 0) { 815 ena_trace(ENA_ALERT, 816 "Unable to create Rx DMA map for buffer %d\n", i); 817 goto err_buf_info_unmap; 818 } 819 } 820 821 /* Create LRO for the ring */ 822 if ((adapter->ifp->if_capenable & IFCAP_LRO) != 0) { 823 int err = tcp_lro_init(&rx_ring->lro); 824 if (err != 0) { 825 device_printf(adapter->pdev, 826 "LRO[%d] Initialization failed!\n", qid); 827 } else { 828 ena_trace(ENA_INFO, 829 "RX Soft LRO[%d] Initialized\n", qid); 830 rx_ring->lro.ifp = adapter->ifp; 831 } 832 } 833 834 /* Allocate taskqueues */ 835 TASK_INIT(&rx_ring->cmpl_task, 0, ena_deferred_rx_cleanup, rx_ring); 836 rx_ring->cmpl_tq = taskqueue_create_fast("ena RX completion", M_WAITOK, 837 taskqueue_thread_enqueue, &rx_ring->cmpl_tq); 838 839 /* RSS set cpu for thread */ 840#ifdef RSS 841 CPU_SETOF(que->cpu, &cpu_mask); 842 taskqueue_start_threads_cpuset(&rx_ring->cmpl_tq, 1, PI_NET, &cpu_mask, 843 "%s rx_ring cmpl (bucket %d)", 844 device_get_nameunit(adapter->pdev), que->cpu); 845#else 846 taskqueue_start_threads(&rx_ring->cmpl_tq, 1, PI_NET, 847 "%s rx_ring cmpl %d", device_get_nameunit(adapter->pdev), que->cpu); 848#endif 849 850 return (0); 851 852err_buf_info_unmap: 853 while (i--) { 854 bus_dmamap_destroy(adapter->rx_buf_tag, 855 rx_ring->rx_buffer_info[i].map); 856 } 857 858 free(rx_ring->free_rx_ids, M_DEVBUF); 859 rx_ring->free_rx_ids = NULL; 860 free(rx_ring->rx_buffer_info, M_DEVBUF); 861 rx_ring->rx_buffer_info = NULL; 862 return (ENOMEM); 863} 864 865/** 866 * ena_free_rx_resources - Free Rx Resources 867 * @adapter: network interface device structure 868 * @qid: queue index 869 * 870 * Free all receive software resources 871 **/ 872static void 873ena_free_rx_resources(struct ena_adapter *adapter, unsigned int qid) 874{ 875 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 876 877 while (taskqueue_cancel(rx_ring->cmpl_tq, &rx_ring->cmpl_task, NULL) != 0) 878 taskqueue_drain(rx_ring->cmpl_tq, &rx_ring->cmpl_task); 879 880 taskqueue_free(rx_ring->cmpl_tq); 881 882 /* Free buffer DMA maps, */ 883 for (int i = 0; i < rx_ring->ring_size; i++) { 884 m_freem(rx_ring->rx_buffer_info[i].mbuf); 885 rx_ring->rx_buffer_info[i].mbuf = NULL; 886 bus_dmamap_unload(adapter->rx_buf_tag, 887 rx_ring->rx_buffer_info[i].map); 888 bus_dmamap_destroy(adapter->rx_buf_tag, 889 rx_ring->rx_buffer_info[i].map); 890 } 891 892 /* free LRO resources, */ 893 tcp_lro_free(&rx_ring->lro); 894 895 /* free allocated memory */ 896 free(rx_ring->rx_buffer_info, M_DEVBUF); 897 rx_ring->rx_buffer_info = NULL; 898 899 free(rx_ring->free_rx_ids, M_DEVBUF); 900 rx_ring->free_rx_ids = NULL; 901} 902 903/** 904 * ena_setup_all_rx_resources - allocate all queues Rx resources 905 * @adapter: network interface device structure 906 * 907 * Returns 0 on success, otherwise on failure. 908 **/ 909static int 910ena_setup_all_rx_resources(struct ena_adapter *adapter) 911{ 912 int i, rc = 0; 913 914 for (i = 0; i < adapter->num_queues; i++) { 915 rc = ena_setup_rx_resources(adapter, i); 916 if (rc != 0) { 917 device_printf(adapter->pdev, 918 "Allocation for Rx Queue %u failed\n", i); 919 goto err_setup_rx; 920 } 921 } 922 return (0); 923 924err_setup_rx: 925 /* rewind the index freeing the rings as we go */ 926 while (i--) 927 ena_free_rx_resources(adapter, i); 928 return (rc); 929} 930 931/** 932 * ena_free_all_rx_resources - Free Rx resources for all queues 933 * @adapter: network interface device structure 934 * 935 * Free all receive software resources 936 **/ 937static void 938ena_free_all_rx_resources(struct ena_adapter *adapter) 939{ 940 int i; 941 942 for (i = 0; i < adapter->num_queues; i++) 943 ena_free_rx_resources(adapter, i); 944} 945 946static inline int 947ena_alloc_rx_mbuf(struct ena_adapter *adapter, 948 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 949{ 950 struct ena_com_buf *ena_buf; 951 bus_dma_segment_t segs[1]; 952 int nsegs, error; 953 int mlen; 954 955 /* if previous allocated frag is not used */ 956 if (unlikely(rx_info->mbuf != NULL)) 957 return (0); 958 959 /* Get mbuf using UMA allocator */ 960 rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); 961 962 if (unlikely(rx_info->mbuf == NULL)) { 963 counter_u64_add(rx_ring->rx_stats.mjum_alloc_fail, 1); 964 rx_info->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 965 if (unlikely(rx_info->mbuf == NULL)) { 966 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 967 return (ENOMEM); 968 } 969 mlen = MCLBYTES; 970 } else { 971 mlen = MJUM16BYTES; 972 } 973 /* Set mbuf length*/ 974 rx_info->mbuf->m_pkthdr.len = rx_info->mbuf->m_len = mlen; 975 976 /* Map packets for DMA */ 977 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 978 "Using tag %p for buffers' DMA mapping, mbuf %p len: %d", 979 adapter->rx_buf_tag,rx_info->mbuf, rx_info->mbuf->m_len); 980 error = bus_dmamap_load_mbuf_sg(adapter->rx_buf_tag, rx_info->map, 981 rx_info->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 982 if (unlikely((error != 0) || (nsegs != 1))) { 983 ena_trace(ENA_WARNING, "failed to map mbuf, error: %d, " 984 "nsegs: %d\n", error, nsegs); 985 counter_u64_add(rx_ring->rx_stats.dma_mapping_err, 1); 986 goto exit; 987 988 } 989 990 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map, BUS_DMASYNC_PREREAD); 991 992 ena_buf = &rx_info->ena_buf; 993 ena_buf->paddr = segs[0].ds_addr; 994 ena_buf->len = mlen; 995 996 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 997 "ALLOC RX BUF: mbuf %p, rx_info %p, len %d, paddr %#jx\n", 998 rx_info->mbuf, rx_info,ena_buf->len, (uintmax_t)ena_buf->paddr); 999 1000 return (0); 1001 1002exit: 1003 m_freem(rx_info->mbuf); 1004 rx_info->mbuf = NULL; 1005 return (EFAULT); 1006} 1007 1008static void 1009ena_free_rx_mbuf(struct ena_adapter *adapter, struct ena_ring *rx_ring, 1010 struct ena_rx_buffer *rx_info) 1011{ 1012 1013 if (rx_info->mbuf == NULL) { 1014 ena_trace(ENA_WARNING, "Trying to free unallocated buffer\n"); 1015 return; 1016 } 1017 1018 bus_dmamap_unload(adapter->rx_buf_tag, rx_info->map); 1019 m_freem(rx_info->mbuf); 1020 rx_info->mbuf = NULL; 1021} 1022 1023/** 1024 * ena_refill_rx_bufs - Refills ring with descriptors 1025 * @rx_ring: the ring which we want to feed with free descriptors 1026 * @num: number of descriptors to refill 1027 * Refills the ring with newly allocated DMA-mapped mbufs for receiving 1028 **/ 1029static int 1030ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num) 1031{ 1032 struct ena_adapter *adapter = rx_ring->adapter; 1033 uint16_t next_to_use, req_id; 1034 uint32_t i; 1035 int rc; 1036 1037 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, "refill qid: %d", 1038 rx_ring->qid); 1039 1040 next_to_use = rx_ring->next_to_use; 1041 1042 for (i = 0; i < num; i++) { 1043 struct ena_rx_buffer *rx_info; 1044 1045 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, 1046 "RX buffer - next to use: %d", next_to_use); 1047 1048 req_id = rx_ring->free_rx_ids[next_to_use]; 1049 rx_info = &rx_ring->rx_buffer_info[req_id]; 1050 1051 rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info); 1052 if (unlikely(rc != 0)) { 1053 ena_trace(ENA_WARNING, 1054 "failed to alloc buffer for rx queue %d\n", 1055 rx_ring->qid); 1056 break; 1057 } 1058 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 1059 &rx_info->ena_buf, req_id); 1060 if (unlikely(rc != 0)) { 1061 ena_trace(ENA_WARNING, 1062 "failed to add buffer for rx queue %d\n", 1063 rx_ring->qid); 1064 break; 1065 } 1066 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 1067 rx_ring->ring_size); 1068 } 1069 1070 if (unlikely(i < num)) { 1071 counter_u64_add(rx_ring->rx_stats.refil_partial, 1); 1072 ena_trace(ENA_WARNING, 1073 "refilled rx qid %d with only %d mbufs (from %d)\n", 1074 rx_ring->qid, i, num); 1075 } 1076 1077 if (likely(i != 0)) { 1078 wmb(); 1079 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 1080 } 1081 rx_ring->next_to_use = next_to_use; 1082 return (i); 1083} 1084 1085static void 1086ena_free_rx_bufs(struct ena_adapter *adapter, unsigned int qid) 1087{ 1088 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 1089 unsigned int i; 1090 1091 for (i = 0; i < rx_ring->ring_size; i++) { 1092 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 1093 1094 if (rx_info->mbuf != NULL) 1095 ena_free_rx_mbuf(adapter, rx_ring, rx_info); 1096 } 1097} 1098 1099/** 1100 * ena_refill_all_rx_bufs - allocate all queues Rx buffers 1101 * @adapter: network interface device structure 1102 * 1103 */ 1104static void 1105ena_refill_all_rx_bufs(struct ena_adapter *adapter) 1106{ 1107 struct ena_ring *rx_ring; 1108 int i, rc, bufs_num; 1109 1110 for (i = 0; i < adapter->num_queues; i++) { 1111 rx_ring = &adapter->rx_ring[i]; 1112 bufs_num = rx_ring->ring_size - 1; 1113 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 1114 1115 if (unlikely(rc != bufs_num)) 1116 ena_trace(ENA_WARNING, "refilling Queue %d failed. " 1117 "Allocated %d buffers from: %d\n", i, rc, bufs_num); 1118 } 1119} 1120 1121static void 1122ena_free_all_rx_bufs(struct ena_adapter *adapter) 1123{ 1124 int i; 1125 1126 for (i = 0; i < adapter->num_queues; i++) 1127 ena_free_rx_bufs(adapter, i); 1128} 1129 1130/** 1131 * ena_free_tx_bufs - Free Tx Buffers per Queue 1132 * @adapter: network interface device structure 1133 * @qid: queue index 1134 **/ 1135static void 1136ena_free_tx_bufs(struct ena_adapter *adapter, unsigned int qid) 1137{ 1138 bool print_once = true; 1139 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 1140 1141 ENA_RING_MTX_LOCK(tx_ring); 1142 for (int i = 0; i < tx_ring->ring_size; i++) { 1143 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 1144 1145 if (tx_info->mbuf == NULL) 1146 continue; 1147 1148 if (print_once) { 1149 device_printf(adapter->pdev, 1150 "free uncompleted tx mbuf qid %d idx 0x%x", 1151 qid, i); 1152 print_once = false; 1153 } else { 1154 ena_trace(ENA_DBG, 1155 "free uncompleted tx mbuf qid %d idx 0x%x", 1156 qid, i); 1157 } 1158 1159 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->map); 1160 m_free(tx_info->mbuf); 1161 tx_info->mbuf = NULL; 1162 } 1163 ENA_RING_MTX_UNLOCK(tx_ring); 1164} 1165 1166static void 1167ena_free_all_tx_bufs(struct ena_adapter *adapter) 1168{ 1169 1170 for (int i = 0; i < adapter->num_queues; i++) 1171 ena_free_tx_bufs(adapter, i); 1172} 1173 1174static void 1175ena_destroy_all_tx_queues(struct ena_adapter *adapter) 1176{ 1177 uint16_t ena_qid; 1178 int i; 1179 1180 for (i = 0; i < adapter->num_queues; i++) { 1181 ena_qid = ENA_IO_TXQ_IDX(i); 1182 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1183 } 1184} 1185 1186static void 1187ena_destroy_all_rx_queues(struct ena_adapter *adapter) 1188{ 1189 uint16_t ena_qid; 1190 int i; 1191 1192 for (i = 0; i < adapter->num_queues; i++) { 1193 ena_qid = ENA_IO_RXQ_IDX(i); 1194 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1195 } 1196} 1197 1198static void 1199ena_destroy_all_io_queues(struct ena_adapter *adapter) 1200{ 1201 ena_destroy_all_tx_queues(adapter); 1202 ena_destroy_all_rx_queues(adapter); 1203} 1204 1205static inline int 1206validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 1207{ 1208 struct ena_adapter *adapter = tx_ring->adapter; 1209 struct ena_tx_buffer *tx_info = NULL; 1210 1211 if (likely(req_id < tx_ring->ring_size)) { 1212 tx_info = &tx_ring->tx_buffer_info[req_id]; 1213 if (tx_info->mbuf != NULL) 1214 return (0); 1215 } 1216 1217 if (tx_info->mbuf == NULL) 1218 device_printf(adapter->pdev, 1219 "tx_info doesn't have valid mbuf\n"); 1220 else 1221 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 1222 1223 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 1224 1225 return (EFAULT); 1226} 1227 1228static int 1229ena_create_io_queues(struct ena_adapter *adapter) 1230{ 1231 struct ena_com_dev *ena_dev = adapter->ena_dev; 1232 struct ena_com_create_io_ctx ctx; 1233 struct ena_ring *ring; 1234 uint16_t ena_qid; 1235 uint32_t msix_vector; 1236 int rc, i; 1237 1238 /* Create TX queues */ 1239 for (i = 0; i < adapter->num_queues; i++) { 1240 msix_vector = ENA_IO_IRQ_IDX(i); 1241 ena_qid = ENA_IO_TXQ_IDX(i); 1242 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1243 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1244 ctx.queue_size = adapter->tx_ring_size; 1245 ctx.msix_vector = msix_vector; 1246 ctx.qid = ena_qid; 1247 rc = ena_com_create_io_queue(ena_dev, &ctx); 1248 if (rc != 0) { 1249 device_printf(adapter->pdev, 1250 "Failed to create io TX queue #%d rc: %d\n", i, rc); 1251 goto err_tx; 1252 } 1253 ring = &adapter->tx_ring[i]; 1254 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1255 &ring->ena_com_io_sq, 1256 &ring->ena_com_io_cq); 1257 if (rc != 0) { 1258 device_printf(adapter->pdev, 1259 "Failed to get TX queue handlers. TX queue num" 1260 " %d rc: %d\n", i, rc); 1261 ena_com_destroy_io_queue(ena_dev, ena_qid); 1262 goto err_tx; 1263 } 1264 } 1265 1266 /* Create RX queues */ 1267 for (i = 0; i < adapter->num_queues; i++) { 1268 msix_vector = ENA_IO_IRQ_IDX(i); 1269 ena_qid = ENA_IO_RXQ_IDX(i); 1270 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1271 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1272 ctx.queue_size = adapter->rx_ring_size; 1273 ctx.msix_vector = msix_vector; 1274 ctx.qid = ena_qid; 1275 rc = ena_com_create_io_queue(ena_dev, &ctx); 1276 if (unlikely(rc != 0)) { 1277 device_printf(adapter->pdev, 1278 "Failed to create io RX queue[%d] rc: %d\n", i, rc); 1279 goto err_rx; 1280 } 1281 1282 ring = &adapter->rx_ring[i]; 1283 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1284 &ring->ena_com_io_sq, 1285 &ring->ena_com_io_cq); 1286 if (unlikely(rc != 0)) { 1287 device_printf(adapter->pdev, 1288 "Failed to get RX queue handlers. RX queue num" 1289 " %d rc: %d\n", i, rc); 1290 ena_com_destroy_io_queue(ena_dev, ena_qid); 1291 goto err_rx; 1292 } 1293 } 1294 1295 return (0); 1296 1297err_rx: 1298 while (i--) 1299 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1300 i = adapter->num_queues; 1301err_tx: 1302 while (i--) 1303 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1304 1305 return (ENXIO); 1306} 1307 1308/** 1309 * ena_tx_cleanup - clear sent packets and corresponding descriptors 1310 * @tx_ring: ring for which we want to clean packets 1311 * 1312 * Once packets are sent, we ask the device in a loop for no longer used 1313 * descriptors. We find the related mbuf chain in a map (index in an array) 1314 * and free it, then update ring state. 1315 * This is performed in "endless" loop, updating ring pointers every 1316 * TX_COMMIT. The first check of free descriptor is performed before the actual 1317 * loop, then repeated at the loop end. 1318 **/ 1319static int 1320ena_tx_cleanup(struct ena_ring *tx_ring) 1321{ 1322 struct ena_adapter *adapter; 1323 struct ena_com_io_cq* io_cq; 1324 uint16_t next_to_clean; 1325 uint16_t req_id; 1326 uint16_t ena_qid; 1327 unsigned int total_done = 0; 1328 int rc; 1329 int commit = TX_COMMIT; 1330 int budget = TX_BUDGET; 1331 int work_done; 1332 1333 adapter = tx_ring->que->adapter; 1334 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1335 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1336 next_to_clean = tx_ring->next_to_clean; 1337 1338 do { 1339 struct ena_tx_buffer *tx_info; 1340 struct mbuf *mbuf; 1341 1342 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 1343 if (unlikely(rc != 0)) 1344 break; 1345 1346 rc = validate_tx_req_id(tx_ring, req_id); 1347 if (unlikely(rc != 0)) 1348 break; 1349 1350 tx_info = &tx_ring->tx_buffer_info[req_id]; 1351 1352 mbuf = tx_info->mbuf; 1353 1354 tx_info->mbuf = NULL; 1355 bintime_clear(&tx_info->timestamp); 1356 1357 if (likely(tx_info->num_of_bufs != 0)) { 1358 /* Map is no longer required */ 1359 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->map); 1360 } 1361 1362 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed", 1363 tx_ring->qid, mbuf); 1364 1365 m_freem(mbuf); 1366 1367 total_done += tx_info->tx_descs; 1368 1369 tx_ring->free_tx_ids[next_to_clean] = req_id; 1370 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 1371 tx_ring->ring_size); 1372 1373 if (unlikely(--commit == 0)) { 1374 commit = TX_COMMIT; 1375 /* update ring state every TX_COMMIT descriptor */ 1376 tx_ring->next_to_clean = next_to_clean; 1377 ena_com_comp_ack( 1378 &adapter->ena_dev->io_sq_queues[ena_qid], 1379 total_done); 1380 ena_com_update_dev_comp_head(io_cq); 1381 total_done = 0; 1382 } 1383 } while (likely(--budget)); 1384 1385 work_done = TX_BUDGET - budget; 1386 1387 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d", 1388 tx_ring->qid, work_done); 1389 1390 /* If there is still something to commit update ring state */ 1391 if (likely(commit != TX_COMMIT)) { 1392 tx_ring->next_to_clean = next_to_clean; 1393 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 1394 total_done); 1395 ena_com_update_dev_comp_head(io_cq); 1396 } 1397 1398 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 1399 1400 return (work_done); 1401} 1402 1403static void 1404ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1405 struct mbuf *mbuf) 1406{ 1407 struct ena_adapter *adapter = rx_ring->adapter; 1408 1409 if (likely(adapter->rss_support)) { 1410 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 1411 1412 if (ena_rx_ctx->frag && 1413 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 1414 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1415 return; 1416 } 1417 1418 switch (ena_rx_ctx->l3_proto) { 1419 case ENA_ETH_IO_L3_PROTO_IPV4: 1420 switch (ena_rx_ctx->l4_proto) { 1421 case ENA_ETH_IO_L4_PROTO_TCP: 1422 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 1423 break; 1424 case ENA_ETH_IO_L4_PROTO_UDP: 1425 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 1426 break; 1427 default: 1428 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 1429 } 1430 break; 1431 case ENA_ETH_IO_L3_PROTO_IPV6: 1432 switch (ena_rx_ctx->l4_proto) { 1433 case ENA_ETH_IO_L4_PROTO_TCP: 1434 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 1435 break; 1436 case ENA_ETH_IO_L4_PROTO_UDP: 1437 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 1438 break; 1439 default: 1440 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 1441 } 1442 break; 1443 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 1444 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1445 break; 1446 default: 1447 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1448 } 1449 } else { 1450 mbuf->m_pkthdr.flowid = rx_ring->qid; 1451 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1452 } 1453} 1454 1455/** 1456 * ena_rx_mbuf - assemble mbuf from descriptors 1457 * @rx_ring: ring for which we want to clean packets 1458 * @ena_bufs: buffer info 1459 * @ena_rx_ctx: metadata for this packet(s) 1460 * @next_to_clean: ring pointer, will be updated only upon success 1461 * 1462 **/ 1463static struct mbuf* 1464ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 1465 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 1466{ 1467 struct mbuf *mbuf; 1468 struct ena_rx_buffer *rx_info; 1469 struct ena_adapter *adapter; 1470 unsigned int descs = ena_rx_ctx->descs; 1471 int rc; 1472 uint16_t ntc, len, req_id, buf = 0; 1473 1474 ntc = *next_to_clean; 1475 adapter = rx_ring->adapter; 1476 1477 len = ena_bufs[buf].len; 1478 req_id = ena_bufs[buf].req_id; 1479 rc = validate_rx_req_id(rx_ring, req_id); 1480 if (unlikely(rc != 0)) 1481 return (NULL); 1482 1483 rx_info = &rx_ring->rx_buffer_info[req_id]; 1484 if (unlikely(rx_info->mbuf == NULL)) { 1485 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1486 return (NULL); 1487 } 1488 1489 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx", 1490 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 1491 1492 mbuf = rx_info->mbuf; 1493 mbuf->m_flags |= M_PKTHDR; 1494 mbuf->m_pkthdr.len = len; 1495 mbuf->m_len = len; 1496 mbuf->m_pkthdr.rcvif = rx_ring->que->adapter->ifp; 1497 1498 /* Fill mbuf with hash key and it's interpretation for optimization */ 1499 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 1500 1501 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf 0x%p, flags=0x%x, len: %d", 1502 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 1503 1504 /* DMA address is not needed anymore, unmap it */ 1505 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map); 1506 1507 rx_info->mbuf = NULL; 1508 rx_ring->free_rx_ids[ntc] = req_id; 1509 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1510 1511 /* 1512 * While we have more than 1 descriptors for one rcvd packet, append 1513 * other mbufs to the main one 1514 */ 1515 while (--descs) { 1516 ++buf; 1517 len = ena_bufs[buf].len; 1518 req_id = ena_bufs[buf].req_id; 1519 rc = validate_rx_req_id(rx_ring, req_id); 1520 if (unlikely(rc != 0)) { 1521 /* 1522 * If the req_id is invalid, then the device will be 1523 * reset. In that case we must free all mbufs that 1524 * were already gathered. 1525 */ 1526 m_freem(mbuf); 1527 return (NULL); 1528 } 1529 rx_info = &rx_ring->rx_buffer_info[req_id]; 1530 1531 if (unlikely(rx_info->mbuf == NULL)) { 1532 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1533 /* 1534 * If one of the required mbufs was not allocated yet, 1535 * we can break there. 1536 * All earlier used descriptors will be reallocated 1537 * later and not used mbufs can be reused. 1538 * The next_to_clean pointer will not be updated in case 1539 * of an error, so caller should advance it manually 1540 * in error handling routine to keep it up to date 1541 * with hw ring. 1542 */ 1543 m_freem(mbuf); 1544 return (NULL); 1545 } 1546 1547 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 1548 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1549 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p", 1550 mbuf); 1551 } 1552 1553 ena_trace(ENA_DBG | ENA_RXPTH, 1554 "rx mbuf updated. len %d", mbuf->m_pkthdr.len); 1555 1556 /* Free already appended mbuf, it won't be useful anymore */ 1557 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map); 1558 m_freem(rx_info->mbuf); 1559 rx_info->mbuf = NULL; 1560 1561 rx_ring->free_rx_ids[ntc] = req_id; 1562 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1563 } 1564 1565 *next_to_clean = ntc; 1566 1567 return (mbuf); 1568} 1569 1570/** 1571 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 1572 **/ 1573static inline void 1574ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1575 struct mbuf *mbuf) 1576{ 1577 1578 /* if IP and error */ 1579 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) && 1580 ena_rx_ctx->l3_csum_err)) { 1581 /* ipv4 checksum error */ 1582 mbuf->m_pkthdr.csum_flags = 0; 1583 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1584 ena_trace(ENA_DBG, "RX IPv4 header checksum error"); 1585 return; 1586 } 1587 1588 /* if TCP/UDP */ 1589 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1590 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1591 if (ena_rx_ctx->l4_csum_err) { 1592 /* TCP/UDP checksum error */ 1593 mbuf->m_pkthdr.csum_flags = 0; 1594 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1595 ena_trace(ENA_DBG, "RX L4 checksum error"); 1596 } else { 1597 mbuf->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 1598 mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1599 } 1600 } 1601} 1602 1603static void 1604ena_deferred_rx_cleanup(void *arg, int pending) 1605{ 1606 struct ena_ring *rx_ring = arg; 1607 int budget = CLEAN_BUDGET; 1608 1609 ENA_RING_MTX_LOCK(rx_ring); 1610 /* 1611 * If deferred task was executed, perform cleanup of all awaiting 1612 * descs (or until given budget is depleted to avoid infinite loop). 1613 */ 1614 while (likely(budget--)) { 1615 if (ena_rx_cleanup(rx_ring) == 0) 1616 break; 1617 } 1618 ENA_RING_MTX_UNLOCK(rx_ring); 1619} 1620 1621/** 1622 * ena_rx_cleanup - handle rx irq 1623 * @arg: ring for which irq is being handled 1624 **/ 1625static int 1626ena_rx_cleanup(struct ena_ring *rx_ring) 1627{ 1628 struct ena_adapter *adapter; 1629 struct mbuf *mbuf; 1630 struct ena_com_rx_ctx ena_rx_ctx; 1631 struct ena_com_io_cq* io_cq; 1632 struct ena_com_io_sq* io_sq; 1633 if_t ifp; 1634 uint16_t ena_qid; 1635 uint16_t next_to_clean; 1636 uint32_t refill_required; 1637 uint32_t refill_threshold; 1638 uint32_t do_if_input = 0; 1639 unsigned int qid; 1640 int rc, i; 1641 int budget = RX_BUDGET; 1642 1643 adapter = rx_ring->que->adapter; 1644 ifp = adapter->ifp; 1645 qid = rx_ring->que->id; 1646 ena_qid = ENA_IO_RXQ_IDX(qid); 1647 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1648 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1649 next_to_clean = rx_ring->next_to_clean; 1650 1651 ena_trace(ENA_DBG, "rx: qid %d", qid); 1652 1653 do { 1654 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1655 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 1656 ena_rx_ctx.descs = 0; 1657 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 1658 1659 if (unlikely(rc != 0)) 1660 goto error; 1661 1662 if (unlikely(ena_rx_ctx.descs == 0)) 1663 break; 1664 1665 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 1666 "descs #: %d l3 proto %d l4 proto %d hash: %x", 1667 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1668 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1669 1670 /* Receive mbuf from the ring */ 1671 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 1672 &ena_rx_ctx, &next_to_clean); 1673 1674 /* Exit if we failed to retrieve a buffer */ 1675 if (unlikely(mbuf == NULL)) { 1676 for (i = 0; i < ena_rx_ctx.descs; ++i) { 1677 rx_ring->free_rx_ids[next_to_clean] = 1678 rx_ring->ena_bufs[i].req_id; 1679 next_to_clean = 1680 ENA_RX_RING_IDX_NEXT(next_to_clean, 1681 rx_ring->ring_size); 1682 1683 } 1684 break; 1685 } 1686 1687 if (((ifp->if_capenable & IFCAP_RXCSUM) != 0) || 1688 ((ifp->if_capenable & IFCAP_RXCSUM_IPV6) != 0)) { 1689 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 1690 } 1691 1692 counter_enter(); 1693 counter_u64_add_protected(rx_ring->rx_stats.bytes, 1694 mbuf->m_pkthdr.len); 1695 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 1696 mbuf->m_pkthdr.len); 1697 counter_exit(); 1698 /* 1699 * LRO is only for IP/TCP packets and TCP checksum of the packet 1700 * should be computed by hardware. 1701 */ 1702 do_if_input = 1; 1703 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 1704 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 1705 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 1706 /* 1707 * Send to the stack if: 1708 * - LRO not enabled, or 1709 * - no LRO resources, or 1710 * - lro enqueue fails 1711 */ 1712 if ((rx_ring->lro.lro_cnt != 0) && 1713 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 1714 do_if_input = 0; 1715 } 1716 if (do_if_input != 0) { 1717 ena_trace(ENA_DBG | ENA_RXPTH, 1718 "calling if_input() with mbuf %p", mbuf); 1719 (*ifp->if_input)(ifp, mbuf); 1720 } 1721 1722 counter_enter(); 1723 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 1724 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 1725 counter_exit(); 1726 } while (--budget); 1727 1728 rx_ring->next_to_clean = next_to_clean; 1729 1730 refill_required = ena_com_free_desc(io_sq); 1731 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1732 1733 if (refill_required > refill_threshold) { 1734 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1735 ena_refill_rx_bufs(rx_ring, refill_required); 1736 } 1737 1738 tcp_lro_flush_all(&rx_ring->lro); 1739 1740 return (RX_BUDGET - budget); 1741 1742error: 1743 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 1744 return (RX_BUDGET - budget); 1745} 1746 1747/********************************************************************* 1748 * 1749 * MSIX & Interrupt Service routine 1750 * 1751 **********************************************************************/ 1752 1753/** 1754 * ena_handle_msix - MSIX Interrupt Handler for admin/async queue 1755 * @arg: interrupt number 1756 **/ 1757static void 1758ena_intr_msix_mgmnt(void *arg) 1759{ 1760 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1761 1762 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1763 if (likely(adapter->running)) 1764 ena_com_aenq_intr_handler(adapter->ena_dev, arg); 1765} 1766 1767/** 1768 * ena_handle_msix - MSIX Interrupt Handler for Tx/Rx 1769 * @arg: interrupt number 1770 **/ 1771static void 1772ena_handle_msix(void *arg) 1773{ 1774 struct ena_que *que = arg; 1775 struct ena_adapter *adapter = que->adapter; 1776 if_t ifp = adapter->ifp; 1777 struct ena_ring *tx_ring; 1778 struct ena_ring *rx_ring; 1779 struct ena_com_io_cq* io_cq; 1780 struct ena_eth_io_intr_reg intr_reg; 1781 int qid, ena_qid; 1782 int txc, rxc, i; 1783 1784 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)) 1785 return; 1786 1787 ena_trace(ENA_DBG, "MSI-X TX/RX routine"); 1788 1789 tx_ring = que->tx_ring; 1790 rx_ring = que->rx_ring; 1791 qid = que->id; 1792 ena_qid = ENA_IO_TXQ_IDX(qid); 1793 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1794 1795 for (i = 0; i < CLEAN_BUDGET; ++i) { 1796 /* 1797 * If lock cannot be acquired, then deferred cleanup task was 1798 * being executed and rx ring is being cleaned up in 1799 * another thread. 1800 */ 1801 if (likely(ENA_RING_MTX_TRYLOCK(rx_ring) != 0)) { 1802 rxc = ena_rx_cleanup(rx_ring); 1803 ENA_RING_MTX_UNLOCK(rx_ring); 1804 } else { 1805 rxc = 0; 1806 } 1807 1808 /* Protection from calling ena_tx_cleanup from ena_start_xmit */ 1809 ENA_RING_MTX_LOCK(tx_ring); 1810 txc = ena_tx_cleanup(tx_ring); 1811 ENA_RING_MTX_UNLOCK(tx_ring); 1812 1813 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)) 1814 return; 1815 1816 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 1817 break; 1818 } 1819 1820 /* Signal that work is done and unmask interrupt */ 1821 ena_com_update_intr_reg(&intr_reg, 1822 RX_IRQ_INTERVAL, 1823 TX_IRQ_INTERVAL, 1824 true); 1825 ena_com_unmask_intr(io_cq, &intr_reg); 1826} 1827 1828static int 1829ena_enable_msix(struct ena_adapter *adapter) 1830{ 1831 device_t dev = adapter->pdev; 1832 int msix_vecs, msix_req; 1833 int i, rc = 0; 1834 1835 /* Reserved the max msix vectors we might need */ 1836 msix_vecs = ENA_MAX_MSIX_VEC(adapter->num_queues); 1837 1838 adapter->msix_entries = malloc(msix_vecs * sizeof(struct msix_entry), 1839 M_DEVBUF, M_WAITOK | M_ZERO); 1840 1841 ena_trace(ENA_DBG, "trying to enable MSI-X, vectors: %d", msix_vecs); 1842 1843 for (i = 0; i < msix_vecs; i++) { 1844 adapter->msix_entries[i].entry = i; 1845 /* Vectors must start from 1 */ 1846 adapter->msix_entries[i].vector = i + 1; 1847 } 1848 1849 msix_req = msix_vecs; 1850 rc = pci_alloc_msix(dev, &msix_vecs); 1851 if (unlikely(rc != 0)) { 1852 device_printf(dev, 1853 "Failed to enable MSIX, vectors %d rc %d\n", msix_vecs, rc); 1854 1855 rc = ENOSPC; 1856 goto err_msix_free; 1857 } 1858 1859 if (msix_vecs != msix_req) { 1860 device_printf(dev, "Enable only %d MSI-x (out of %d), reduce " 1861 "the number of queues\n", msix_vecs, msix_req); 1862 adapter->num_queues = msix_vecs - ENA_ADMIN_MSIX_VEC; 1863 } 1864 1865 adapter->msix_vecs = msix_vecs; 1866 adapter->msix_enabled = true; 1867 1868 return (0); 1869 1870err_msix_free: 1871 free(adapter->msix_entries, M_DEVBUF); 1872 adapter->msix_entries = NULL; 1873 1874 return (rc); 1875} 1876 1877static void 1878ena_setup_mgmnt_intr(struct ena_adapter *adapter) 1879{ 1880 1881 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name, 1882 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s", 1883 device_get_nameunit(adapter->pdev)); 1884 /* 1885 * Handler is NULL on purpose, it will be set 1886 * when mgmnt interrupt is acquired 1887 */ 1888 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler = NULL; 1889 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter; 1890 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector = 1891 adapter->msix_entries[ENA_MGMNT_IRQ_IDX].vector; 1892} 1893 1894static void 1895ena_setup_io_intr(struct ena_adapter *adapter) 1896{ 1897 static int last_bind_cpu = -1; 1898 int irq_idx; 1899 1900 for (int i = 0; i < adapter->num_queues; i++) { 1901 irq_idx = ENA_IO_IRQ_IDX(i); 1902 1903 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1904 "%s-TxRx-%d", device_get_nameunit(adapter->pdev), i); 1905 adapter->irq_tbl[irq_idx].handler = ena_handle_msix; 1906 adapter->irq_tbl[irq_idx].data = &adapter->que[i]; 1907 adapter->irq_tbl[irq_idx].vector = 1908 adapter->msix_entries[irq_idx].vector; 1909 ena_trace(ENA_INFO | ENA_IOQ, "ena_setup_io_intr vector: %d\n", 1910 adapter->msix_entries[irq_idx].vector); 1911#ifdef RSS 1912 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1913 rss_getcpu(i % rss_getnumbuckets()); 1914#else 1915 /* 1916 * We still want to bind rings to the corresponding cpu 1917 * using something similar to the RSS round-robin technique. 1918 */ 1919 if (unlikely(last_bind_cpu < 0)) 1920 last_bind_cpu = CPU_FIRST(); 1921 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1922 last_bind_cpu; 1923 last_bind_cpu = CPU_NEXT(last_bind_cpu); 1924#endif 1925 } 1926} 1927 1928static int 1929ena_request_mgmnt_irq(struct ena_adapter *adapter) 1930{ 1931 struct ena_irq *irq; 1932 unsigned long flags; 1933 int rc, rcc; 1934 1935 flags = RF_ACTIVE | RF_SHAREABLE; 1936 1937 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 1938 irq->res = bus_alloc_resource_any(adapter->pdev, SYS_RES_IRQ, 1939 &irq->vector, flags); 1940 1941 if (unlikely(irq->res == NULL)) { 1942 device_printf(adapter->pdev, "could not allocate " 1943 "irq vector: %d\n", irq->vector); 1944 return (ENXIO); 1945 } 1946 1947 rc = bus_activate_resource(adapter->pdev, SYS_RES_IRQ, 1948 irq->vector, irq->res); 1949 if (unlikely(rc != 0)) { 1950 device_printf(adapter->pdev, "could not activate " 1951 "irq vector: %d\n", irq->vector); 1952 goto err_res_free; 1953 } 1954 1955 rc = bus_setup_intr(adapter->pdev, irq->res, 1956 INTR_TYPE_NET | INTR_MPSAFE, NULL, ena_intr_msix_mgmnt, 1957 irq->data, &irq->cookie); 1958 if (unlikely(rc != 0)) { 1959 device_printf(adapter->pdev, "failed to register " 1960 "interrupt handler for irq %ju: %d\n", 1961 rman_get_start(irq->res), rc); 1962 goto err_res_free; 1963 } 1964 irq->requested = true; 1965 1966 return (rc); 1967 1968err_res_free: 1969 ena_trace(ENA_INFO | ENA_ADMQ, "releasing resource for irq %d\n", 1970 irq->vector); 1971 rcc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 1972 irq->vector, irq->res); 1973 if (unlikely(rcc != 0)) 1974 device_printf(adapter->pdev, "dev has no parent while " 1975 "releasing res for irq: %d\n", irq->vector); 1976 irq->res = NULL; 1977 1978 return (rc); 1979} 1980 1981static int 1982ena_request_io_irq(struct ena_adapter *adapter) 1983{ 1984 struct ena_irq *irq; 1985 unsigned long flags = 0; 1986 int rc = 0, i, rcc; 1987 1988 if (unlikely(adapter->msix_enabled == 0)) { 1989 device_printf(adapter->pdev, 1990 "failed to request I/O IRQ: MSI-X is not enabled\n"); 1991 return (EINVAL); 1992 } else { 1993 flags = RF_ACTIVE | RF_SHAREABLE; 1994 } 1995 1996 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 1997 irq = &adapter->irq_tbl[i]; 1998 1999 if (unlikely(irq->requested)) 2000 continue; 2001 2002 irq->res = bus_alloc_resource_any(adapter->pdev, SYS_RES_IRQ, 2003 &irq->vector, flags); 2004 if (unlikely(irq->res == NULL)) { 2005 device_printf(adapter->pdev, "could not allocate " 2006 "irq vector: %d\n", irq->vector); 2007 goto err; 2008 } 2009 2010 rc = bus_setup_intr(adapter->pdev, irq->res, 2011 INTR_TYPE_NET | INTR_MPSAFE, NULL, 2012 irq->handler, irq->data, &irq->cookie); 2013 if (unlikely(rc != 0)) { 2014 device_printf(adapter->pdev, "failed to register " 2015 "interrupt handler for irq %ju: %d\n", 2016 rman_get_start(irq->res), rc); 2017 goto err; 2018 } 2019 irq->requested = true; 2020 2021#ifdef RSS 2022 ena_trace(ENA_INFO, "queue %d - RSS bucket %d\n", 2023 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2024#else 2025 ena_trace(ENA_INFO, "queue %d - cpu %d\n", 2026 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2027#endif 2028 } 2029 2030 return (rc); 2031 2032err: 2033 2034 for (; i >= ENA_IO_IRQ_FIRST_IDX; i--) { 2035 irq = &adapter->irq_tbl[i]; 2036 rcc = 0; 2037 2038 /* Once we entered err: section and irq->requested is true we 2039 free both intr and resources */ 2040 if (irq->requested) 2041 rcc = bus_teardown_intr(adapter->pdev, irq->res, irq->cookie); 2042 if (unlikely(rcc != 0)) 2043 device_printf(adapter->pdev, "could not release" 2044 " irq: %d, error: %d\n", irq->vector, rcc); 2045 2046 /* If we entred err: section without irq->requested set we know 2047 it was bus_alloc_resource_any() that needs cleanup, provided 2048 res is not NULL. In case res is NULL no work in needed in 2049 this iteration */ 2050 rcc = 0; 2051 if (irq->res != NULL) { 2052 rcc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 2053 irq->vector, irq->res); 2054 } 2055 if (unlikely(rcc != 0)) 2056 device_printf(adapter->pdev, "dev has no parent while " 2057 "releasing res for irq: %d\n", irq->vector); 2058 irq->requested = false; 2059 irq->res = NULL; 2060 } 2061 2062 return (rc); 2063} 2064 2065static void 2066ena_free_mgmnt_irq(struct ena_adapter *adapter) 2067{ 2068 struct ena_irq *irq; 2069 int rc; 2070 2071 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 2072 if (irq->requested) { 2073 ena_trace(ENA_INFO | ENA_ADMQ, "tear down irq: %d\n", 2074 irq->vector); 2075 rc = bus_teardown_intr(adapter->pdev, irq->res, irq->cookie); 2076 if (unlikely(rc != 0)) 2077 device_printf(adapter->pdev, "failed to tear " 2078 "down irq: %d\n", irq->vector); 2079 irq->requested = 0; 2080 } 2081 2082 if (irq->res != NULL) { 2083 ena_trace(ENA_INFO | ENA_ADMQ, "release resource irq: %d\n", 2084 irq->vector); 2085 rc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 2086 irq->vector, irq->res); 2087 irq->res = NULL; 2088 if (unlikely(rc != 0)) 2089 device_printf(adapter->pdev, "dev has no parent while " 2090 "releasing res for irq: %d\n", irq->vector); 2091 } 2092} 2093 2094static void 2095ena_free_io_irq(struct ena_adapter *adapter) 2096{ 2097 struct ena_irq *irq; 2098 int rc; 2099 2100 for (int i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 2101 irq = &adapter->irq_tbl[i]; 2102 if (irq->requested) { 2103 ena_trace(ENA_INFO | ENA_IOQ, "tear down irq: %d\n", 2104 irq->vector); 2105 rc = bus_teardown_intr(adapter->pdev, irq->res, 2106 irq->cookie); 2107 if (unlikely(rc != 0)) { 2108 device_printf(adapter->pdev, "failed to tear " 2109 "down irq: %d\n", irq->vector); 2110 } 2111 irq->requested = 0; 2112 } 2113 2114 if (irq->res != NULL) { 2115 ena_trace(ENA_INFO | ENA_IOQ, "release resource irq: %d\n", 2116 irq->vector); 2117 rc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 2118 irq->vector, irq->res); 2119 irq->res = NULL; 2120 if (unlikely(rc != 0)) { 2121 device_printf(adapter->pdev, "dev has no parent" 2122 " while releasing res for irq: %d\n", 2123 irq->vector); 2124 } 2125 } 2126 } 2127} 2128 2129static void 2130ena_free_irqs(struct ena_adapter* adapter) 2131{ 2132 2133 ena_free_io_irq(adapter); 2134 ena_free_mgmnt_irq(adapter); 2135 ena_disable_msix(adapter); 2136} 2137 2138static void 2139ena_disable_msix(struct ena_adapter *adapter) 2140{ 2141 2142 pci_release_msi(adapter->pdev); 2143 2144 adapter->msix_vecs = 0; 2145 free(adapter->msix_entries, M_DEVBUF); 2146 adapter->msix_entries = NULL; 2147} 2148 2149static void 2150ena_unmask_all_io_irqs(struct ena_adapter *adapter) 2151{ 2152 struct ena_com_io_cq* io_cq; 2153 struct ena_eth_io_intr_reg intr_reg; 2154 uint16_t ena_qid; 2155 int i; 2156 2157 /* Unmask interrupts for all queues */ 2158 for (i = 0; i < adapter->num_queues; i++) { 2159 ena_qid = ENA_IO_TXQ_IDX(i); 2160 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 2161 ena_com_update_intr_reg(&intr_reg, 0, 0, true); 2162 ena_com_unmask_intr(io_cq, &intr_reg); 2163 } 2164} 2165 2166/* Configure the Rx forwarding */ 2167static int 2168ena_rss_configure(struct ena_adapter *adapter) 2169{ 2170 struct ena_com_dev *ena_dev = adapter->ena_dev; 2171 int rc; 2172 2173 /* Set indirect table */ 2174 rc = ena_com_indirect_table_set(ena_dev); 2175 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2176 return (rc); 2177 2178 /* Configure hash function (if supported) */ 2179 rc = ena_com_set_hash_function(ena_dev); 2180 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2181 return (rc); 2182 2183 /* Configure hash inputs (if supported) */ 2184 rc = ena_com_set_hash_ctrl(ena_dev); 2185 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2186 return (rc); 2187 2188 return (0); 2189} 2190 2191static int 2192ena_up_complete(struct ena_adapter *adapter) 2193{ 2194 int rc; 2195 2196 if (likely(adapter->rss_support)) { 2197 rc = ena_rss_configure(adapter); 2198 if (rc != 0) 2199 return (rc); 2200 } 2201 2202 rc = ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu); 2203 if (unlikely(rc != 0)) 2204 return (rc); 2205 2206 ena_refill_all_rx_bufs(adapter); 2207 ena_reset_counters((counter_u64_t *)&adapter->hw_stats, 2208 sizeof(adapter->hw_stats)); 2209 2210 return (0); 2211} 2212 2213static int 2214ena_up(struct ena_adapter *adapter) 2215{ 2216 int rc = 0; 2217 2218 if (unlikely(device_is_attached(adapter->pdev) == 0)) { 2219 device_printf(adapter->pdev, "device is not attached!\n"); 2220 return (ENXIO); 2221 } 2222 2223 if (unlikely(!adapter->running)) { 2224 device_printf(adapter->pdev, "device is not running!\n"); 2225 return (ENXIO); 2226 } 2227 2228 if (!adapter->up) { 2229 device_printf(adapter->pdev, "device is going UP\n"); 2230 2231 /* setup interrupts for IO queues */ 2232 ena_setup_io_intr(adapter); 2233 rc = ena_request_io_irq(adapter); 2234 if (unlikely(rc != 0)) { 2235 ena_trace(ENA_ALERT, "err_req_irq"); 2236 goto err_req_irq; 2237 } 2238 2239 /* allocate transmit descriptors */ 2240 rc = ena_setup_all_tx_resources(adapter); 2241 if (unlikely(rc != 0)) { 2242 ena_trace(ENA_ALERT, "err_setup_tx"); 2243 goto err_setup_tx; 2244 } 2245 2246 /* allocate receive descriptors */ 2247 rc = ena_setup_all_rx_resources(adapter); 2248 if (unlikely(rc != 0)) { 2249 ena_trace(ENA_ALERT, "err_setup_rx"); 2250 goto err_setup_rx; 2251 } 2252 2253 /* create IO queues for Rx & Tx */ 2254 rc = ena_create_io_queues(adapter); 2255 if (unlikely(rc != 0)) { 2256 ena_trace(ENA_ALERT, 2257 "create IO queues failed"); 2258 goto err_io_que; 2259 } 2260 2261 if (unlikely(adapter->link_status)) 2262 if_link_state_change(adapter->ifp, LINK_STATE_UP); 2263 2264 rc = ena_up_complete(adapter); 2265 if (unlikely(rc != 0)) 2266 goto err_up_complete; 2267 2268 counter_u64_add(adapter->dev_stats.interface_up, 1); 2269 2270 ena_update_hwassist(adapter); 2271 2272 if_setdrvflagbits(adapter->ifp, IFF_DRV_RUNNING, 2273 IFF_DRV_OACTIVE); 2274 2275 callout_reset_sbt(&adapter->timer_service, SBT_1S, SBT_1S, 2276 ena_timer_service, (void *)adapter, 0); 2277 2278 adapter->up = true; 2279 2280 ena_unmask_all_io_irqs(adapter); 2281 } 2282 2283 return (0); 2284 2285err_up_complete: 2286 ena_destroy_all_io_queues(adapter); 2287err_io_que: 2288 ena_free_all_rx_resources(adapter); 2289err_setup_rx: 2290 ena_free_all_tx_resources(adapter); 2291err_setup_tx: 2292 ena_free_io_irq(adapter); 2293err_req_irq: 2294 return (rc); 2295} 2296 2297static uint64_t 2298ena_get_counter(if_t ifp, ift_counter cnt) 2299{ 2300 struct ena_adapter *adapter; 2301 struct ena_hw_stats *stats; 2302 2303 adapter = if_getsoftc(ifp); 2304 stats = &adapter->hw_stats; 2305 2306 switch (cnt) { 2307 case IFCOUNTER_IPACKETS: 2308 return (counter_u64_fetch(stats->rx_packets)); 2309 case IFCOUNTER_OPACKETS: 2310 return (counter_u64_fetch(stats->tx_packets)); 2311 case IFCOUNTER_IBYTES: 2312 return (counter_u64_fetch(stats->rx_bytes)); 2313 case IFCOUNTER_OBYTES: 2314 return (counter_u64_fetch(stats->tx_bytes)); 2315 case IFCOUNTER_IQDROPS: 2316 return (counter_u64_fetch(stats->rx_drops)); 2317 default: 2318 return (if_get_counter_default(ifp, cnt)); 2319 } 2320} 2321 2322static int 2323ena_media_change(if_t ifp) 2324{ 2325 /* Media Change is not supported by firmware */ 2326 return (0); 2327} 2328 2329static void 2330ena_media_status(if_t ifp, struct ifmediareq *ifmr) 2331{ 2332 struct ena_adapter *adapter = if_getsoftc(ifp); 2333 ena_trace(ENA_DBG, "enter"); 2334 2335 mtx_lock(&adapter->global_mtx); 2336 2337 ifmr->ifm_status = IFM_AVALID; 2338 ifmr->ifm_active = IFM_ETHER; 2339 2340 if (!adapter->link_status) { 2341 mtx_unlock(&adapter->global_mtx); 2342 ena_trace(ENA_INFO, "link_status = false"); 2343 return; 2344 } 2345 2346 ifmr->ifm_status |= IFM_ACTIVE; 2347 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2348 2349 mtx_unlock(&adapter->global_mtx); 2350} 2351 2352static void 2353ena_init(void *arg) 2354{ 2355 struct ena_adapter *adapter = (struct ena_adapter *)arg; 2356 2357 if (!adapter->up) { 2358 sx_xlock(&adapter->ioctl_sx); 2359 ena_up(adapter); 2360 sx_unlock(&adapter->ioctl_sx); 2361 } 2362} 2363 2364static int 2365ena_ioctl(if_t ifp, u_long command, caddr_t data) 2366{ 2367 struct ena_adapter *adapter; 2368 struct ifreq *ifr; 2369 int rc; 2370 2371 adapter = ifp->if_softc; 2372 ifr = (struct ifreq *)data; 2373 2374 /* 2375 * Acquiring lock to prevent from running up and down routines parallel. 2376 */ 2377 rc = 0; 2378 switch (command) { 2379 case SIOCSIFMTU: 2380 if (ifp->if_mtu == ifr->ifr_mtu) 2381 break; 2382 sx_xlock(&adapter->ioctl_sx); 2383 ena_down(adapter); 2384 2385 ena_change_mtu(ifp, ifr->ifr_mtu); 2386 2387 rc = ena_up(adapter); 2388 sx_unlock(&adapter->ioctl_sx); 2389 break; 2390 2391 case SIOCSIFFLAGS: 2392 if ((ifp->if_flags & IFF_UP) != 0) { 2393 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2394 if ((ifp->if_flags & (IFF_PROMISC | 2395 IFF_ALLMULTI)) != 0) { 2396 device_printf(adapter->pdev, 2397 "ioctl promisc/allmulti\n"); 2398 } 2399 } else { 2400 sx_xlock(&adapter->ioctl_sx); 2401 rc = ena_up(adapter); 2402 sx_unlock(&adapter->ioctl_sx); 2403 } 2404 } else { 2405 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2406 sx_xlock(&adapter->ioctl_sx); 2407 ena_down(adapter); 2408 sx_unlock(&adapter->ioctl_sx); 2409 } 2410 } 2411 break; 2412 2413 case SIOCADDMULTI: 2414 case SIOCDELMULTI: 2415 break; 2416 2417 case SIOCSIFMEDIA: 2418 case SIOCGIFMEDIA: 2419 rc = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 2420 break; 2421 2422 case SIOCSIFCAP: 2423 { 2424 int reinit = 0; 2425 2426 if (ifr->ifr_reqcap != ifp->if_capenable) { 2427 ifp->if_capenable = ifr->ifr_reqcap; 2428 reinit = 1; 2429 } 2430 2431 if ((reinit != 0) && 2432 ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)) { 2433 sx_xlock(&adapter->ioctl_sx); 2434 ena_down(adapter); 2435 rc = ena_up(adapter); 2436 sx_unlock(&adapter->ioctl_sx); 2437 } 2438 } 2439 2440 break; 2441 default: 2442 rc = ether_ioctl(ifp, command, data); 2443 break; 2444 } 2445 2446 return (rc); 2447} 2448 2449static int 2450ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *feat) 2451{ 2452 int caps = 0; 2453 2454 if ((feat->offload.tx & 2455 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2456 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK | 2457 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)) != 0) 2458 caps |= IFCAP_TXCSUM; 2459 2460 if ((feat->offload.tx & 2461 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK | 2462 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)) != 0) 2463 caps |= IFCAP_TXCSUM_IPV6; 2464 2465 if ((feat->offload.tx & 2466 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0) 2467 caps |= IFCAP_TSO4; 2468 2469 if ((feat->offload.tx & 2470 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) != 0) 2471 caps |= IFCAP_TSO6; 2472 2473 if ((feat->offload.rx_supported & 2474 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK | 2475 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)) != 0) 2476 caps |= IFCAP_RXCSUM; 2477 2478 if ((feat->offload.rx_supported & 2479 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) != 0) 2480 caps |= IFCAP_RXCSUM_IPV6; 2481 2482 caps |= IFCAP_LRO | IFCAP_JUMBO_MTU; 2483 2484 return (caps); 2485} 2486 2487static void 2488ena_update_host_info(struct ena_admin_host_info *host_info, if_t ifp) 2489{ 2490 2491 host_info->supported_network_features[0] = 2492 (uint32_t)if_getcapabilities(ifp); 2493} 2494 2495static void 2496ena_update_hwassist(struct ena_adapter *adapter) 2497{ 2498 if_t ifp = adapter->ifp; 2499 uint32_t feat = adapter->tx_offload_cap; 2500 int cap = if_getcapenable(ifp); 2501 int flags = 0; 2502 2503 if_clearhwassist(ifp); 2504 2505 if ((cap & IFCAP_TXCSUM) != 0) { 2506 if ((feat & 2507 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) != 0) 2508 flags |= CSUM_IP; 2509 if ((feat & 2510 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2511 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)) != 0) 2512 flags |= CSUM_IP_UDP | CSUM_IP_TCP; 2513 } 2514 2515 if ((cap & IFCAP_TXCSUM_IPV6) != 0) 2516 flags |= CSUM_IP6_UDP | CSUM_IP6_TCP; 2517 2518 if ((cap & IFCAP_TSO4) != 0) 2519 flags |= CSUM_IP_TSO; 2520 2521 if ((cap & IFCAP_TSO6) != 0) 2522 flags |= CSUM_IP6_TSO; 2523 2524 if_sethwassistbits(ifp, flags, 0); 2525} 2526 2527static int 2528ena_setup_ifnet(device_t pdev, struct ena_adapter *adapter, 2529 struct ena_com_dev_get_features_ctx *feat) 2530{ 2531 if_t ifp; 2532 int caps = 0; 2533 2534 ifp = adapter->ifp = if_gethandle(IFT_ETHER); 2535 if (unlikely(ifp == NULL)) { 2536 ena_trace(ENA_ALERT, "can not allocate ifnet structure\n"); 2537 return (ENXIO); 2538 } 2539 if_initname(ifp, device_get_name(pdev), device_get_unit(pdev)); 2540 if_setdev(ifp, pdev); 2541 if_setsoftc(ifp, adapter); 2542 2543 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2544 if_setinitfn(ifp, ena_init); 2545 if_settransmitfn(ifp, ena_mq_start); 2546 if_setqflushfn(ifp, ena_qflush); 2547 if_setioctlfn(ifp, ena_ioctl); 2548 if_setgetcounterfn(ifp, ena_get_counter); 2549 2550 if_setsendqlen(ifp, adapter->tx_ring_size); 2551 if_setsendqready(ifp); 2552 if_setmtu(ifp, ETHERMTU); 2553 if_setbaudrate(ifp, 0); 2554 /* Zeroize capabilities... */ 2555 if_setcapabilities(ifp, 0); 2556 if_setcapenable(ifp, 0); 2557 /* check hardware support */ 2558 caps = ena_get_dev_offloads(feat); 2559 /* ... and set them */ 2560 if_setcapabilitiesbit(ifp, caps, 0); 2561 2562 /* TSO parameters */ 2563 ifp->if_hw_tsomax = ENA_TSO_MAXSIZE - 2564 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2565 ifp->if_hw_tsomaxsegcount = adapter->max_tx_sgl_size - 1; 2566 ifp->if_hw_tsomaxsegsize = ENA_TSO_MAXSIZE; 2567 2568 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2569 if_setcapenable(ifp, if_getcapabilities(ifp)); 2570 2571 /* 2572 * Specify the media types supported by this adapter and register 2573 * callbacks to update media and link information 2574 */ 2575 ifmedia_init(&adapter->media, IFM_IMASK, 2576 ena_media_change, ena_media_status); 2577 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2578 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2579 2580 ether_ifattach(ifp, adapter->mac_addr); 2581 2582 return (0); 2583} 2584 2585static void 2586ena_down(struct ena_adapter *adapter) 2587{ 2588 int rc; 2589 2590 if (adapter->up) { 2591 device_printf(adapter->pdev, "device is going DOWN\n"); 2592 2593 callout_drain(&adapter->timer_service); 2594 2595 adapter->up = false; 2596 if_setdrvflagbits(adapter->ifp, IFF_DRV_OACTIVE, 2597 IFF_DRV_RUNNING); 2598 2599 ena_free_io_irq(adapter); 2600 2601 if (adapter->trigger_reset) { 2602 rc = ena_com_dev_reset(adapter->ena_dev, 2603 adapter->reset_reason); 2604 if (unlikely(rc != 0)) 2605 device_printf(adapter->pdev, 2606 "Device reset failed\n"); 2607 } 2608 2609 ena_destroy_all_io_queues(adapter); 2610 2611 ena_free_all_tx_bufs(adapter); 2612 ena_free_all_rx_bufs(adapter); 2613 ena_free_all_tx_resources(adapter); 2614 ena_free_all_rx_resources(adapter); 2615 2616 counter_u64_add(adapter->dev_stats.interface_down, 1); 2617 } 2618} 2619 2620static void 2621ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf) 2622{ 2623 struct ena_com_tx_meta *ena_meta; 2624 struct ether_vlan_header *eh; 2625 u32 mss; 2626 bool offload; 2627 uint16_t etype; 2628 int ehdrlen; 2629 struct ip *ip; 2630 int iphlen; 2631 struct tcphdr *th; 2632 2633 offload = false; 2634 ena_meta = &ena_tx_ctx->ena_meta; 2635 mss = mbuf->m_pkthdr.tso_segsz; 2636 2637 if (mss != 0) 2638 offload = true; 2639 2640 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2641 offload = true; 2642 2643 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 2644 offload = true; 2645 2646 if (!offload) { 2647 ena_tx_ctx->meta_valid = 0; 2648 return; 2649 } 2650 2651 /* Determine where frame payload starts. */ 2652 eh = mtod(mbuf, struct ether_vlan_header *); 2653 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2654 etype = ntohs(eh->evl_proto); 2655 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2656 } else { 2657 etype = ntohs(eh->evl_encap_proto); 2658 ehdrlen = ETHER_HDR_LEN; 2659 } 2660 2661 ip = (struct ip *)(mbuf->m_data + ehdrlen); 2662 iphlen = ip->ip_hl << 2; 2663 th = (struct tcphdr *)((caddr_t)ip + iphlen); 2664 2665 if ((mbuf->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2666 ena_tx_ctx->l3_csum_enable = 1; 2667 } 2668 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2669 ena_tx_ctx->tso_enable = 1; 2670 ena_meta->l4_hdr_len = (th->th_off); 2671 } 2672 2673 switch (etype) { 2674 case ETHERTYPE_IP: 2675 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 2676 if ((ip->ip_off & htons(IP_DF)) != 0) 2677 ena_tx_ctx->df = 1; 2678 break; 2679 case ETHERTYPE_IPV6: 2680 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 2681 2682 default: 2683 break; 2684 } 2685 2686 if (ip->ip_p == IPPROTO_TCP) { 2687 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 2688 if ((mbuf->m_pkthdr.csum_flags & 2689 (CSUM_IP_TCP | CSUM_IP6_TCP)) != 0) 2690 ena_tx_ctx->l4_csum_enable = 1; 2691 else 2692 ena_tx_ctx->l4_csum_enable = 0; 2693 } else if (ip->ip_p == IPPROTO_UDP) { 2694 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 2695 if ((mbuf->m_pkthdr.csum_flags & 2696 (CSUM_IP_UDP | CSUM_IP6_UDP)) != 0) 2697 ena_tx_ctx->l4_csum_enable = 1; 2698 else 2699 ena_tx_ctx->l4_csum_enable = 0; 2700 } else { 2701 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 2702 ena_tx_ctx->l4_csum_enable = 0; 2703 } 2704 2705 ena_meta->mss = mss; 2706 ena_meta->l3_hdr_len = iphlen; 2707 ena_meta->l3_hdr_offset = ehdrlen; 2708 ena_tx_ctx->meta_valid = 1; 2709} 2710 2711static int 2712ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2713{ 2714 struct ena_adapter *adapter; 2715 struct mbuf *collapsed_mbuf; 2716 int num_frags; 2717 2718 adapter = tx_ring->adapter; 2719 num_frags = ena_mbuf_count(*mbuf); 2720 2721 /* One segment must be reserved for configuration descriptor. */ 2722 if (num_frags < adapter->max_tx_sgl_size) 2723 return (0); 2724 counter_u64_add(tx_ring->tx_stats.collapse, 1); 2725 2726 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 2727 adapter->max_tx_sgl_size - 1); 2728 if (unlikely(collapsed_mbuf == NULL)) { 2729 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 2730 return (ENOMEM); 2731 } 2732 2733 /* If mbuf was collapsed succesfully, original mbuf is released. */ 2734 *mbuf = collapsed_mbuf; 2735 2736 return (0); 2737} 2738 2739static int 2740ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2741{ 2742 struct ena_adapter *adapter; 2743 struct ena_tx_buffer *tx_info; 2744 struct ena_com_tx_ctx ena_tx_ctx; 2745 struct ena_com_dev *ena_dev; 2746 struct ena_com_buf *ena_buf; 2747 struct ena_com_io_sq* io_sq; 2748 bus_dma_segment_t segs[ENA_BUS_DMA_SEGS]; 2749 void *push_hdr; 2750 uint16_t next_to_use; 2751 uint16_t req_id; 2752 uint16_t push_len; 2753 uint16_t ena_qid; 2754 uint32_t nsegs, header_len; 2755 int i, rc; 2756 int nb_hw_desc; 2757 2758 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2759 adapter = tx_ring->que->adapter; 2760 ena_dev = adapter->ena_dev; 2761 io_sq = &ena_dev->io_sq_queues[ena_qid]; 2762 2763 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 2764 if (unlikely(rc != 0)) { 2765 ena_trace(ENA_WARNING, 2766 "Failed to collapse mbuf! err: %d", rc); 2767 return (rc); 2768 } 2769 2770 next_to_use = tx_ring->next_to_use; 2771 req_id = tx_ring->free_tx_ids[next_to_use]; 2772 tx_info = &tx_ring->tx_buffer_info[req_id]; 2773 2774 tx_info->mbuf = *mbuf; 2775 tx_info->num_of_bufs = 0; 2776 2777 ena_buf = tx_info->bufs; 2778 2779 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes", (*mbuf)->m_pkthdr.len); 2780 2781 push_len = 0; 2782 /* 2783 * header_len is just a hint for the device. Because FreeBSD is not 2784 * giving us information about packet header length and it is not 2785 * guaranteed that all packet headers will be in the 1st mbuf, setting 2786 * header_len to 0 is making the device ignore this value and resolve 2787 * header on it's own. 2788 */ 2789 header_len = 0; 2790 push_hdr = NULL; 2791 2792 rc = bus_dmamap_load_mbuf_sg(adapter->tx_buf_tag, tx_info->map, 2793 *mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 2794 2795 if (unlikely((rc != 0) || (nsegs == 0))) { 2796 ena_trace(ENA_WARNING, 2797 "dmamap load failed! err: %d nsegs: %d", rc, nsegs); 2798 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 2799 tx_info->mbuf = NULL; 2800 if (rc == ENOMEM) 2801 return (ENA_COM_NO_MEM); 2802 else 2803 return (ENA_COM_INVAL); 2804 } 2805 2806 for (i = 0; i < nsegs; i++) { 2807 ena_buf->len = segs[i].ds_len; 2808 ena_buf->paddr = segs[i].ds_addr; 2809 ena_buf++; 2810 } 2811 tx_info->num_of_bufs = nsegs; 2812 2813 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2814 ena_tx_ctx.ena_bufs = tx_info->bufs; 2815 ena_tx_ctx.push_header = push_hdr; 2816 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2817 ena_tx_ctx.req_id = req_id; 2818 ena_tx_ctx.header_len = header_len; 2819 2820 /* Set flags and meta data */ 2821 ena_tx_csum(&ena_tx_ctx, *mbuf); 2822 /* Prepare the packet's descriptors and send them to device */ 2823 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 2824 if (unlikely(rc != 0)) { 2825 ena_trace(ENA_DBG | ENA_TXPTH, "failed to prepare tx bufs\n"); 2826 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 2827 goto dma_error; 2828 } 2829 2830 counter_enter(); 2831 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 2832 counter_u64_add_protected(tx_ring->tx_stats.bytes, 2833 (*mbuf)->m_pkthdr.len); 2834 2835 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 2836 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 2837 (*mbuf)->m_pkthdr.len); 2838 counter_exit(); 2839 2840 tx_info->tx_descs = nb_hw_desc; 2841 getbinuptime(&tx_info->timestamp); 2842 tx_info->print_once = true; 2843 2844 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2845 tx_ring->ring_size); 2846 2847 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->map, 2848 BUS_DMASYNC_PREWRITE); 2849 2850 return (0); 2851 2852dma_error: 2853 tx_info->mbuf = NULL; 2854 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->map); 2855 2856 return (rc); 2857} 2858 2859static void 2860ena_start_xmit(struct ena_ring *tx_ring) 2861{ 2862 struct mbuf *mbuf; 2863 struct ena_adapter *adapter = tx_ring->adapter; 2864 struct ena_com_io_sq* io_sq; 2865 int ena_qid; 2866 int acum_pkts = 0; 2867 int ret = 0; 2868 2869 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0)) 2870 return; 2871 2872 if (unlikely(!adapter->link_status)) 2873 return; 2874 2875 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2876 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 2877 2878 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 2879 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 2880 " header csum flags %#jx", 2881 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 2882 2883 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 2884 ENA_TX_CLEANUP_THRESHOLD))) 2885 ena_tx_cleanup(tx_ring); 2886 2887 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 2888 if (ret == ENA_COM_NO_MEM) { 2889 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2890 } else if (ret == ENA_COM_NO_SPACE) { 2891 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2892 } else { 2893 m_freem(mbuf); 2894 drbr_advance(adapter->ifp, tx_ring->br); 2895 } 2896 2897 break; 2898 } 2899 2900 drbr_advance(adapter->ifp, tx_ring->br); 2901 2902 if (unlikely((if_getdrvflags(adapter->ifp) & 2903 IFF_DRV_RUNNING) == 0)) 2904 return; 2905 2906 acum_pkts++; 2907 2908 BPF_MTAP(adapter->ifp, mbuf); 2909 2910 if (unlikely(acum_pkts == DB_THRESHOLD)) { 2911 acum_pkts = 0; 2912 wmb(); 2913 /* Trigger the dma engine */ 2914 ena_com_write_sq_doorbell(io_sq); 2915 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2916 } 2917 2918 } 2919 2920 if (likely(acum_pkts != 0)) { 2921 wmb(); 2922 /* Trigger the dma engine */ 2923 ena_com_write_sq_doorbell(io_sq); 2924 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2925 } 2926 2927 if (!ena_com_sq_have_enough_space(io_sq, ENA_TX_CLEANUP_THRESHOLD)) 2928 ena_tx_cleanup(tx_ring); 2929} 2930 2931static void 2932ena_deferred_mq_start(void *arg, int pending) 2933{ 2934 struct ena_ring *tx_ring = (struct ena_ring *)arg; 2935 struct ifnet *ifp = tx_ring->adapter->ifp; 2936 2937 while (!drbr_empty(ifp, tx_ring->br) && 2938 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2939 ENA_RING_MTX_LOCK(tx_ring); 2940 ena_start_xmit(tx_ring); 2941 ENA_RING_MTX_UNLOCK(tx_ring); 2942 } 2943} 2944 2945static int 2946ena_mq_start(if_t ifp, struct mbuf *m) 2947{ 2948 struct ena_adapter *adapter = ifp->if_softc; 2949 struct ena_ring *tx_ring; 2950 int ret, is_drbr_empty; 2951 uint32_t i; 2952 2953 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0)) 2954 return (ENODEV); 2955 2956 /* Which queue to use */ 2957 /* 2958 * If everything is setup correctly, it should be the 2959 * same bucket that the current CPU we're on is. 2960 * It should improve performance. 2961 */ 2962 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 2963#ifdef RSS 2964 if (rss_hash2bucket(m->m_pkthdr.flowid, 2965 M_HASHTYPE_GET(m), &i) == 0) { 2966 i = i % adapter->num_queues; 2967 2968 } else 2969#endif 2970 { 2971 i = m->m_pkthdr.flowid % adapter->num_queues; 2972 } 2973 } else { 2974 i = curcpu % adapter->num_queues; 2975 } 2976 tx_ring = &adapter->tx_ring[i]; 2977 2978 /* Check if drbr is empty before putting packet */ 2979 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 2980 ret = drbr_enqueue(ifp, tx_ring->br, m); 2981 if (unlikely(ret != 0)) { 2982 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 2983 return (ret); 2984 } 2985 2986 if ((is_drbr_empty != 0) && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 2987 ena_start_xmit(tx_ring); 2988 ENA_RING_MTX_UNLOCK(tx_ring); 2989 } else { 2990 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 2991 } 2992 2993 return (0); 2994} 2995 2996static void 2997ena_qflush(if_t ifp) 2998{ 2999 struct ena_adapter *adapter = ifp->if_softc; 3000 struct ena_ring *tx_ring = adapter->tx_ring; 3001 int i; 3002 3003 for(i = 0; i < adapter->num_queues; ++i, ++tx_ring) 3004 if (!drbr_empty(ifp, tx_ring->br)) { 3005 ENA_RING_MTX_LOCK(tx_ring); 3006 drbr_flush(ifp, tx_ring->br); 3007 ENA_RING_MTX_UNLOCK(tx_ring); 3008 } 3009 3010 if_qflush(ifp); 3011} 3012 3013static int 3014ena_calc_io_queue_num(struct ena_adapter *adapter, 3015 struct ena_com_dev_get_features_ctx *get_feat_ctx) 3016{ 3017 int io_sq_num, io_cq_num, io_queue_num; 3018 3019 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 3020 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 3021 3022 io_queue_num = min_t(int, mp_ncpus, ENA_MAX_NUM_IO_QUEUES); 3023 io_queue_num = min_t(int, io_queue_num, io_sq_num); 3024 io_queue_num = min_t(int, io_queue_num, io_cq_num); 3025 /* 1 IRQ for for mgmnt and 1 IRQ for each TX/RX pair */ 3026 io_queue_num = min_t(int, io_queue_num, 3027 pci_msix_count(adapter->pdev) - 1); 3028#ifdef RSS 3029 io_queue_num = min_t(int, io_queue_num, rss_getnumbuckets()); 3030#endif 3031 3032 return (io_queue_num); 3033} 3034 3035static int 3036ena_calc_queue_size(struct ena_adapter *adapter, uint16_t *max_tx_sgl_size, 3037 uint16_t *max_rx_sgl_size, struct ena_com_dev_get_features_ctx *feat) 3038{ 3039 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 3040 uint32_t v; 3041 uint32_t q; 3042 3043 queue_size = min_t(uint32_t, queue_size, 3044 feat->max_queues.max_cq_depth); 3045 queue_size = min_t(uint32_t, queue_size, 3046 feat->max_queues.max_sq_depth); 3047 3048 /* round down to the nearest power of 2 */ 3049 v = queue_size; 3050 while (v != 0) { 3051 if (powerof2(queue_size) != 0) 3052 break; 3053 v /= 2; 3054 q = rounddown2(queue_size, v); 3055 if (q != 0) { 3056 queue_size = q; 3057 break; 3058 } 3059 } 3060 3061 if (unlikely(queue_size == 0)) { 3062 device_printf(adapter->pdev, "Invalid queue size\n"); 3063 return (ENA_COM_FAULT); 3064 } 3065 3066 *max_tx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3067 feat->max_queues.max_packet_tx_descs); 3068 *max_rx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3069 feat->max_queues.max_packet_rx_descs); 3070 3071 return (queue_size); 3072} 3073 3074static int 3075ena_rss_init_default(struct ena_adapter *adapter) 3076{ 3077 struct ena_com_dev *ena_dev = adapter->ena_dev; 3078 device_t dev = adapter->pdev; 3079 int qid, rc, i; 3080 3081 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3082 if (unlikely(rc != 0)) { 3083 device_printf(dev, "Cannot init indirect table\n"); 3084 return (rc); 3085 } 3086 3087 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3088#ifdef RSS 3089 qid = rss_get_indirection_to_bucket(i); 3090 qid = qid % adapter->num_queues; 3091#else 3092 qid = i % adapter->num_queues; 3093#endif 3094 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3095 ENA_IO_RXQ_IDX(qid)); 3096 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3097 device_printf(dev, "Cannot fill indirect table\n"); 3098 goto err_rss_destroy; 3099 } 3100 } 3101 3102 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3103 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3104 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3105 device_printf(dev, "Cannot fill hash function\n"); 3106 goto err_rss_destroy; 3107 } 3108 3109 rc = ena_com_set_default_hash_ctrl(ena_dev); 3110 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3111 device_printf(dev, "Cannot fill hash control\n"); 3112 goto err_rss_destroy; 3113 } 3114 3115 return (0); 3116 3117err_rss_destroy: 3118 ena_com_rss_destroy(ena_dev); 3119 return (rc); 3120} 3121 3122static void 3123ena_rss_init_default_deferred(void *arg) 3124{ 3125 struct ena_adapter *adapter; 3126 devclass_t dc; 3127 int max; 3128 int rc; 3129 3130 dc = devclass_find("ena"); 3131 if (unlikely(dc == NULL)) { 3132 ena_trace(ENA_ALERT, "No devclass ena\n"); 3133 return; 3134 } 3135 3136 max = devclass_get_maxunit(dc); 3137 while (max-- >= 0) { 3138 adapter = devclass_get_softc(dc, max); 3139 if (adapter != NULL) { 3140 rc = ena_rss_init_default(adapter); 3141 adapter->rss_support = true; 3142 if (unlikely(rc != 0)) { 3143 device_printf(adapter->pdev, 3144 "WARNING: RSS was not properly initialized," 3145 " it will affect bandwidth\n"); 3146 adapter->rss_support = false; 3147 } 3148 } 3149 } 3150} 3151SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL); 3152 3153static void 3154ena_config_host_info(struct ena_com_dev *ena_dev) 3155{ 3156 struct ena_admin_host_info *host_info; 3157 int rc; 3158 3159 /* Allocate only the host info */ 3160 rc = ena_com_allocate_host_info(ena_dev); 3161 if (unlikely(rc != 0)) { 3162 ena_trace(ENA_ALERT, "Cannot allocate host info\n"); 3163 return; 3164 } 3165 3166 host_info = ena_dev->host_attr.host_info; 3167 3168 host_info->os_type = ENA_ADMIN_OS_FREEBSD; 3169 host_info->kernel_ver = osreldate; 3170 3171 sprintf(host_info->kernel_ver_str, "%d", osreldate); 3172 host_info->os_dist = 0; 3173 strncpy(host_info->os_dist_str, osrelease, 3174 sizeof(host_info->os_dist_str) - 1); 3175 3176 host_info->driver_version = 3177 (DRV_MODULE_VER_MAJOR) | 3178 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 3179 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 3180 3181 rc = ena_com_set_host_attributes(ena_dev); 3182 if (unlikely(rc != 0)) { 3183 if (rc == EOPNOTSUPP) 3184 ena_trace(ENA_WARNING, "Cannot set host attributes\n"); 3185 else 3186 ena_trace(ENA_ALERT, "Cannot set host attributes\n"); 3187 3188 goto err; 3189 } 3190 3191 return; 3192 3193err: 3194 ena_com_delete_host_info(ena_dev); 3195} 3196 3197static int 3198ena_device_init(struct ena_adapter *adapter, device_t pdev, 3199 struct ena_com_dev_get_features_ctx *get_feat_ctx, int *wd_active) 3200{ 3201 struct ena_com_dev* ena_dev = adapter->ena_dev; 3202 bool readless_supported; 3203 uint32_t aenq_groups; 3204 int dma_width; 3205 int rc; 3206 3207 rc = ena_com_mmio_reg_read_request_init(ena_dev); 3208 if (unlikely(rc != 0)) { 3209 device_printf(pdev, "failed to init mmio read less\n"); 3210 return (rc); 3211 } 3212 3213 /* 3214 * The PCIe configuration space revision id indicate if mmio reg 3215 * read is disabled 3216 */ 3217 readless_supported = !(pci_get_revid(pdev) & ENA_MMIO_DISABLE_REG_READ); 3218 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 3219 3220 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 3221 if (unlikely(rc != 0)) { 3222 device_printf(pdev, "Can not reset device\n"); 3223 goto err_mmio_read_less; 3224 } 3225 3226 rc = ena_com_validate_version(ena_dev); 3227 if (unlikely(rc != 0)) { 3228 device_printf(pdev, "device version is too low\n"); 3229 goto err_mmio_read_less; 3230 } 3231 3232 dma_width = ena_com_get_dma_width(ena_dev); 3233 if (unlikely(dma_width < 0)) { 3234 device_printf(pdev, "Invalid dma width value %d", dma_width); 3235 rc = dma_width; 3236 goto err_mmio_read_less; 3237 } 3238 adapter->dma_width = dma_width; 3239 3240 /* ENA admin level init */ 3241 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 3242 if (unlikely(rc != 0)) { 3243 device_printf(pdev, 3244 "Can not initialize ena admin queue with device\n"); 3245 goto err_mmio_read_less; 3246 } 3247 3248 /* 3249 * To enable the msix interrupts the driver needs to know the number 3250 * of queues. So the driver uses polling mode to retrieve this 3251 * information 3252 */ 3253 ena_com_set_admin_polling_mode(ena_dev, true); 3254 3255 ena_config_host_info(ena_dev); 3256 3257 /* Get Device Attributes */ 3258 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 3259 if (unlikely(rc != 0)) { 3260 device_printf(pdev, 3261 "Cannot get attribute for ena device rc: %d\n", rc); 3262 goto err_admin_init; 3263 } 3264 3265 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT(ENA_ADMIN_KEEP_ALIVE); 3266 3267 aenq_groups &= get_feat_ctx->aenq.supported_groups; 3268 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 3269 if (unlikely(rc != 0)) { 3270 device_printf(pdev, "Cannot configure aenq groups rc: %d\n", rc); 3271 goto err_admin_init; 3272 } 3273 3274 *wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 3275 3276 return (0); 3277 3278err_admin_init: 3279 ena_com_delete_host_info(ena_dev); 3280 ena_com_admin_destroy(ena_dev); 3281err_mmio_read_less: 3282 ena_com_mmio_reg_read_request_destroy(ena_dev); 3283 3284 return (rc); 3285} 3286 3287static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 3288 int io_vectors) 3289{ 3290 struct ena_com_dev *ena_dev = adapter->ena_dev; 3291 int rc; 3292 3293 rc = ena_enable_msix(adapter); 3294 if (unlikely(rc != 0)) { 3295 device_printf(adapter->pdev, "Error with MSI-X enablement\n"); 3296 return (rc); 3297 } 3298 3299 ena_setup_mgmnt_intr(adapter); 3300 3301 rc = ena_request_mgmnt_irq(adapter); 3302 if (unlikely(rc != 0)) { 3303 device_printf(adapter->pdev, "Cannot setup mgmnt queue intr\n"); 3304 goto err_disable_msix; 3305 } 3306 3307 ena_com_set_admin_polling_mode(ena_dev, false); 3308 3309 ena_com_admin_aenq_enable(ena_dev); 3310 3311 return (0); 3312 3313err_disable_msix: 3314 ena_disable_msix(adapter); 3315 3316 return (rc); 3317} 3318 3319/* Function called on ENA_ADMIN_KEEP_ALIVE event */ 3320static void ena_keep_alive_wd(void *adapter_data, 3321 struct ena_admin_aenq_entry *aenq_e) 3322{ 3323 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3324 struct ena_admin_aenq_keep_alive_desc *desc; 3325 sbintime_t stime; 3326 uint64_t rx_drops; 3327 3328 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3329 3330 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3331 counter_u64_zero(adapter->hw_stats.rx_drops); 3332 counter_u64_add(adapter->hw_stats.rx_drops, rx_drops); 3333 3334 stime = getsbinuptime(); 3335 atomic_store_rel_64(&adapter->keep_alive_timestamp, stime); 3336} 3337 3338/* Check for keep alive expiration */ 3339static void check_for_missing_keep_alive(struct ena_adapter *adapter) 3340{ 3341 sbintime_t timestamp, time; 3342 3343 if (adapter->wd_active == 0) 3344 return; 3345 3346 if (likely(adapter->keep_alive_timeout == 0)) 3347 return; 3348 3349 timestamp = atomic_load_acq_64(&adapter->keep_alive_timestamp); 3350 time = getsbinuptime() - timestamp; 3351 if (unlikely(time > adapter->keep_alive_timeout)) { 3352 device_printf(adapter->pdev, 3353 "Keep alive watchdog timeout.\n"); 3354 counter_u64_add(adapter->dev_stats.wd_expired, 1); 3355 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 3356 adapter->trigger_reset = true; 3357 } 3358} 3359 3360/* Check if admin queue is enabled */ 3361static void check_for_admin_com_state(struct ena_adapter *adapter) 3362{ 3363 if (unlikely(ena_com_get_admin_running_state(adapter->ena_dev) == 3364 false)) { 3365 device_printf(adapter->pdev, 3366 "ENA admin queue is not in running state!\n"); 3367 counter_u64_add(adapter->dev_stats.admin_q_pause, 1); 3368 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 3369 adapter->trigger_reset = true; 3370 } 3371} 3372 3373static int 3374check_missing_comp_in_queue(struct ena_adapter *adapter, 3375 struct ena_ring *tx_ring) 3376{ 3377 struct bintime curtime, time; 3378 struct ena_tx_buffer *tx_buf; 3379 uint32_t missed_tx = 0; 3380 int i; 3381 3382 getbinuptime(&curtime); 3383 3384 for (i = 0; i < tx_ring->ring_size; i++) { 3385 tx_buf = &tx_ring->tx_buffer_info[i]; 3386 3387 if (bintime_isset(&tx_buf->timestamp) == 0) 3388 continue; 3389 3390 time = curtime; 3391 bintime_sub(&time, &tx_buf->timestamp); 3392 3393 /* Check again if packet is still waiting */ 3394 if (unlikely(bttosbt(time) > adapter->missing_tx_timeout)) { 3395 3396 if (!tx_buf->print_once) 3397 ena_trace(ENA_WARNING, "Found a Tx that wasn't " 3398 "completed on time, qid %d, index %d.\n", 3399 tx_ring->qid, i); 3400 3401 tx_buf->print_once = true; 3402 missed_tx++; 3403 counter_u64_add(tx_ring->tx_stats.missing_tx_comp, 1); 3404 3405 if (unlikely(missed_tx > 3406 adapter->missing_tx_threshold)) { 3407 device_printf(adapter->pdev, 3408 "The number of lost tx completion " 3409 "is above the threshold (%d > %d). " 3410 "Reset the device\n", 3411 missed_tx, adapter->missing_tx_threshold); 3412 adapter->reset_reason = 3413 ENA_REGS_RESET_MISS_TX_CMPL; 3414 adapter->trigger_reset = true; 3415 return (EIO); 3416 } 3417 } 3418 } 3419 3420 return (0); 3421} 3422 3423/* 3424 * Check for TX which were not completed on time. 3425 * Timeout is defined by "missing_tx_timeout". 3426 * Reset will be performed if number of incompleted 3427 * transactions exceeds "missing_tx_threshold". 3428 */ 3429static void 3430check_for_missing_tx_completions(struct ena_adapter *adapter) 3431{ 3432 struct ena_ring *tx_ring; 3433 int i, budget, rc; 3434 3435 /* Make sure the driver doesn't turn the device in other process */ 3436 rmb(); 3437 3438 if (!adapter->up) 3439 return; 3440 3441 if (adapter->trigger_reset) 3442 return; 3443 3444 if (adapter->missing_tx_timeout == 0) 3445 return; 3446 3447 budget = adapter->missing_tx_max_queues; 3448 3449 for (i = adapter->next_monitored_tx_qid; i < adapter->num_queues; i++) { 3450 tx_ring = &adapter->tx_ring[i]; 3451 3452 rc = check_missing_comp_in_queue(adapter, tx_ring); 3453 if (unlikely(rc != 0)) 3454 return; 3455 3456 budget--; 3457 if (budget == 0) { 3458 i++; 3459 break; 3460 } 3461 } 3462 3463 adapter->next_monitored_tx_qid = i % adapter->num_queues; 3464} 3465 3466/* trigger deferred rx cleanup after 2 consecutive detections */ 3467#define EMPTY_RX_REFILL 2 3468/* For the rare case where the device runs out of Rx descriptors and the 3469 * msix handler failed to refill new Rx descriptors (due to a lack of memory 3470 * for example). 3471 * This case will lead to a deadlock: 3472 * The device won't send interrupts since all the new Rx packets will be dropped 3473 * The msix handler won't allocate new Rx descriptors so the device won't be 3474 * able to send new packets. 3475 * 3476 * When such a situation is detected - execute rx cleanup task in another thread 3477 */ 3478static void 3479check_for_empty_rx_ring(struct ena_adapter *adapter) 3480{ 3481 struct ena_ring *rx_ring; 3482 int i, refill_required; 3483 3484 if (!adapter->up) 3485 return; 3486 3487 if (adapter->trigger_reset) 3488 return; 3489 3490 for (i = 0; i < adapter->num_queues; i++) { 3491 rx_ring = &adapter->rx_ring[i]; 3492 3493 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 3494 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 3495 rx_ring->empty_rx_queue++; 3496 3497 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 3498 counter_u64_add(rx_ring->rx_stats.empty_rx_ring, 3499 1); 3500 3501 device_printf(adapter->pdev, 3502 "trigger refill for ring %d\n", i); 3503 3504 taskqueue_enqueue(rx_ring->cmpl_tq, 3505 &rx_ring->cmpl_task); 3506 rx_ring->empty_rx_queue = 0; 3507 } 3508 } else { 3509 rx_ring->empty_rx_queue = 0; 3510 } 3511 } 3512} 3513 3514static void 3515ena_timer_service(void *data) 3516{ 3517 struct ena_adapter *adapter = (struct ena_adapter *)data; 3518 struct ena_admin_host_info *host_info = 3519 adapter->ena_dev->host_attr.host_info; 3520 3521 check_for_missing_keep_alive(adapter); 3522 3523 check_for_admin_com_state(adapter); 3524 3525 check_for_missing_tx_completions(adapter); 3526 3527 check_for_empty_rx_ring(adapter); 3528 3529 if (host_info != NULL) 3530 ena_update_host_info(host_info, adapter->ifp); 3531 3532 if (unlikely(adapter->trigger_reset)) { 3533 device_printf(adapter->pdev, "Trigger reset is on\n"); 3534 taskqueue_enqueue(adapter->reset_tq, &adapter->reset_task); 3535 return; 3536 } 3537 3538 /* 3539 * Schedule another timeout one second from now. 3540 */ 3541 callout_schedule_sbt(&adapter->timer_service, SBT_1S, SBT_1S, 0); 3542} 3543 3544static void 3545ena_reset_task(void *arg, int pending) 3546{ 3547 struct ena_com_dev_get_features_ctx get_feat_ctx; 3548 struct ena_adapter *adapter = (struct ena_adapter *)arg; 3549 struct ena_com_dev *ena_dev = adapter->ena_dev; 3550 bool dev_up; 3551 int rc; 3552 3553 if (unlikely(!adapter->trigger_reset)) { 3554 device_printf(adapter->pdev, 3555 "device reset scheduled but trigger_reset is off\n"); 3556 return; 3557 } 3558 3559 sx_xlock(&adapter->ioctl_sx); 3560 3561 callout_drain(&adapter->timer_service); 3562 3563 dev_up = adapter->up; 3564 3565 ena_com_set_admin_running_state(ena_dev, false); 3566 ena_down(adapter); 3567 ena_free_mgmnt_irq(adapter); 3568 ena_disable_msix(adapter); 3569 ena_com_abort_admin_commands(ena_dev); 3570 ena_com_wait_for_abort_completion(ena_dev); 3571 ena_com_admin_destroy(ena_dev); 3572 ena_com_mmio_reg_read_request_destroy(ena_dev); 3573 3574 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3575 adapter->trigger_reset = false; 3576 3577 /* Finished destroy part. Restart the device */ 3578 rc = ena_device_init(adapter, adapter->pdev, &get_feat_ctx, 3579 &adapter->wd_active); 3580 if (unlikely(rc != 0)) { 3581 device_printf(adapter->pdev, 3582 "ENA device init failed! (err: %d)\n", rc); 3583 goto err_dev_free; 3584 } 3585 3586 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 3587 adapter->num_queues); 3588 if (unlikely(rc != 0)) { 3589 device_printf(adapter->pdev, "Enable MSI-X failed\n"); 3590 goto err_com_free; 3591 } 3592 3593 /* If the interface was up before the reset bring it up */ 3594 if (dev_up) { 3595 rc = ena_up(adapter); 3596 if (unlikely(rc != 0)) { 3597 device_printf(adapter->pdev, 3598 "Failed to create I/O queues\n"); 3599 goto err_msix_free; 3600 } 3601 } 3602 3603 callout_reset_sbt(&adapter->timer_service, SBT_1S, SBT_1S, 3604 ena_timer_service, (void *)adapter, 0); 3605 3606 sx_unlock(&adapter->ioctl_sx); 3607 3608 return; 3609 3610err_msix_free: 3611 ena_free_mgmnt_irq(adapter); 3612 ena_disable_msix(adapter); 3613err_com_free: 3614 ena_com_admin_destroy(ena_dev); 3615err_dev_free: 3616 device_printf(adapter->pdev, "ENA reset failed!\n"); 3617 adapter->running = false; 3618 sx_unlock(&adapter->ioctl_sx); 3619} 3620 3621/** 3622 * ena_attach - Device Initialization Routine 3623 * @pdev: device information struct 3624 * 3625 * Returns 0 on success, otherwise on failure. 3626 * 3627 * ena_attach initializes an adapter identified by a device structure. 3628 * The OS initialization, configuring of the adapter private structure, 3629 * and a hardware reset occur. 3630 **/ 3631static int 3632ena_attach(device_t pdev) 3633{ 3634 struct ena_com_dev_get_features_ctx get_feat_ctx; 3635 static int version_printed; 3636 struct ena_adapter *adapter; 3637 struct ena_com_dev *ena_dev = NULL; 3638 uint16_t tx_sgl_size = 0; 3639 uint16_t rx_sgl_size = 0; 3640 int io_queue_num; 3641 int queue_size; 3642 int rc; 3643 adapter = device_get_softc(pdev); 3644 adapter->pdev = pdev; 3645 3646 mtx_init(&adapter->global_mtx, "ENA global mtx", NULL, MTX_DEF); 3647 sx_init(&adapter->ioctl_sx, "ENA ioctl sx"); 3648 3649 /* Set up the timer service */ 3650 callout_init_mtx(&adapter->timer_service, &adapter->global_mtx, 0); 3651 adapter->keep_alive_timeout = DEFAULT_KEEP_ALIVE_TO; 3652 adapter->missing_tx_timeout = DEFAULT_TX_CMP_TO; 3653 adapter->missing_tx_max_queues = DEFAULT_TX_MONITORED_QUEUES; 3654 adapter->missing_tx_threshold = DEFAULT_TX_CMP_THRESHOLD; 3655 3656 if (version_printed++ == 0) 3657 device_printf(pdev, "%s\n", ena_version); 3658 3659 rc = ena_allocate_pci_resources(adapter); 3660 if (unlikely(rc != 0)) { 3661 device_printf(pdev, "PCI resource allocation failed!\n"); 3662 ena_free_pci_resources(adapter); 3663 return (rc); 3664 } 3665 3666 /* Allocate memory for ena_dev structure */ 3667 ena_dev = malloc(sizeof(struct ena_com_dev), M_DEVBUF, 3668 M_WAITOK | M_ZERO); 3669 3670 adapter->ena_dev = ena_dev; 3671 ena_dev->dmadev = pdev; 3672 ena_dev->bus = malloc(sizeof(struct ena_bus), M_DEVBUF, 3673 M_WAITOK | M_ZERO); 3674 3675 /* Store register resources */ 3676 ((struct ena_bus*)(ena_dev->bus))->reg_bar_t = 3677 rman_get_bustag(adapter->registers); 3678 ((struct ena_bus*)(ena_dev->bus))->reg_bar_h = 3679 rman_get_bushandle(adapter->registers); 3680 3681 if (unlikely(((struct ena_bus*)(ena_dev->bus))->reg_bar_h == 0)) { 3682 device_printf(pdev, "failed to pmap registers bar\n"); 3683 rc = ENXIO; 3684 goto err_bus_free; 3685 } 3686 3687 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3688 3689 /* Device initialization */ 3690 rc = ena_device_init(adapter, pdev, &get_feat_ctx, &adapter->wd_active); 3691 if (unlikely(rc != 0)) { 3692 device_printf(pdev, "ENA device init failed! (err: %d)\n", rc); 3693 rc = ENXIO; 3694 goto err_bus_free; 3695 } 3696 3697 adapter->keep_alive_timestamp = getsbinuptime(); 3698 3699 adapter->tx_offload_cap = get_feat_ctx.offload.tx; 3700 3701 /* Set for sure that interface is not up */ 3702 adapter->up = false; 3703 3704 memcpy(adapter->mac_addr, get_feat_ctx.dev_attr.mac_addr, 3705 ETHER_ADDR_LEN); 3706 3707 /* calculate IO queue number to create */ 3708 io_queue_num = ena_calc_io_queue_num(adapter, &get_feat_ctx); 3709 3710 ENA_ASSERT(io_queue_num > 0, "Invalid queue number: %d\n", 3711 io_queue_num); 3712 adapter->num_queues = io_queue_num; 3713 3714 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 3715 3716 /* calculatre ring sizes */ 3717 queue_size = ena_calc_queue_size(adapter,&tx_sgl_size, 3718 &rx_sgl_size, &get_feat_ctx); 3719 if (unlikely((queue_size <= 0) || (io_queue_num <= 0))) { 3720 rc = ENA_COM_FAULT; 3721 goto err_com_free; 3722 } 3723 3724 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3725 3726 adapter->tx_ring_size = queue_size; 3727 adapter->rx_ring_size = queue_size; 3728 3729 adapter->max_tx_sgl_size = tx_sgl_size; 3730 adapter->max_rx_sgl_size = rx_sgl_size; 3731 3732 /* set up dma tags for rx and tx buffers */ 3733 rc = ena_setup_tx_dma_tag(adapter); 3734 if (unlikely(rc != 0)) { 3735 device_printf(pdev, "Failed to create TX DMA tag\n"); 3736 goto err_com_free; 3737 } 3738 3739 rc = ena_setup_rx_dma_tag(adapter); 3740 if (unlikely(rc != 0)) { 3741 device_printf(pdev, "Failed to create RX DMA tag\n"); 3742 goto err_tx_tag_free; 3743 } 3744 3745 /* initialize rings basic information */ 3746 device_printf(pdev, "initalize %d io queues\n", io_queue_num); 3747 ena_init_io_rings(adapter); 3748 3749 /* setup network interface */ 3750 rc = ena_setup_ifnet(pdev, adapter, &get_feat_ctx); 3751 if (unlikely(rc != 0)) { 3752 device_printf(pdev, "Error with network interface setup\n"); 3753 goto err_io_free; 3754 } 3755 3756 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3757 if (unlikely(rc != 0)) { 3758 device_printf(pdev, 3759 "Failed to enable and set the admin interrupts\n"); 3760 goto err_ifp_free; 3761 } 3762 3763 /* Initialize reset task queue */ 3764 TASK_INIT(&adapter->reset_task, 0, ena_reset_task, adapter); 3765 adapter->reset_tq = taskqueue_create("ena_reset_enqueue", 3766 M_WAITOK | M_ZERO, taskqueue_thread_enqueue, &adapter->reset_tq); 3767 taskqueue_start_threads(&adapter->reset_tq, 1, PI_NET, 3768 "%s rstq", device_get_nameunit(adapter->pdev)); 3769 3770 /* Initialize statistics */ 3771 ena_alloc_counters((counter_u64_t *)&adapter->dev_stats, 3772 sizeof(struct ena_stats_dev)); 3773 ena_alloc_counters((counter_u64_t *)&adapter->hw_stats, 3774 sizeof(struct ena_hw_stats)); 3775 ena_sysctl_add_nodes(adapter); 3776 3777 /* Tell the stack that the interface is not active */ 3778 if_setdrvflagbits(adapter->ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 3779 3780 adapter->running = true; 3781 return (0); 3782 3783err_ifp_free: 3784 if_detach(adapter->ifp); 3785 if_free(adapter->ifp); 3786err_io_free: 3787 ena_free_all_io_rings_resources(adapter); 3788 ena_free_rx_dma_tag(adapter); 3789err_tx_tag_free: 3790 ena_free_tx_dma_tag(adapter); 3791err_com_free: 3792 ena_com_admin_destroy(ena_dev); 3793 ena_com_delete_host_info(ena_dev); 3794 ena_com_mmio_reg_read_request_destroy(ena_dev); 3795err_bus_free: 3796 free(ena_dev->bus, M_DEVBUF); 3797 free(ena_dev, M_DEVBUF); 3798 ena_free_pci_resources(adapter); 3799 3800 return (rc); 3801} 3802 3803/** 3804 * ena_detach - Device Removal Routine 3805 * @pdev: device information struct 3806 * 3807 * ena_detach is called by the device subsystem to alert the driver 3808 * that it should release a PCI device. 3809 **/ 3810static int 3811ena_detach(device_t pdev) 3812{ 3813 struct ena_adapter *adapter = device_get_softc(pdev); 3814 struct ena_com_dev *ena_dev = adapter->ena_dev; 3815 int rc; 3816 3817 /* Make sure VLANS are not using driver */ 3818 if (adapter->ifp->if_vlantrunk != NULL) { 3819 device_printf(adapter->pdev ,"VLAN is in use, detach first\n"); 3820 return (EBUSY); 3821 } 3822 3823 /* Free reset task and callout */ 3824 callout_drain(&adapter->timer_service); 3825 while (taskqueue_cancel(adapter->reset_tq, &adapter->reset_task, NULL)) 3826 taskqueue_drain(adapter->reset_tq, &adapter->reset_task); 3827 taskqueue_free(adapter->reset_tq); 3828 3829 sx_xlock(&adapter->ioctl_sx); 3830 ena_down(adapter); 3831 sx_unlock(&adapter->ioctl_sx); 3832 3833 if (adapter->ifp != NULL) { 3834 ether_ifdetach(adapter->ifp); 3835 if_free(adapter->ifp); 3836 } 3837 3838 ena_free_all_io_rings_resources(adapter); 3839 3840 ena_free_counters((counter_u64_t *)&adapter->hw_stats, 3841 sizeof(struct ena_hw_stats)); 3842 ena_free_counters((counter_u64_t *)&adapter->dev_stats, 3843 sizeof(struct ena_stats_dev)); 3844 3845 if (likely(adapter->rss_support)) 3846 ena_com_rss_destroy(ena_dev); 3847 3848 rc = ena_free_rx_dma_tag(adapter); 3849 if (unlikely(rc != 0)) 3850 device_printf(adapter->pdev, 3851 "Unmapped RX DMA tag associations\n"); 3852 3853 rc = ena_free_tx_dma_tag(adapter); 3854 if (unlikely(rc != 0)) 3855 device_printf(adapter->pdev, 3856 "Unmapped TX DMA tag associations\n"); 3857 3858 /* Reset the device only if the device is running. */ 3859 if (adapter->running) 3860 ena_com_dev_reset(ena_dev, adapter->reset_reason); 3861 3862 ena_com_delete_host_info(ena_dev); 3863 3864 ena_free_irqs(adapter); 3865 3866 ena_com_abort_admin_commands(ena_dev); 3867 3868 ena_com_wait_for_abort_completion(ena_dev); 3869 3870 ena_com_admin_destroy(ena_dev); 3871 3872 ena_com_mmio_reg_read_request_destroy(ena_dev); 3873 3874 ena_free_pci_resources(adapter); 3875 3876 mtx_destroy(&adapter->global_mtx); 3877 sx_destroy(&adapter->ioctl_sx); 3878 3879 if (ena_dev->bus != NULL) 3880 free(ena_dev->bus, M_DEVBUF); 3881 3882 if (ena_dev != NULL) 3883 free(ena_dev, M_DEVBUF); 3884 3885 return (bus_generic_detach(pdev)); 3886} 3887 3888/****************************************************************************** 3889 ******************************** AENQ Handlers ******************************* 3890 *****************************************************************************/ 3891/** 3892 * ena_update_on_link_change: 3893 * Notify the network interface about the change in link status 3894 **/ 3895static void 3896ena_update_on_link_change(void *adapter_data, 3897 struct ena_admin_aenq_entry *aenq_e) 3898{ 3899 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3900 struct ena_admin_aenq_link_change_desc *aenq_desc; 3901 int status; 3902 if_t ifp; 3903 3904 aenq_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3905 ifp = adapter->ifp; 3906 status = aenq_desc->flags & 3907 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3908 3909 if (status != 0) { 3910 device_printf(adapter->pdev, "link is UP\n"); 3911 if_link_state_change(ifp, LINK_STATE_UP); 3912 } else if (status == 0) { 3913 device_printf(adapter->pdev, "link is DOWN\n"); 3914 if_link_state_change(ifp, LINK_STATE_DOWN); 3915 } else { 3916 device_printf(adapter->pdev, "invalid value recvd\n"); 3917 BUG(); 3918 } 3919 3920 adapter->link_status = status; 3921} 3922 3923/** 3924 * This handler will called for unknown event group or unimplemented handlers 3925 **/ 3926static void 3927unimplemented_aenq_handler(void *data, 3928 struct ena_admin_aenq_entry *aenq_e) 3929{ 3930 return; 3931} 3932 3933static struct ena_aenq_handlers aenq_handlers = { 3934 .handlers = { 3935 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3936 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 3937 }, 3938 .unimplemented_handler = unimplemented_aenq_handler 3939}; 3940 3941/********************************************************************* 3942 * FreeBSD Device Interface Entry Points 3943 *********************************************************************/ 3944 3945static device_method_t ena_methods[] = { 3946 /* Device interface */ 3947 DEVMETHOD(device_probe, ena_probe), 3948 DEVMETHOD(device_attach, ena_attach), 3949 DEVMETHOD(device_detach, ena_detach), 3950 DEVMETHOD_END 3951}; 3952 3953static driver_t ena_driver = { 3954 "ena", ena_methods, sizeof(struct ena_adapter), 3955}; 3956 3957devclass_t ena_devclass; 3958DRIVER_MODULE(ena, pci, ena_driver, ena_devclass, 0, 0); 3959MODULE_PNP_INFO("U16:vendor;U16:device", pci, ena, ena_vendor_info_array, 3960 sizeof(ena_vendor_info_array[0]), nitems(ena_vendor_info_array) - 1); 3961MODULE_DEPEND(ena, pci, 1, 1, 1); 3962MODULE_DEPEND(ena, ether, 1, 1, 1); 3963 3964/*********************************************************************/ 3965