if_edvar.h revision 149840
1/*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/ed/if_edvar.h 149840 2005-09-07 03:20:33Z imp $ 28 */ 29 30#ifndef SYS_DEV_ED_IF_EDVAR_H 31#define SYS_DEV_ED_IF_EDVAR_H 32/* 33 * ed_softc: per line info and status 34 */ 35struct ed_softc { 36 struct ifnet *ifp; 37 struct ifmedia ifmedia; /* Media info */ 38 device_t dev; 39 struct mtx sc_mtx; 40 41 char *type_str; /* pointer to type string */ 42 u_char vendor; /* interface vendor */ 43 u_char type; /* interface type code */ 44 u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */ 45 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 46 u_char mem_shared; /* NIC memory is shared with host */ 47 u_char xmit_busy; /* transmitter is busy */ 48 u_char enaddr[6]; 49 50 int port_rid; /* resource id for port range */ 51 int port_used; /* nonzero if ports used */ 52 struct resource* port_res; /* resource for port range */ 53 bus_space_tag_t port_bst; 54 bus_space_handle_t port_bsh; 55 int mem_rid; /* resource id for memory range */ 56 int mem_used; /* nonzero if memory used */ 57 struct resource* mem_res; /* resource for memory range */ 58 bus_space_tag_t mem_bst; 59 bus_space_handle_t mem_bsh; 60 int irq_rid; /* resource id for irq */ 61 struct resource* irq_res; /* resource for irq */ 62 void* irq_handle; /* handle for irq handler */ 63 int modem_rid; /* resource ID for modem part of device */ 64 device_t miibus; /* MII bus for cards with MII. */ 65 void (*mii_writebits)(struct ed_softc *, u_int, int); 66 u_int (*mii_readbits)(struct ed_softc *, int); 67 struct callout tick_ch; 68 void (*readmem)(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 69 uint16_t amount); 70 71 int nic_offset; /* NIC (DS8390) I/O bus address offset */ 72 int asic_offset; /* ASIC I/O bus address offset */ 73 74/* 75 * The following 'proto' variable is part of a work-around for 8013EBT asics 76 * being write-only. It's sort of a prototype/shadow of the real thing. 77 */ 78 u_char wd_laar_proto; 79 u_char cr_proto; 80 81/* 82 * HP PC LAN PLUS card support. 83 */ 84 85 u_short hpp_options; /* flags controlling behaviour of the HP card */ 86 u_short hpp_id; /* software revision and other fields */ 87 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 88 89 bus_size_t mem_start; /* NIC memory start address */ 90 bus_size_t mem_end; /* NIC memory end address */ 91 uint32_t mem_size; /* total NIC memory size */ 92 bus_size_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 93 94 u_char txb_cnt; /* number of transmit buffers */ 95 u_char txb_inuse; /* number of TX buffers currently in-use */ 96 97 u_char txb_new; /* pointer to where new buffer will be added */ 98 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 99 u_short txb_len[8]; /* buffered xmit buffer lengths */ 100 u_char tx_page_start; /* first page of TX buffer area */ 101 u_char rec_page_start; /* first page of RX ring-buffer */ 102 u_char rec_page_stop; /* last page of RX ring-buffer */ 103 u_char next_packet; /* pointer to next unread RX packet */ 104 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 105}; 106 107#define ed_nic_inb(sc, port) \ 108 bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 109 110#define ed_nic_outb(sc, port, value) \ 111 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 112 (sc)->nic_offset + (port), (value)) 113 114#define ed_nic_inw(sc, port) \ 115 bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 116 117#define ed_nic_outw(sc, port, value) \ 118 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 119 (sc)->nic_offset + (port), (value)) 120 121#define ed_nic_insb(sc, port, addr, count) \ 122 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 123 (sc)->nic_offset + (port), (addr), (count)) 124 125#define ed_nic_outsb(sc, port, addr, count) \ 126 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 127 (sc)->nic_offset + (port), (addr), (count)) 128 129#define ed_nic_insw(sc, port, addr, count) \ 130 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 131 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 132 133#define ed_nic_outsw(sc, port, addr, count) \ 134 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 135 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 136 137#define ed_nic_insl(sc, port, addr, count) \ 138 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 139 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 140 141#define ed_nic_outsl(sc, port, addr, count) \ 142 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 143 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 144 145#define ed_asic_inb(sc, port) \ 146 bus_space_read_1(sc->port_bst, sc->port_bsh, \ 147 (sc)->asic_offset + (port)) 148 149#define ed_asic_outb(sc, port, value) \ 150 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 151 (sc)->asic_offset + (port), (value)) 152 153#define ed_asic_inw(sc, port) \ 154 bus_space_read_2(sc->port_bst, sc->port_bsh, \ 155 (sc)->asic_offset + (port)) 156 157#define ed_asic_outw(sc, port, value) \ 158 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 159 (sc)->asic_offset + (port), (value)) 160 161#define ed_asic_insb(sc, port, addr, count) \ 162 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 163 (sc)->asic_offset + (port), (addr), (count)) 164 165#define ed_asic_outsb(sc, port, addr, count) \ 166 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 167 (sc)->asic_offset + (port), (addr), (count)) 168 169#define ed_asic_insw(sc, port, addr, count) \ 170 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 171 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 172 173#define ed_asic_outsw(sc, port, addr, count) \ 174 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 175 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 176 177#define ed_asic_insl(sc, port, addr, count) \ 178 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 179 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 180 181#define ed_asic_outsl(sc, port, addr, count) \ 182 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 183 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 184 185void ed_release_resources(device_t); 186int ed_alloc_port(device_t, int, int); 187int ed_alloc_memory(device_t, int, int); 188int ed_alloc_irq(device_t, int, int); 189 190int ed_probe_generic8390(struct ed_softc *); 191int ed_probe_WD80x3(device_t, int, int); 192int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]); 193#ifdef ED_3C503 194int ed_probe_3Com(device_t, int, int); 195#endif 196#ifdef ED_SIC 197int ed_probe_SIC(device_t, int, int); 198#endif 199int ed_probe_Novell_generic(device_t, int); 200int ed_probe_Novell(device_t, int, int); 201void ed_Novell_read_mac(struct ed_softc *); 202#ifdef ED_HPP 203int ed_probe_HP_pclanp(device_t, int, int); 204#endif 205 206int ed_attach(device_t); 207int ed_detach(device_t); 208int ed_clear_memory(device_t); 209int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */ 210void ed_stop(struct ed_softc *); 211void ed_shmem_readmem16(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 212void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 213void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 214void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t); 215#ifndef ED_NO_MIIBUS 216int ed_miibus_readreg(device_t, int, int); 217void ed_miibus_writereg(device_t, int, int, int); 218int ed_ifmedia_upd(struct ifnet *); 219void ed_ifmedia_sts(struct ifnet *, struct ifmediareq *); 220void ed_child_detached(device_t, device_t); 221#endif 222 223/* The following is unsatisfying XXX */ 224#ifdef ED_HPP 225void ed_hpp_set_physical_link(struct ed_softc *); 226void ed_hpp_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 227u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int); 228#endif 229 230void ed_disable_16bit_access(struct ed_softc *); 231void ed_enable_16bit_access(struct ed_softc *); 232 233driver_intr_t edintr; 234 235extern devclass_t ed_devclass; 236 237 238/* 239 * Vendor types 240 */ 241#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 242#define ED_VENDOR_3COM 0x01 /* 3Com */ 243#define ED_VENDOR_NOVELL 0x02 /* Novell */ 244#define ED_VENDOR_HP 0x03 /* Hewlett Packard */ 245#define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */ 246 247/* 248 * Compile-time config flags 249 */ 250/* 251 * this sets the default for enabling/disabling the transceiver 252 */ 253#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 254 255/* 256 * This forces the board to be used in 8/16bit mode even if it 257 * autoconfigs differently 258 */ 259#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 260#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 261 262/* 263 * This disables the use of double transmit buffers. 264 */ 265#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 266 267/* 268 * This forces all operations with the NIC memory to use Programmed 269 * I/O (i.e. not via shared memory) 270 */ 271#define ED_FLAGS_FORCE_PIO 0x0010 272 273/* 274 * These are flags describing the chip type. 275 */ 276#define ED_FLAGS_TOSH_ETHER 0x10000 277#define ED_FLAGS_GWETHER 0x20000 278#define ED_FLAGS_AX88190 0x30000 279#define ED_FLAGS_LINKSYS 0x80000 280 281#define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000) 282 283#define ED_MUTEX(_sc) (&(_sc)->sc_mtx) 284#define ED_LOCK(_sc) mtx_lock(ED_MUTEX(_sc)) 285#define ED_UNLOCK(_sc) mtx_unlock(ED_MUTEX(_sc)) 286#define ED_LOCK_INIT(_sc) \ 287 mtx_init(ED_MUTEX(_sc), device_get_nameunit(_sc->dev), \ 288 MTX_NETWORK_LOCK, MTX_DEF) 289#define ED_LOCK_DESTROY(_sc) mtx_destroy(ED_MUTEX(_sc)); 290#define ED_ASSERT_LOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_OWNED); 291#define ED_ASSERT_UNLOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_NOTOWNED); 292 293#endif /* SYS_DEV_ED_IF_EDVAR_H */ 294