if_em.h revision 293854
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/if_em.h 293854 2016-01-13 21:47:27Z marius $*/ 34 35 36#ifndef _EM_H_DEFINED_ 37#define _EM_H_DEFINED_ 38 39 40/* Tunables */ 41 42/* 43 * EM_TXD: Maximum number of Transmit Descriptors 44 * Valid Range: 80-256 for 82542 and 82543-based adapters 45 * 80-4096 for others 46 * Default Value: 256 47 * This value is the number of transmit descriptors allocated by the driver. 48 * Increasing this value allows the driver to queue more transmits. Each 49 * descriptor is 16 bytes. 50 * Since TDLEN should be multiple of 128bytes, the number of transmit 51 * desscriptors should meet the following condition. 52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53 */ 54#define EM_MIN_TXD 80 55#define EM_MAX_TXD 4096 56#ifdef EM_MULTIQUEUE 57#define EM_DEFAULT_TXD 4096 58#else 59#define EM_DEFAULT_TXD 1024 60#endif 61 62/* 63 * EM_RXD - Maximum number of receive Descriptors 64 * Valid Range: 80-256 for 82542 and 82543-based adapters 65 * 80-4096 for others 66 * Default Value: 256 67 * This value is the number of receive descriptors allocated by the driver. 68 * Increasing this value allows the driver to buffer more incoming packets. 69 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 70 * descriptor. The maximum MTU size is 16110. 71 * Since TDLEN should be multiple of 128bytes, the number of transmit 72 * desscriptors should meet the following condition. 73 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 74 */ 75#define EM_MIN_RXD 80 76#define EM_MAX_RXD 4096 77#ifdef EM_MULTIQUEUE 78#define EM_DEFAULT_RXD 4096 79#else 80#define EM_DEFAULT_RXD 1024 81#endif 82 83/* 84 * EM_TIDV - Transmit Interrupt Delay Value 85 * Valid Range: 0-65535 (0=off) 86 * Default Value: 64 87 * This value delays the generation of transmit interrupts in units of 88 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 89 * efficiency if properly tuned for specific network traffic. If the 90 * system is reporting dropped transmits, this value may be set too high 91 * causing the driver to run out of available transmit descriptors. 92 */ 93#define EM_TIDV 64 94 95/* 96 * EM_TADV - Transmit Absolute Interrupt Delay Value 97 * (Not valid for 82542/82543/82544) 98 * Valid Range: 0-65535 (0=off) 99 * Default Value: 64 100 * This value, in units of 1.024 microseconds, limits the delay in which a 101 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 102 * this value ensures that an interrupt is generated after the initial 103 * packet is sent on the wire within the set amount of time. Proper tuning, 104 * along with EM_TIDV, may improve traffic throughput in specific 105 * network conditions. 106 */ 107#define EM_TADV 64 108 109/* 110 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 111 * Valid Range: 0-65535 (0=off) 112 * Default Value: 0 113 * This value delays the generation of receive interrupts in units of 1.024 114 * microseconds. Receive interrupt reduction can improve CPU efficiency if 115 * properly tuned for specific network traffic. Increasing this value adds 116 * extra latency to frame reception and can end up decreasing the throughput 117 * of TCP traffic. If the system is reporting dropped receives, this value 118 * may be set too high, causing the driver to run out of available receive 119 * descriptors. 120 * 121 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 122 * may hang (stop transmitting) under certain network conditions. 123 * If this occurs a WATCHDOG message is logged in the system 124 * event log. In addition, the controller is automatically reset, 125 * restoring the network connection. To eliminate the potential 126 * for the hang ensure that EM_RDTR is set to 0. 127 */ 128#ifdef EM_MULTIQUEUE 129#define EM_RDTR 64 130#else 131#define EM_RDTR 0 132#endif 133 134/* 135 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 136 * Valid Range: 0-65535 (0=off) 137 * Default Value: 64 138 * This value, in units of 1.024 microseconds, limits the delay in which a 139 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 140 * this value ensures that an interrupt is generated after the initial 141 * packet is received within the set amount of time. Proper tuning, 142 * along with EM_RDTR, may improve traffic throughput in specific network 143 * conditions. 144 */ 145#ifdef EM_MULTIQUEUE 146#define EM_RADV 128 147#else 148#define EM_RADV 64 149#endif 150 151/* 152 * This parameter controls the max duration of transmit watchdog. 153 */ 154#define EM_WATCHDOG (10 * hz) 155 156/* 157 * This parameter controls when the driver calls the routine to reclaim 158 * transmit descriptors. 159 */ 160#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 161 162/* 163 * This parameter controls whether or not autonegotation is enabled. 164 * 0 - Disable autonegotiation 165 * 1 - Enable autonegotiation 166 */ 167#define DO_AUTO_NEG 1 168 169/* 170 * This parameter control whether or not the driver will wait for 171 * autonegotiation to complete. 172 * 1 - Wait for autonegotiation to complete 173 * 0 - Don't wait for autonegotiation to complete 174 */ 175#define WAIT_FOR_AUTO_NEG_DEFAULT 0 176 177/* Tunables -- End */ 178 179#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 180 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 181 ADVERTISE_1000_FULL) 182 183#define AUTO_ALL_MODES 0 184 185/* PHY master/slave setting */ 186#define EM_MASTER_SLAVE e1000_ms_hw_default 187 188/* 189 * Micellaneous constants 190 */ 191#define EM_VENDOR_ID 0x8086 192#define EM_FLASH 0x0014 193 194#define EM_JUMBO_PBA 0x00000028 195#define EM_DEFAULT_PBA 0x00000030 196#define EM_SMARTSPEED_DOWNSHIFT 3 197#define EM_SMARTSPEED_MAX 15 198#define EM_MAX_LOOP 10 199 200#define MAX_NUM_MULTICAST_ADDRESSES 128 201#define PCI_ANY_ID (~0U) 202#define ETHER_ALIGN 2 203#define EM_FC_PAUSE_TIME 0x0680 204#define EM_EEPROM_APME 0x400; 205#define EM_82544_APME 0x0004; 206 207/* 208 * Driver state logic for the detection of a hung state 209 * in hardware. Set TX_HUNG whenever a TX packet is used 210 * (data is sent) and clear it when txeof() is invoked if 211 * any descriptors from the ring are cleaned/reclaimed. 212 * Increment internal counter if no descriptors are cleaned 213 * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 214 * reset adapter. 215 */ 216#define EM_TX_IDLE 0x00000000 217#define EM_TX_BUSY 0x00000001 218#define EM_TX_HUNG 0x80000000 219#define EM_TX_MAXTRIES 10 220 221/* 222 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 223 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 224 * also optimize cache line size effect. H/W supports up to cache line size 128. 225 */ 226#define EM_DBA_ALIGN 128 227 228/* 229 * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 230 */ 231#define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 232#define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 233#define TARC_MQ_FIX (1 << 23) | \ 234 (1 << 24) | \ 235 (1 << 25) /* Handle errata in MQ mode */ 236#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 237 238/* PCI Config defines */ 239#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 240#define EM_BAR_TYPE_MASK 0x00000001 241#define EM_BAR_TYPE_MMEM 0x00000000 242#define EM_BAR_TYPE_FLASH 0x0014 243#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 244#define EM_BAR_MEM_TYPE_MASK 0x00000006 245#define EM_BAR_MEM_TYPE_32BIT 0x00000000 246#define EM_BAR_MEM_TYPE_64BIT 0x00000004 247#define EM_MSIX_BAR 3 /* On 82575 */ 248 249/* More backward compatibility */ 250#if __FreeBSD_version < 900000 251#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 252#endif 253 254/* Defines for printing debug information */ 255#define DEBUG_INIT 0 256#define DEBUG_IOCTL 0 257#define DEBUG_HW 0 258 259#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 260#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 261#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 262#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 263#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 264#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 265#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 266#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 267#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 268 269#define EM_MAX_SCATTER 64 270#define EM_VFTA_SIZE 128 271#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 272#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 273#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 274#define EM_MSIX_LINK 0x01000000 /* For 82574 use */ 275#define ETH_ZLEN 60 276#define ETH_ADDR_LEN 6 277#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 278 279/* 280 * 82574 has a nonstandard address for EIAC 281 * and since its only used in MSIX, and in 282 * the em driver only 82574 uses MSIX we can 283 * solve it just using this define. 284 */ 285#define EM_EIAC 0x000DC 286/* 287 * 82574 only reports 3 MSI-X vectors by default; 288 * defines assisting with making it report 5 are 289 * located here. 290 */ 291#define EM_NVM_PCIE_CTRL 0x1B 292#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 293#define EM_NVM_MSIX_N_SHIFT 7 294 295/* 296 * Bus dma allocation structure used by 297 * e1000_dma_malloc and e1000_dma_free. 298 */ 299struct em_dma_alloc { 300 bus_addr_t dma_paddr; 301 caddr_t dma_vaddr; 302 bus_dma_tag_t dma_tag; 303 bus_dmamap_t dma_map; 304 bus_dma_segment_t dma_seg; 305 int dma_nseg; 306}; 307 308struct adapter; 309 310struct em_int_delay_info { 311 struct adapter *adapter; /* Back-pointer to the adapter struct */ 312 int offset; /* Register offset to read/write */ 313 int value; /* Current value in usecs */ 314}; 315 316/* 317 * The transmit ring, one per tx queue 318 */ 319struct tx_ring { 320 struct adapter *adapter; 321 struct mtx tx_mtx; 322 char mtx_name[16]; 323 u32 me; 324 u32 msix; 325 u32 ims; 326 int busy; 327 struct em_dma_alloc txdma; 328 struct e1000_tx_desc *tx_base; 329 struct task tx_task; 330 struct taskqueue *tq; 331 u32 next_avail_desc; 332 u32 next_to_clean; 333 struct em_txbuffer *tx_buffers; 334 volatile u16 tx_avail; 335 u32 tx_tso; /* last tx was tso */ 336 u16 last_hw_offload; 337 u8 last_hw_ipcso; 338 u8 last_hw_ipcss; 339 u8 last_hw_tucso; 340 u8 last_hw_tucss; 341#if __FreeBSD_version >= 800000 342 struct buf_ring *br; 343#endif 344 /* Interrupt resources */ 345 bus_dma_tag_t txtag; 346 void *tag; 347 struct resource *res; 348 unsigned long tx_irq; 349 unsigned long no_desc_avail; 350}; 351 352/* 353 * The Receive ring, one per rx queue 354 */ 355struct rx_ring { 356 struct adapter *adapter; 357 u32 me; 358 u32 msix; 359 u32 ims; 360 struct mtx rx_mtx; 361 char mtx_name[16]; 362 u32 payload; 363 struct task rx_task; 364 struct taskqueue *tq; 365 union e1000_rx_desc_extended *rx_base; 366 struct em_dma_alloc rxdma; 367 u32 next_to_refresh; 368 u32 next_to_check; 369 struct em_rxbuffer *rx_buffers; 370 struct mbuf *fmp; 371 struct mbuf *lmp; 372 373 /* Interrupt resources */ 374 void *tag; 375 struct resource *res; 376 bus_dma_tag_t rxtag; 377 bool discard; 378 379 /* Soft stats */ 380 unsigned long rx_irq; 381 unsigned long rx_discarded; 382 unsigned long rx_packets; 383 unsigned long rx_bytes; 384}; 385 386 387/* Our adapter structure */ 388struct adapter { 389 if_t ifp; 390 struct e1000_hw hw; 391 392 /* FreeBSD operating-system-specific structures. */ 393 struct e1000_osdep osdep; 394 struct device *dev; 395 struct cdev *led_dev; 396 397 struct resource *memory; 398 struct resource *flash; 399 struct resource *msix_mem; 400 401 struct resource *res; 402 void *tag; 403 u32 linkvec; 404 u32 ivars; 405 406 struct ifmedia media; 407 struct callout timer; 408 int msix; 409 int if_flags; 410 int max_frame_size; 411 int min_frame_size; 412 struct mtx core_mtx; 413 int em_insert_vlan_header; 414 u32 ims; 415 bool in_detach; 416 417 /* Task for FAST handling */ 418 struct task link_task; 419 struct task que_task; 420 struct taskqueue *tq; /* private task queue */ 421 422 eventhandler_tag vlan_attach; 423 eventhandler_tag vlan_detach; 424 425 u16 num_vlans; 426 u8 num_queues; 427 428 /* 429 * Transmit rings: 430 * Allocated at run time, an array of rings. 431 */ 432 struct tx_ring *tx_rings; 433 int num_tx_desc; 434 u32 txd_cmd; 435 436 /* 437 * Receive rings: 438 * Allocated at run time, an array of rings. 439 */ 440 struct rx_ring *rx_rings; 441 int num_rx_desc; 442 u32 rx_process_limit; 443 u32 rx_mbuf_sz; 444 445 /* Management and WOL features */ 446 u32 wol; 447 bool has_manage; 448 bool has_amt; 449 450 /* Multicast array memory */ 451 u8 *mta; 452 453 /* 454 ** Shadow VFTA table, this is needed because 455 ** the real vlan filter table gets cleared during 456 ** a soft reset and the driver needs to be able 457 ** to repopulate it. 458 */ 459 u32 shadow_vfta[EM_VFTA_SIZE]; 460 461 /* Info about the interface */ 462 u16 link_active; 463 u16 fc; 464 u16 link_speed; 465 u16 link_duplex; 466 u32 smartspeed; 467 468 struct em_int_delay_info tx_int_delay; 469 struct em_int_delay_info tx_abs_int_delay; 470 struct em_int_delay_info rx_int_delay; 471 struct em_int_delay_info rx_abs_int_delay; 472 struct em_int_delay_info tx_itr; 473 474 /* Misc stats maintained by the driver */ 475 unsigned long dropped_pkts; 476 unsigned long link_irq; 477 unsigned long mbuf_defrag_failed; 478 unsigned long no_tx_dma_setup; 479 unsigned long no_tx_map_avail; 480 unsigned long rx_overruns; 481 unsigned long watchdog_events; 482 483 struct e1000_hw_stats stats; 484}; 485 486/******************************************************************************** 487 * vendor_info_array 488 * 489 * This array contains the list of Subvendor/Subdevice IDs on which the driver 490 * should load. 491 * 492 ********************************************************************************/ 493typedef struct _em_vendor_info_t { 494 unsigned int vendor_id; 495 unsigned int device_id; 496 unsigned int subvendor_id; 497 unsigned int subdevice_id; 498 unsigned int index; 499} em_vendor_info_t; 500 501struct em_txbuffer { 502 int next_eop; /* Index of the desc to watch */ 503 struct mbuf *m_head; 504 bus_dmamap_t map; /* bus_dma map for packet */ 505}; 506 507struct em_rxbuffer { 508 int next_eop; /* Index of the desc to watch */ 509 struct mbuf *m_head; 510 bus_dmamap_t map; /* bus_dma map for packet */ 511 bus_addr_t paddr; 512}; 513 514 515/* 516** Find the number of unrefreshed RX descriptors 517*/ 518static inline u16 519e1000_rx_unrefreshed(struct rx_ring *rxr) 520{ 521 struct adapter *adapter = rxr->adapter; 522 523 if (rxr->next_to_check > rxr->next_to_refresh) 524 return (rxr->next_to_check - rxr->next_to_refresh - 1); 525 else 526 return ((adapter->num_rx_desc + rxr->next_to_check) - 527 rxr->next_to_refresh - 1); 528} 529 530#define EM_CORE_LOCK_INIT(_sc, _name) \ 531 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 532#define EM_TX_LOCK_INIT(_sc, _name) \ 533 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 534#define EM_RX_LOCK_INIT(_sc, _name) \ 535 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 536#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 537#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 538#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 539#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 540#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 541#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 542#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 543#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 544#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 545#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 546#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 547#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 548#define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 549 550#define EM_RSSRK_SIZE 4 551#define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ 552 key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ 553 key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ 554 key[(i) * EM_RSSRK_SIZE + 3] << 24) 555#endif /* _EM_H_DEFINED_ */ 556