if_em.h revision 266978
1178523Sjfv/****************************************************************************** 287189Spdeuskar 3220251Sjfv Copyright (c) 2001-2011, Intel Corporation 4178523Sjfv All rights reserved. 5178523Sjfv 6178523Sjfv Redistribution and use in source and binary forms, with or without 7178523Sjfv modification, are permitted provided that the following conditions are met: 8178523Sjfv 9178523Sjfv 1. Redistributions of source code must retain the above copyright notice, 10178523Sjfv this list of conditions and the following disclaimer. 11178523Sjfv 12178523Sjfv 2. Redistributions in binary form must reproduce the above copyright 13178523Sjfv notice, this list of conditions and the following disclaimer in the 14178523Sjfv documentation and/or other materials provided with the distribution. 15178523Sjfv 16178523Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17178523Sjfv contributors may be used to endorse or promote products derived from 18178523Sjfv this software without specific prior written permission. 19178523Sjfv 20178523Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21178523Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22178523Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23178523Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24178523Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25178523Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26178523Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27178523Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28178523Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29178523Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30178523Sjfv POSSIBILITY OF SUCH DAMAGE. 3187189Spdeuskar 32178523Sjfv******************************************************************************/ 33178523Sjfv/*$FreeBSD: head/sys/dev/e1000/if_em.h 266978 2014-06-02 18:52:03Z marcel $*/ 3487189Spdeuskar 3587189Spdeuskar 3687189Spdeuskar#ifndef _EM_H_DEFINED_ 3787189Spdeuskar#define _EM_H_DEFINED_ 3887189Spdeuskar 39194865Sjfv 40108229Spdeuskar/* Tunables */ 41108229Spdeuskar 42108229Spdeuskar/* 43152276Sglebius * EM_TXD: Maximum number of Transmit Descriptors 44106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 45115878Spdeuskar * 80-4096 for others 46106649Spdeuskar * Default Value: 256 47106649Spdeuskar * This value is the number of transmit descriptors allocated by the driver. 48106649Spdeuskar * Increasing this value allows the driver to queue more transmits. Each 49108229Spdeuskar * descriptor is 16 bytes. 50152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 51152645Syongari * desscriptors should meet the following condition. 52169240Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53108229Spdeuskar */ 54152545Sglebius#define EM_MIN_TXD 80 55152545Sglebius#define EM_MAX_TXD 4096 56203049Sjfv#define EM_DEFAULT_TXD 1024 57106649Spdeuskar 58106649Spdeuskar/* 59152276Sglebius * EM_RXD - Maximum number of receive Descriptors 60106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 61115878Spdeuskar * 80-4096 for others 62108229Spdeuskar * Default Value: 256 63106649Spdeuskar * This value is the number of receive descriptors allocated by the driver. 64106649Spdeuskar * Increasing this value allows the driver to buffer more incoming packets. 65106649Spdeuskar * Each descriptor is 16 bytes. A receive buffer is also allocated for each 66106649Spdeuskar * descriptor. The maximum MTU size is 16110. 67152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 68152645Syongari * desscriptors should meet the following condition. 69169240Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 70106649Spdeuskar */ 71152545Sglebius#define EM_MIN_RXD 80 72152545Sglebius#define EM_MAX_RXD 4096 73203049Sjfv#define EM_DEFAULT_RXD 1024 74106649Spdeuskar 75106649Spdeuskar/* 76119509Spdeuskar * EM_TIDV - Transmit Interrupt Delay Value 77106649Spdeuskar * Valid Range: 0-65535 (0=off) 78106649Spdeuskar * Default Value: 64 79106649Spdeuskar * This value delays the generation of transmit interrupts in units of 80106649Spdeuskar * 1.024 microseconds. Transmit interrupt reduction can improve CPU 81106649Spdeuskar * efficiency if properly tuned for specific network traffic. If the 82106649Spdeuskar * system is reporting dropped transmits, this value may be set too high 83106649Spdeuskar * causing the driver to run out of available transmit descriptors. 84106649Spdeuskar */ 85108229Spdeuskar#define EM_TIDV 64 86106649Spdeuskar 87106649Spdeuskar/* 88163824Sglebius * EM_TADV - Transmit Absolute Interrupt Delay Value 89163824Sglebius * (Not valid for 82542/82543/82544) 90108229Spdeuskar * Valid Range: 0-65535 (0=off) 91108229Spdeuskar * Default Value: 64 92108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 93119509Spdeuskar * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94108229Spdeuskar * this value ensures that an interrupt is generated after the initial 95108229Spdeuskar * packet is sent on the wire within the set amount of time. Proper tuning, 96119509Spdeuskar * along with EM_TIDV, may improve traffic throughput in specific 97108229Spdeuskar * network conditions. 98108229Spdeuskar */ 99108229Spdeuskar#define EM_TADV 64 100108229Spdeuskar 101108229Spdeuskar/* 102119509Spdeuskar * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103106649Spdeuskar * Valid Range: 0-65535 (0=off) 104106649Spdeuskar * Default Value: 0 105106649Spdeuskar * This value delays the generation of receive interrupts in units of 1.024 106106649Spdeuskar * microseconds. Receive interrupt reduction can improve CPU efficiency if 107106649Spdeuskar * properly tuned for specific network traffic. Increasing this value adds 108106649Spdeuskar * extra latency to frame reception and can end up decreasing the throughput 109106649Spdeuskar * of TCP traffic. If the system is reporting dropped receives, this value 110106649Spdeuskar * may be set too high, causing the driver to run out of available receive 111106649Spdeuskar * descriptors. 112106649Spdeuskar * 113119509Spdeuskar * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114108229Spdeuskar * may hang (stop transmitting) under certain network conditions. 115163824Sglebius * If this occurs a WATCHDOG message is logged in the system 116163824Sglebius * event log. In addition, the controller is automatically reset, 117163824Sglebius * restoring the network connection. To eliminate the potential 118163824Sglebius * for the hang ensure that EM_RDTR is set to 0. 119106649Spdeuskar */ 120108229Spdeuskar#define EM_RDTR 0 121106649Spdeuskar 122108229Spdeuskar/* 123119509Spdeuskar * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124108229Spdeuskar * Valid Range: 0-65535 (0=off) 125108229Spdeuskar * Default Value: 64 126108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 127119509Spdeuskar * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128108229Spdeuskar * this value ensures that an interrupt is generated after the initial 129108229Spdeuskar * packet is received within the set amount of time. Proper tuning, 130119509Spdeuskar * along with EM_RDTR, may improve traffic throughput in specific network 131108229Spdeuskar * conditions. 132108229Spdeuskar */ 133108229Spdeuskar#define EM_RADV 64 134106649Spdeuskar 135106649Spdeuskar/* 136203081Sjfv * This parameter controls the max duration of transmit watchdog. 137106649Spdeuskar */ 138203049Sjfv#define EM_WATCHDOG (10 * hz) 13987189Spdeuskar 140106649Spdeuskar/* 141106649Spdeuskar * This parameter controls when the driver calls the routine to reclaim 142106649Spdeuskar * transmit descriptors. 143106649Spdeuskar */ 144169240Sjfv#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 14587189Spdeuskar 146106649Spdeuskar/* 147106649Spdeuskar * This parameter controls whether or not autonegotation is enabled. 148106649Spdeuskar * 0 - Disable autonegotiation 149106649Spdeuskar * 1 - Enable autonegotiation 150106649Spdeuskar */ 151106649Spdeuskar#define DO_AUTO_NEG 1 152106649Spdeuskar 153106649Spdeuskar/* 154106649Spdeuskar * This parameter control whether or not the driver will wait for 155106649Spdeuskar * autonegotiation to complete. 156106649Spdeuskar * 1 - Wait for autonegotiation to complete 157106649Spdeuskar * 0 - Don't wait for autonegotiation to complete 158106649Spdeuskar */ 159115878Spdeuskar#define WAIT_FOR_AUTO_NEG_DEFAULT 0 160106649Spdeuskar 161169240Sjfv/* Tunables -- End */ 162106649Spdeuskar 163169240Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 164169240Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 165169240Sjfv ADVERTISE_1000_FULL) 166164546Skmacy 167169240Sjfv#define AUTO_ALL_MODES 0 168169240Sjfv 169169240Sjfv/* PHY master/slave setting */ 170169240Sjfv#define EM_MASTER_SLAVE e1000_ms_hw_default 171169240Sjfv 172164546Skmacy/* 173169240Sjfv * Micellaneous constants 174164546Skmacy */ 17587189Spdeuskar#define EM_VENDOR_ID 0x8086 176169240Sjfv#define EM_FLASH 0x0014 177112472Spdeuskar 17887189Spdeuskar#define EM_JUMBO_PBA 0x00000028 17987189Spdeuskar#define EM_DEFAULT_PBA 0x00000030 180112472Spdeuskar#define EM_SMARTSPEED_DOWNSHIFT 3 181112472Spdeuskar#define EM_SMARTSPEED_MAX 15 182205869Sjfv#define EM_MAX_LOOP 10 18387189Spdeuskar 18487189Spdeuskar#define MAX_NUM_MULTICAST_ADDRESSES 128 18587189Spdeuskar#define PCI_ANY_ID (~0U) 18687189Spdeuskar#define ETHER_ALIGN 2 187169240Sjfv#define EM_FC_PAUSE_TIME 0x0680 188169240Sjfv#define EM_EEPROM_APME 0x400; 189200243Sjfv#define EM_82544_APME 0x0004; 190108229Spdeuskar 191214363Sjfv#define EM_QUEUE_IDLE 0 192214363Sjfv#define EM_QUEUE_WORKING 1 193214363Sjfv#define EM_QUEUE_HUNG 2 194214363Sjfv 195160949Sglebius/* 196160949Sglebius * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 197160949Sglebius * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 198160949Sglebius * also optimize cache line size effect. H/W supports up to cache line size 128. 199160949Sglebius */ 200160949Sglebius#define EM_DBA_ALIGN 128 201160949Sglebius 202160949Sglebius#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 203160949Sglebius 204163824Sglebius/* PCI Config defines */ 205169240Sjfv#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 206169240Sjfv#define EM_BAR_TYPE_MASK 0x00000001 207169240Sjfv#define EM_BAR_TYPE_MMEM 0x00000000 208169240Sjfv#define EM_BAR_TYPE_FLASH 0x0014 209169240Sjfv#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 210169240Sjfv#define EM_BAR_MEM_TYPE_MASK 0x00000006 211169240Sjfv#define EM_BAR_MEM_TYPE_32BIT 0x00000000 212169240Sjfv#define EM_BAR_MEM_TYPE_64BIT 0x00000004 213169637Sjfv#define EM_MSIX_BAR 3 /* On 82575 */ 214163824Sglebius 215228387Sjfv/* More backward compatibility */ 216228387Sjfv#if __FreeBSD_version < 900000 217219753Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 218219753Sjfv#endif 219219753Sjfv 22087189Spdeuskar/* Defines for printing debug information */ 22187189Spdeuskar#define DEBUG_INIT 0 22287189Spdeuskar#define DEBUG_IOCTL 0 22387189Spdeuskar#define DEBUG_HW 0 22487189Spdeuskar 22587189Spdeuskar#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 22687189Spdeuskar#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 22787189Spdeuskar#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 22887189Spdeuskar#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 22987189Spdeuskar#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 23087189Spdeuskar#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 23187189Spdeuskar#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 23287189Spdeuskar#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 23387189Spdeuskar#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 23487189Spdeuskar 235206429Sjfv#define EM_MAX_SCATTER 32 236194865Sjfv#define EM_VFTA_SIZE 128 237173788Sjfv#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 238169240Sjfv#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 239178523Sjfv#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 240205869Sjfv#define EM_MSIX_LINK 0x01000000 /* For 82574 use */ 241169240Sjfv#define ETH_ZLEN 60 242169240Sjfv#define ETH_ADDR_LEN 6 243173788Sjfv#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 24487189Spdeuskar 245178523Sjfv/* 246178523Sjfv * 82574 has a nonstandard address for EIAC 247178523Sjfv * and since its only used in MSIX, and in 248178523Sjfv * the em driver only 82574 uses MSIX we can 249178523Sjfv * solve it just using this define. 250178523Sjfv */ 251178523Sjfv#define EM_EIAC 0x000DC 252178523Sjfv 253155709Sglebius/* 254155709Sglebius * Bus dma allocation structure used by 255169240Sjfv * e1000_dma_malloc and e1000_dma_free. 256155709Sglebius */ 257155709Sglebiusstruct em_dma_alloc { 258169240Sjfv bus_addr_t dma_paddr; 259169240Sjfv caddr_t dma_vaddr; 260169240Sjfv bus_dma_tag_t dma_tag; 261169240Sjfv bus_dmamap_t dma_map; 262169240Sjfv bus_dma_segment_t dma_seg; 263169240Sjfv int dma_nseg; 264155709Sglebius}; 265119509Spdeuskar 266194865Sjfvstruct adapter; 267194865Sjfv 268194865Sjfvstruct em_int_delay_info { 269194865Sjfv struct adapter *adapter; /* Back-pointer to the adapter struct */ 270194865Sjfv int offset; /* Register offset to read/write */ 271194865Sjfv int value; /* Current value in usecs */ 272194865Sjfv}; 273194865Sjfv 274205869Sjfv/* 275205869Sjfv * The transmit ring, one per tx queue 276205869Sjfv */ 277205869Sjfvstruct tx_ring { 278205869Sjfv struct adapter *adapter; 279205869Sjfv struct mtx tx_mtx; 280205869Sjfv char mtx_name[16]; 281205869Sjfv u32 me; 282205869Sjfv u32 msix; 283205869Sjfv u32 ims; 284214363Sjfv int queue_status; 285205869Sjfv int watchdog_time; 286205869Sjfv struct em_dma_alloc txdma; 287205869Sjfv struct e1000_tx_desc *tx_base; 288205869Sjfv struct task tx_task; 289205869Sjfv struct taskqueue *tq; 290205869Sjfv u32 next_avail_desc; 291205869Sjfv u32 next_to_clean; 292205869Sjfv struct em_buffer *tx_buffers; 293205869Sjfv volatile u16 tx_avail; 294205869Sjfv u32 tx_tso; /* last tx was tso */ 295205869Sjfv u16 last_hw_offload; 296213234Sjfv u8 last_hw_ipcso; 297213234Sjfv u8 last_hw_ipcss; 298213234Sjfv u8 last_hw_tucso; 299213234Sjfv u8 last_hw_tucss; 300205869Sjfv#if __FreeBSD_version >= 800000 301205869Sjfv struct buf_ring *br; 302205869Sjfv#endif 303205869Sjfv /* Interrupt resources */ 304205869Sjfv bus_dma_tag_t txtag; 305205869Sjfv void *tag; 306205869Sjfv struct resource *res; 307205884Sjfv unsigned long tx_irq; 308205884Sjfv unsigned long no_desc_avail; 309205869Sjfv}; 310205869Sjfv 311205869Sjfv/* 312205869Sjfv * The Receive ring, one per rx queue 313205869Sjfv */ 314205869Sjfvstruct rx_ring { 315205869Sjfv struct adapter *adapter; 316205869Sjfv u32 me; 317205869Sjfv u32 msix; 318205869Sjfv u32 ims; 319205869Sjfv struct mtx rx_mtx; 320205869Sjfv char mtx_name[16]; 321205869Sjfv u32 payload; 322205869Sjfv struct task rx_task; 323205869Sjfv struct taskqueue *tq; 324205869Sjfv struct e1000_rx_desc *rx_base; 325205869Sjfv struct em_dma_alloc rxdma; 326205884Sjfv u32 next_to_refresh; 327205884Sjfv u32 next_to_check; 328205869Sjfv struct em_buffer *rx_buffers; 329205869Sjfv struct mbuf *fmp; 330205869Sjfv struct mbuf *lmp; 331205869Sjfv 332205869Sjfv /* Interrupt resources */ 333205869Sjfv void *tag; 334205869Sjfv struct resource *res; 335205869Sjfv bus_dma_tag_t rxtag; 336212303Sjfv bool discard; 337205869Sjfv 338205869Sjfv /* Soft stats */ 339205884Sjfv unsigned long rx_irq; 340212303Sjfv unsigned long rx_discarded; 341205884Sjfv unsigned long rx_packets; 342205884Sjfv unsigned long rx_bytes; 343205869Sjfv}; 344205869Sjfv 345205869Sjfv 346203081Sjfv/* Our adapter structure */ 347203081Sjfvstruct adapter { 348266978Smarcel if_t ifp; 349169240Sjfv struct e1000_hw hw; 350119509Spdeuskar 351203081Sjfv /* FreeBSD operating-system-specific structures. */ 352169240Sjfv struct e1000_osdep osdep; 353155709Sglebius struct device *dev; 354206001Smarius struct cdev *led_dev; 355176667Sjfv 356203081Sjfv struct resource *memory; 357203081Sjfv struct resource *flash; 358205869Sjfv struct resource *msix_mem; 359176667Sjfv 360205869Sjfv struct resource *res; 361205869Sjfv void *tag; 362205869Sjfv u32 linkvec; 363205869Sjfv u32 ivars; 364176667Sjfv 365155709Sglebius struct ifmedia media; 366120364Ssam struct callout timer; 367205869Sjfv int msix; 368160519Syongari int if_flags; 369173788Sjfv int max_frame_size; 370173788Sjfv int min_frame_size; 371213234Sjfv int pause_frames; 372173788Sjfv struct mtx core_mtx; 373137609Srwatson int em_insert_vlan_header; 374205869Sjfv u32 ims; 375205869Sjfv bool in_detach; 376203081Sjfv 377203081Sjfv /* Task for FAST handling */ 378203081Sjfv struct task link_task; 379205869Sjfv struct task que_task; 380169240Sjfv struct taskqueue *tq; /* private task queue */ 381176667Sjfv 382185353Sjfv eventhandler_tag vlan_attach; 383185353Sjfv eventhandler_tag vlan_detach; 384185353Sjfv 385205869Sjfv u16 num_vlans; 386205869Sjfv u16 num_queues; 387205869Sjfv 388205869Sjfv /* 389205869Sjfv * Transmit rings: 390205869Sjfv * Allocated at run time, an array of rings. 391205869Sjfv */ 392205869Sjfv struct tx_ring *tx_rings; 393205869Sjfv int num_tx_desc; 394205869Sjfv u32 txd_cmd; 395205869Sjfv 396205869Sjfv /* 397205869Sjfv * Receive rings: 398205869Sjfv * Allocated at run time, an array of rings. 399205869Sjfv */ 400205869Sjfv struct rx_ring *rx_rings; 401205869Sjfv int num_rx_desc; 402205869Sjfv u32 rx_process_limit; 403214363Sjfv u32 rx_mbuf_sz; 404205869Sjfv 405169240Sjfv /* Management and WOL features */ 406203081Sjfv u32 wol; 407203081Sjfv bool has_manage; 408203081Sjfv bool has_amt; 409163730Sjfv 410211913Syongari /* Multicast array memory */ 411211913Syongari u8 *mta; 412212303Sjfv 413214363Sjfv /* 414214363Sjfv ** Shadow VFTA table, this is needed because 415214363Sjfv ** the real vlan filter table gets cleared during 416214363Sjfv ** a soft reset and the driver needs to be able 417214363Sjfv ** to repopulate it. 418214363Sjfv */ 419214363Sjfv u32 shadow_vfta[EM_VFTA_SIZE]; 420214363Sjfv 421214363Sjfv /* Info about the interface */ 422228387Sjfv u16 link_active; 423228387Sjfv u16 fc; 424214363Sjfv u16 link_speed; 425214363Sjfv u16 link_duplex; 426214363Sjfv u32 smartspeed; 427214363Sjfv 428203081Sjfv struct em_int_delay_info tx_int_delay; 429203081Sjfv struct em_int_delay_info tx_abs_int_delay; 430203081Sjfv struct em_int_delay_info rx_int_delay; 431203081Sjfv struct em_int_delay_info rx_abs_int_delay; 432250414Sluigi struct em_int_delay_info tx_itr; 43387189Spdeuskar 43497785Spdeuskar /* Misc stats maintained by the driver */ 435169240Sjfv unsigned long dropped_pkts; 436203081Sjfv unsigned long mbuf_alloc_failed; 437203081Sjfv unsigned long mbuf_cluster_failed; 438155709Sglebius unsigned long no_tx_map_avail; 439155709Sglebius unsigned long no_tx_dma_setup; 440205869Sjfv unsigned long rx_overruns; 441152247Sglebius unsigned long watchdog_events; 442203081Sjfv unsigned long link_irq; 443112472Spdeuskar 444169240Sjfv struct e1000_hw_stats stats; 44587189Spdeuskar}; 44687189Spdeuskar 447205869Sjfv/******************************************************************************** 448163730Sjfv * vendor_info_array 449163730Sjfv * 450163730Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 451163730Sjfv * should load. 452163730Sjfv * 453205869Sjfv ********************************************************************************/ 454163730Sjfvtypedef struct _em_vendor_info_t { 455163730Sjfv unsigned int vendor_id; 456163730Sjfv unsigned int device_id; 457163730Sjfv unsigned int subvendor_id; 458163730Sjfv unsigned int subdevice_id; 459163730Sjfv unsigned int index; 460163730Sjfv} em_vendor_info_t; 461163730Sjfv 462163730Sjfvstruct em_buffer { 463169240Sjfv int next_eop; /* Index of the desc to watch */ 464163730Sjfv struct mbuf *m_head; 465163730Sjfv bus_dmamap_t map; /* bus_dma map for packet */ 466163730Sjfv}; 467163730Sjfv 468220251Sjfv 469220251Sjfv/* 470220251Sjfv** Find the number of unrefreshed RX descriptors 471220251Sjfv*/ 472220251Sjfvstatic inline u16 473220251Sjfve1000_rx_unrefreshed(struct rx_ring *rxr) 474220251Sjfv{ 475220251Sjfv struct adapter *adapter = rxr->adapter; 476220251Sjfv 477220251Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 478220251Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 479220251Sjfv else 480220251Sjfv return ((adapter->num_rx_desc + rxr->next_to_check) - 481220251Sjfv rxr->next_to_refresh - 1); 482220251Sjfv} 483220251Sjfv 484173788Sjfv#define EM_CORE_LOCK_INIT(_sc, _name) \ 485174029Sjfv mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 486173788Sjfv#define EM_TX_LOCK_INIT(_sc, _name) \ 487174029Sjfv mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 488178523Sjfv#define EM_RX_LOCK_INIT(_sc, _name) \ 489178523Sjfv mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 490173788Sjfv#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 491173788Sjfv#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 492178523Sjfv#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 493173788Sjfv#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 494173788Sjfv#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 495191038Skmacy#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 496178523Sjfv#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 497173788Sjfv#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 498173788Sjfv#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 499178523Sjfv#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 500173788Sjfv#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 501173788Sjfv#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 502206437Sjfv#define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 503120364Ssam 504155709Sglebius#endif /* _EM_H_DEFINED_ */ 505