if_em.h revision 169637
187189Spdeuskar/************************************************************************** 287189Spdeuskar 3169240SjfvCopyright (c) 2001-2007, Intel Corporation 487189SpdeuskarAll rights reserved. 587189Spdeuskar 6103895SpdeuskarRedistribution and use in source and binary forms, with or without 7103895Spdeuskarmodification, are permitted provided that the following conditions are met: 887189Spdeuskar 9103895Spdeuskar 1. Redistributions of source code must retain the above copyright notice, 10103895Spdeuskar this list of conditions and the following disclaimer. 1187189Spdeuskar 12103895Spdeuskar 2. Redistributions in binary form must reproduce the above copyright 13103895Spdeuskar notice, this list of conditions and the following disclaimer in the 14103895Spdeuskar documentation and/or other materials provided with the distribution. 1587189Spdeuskar 1687189Spdeuskar 3. Neither the name of the Intel Corporation nor the names of its 17103895Spdeuskar contributors may be used to endorse or promote products derived from 18103895Spdeuskar this software without specific prior written permission. 1987189Spdeuskar 2087189SpdeuskarTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2187189SpdeuskarAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2287189SpdeuskarIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23103895SpdeuskarARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24103895SpdeuskarLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25103895SpdeuskarCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26103895SpdeuskarSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27103895SpdeuskarINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28103895SpdeuskarCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29103895SpdeuskarARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30103895SpdeuskarPOSSIBILITY OF SUCH DAMAGE. 3187189Spdeuskar 3287189Spdeuskar***************************************************************************/ 33169589Sjfv/*$FreeBSD: head/sys/dev/em/if_em.h 169637 2007-05-17 00:14:03Z jfv $*/ 34163730Sjfv 3587189Spdeuskar#ifndef _EM_H_DEFINED_ 3687189Spdeuskar#define _EM_H_DEFINED_ 3787189Spdeuskar 38108229Spdeuskar/* Tunables */ 39108229Spdeuskar 40108229Spdeuskar/* 41152276Sglebius * EM_TXD: Maximum number of Transmit Descriptors 42106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 43115878Spdeuskar * 80-4096 for others 44106649Spdeuskar * Default Value: 256 45106649Spdeuskar * This value is the number of transmit descriptors allocated by the driver. 46106649Spdeuskar * Increasing this value allows the driver to queue more transmits. Each 47108229Spdeuskar * descriptor is 16 bytes. 48152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 49152645Syongari * desscriptors should meet the following condition. 50169240Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 51108229Spdeuskar */ 52152545Sglebius#define EM_MIN_TXD 80 53152545Sglebius#define EM_MAX_TXD_82543 256 54152545Sglebius#define EM_MAX_TXD 4096 55152545Sglebius#define EM_DEFAULT_TXD EM_MAX_TXD_82543 56106649Spdeuskar 57106649Spdeuskar/* 58152276Sglebius * EM_RXD - Maximum number of receive Descriptors 59106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 60115878Spdeuskar * 80-4096 for others 61108229Spdeuskar * Default Value: 256 62106649Spdeuskar * This value is the number of receive descriptors allocated by the driver. 63106649Spdeuskar * Increasing this value allows the driver to buffer more incoming packets. 64106649Spdeuskar * Each descriptor is 16 bytes. A receive buffer is also allocated for each 65106649Spdeuskar * descriptor. The maximum MTU size is 16110. 66152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 67152645Syongari * desscriptors should meet the following condition. 68169240Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 69106649Spdeuskar */ 70152545Sglebius#define EM_MIN_RXD 80 71152545Sglebius#define EM_MAX_RXD_82543 256 72152545Sglebius#define EM_MAX_RXD 4096 73169240Sjfv#define EM_DEFAULT_RXD EM_MAX_RXD_82543 74106649Spdeuskar 75106649Spdeuskar/* 76119509Spdeuskar * EM_TIDV - Transmit Interrupt Delay Value 77106649Spdeuskar * Valid Range: 0-65535 (0=off) 78106649Spdeuskar * Default Value: 64 79106649Spdeuskar * This value delays the generation of transmit interrupts in units of 80106649Spdeuskar * 1.024 microseconds. Transmit interrupt reduction can improve CPU 81106649Spdeuskar * efficiency if properly tuned for specific network traffic. If the 82106649Spdeuskar * system is reporting dropped transmits, this value may be set too high 83106649Spdeuskar * causing the driver to run out of available transmit descriptors. 84106649Spdeuskar */ 85108229Spdeuskar#define EM_TIDV 64 86106649Spdeuskar 87106649Spdeuskar/* 88163824Sglebius * EM_TADV - Transmit Absolute Interrupt Delay Value 89163824Sglebius * (Not valid for 82542/82543/82544) 90108229Spdeuskar * Valid Range: 0-65535 (0=off) 91108229Spdeuskar * Default Value: 64 92108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 93119509Spdeuskar * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94108229Spdeuskar * this value ensures that an interrupt is generated after the initial 95108229Spdeuskar * packet is sent on the wire within the set amount of time. Proper tuning, 96119509Spdeuskar * along with EM_TIDV, may improve traffic throughput in specific 97108229Spdeuskar * network conditions. 98108229Spdeuskar */ 99108229Spdeuskar#define EM_TADV 64 100108229Spdeuskar 101108229Spdeuskar/* 102119509Spdeuskar * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103106649Spdeuskar * Valid Range: 0-65535 (0=off) 104106649Spdeuskar * Default Value: 0 105106649Spdeuskar * This value delays the generation of receive interrupts in units of 1.024 106106649Spdeuskar * microseconds. Receive interrupt reduction can improve CPU efficiency if 107106649Spdeuskar * properly tuned for specific network traffic. Increasing this value adds 108106649Spdeuskar * extra latency to frame reception and can end up decreasing the throughput 109106649Spdeuskar * of TCP traffic. If the system is reporting dropped receives, this value 110106649Spdeuskar * may be set too high, causing the driver to run out of available receive 111106649Spdeuskar * descriptors. 112106649Spdeuskar * 113119509Spdeuskar * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114108229Spdeuskar * may hang (stop transmitting) under certain network conditions. 115163824Sglebius * If this occurs a WATCHDOG message is logged in the system 116163824Sglebius * event log. In addition, the controller is automatically reset, 117163824Sglebius * restoring the network connection. To eliminate the potential 118163824Sglebius * for the hang ensure that EM_RDTR is set to 0. 119106649Spdeuskar */ 120108229Spdeuskar#define EM_RDTR 0 121106649Spdeuskar 122108229Spdeuskar/* 123119509Spdeuskar * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124108229Spdeuskar * Valid Range: 0-65535 (0=off) 125108229Spdeuskar * Default Value: 64 126108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 127119509Spdeuskar * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128108229Spdeuskar * this value ensures that an interrupt is generated after the initial 129108229Spdeuskar * packet is received within the set amount of time. Proper tuning, 130119509Spdeuskar * along with EM_RDTR, may improve traffic throughput in specific network 131108229Spdeuskar * conditions. 132108229Spdeuskar */ 133108229Spdeuskar#define EM_RADV 64 134106649Spdeuskar 135106649Spdeuskar/* 136106649Spdeuskar * This parameter controls the duration of transmit watchdog timer. 137106649Spdeuskar */ 13887189Spdeuskar#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 13987189Spdeuskar 140106649Spdeuskar/* 141106649Spdeuskar * This parameter controls when the driver calls the routine to reclaim 142106649Spdeuskar * transmit descriptors. 143106649Spdeuskar */ 144169240Sjfv#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 145169589Sjfv#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 14687189Spdeuskar 147106649Spdeuskar/* 148106649Spdeuskar * This parameter controls whether or not autonegotation is enabled. 149106649Spdeuskar * 0 - Disable autonegotiation 150106649Spdeuskar * 1 - Enable autonegotiation 151106649Spdeuskar */ 152106649Spdeuskar#define DO_AUTO_NEG 1 153106649Spdeuskar 154106649Spdeuskar/* 155106649Spdeuskar * This parameter control whether or not the driver will wait for 156106649Spdeuskar * autonegotiation to complete. 157106649Spdeuskar * 1 - Wait for autonegotiation to complete 158106649Spdeuskar * 0 - Don't wait for autonegotiation to complete 159106649Spdeuskar */ 160115878Spdeuskar#define WAIT_FOR_AUTO_NEG_DEFAULT 0 161106649Spdeuskar 162169240Sjfv/* Tunables -- End */ 163106649Spdeuskar 164169240Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 165169240Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 166169240Sjfv ADVERTISE_1000_FULL) 167164546Skmacy 168169240Sjfv#define AUTO_ALL_MODES 0 169169240Sjfv 170169240Sjfv/* PHY master/slave setting */ 171169240Sjfv#define EM_MASTER_SLAVE e1000_ms_hw_default 172169240Sjfv 173164546Skmacy/* 174169240Sjfv * Micellaneous constants 175164546Skmacy */ 17687189Spdeuskar#define EM_VENDOR_ID 0x8086 177169240Sjfv#define EM_FLASH 0x0014 178112472Spdeuskar 17987189Spdeuskar#define EM_JUMBO_PBA 0x00000028 18087189Spdeuskar#define EM_DEFAULT_PBA 0x00000030 181112472Spdeuskar#define EM_SMARTSPEED_DOWNSHIFT 3 182112472Spdeuskar#define EM_SMARTSPEED_MAX 15 183169240Sjfv#define EM_MAX_INTR 10 184169240Sjfv#define EM_TSO_SEG_SIZE 4096 /* Max dma seg size */ 18587189Spdeuskar 18687189Spdeuskar#define MAX_NUM_MULTICAST_ADDRESSES 128 18787189Spdeuskar#define PCI_ANY_ID (~0U) 18887189Spdeuskar#define ETHER_ALIGN 2 189169240Sjfv#define EM_TX_BUFFER_SIZE ((uint32_t) 1514) 190169240Sjfv#define EM_FC_PAUSE_TIME 0x0680 191169240Sjfv#define EM_EEPROM_APME 0x400; 192108229Spdeuskar 193160949Sglebius/* 194160949Sglebius * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 195160949Sglebius * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 196160949Sglebius * also optimize cache line size effect. H/W supports up to cache line size 128. 197160949Sglebius */ 198160949Sglebius#define EM_DBA_ALIGN 128 199160949Sglebius 200160949Sglebius#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 201160949Sglebius 202163824Sglebius/* PCI Config defines */ 203169240Sjfv#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 204169240Sjfv#define EM_BAR_TYPE_MASK 0x00000001 205169240Sjfv#define EM_BAR_TYPE_MMEM 0x00000000 206169240Sjfv#define EM_BAR_TYPE_IO 0x00000001 207169240Sjfv#define EM_BAR_TYPE_FLASH 0x0014 208169240Sjfv#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 209169240Sjfv#define EM_BAR_MEM_TYPE_MASK 0x00000006 210169240Sjfv#define EM_BAR_MEM_TYPE_32BIT 0x00000000 211169240Sjfv#define EM_BAR_MEM_TYPE_64BIT 0x00000004 212169637Sjfv#define EM_MSIX_BAR 3 /* On 82575 */ 213163824Sglebius 21487189Spdeuskar/* Defines for printing debug information */ 21587189Spdeuskar#define DEBUG_INIT 0 21687189Spdeuskar#define DEBUG_IOCTL 0 21787189Spdeuskar#define DEBUG_HW 0 21887189Spdeuskar 21987189Spdeuskar#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 22087189Spdeuskar#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 22187189Spdeuskar#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 22287189Spdeuskar#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 22387189Spdeuskar#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 22487189Spdeuskar#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 22587189Spdeuskar#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 22687189Spdeuskar#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 22787189Spdeuskar#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 22887189Spdeuskar 229169240Sjfv#define EM_MAX_SCATTER 64 230169240Sjfv#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */ 231169240Sjfv#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 232169240Sjfv#define ETH_ZLEN 60 233169240Sjfv#define ETH_ADDR_LEN 6 234169589Sjfv#define CSUM_OFFLOAD 7 /* Offload bits in csum flags */ 23587189Spdeuskar 236163730Sjfvstruct adapter; 237161778Sjhb 238163730Sjfvstruct em_int_delay_info { 239169240Sjfv struct adapter *adapter; /* Back-pointer to the adapter struct */ 240169240Sjfv int offset; /* Register offset to read/write */ 241169240Sjfv int value; /* Current value in usecs */ 242118314Sjdp}; 243118314Sjdp 244155709Sglebius/* 245155709Sglebius * Bus dma allocation structure used by 246169240Sjfv * e1000_dma_malloc and e1000_dma_free. 247155709Sglebius */ 248155709Sglebiusstruct em_dma_alloc { 249169240Sjfv bus_addr_t dma_paddr; 250169240Sjfv caddr_t dma_vaddr; 251169240Sjfv bus_dma_tag_t dma_tag; 252169240Sjfv bus_dmamap_t dma_map; 253169240Sjfv bus_dma_segment_t dma_seg; 254169240Sjfv int dma_nseg; 255155709Sglebius}; 256119509Spdeuskar 257169240Sjfv/* Our adapter structure */ 258160956Spdeuskarstruct adapter { 259155709Sglebius struct ifnet *ifp; 260169240Sjfv struct e1000_hw hw; 261119509Spdeuskar 262155709Sglebius /* FreeBSD operating-system-specific structures. */ 263169240Sjfv struct e1000_osdep osdep; 264155709Sglebius struct device *dev; 26597785Spdeuskar struct resource *res_memory; 266160949Sglebius struct resource *flash_mem; 267169637Sjfv struct resource *msix_mem; 268155709Sglebius struct resource *res_ioport; 269155709Sglebius struct resource *res_interrupt; 270155709Sglebius void *int_handler_tag; 271155709Sglebius struct ifmedia media; 272120364Ssam struct callout timer; 273120364Ssam struct callout tx_fifo_timer; 274164126Sglebius int watchdog_timer; 275155709Sglebius int io_rid; 276164305Sjhb int msi; 277160519Syongari int if_flags; 278120364Ssam struct mtx mtx; 279137609Srwatson int em_insert_vlan_header; 280169240Sjfv struct task link_task; 281169240Sjfv struct task rxtx_task; 282169240Sjfv struct taskqueue *tq; /* private task queue */ 283169240Sjfv /* Management and WOL features */ 284169240Sjfv int wol; 285169240Sjfv int has_manage; 286163730Sjfv 28797785Spdeuskar /* Info about the board itself */ 288155709Sglebius uint32_t part_num; 289155709Sglebius uint8_t link_active; 290155709Sglebius uint16_t link_speed; 291155709Sglebius uint16_t link_duplex; 292155709Sglebius uint32_t smartspeed; 293118314Sjdp struct em_int_delay_info tx_int_delay; 294118314Sjdp struct em_int_delay_info tx_abs_int_delay; 295118314Sjdp struct em_int_delay_info rx_int_delay; 296118314Sjdp struct em_int_delay_info rx_abs_int_delay; 29787189Spdeuskar 298108229Spdeuskar /* 299155709Sglebius * Transmit definitions 300155709Sglebius * 301155709Sglebius * We have an array of num_tx_desc descriptors (handled 302155709Sglebius * by the controller) paired with an array of tx_buffers 303155709Sglebius * (at tx_buffer_area). 304155709Sglebius * The index of the next available descriptor is next_avail_tx_desc. 305155709Sglebius * The number of remaining tx_desc is num_tx_desc_avail. 306155709Sglebius */ 307155709Sglebius struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 308169240Sjfv struct e1000_tx_desc *tx_desc_base; 309155709Sglebius uint32_t next_avail_tx_desc; 310163826Sglebius uint32_t next_tx_to_clean; 311155709Sglebius volatile uint16_t num_tx_desc_avail; 312155709Sglebius uint16_t num_tx_desc; 313155709Sglebius uint32_t txd_cmd; 314155709Sglebius struct em_buffer *tx_buffer_area; 315155709Sglebius bus_dma_tag_t txtag; /* dma tag for tx */ 316169240Sjfv uint32_t tx_tso; /* last tx was tso */ 31787189Spdeuskar 318169240Sjfv /* 319169240Sjfv * Transmit function pointer: 320169240Sjfv * legacy or advanced (82575 and later) 321169240Sjfv */ 322169240Sjfv int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp); 323169240Sjfv 324108229Spdeuskar /* 325108229Spdeuskar * Receive definitions 326155709Sglebius * 327155709Sglebius * we have an array of num_rx_desc rx_desc (handled by the 328155709Sglebius * controller), and paired with an array of rx_buffers 329155709Sglebius * (at rx_buffer_area). 330155709Sglebius * The next pair to check on receive is at offset next_rx_desc_to_check 331155709Sglebius */ 332155709Sglebius struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 333169240Sjfv struct e1000_rx_desc *rx_desc_base; 334155709Sglebius uint32_t next_rx_desc_to_check; 335155709Sglebius uint32_t rx_buffer_len; 336155709Sglebius uint16_t num_rx_desc; 337155709Sglebius int rx_process_limit; 338155709Sglebius struct em_buffer *rx_buffer_area; 339155709Sglebius bus_dma_tag_t rxtag; 340163730Sjfv bus_dmamap_t rx_sparemap; 34187189Spdeuskar 342169240Sjfv /* 343169240Sjfv * First/last mbuf pointers, for 344169240Sjfv * collecting multisegment RX packets. 345169240Sjfv */ 346155709Sglebius struct mbuf *fmp; 347155709Sglebius struct mbuf *lmp; 34887189Spdeuskar 34997785Spdeuskar /* Misc stats maintained by the driver */ 350169240Sjfv unsigned long dropped_pkts; 351155709Sglebius unsigned long mbuf_alloc_failed; 352155709Sglebius unsigned long mbuf_cluster_failed; 353155709Sglebius unsigned long no_tx_desc_avail1; 354155709Sglebius unsigned long no_tx_desc_avail2; 355155709Sglebius unsigned long no_tx_map_avail; 356155709Sglebius unsigned long no_tx_dma_setup; 357152247Sglebius unsigned long watchdog_events; 358152247Sglebius unsigned long rx_overruns; 359112472Spdeuskar 360134619Spdeuskar /* Used in for 82547 10Mb Half workaround */ 361134619Spdeuskar #define EM_PBA_BYTES_SHIFT 0xA 362134619Spdeuskar #define EM_TX_HEAD_ADDR_SHIFT 7 363134619Spdeuskar #define EM_PBA_TX_MASK 0xFFFF0000 364155709Sglebius #define EM_FIFO_HDR 0x10 365134619Spdeuskar 366155709Sglebius #define EM_82547_PKT_THRESH 0x3e0 367134619Spdeuskar 368155709Sglebius uint32_t tx_fifo_size; 369155709Sglebius uint32_t tx_fifo_head; 370155709Sglebius uint32_t tx_fifo_head_addr; 371155709Sglebius uint64_t tx_fifo_reset_cnt; 372155709Sglebius uint64_t tx_fifo_wrk_cnt; 373155709Sglebius uint32_t tx_head_addr; 374134619Spdeuskar 375119509Spdeuskar /* For 82544 PCIX Workaround */ 376155709Sglebius boolean_t pcix_82544; 377122681Spdeuskar boolean_t in_detach; 378119509Spdeuskar 379169240Sjfv struct e1000_hw_stats stats; 38087189Spdeuskar}; 38187189Spdeuskar 382163730Sjfv/* ****************************************************************************** 383163730Sjfv * vendor_info_array 384163730Sjfv * 385163730Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 386163730Sjfv * should load. 387163730Sjfv * 388163730Sjfv * ******************************************************************************/ 389163730Sjfvtypedef struct _em_vendor_info_t { 390163730Sjfv unsigned int vendor_id; 391163730Sjfv unsigned int device_id; 392163730Sjfv unsigned int subvendor_id; 393163730Sjfv unsigned int subdevice_id; 394163730Sjfv unsigned int index; 395163730Sjfv} em_vendor_info_t; 396163730Sjfv 397163730Sjfv 398163730Sjfvstruct em_buffer { 399169240Sjfv int next_eop; /* Index of the desc to watch */ 400163730Sjfv struct mbuf *m_head; 401163730Sjfv bus_dmamap_t map; /* bus_dma map for packet */ 402163730Sjfv}; 403163730Sjfv 404163730Sjfv/* For 82544 PCIX Workaround */ 405163730Sjfvtypedef struct _ADDRESS_LENGTH_PAIR 406163730Sjfv{ 407169240Sjfv uint64_t address; 408169240Sjfv uint32_t length; 409163730Sjfv} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 410163730Sjfv 411163730Sjfvtypedef struct _DESCRIPTOR_PAIR 412163730Sjfv{ 413169240Sjfv ADDRESS_LENGTH_PAIR descriptor[4]; 414169240Sjfv uint32_t elements; 415163730Sjfv} DESC_ARRAY, *PDESC_ARRAY; 416163730Sjfv 417120989Ssam#define EM_LOCK_INIT(_sc, _name) \ 418120989Ssam mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 419120989Ssam#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 420120989Ssam#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx) 421120989Ssam#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 422120989Ssam#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 423120364Ssam 424155709Sglebius#endif /* _EM_H_DEFINED_ */ 425