if_em.h revision 164305
187189Spdeuskar/************************************************************************** 287189Spdeuskar 3160949SglebiusCopyright (c) 2001-2006, Intel Corporation 487189SpdeuskarAll rights reserved. 587189Spdeuskar 6103895SpdeuskarRedistribution and use in source and binary forms, with or without 7103895Spdeuskarmodification, are permitted provided that the following conditions are met: 887189Spdeuskar 9103895Spdeuskar 1. Redistributions of source code must retain the above copyright notice, 10103895Spdeuskar this list of conditions and the following disclaimer. 1187189Spdeuskar 12103895Spdeuskar 2. Redistributions in binary form must reproduce the above copyright 13103895Spdeuskar notice, this list of conditions and the following disclaimer in the 14103895Spdeuskar documentation and/or other materials provided with the distribution. 1587189Spdeuskar 1687189Spdeuskar 3. Neither the name of the Intel Corporation nor the names of its 17103895Spdeuskar contributors may be used to endorse or promote products derived from 18103895Spdeuskar this software without specific prior written permission. 1987189Spdeuskar 2087189SpdeuskarTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2187189SpdeuskarAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2287189SpdeuskarIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23103895SpdeuskarARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24103895SpdeuskarLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25103895SpdeuskarCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26103895SpdeuskarSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27103895SpdeuskarINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28103895SpdeuskarCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29103895SpdeuskarARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30103895SpdeuskarPOSSIBILITY OF SUCH DAMAGE. 3187189Spdeuskar 3287189Spdeuskar***************************************************************************/ 33163730Sjfv 3490628Spdeuskar/*$FreeBSD: head/sys/dev/em/if_em.h 164305 2006-11-15 20:04:57Z jhb $*/ 3590628Spdeuskar 3687189Spdeuskar#ifndef _EM_H_DEFINED_ 3787189Spdeuskar#define _EM_H_DEFINED_ 3887189Spdeuskar 39108229Spdeuskar/* Tunables */ 40108229Spdeuskar 41108229Spdeuskar/* 42152276Sglebius * EM_TXD: Maximum number of Transmit Descriptors 43106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 44115878Spdeuskar * 80-4096 for others 45106649Spdeuskar * Default Value: 256 46106649Spdeuskar * This value is the number of transmit descriptors allocated by the driver. 47106649Spdeuskar * Increasing this value allows the driver to queue more transmits. Each 48108229Spdeuskar * descriptor is 16 bytes. 49152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 50152645Syongari * desscriptors should meet the following condition. 51152645Syongari * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 52108229Spdeuskar */ 53152545Sglebius#define EM_MIN_TXD 80 54152545Sglebius#define EM_MAX_TXD_82543 256 55152545Sglebius#define EM_MAX_TXD 4096 56152545Sglebius#define EM_DEFAULT_TXD EM_MAX_TXD_82543 57106649Spdeuskar 58106649Spdeuskar/* 59152276Sglebius * EM_RXD - Maximum number of receive Descriptors 60106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 61115878Spdeuskar * 80-4096 for others 62108229Spdeuskar * Default Value: 256 63106649Spdeuskar * This value is the number of receive descriptors allocated by the driver. 64106649Spdeuskar * Increasing this value allows the driver to buffer more incoming packets. 65106649Spdeuskar * Each descriptor is 16 bytes. A receive buffer is also allocated for each 66106649Spdeuskar * descriptor. The maximum MTU size is 16110. 67152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 68152645Syongari * desscriptors should meet the following condition. 69152645Syongari * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 70106649Spdeuskar */ 71152545Sglebius#define EM_MIN_RXD 80 72152545Sglebius#define EM_MAX_RXD_82543 256 73152545Sglebius#define EM_MAX_RXD 4096 74152545Sglebius#define EM_DEFAULT_RXD EM_MAX_RXD_82543 75106649Spdeuskar 76106649Spdeuskar/* 77119509Spdeuskar * EM_TIDV - Transmit Interrupt Delay Value 78106649Spdeuskar * Valid Range: 0-65535 (0=off) 79106649Spdeuskar * Default Value: 64 80106649Spdeuskar * This value delays the generation of transmit interrupts in units of 81106649Spdeuskar * 1.024 microseconds. Transmit interrupt reduction can improve CPU 82106649Spdeuskar * efficiency if properly tuned for specific network traffic. If the 83106649Spdeuskar * system is reporting dropped transmits, this value may be set too high 84106649Spdeuskar * causing the driver to run out of available transmit descriptors. 85106649Spdeuskar */ 86108229Spdeuskar#define EM_TIDV 64 87106649Spdeuskar 88106649Spdeuskar/* 89163824Sglebius * EM_TADV - Transmit Absolute Interrupt Delay Value 90163824Sglebius * (Not valid for 82542/82543/82544) 91108229Spdeuskar * Valid Range: 0-65535 (0=off) 92108229Spdeuskar * Default Value: 64 93108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 94119509Spdeuskar * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 95108229Spdeuskar * this value ensures that an interrupt is generated after the initial 96108229Spdeuskar * packet is sent on the wire within the set amount of time. Proper tuning, 97119509Spdeuskar * along with EM_TIDV, may improve traffic throughput in specific 98108229Spdeuskar * network conditions. 99108229Spdeuskar */ 100108229Spdeuskar#define EM_TADV 64 101108229Spdeuskar 102108229Spdeuskar/* 103119509Spdeuskar * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 104106649Spdeuskar * Valid Range: 0-65535 (0=off) 105106649Spdeuskar * Default Value: 0 106106649Spdeuskar * This value delays the generation of receive interrupts in units of 1.024 107106649Spdeuskar * microseconds. Receive interrupt reduction can improve CPU efficiency if 108106649Spdeuskar * properly tuned for specific network traffic. Increasing this value adds 109106649Spdeuskar * extra latency to frame reception and can end up decreasing the throughput 110106649Spdeuskar * of TCP traffic. If the system is reporting dropped receives, this value 111106649Spdeuskar * may be set too high, causing the driver to run out of available receive 112106649Spdeuskar * descriptors. 113106649Spdeuskar * 114119509Spdeuskar * CAUTION: When setting EM_RDTR to a value other than 0, adapters 115108229Spdeuskar * may hang (stop transmitting) under certain network conditions. 116163824Sglebius * If this occurs a WATCHDOG message is logged in the system 117163824Sglebius * event log. In addition, the controller is automatically reset, 118163824Sglebius * restoring the network connection. To eliminate the potential 119163824Sglebius * for the hang ensure that EM_RDTR is set to 0. 120106649Spdeuskar */ 121108229Spdeuskar#define EM_RDTR 0 122106649Spdeuskar 123108229Spdeuskar/* 124119509Spdeuskar * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 125108229Spdeuskar * Valid Range: 0-65535 (0=off) 126108229Spdeuskar * Default Value: 64 127108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 128119509Spdeuskar * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 129108229Spdeuskar * this value ensures that an interrupt is generated after the initial 130108229Spdeuskar * packet is received within the set amount of time. Proper tuning, 131119509Spdeuskar * along with EM_RDTR, may improve traffic throughput in specific network 132108229Spdeuskar * conditions. 133108229Spdeuskar */ 134108229Spdeuskar#define EM_RADV 64 135106649Spdeuskar 136106649Spdeuskar/* 137106649Spdeuskar * Inform the stack about transmit checksum offload capabilities. 138106649Spdeuskar */ 13987189Spdeuskar#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 140106649Spdeuskar 141106649Spdeuskar/* 142162171Spdeuskar * Inform the stack about transmit segmentation offload capabilities. 143162171Spdeuskar */ 144163730Sjfv#define EM_TCPSEG_FEATURES CSUM_TSO 145162171Spdeuskar 146162171Spdeuskar/* 147106649Spdeuskar * This parameter controls the duration of transmit watchdog timer. 148106649Spdeuskar */ 14987189Spdeuskar#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 15087189Spdeuskar 151106649Spdeuskar/* 152106649Spdeuskar * This parameter controls when the driver calls the routine to reclaim 153106649Spdeuskar * transmit descriptors. 154106649Spdeuskar */ 155160956Spdeuskar#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 15687189Spdeuskar 157106649Spdeuskar/* 158106649Spdeuskar * This parameter controls whether or not autonegotation is enabled. 159106649Spdeuskar * 0 - Disable autonegotiation 160106649Spdeuskar * 1 - Enable autonegotiation 161106649Spdeuskar */ 162106649Spdeuskar#define DO_AUTO_NEG 1 163106649Spdeuskar 164106649Spdeuskar/* 165106649Spdeuskar * This parameter control whether or not the driver will wait for 166106649Spdeuskar * autonegotiation to complete. 167106649Spdeuskar * 1 - Wait for autonegotiation to complete 168106649Spdeuskar * 0 - Don't wait for autonegotiation to complete 169106649Spdeuskar */ 170115878Spdeuskar#define WAIT_FOR_AUTO_NEG_DEFAULT 0 171106649Spdeuskar 172119509Spdeuskar/* 173163730Sjfv * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue 174163730Sjfv * with 82541/82547 devices and some switches. See the "Known Limitations" section of 175163730Sjfv * the README file for a complete description and a list of affected switches. 176119509Spdeuskar * 177119509Spdeuskar * 0 = Hardware default 178119509Spdeuskar * 1 = Master mode 179119509Spdeuskar * 2 = Slave mode 180119509Spdeuskar * 3 = Auto master/slave 181119509Spdeuskar */ 182119509Spdeuskar/* #define EM_MASTER_SLAVE 2 */ 183106649Spdeuskar 184106649Spdeuskar/* Tunables -- End */ 185106649Spdeuskar 186163730Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 187163730Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 188163730Sjfv ADVERTISE_1000_FULL) 189108229Spdeuskar 19087189Spdeuskar#define EM_VENDOR_ID 0x8086 191163730Sjfv#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 192112472Spdeuskar 19387189Spdeuskar#define EM_JUMBO_PBA 0x00000028 19487189Spdeuskar#define EM_DEFAULT_PBA 0x00000030 195112472Spdeuskar#define EM_SMARTSPEED_DOWNSHIFT 3 196112472Spdeuskar#define EM_SMARTSPEED_MAX 15 19787189Spdeuskar 19887189Spdeuskar#define MAX_NUM_MULTICAST_ADDRESSES 128 19987189Spdeuskar#define PCI_ANY_ID (~0U) 20087189Spdeuskar#define ETHER_ALIGN 2 201108229Spdeuskar 202160949Sglebius/* 203160949Sglebius * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 204160949Sglebius * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 205160949Sglebius * also optimize cache line size effect. H/W supports up to cache line size 128. 206160949Sglebius */ 207160949Sglebius#define EM_DBA_ALIGN 128 208160949Sglebius 209160949Sglebius#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 210160949Sglebius 211163824Sglebius/* PCI Config defines */ 212163824Sglebius#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 213163824Sglebius#define EM_BAR_TYPE_MASK 0x00000001 214163824Sglebius#define EM_BAR_TYPE_MMEM 0x00000000 215163824Sglebius#define EM_BAR_TYPE_IO 0x00000001 216163824Sglebius#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 217163824Sglebius#define EM_BAR_MEM_TYPE_MASK 0x00000006 218163824Sglebius#define EM_BAR_MEM_TYPE_32BIT 0x00000000 219163824Sglebius#define EM_BAR_MEM_TYPE_64BIT 0x00000004 220163824Sglebius 22187189Spdeuskar/* Defines for printing debug information */ 22287189Spdeuskar#define DEBUG_INIT 0 22387189Spdeuskar#define DEBUG_IOCTL 0 22487189Spdeuskar#define DEBUG_HW 0 22587189Spdeuskar 22687189Spdeuskar#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 22787189Spdeuskar#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 22887189Spdeuskar#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 22987189Spdeuskar#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 23087189Spdeuskar#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 23187189Spdeuskar#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 23287189Spdeuskar#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 23387189Spdeuskar#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 23487189Spdeuskar#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 23587189Spdeuskar 23687189Spdeuskar 23787189Spdeuskar/* Supported RX Buffer Sizes */ 23887189Spdeuskar#define EM_RXBUFFER_2048 2048 23987189Spdeuskar#define EM_RXBUFFER_4096 4096 24087189Spdeuskar#define EM_RXBUFFER_8192 8192 24187189Spdeuskar#define EM_RXBUFFER_16384 16384 24287189Spdeuskar 243163730Sjfv#define EM_MAX_SCATTER 64 244163730Sjfv#define EM_TSO_SIZE 65535 245114554Spdeuskar 246163730Sjfvtypedef enum _XSUM_CONTEXT_T { 247163730Sjfv OFFLOAD_NONE, 248163730Sjfv OFFLOAD_TCP_IP, 249163730Sjfv OFFLOAD_UDP_IP 250163730Sjfv} XSUM_CONTEXT_T; 25187189Spdeuskar 252163730Sjfvstruct adapter; 253161778Sjhb 254163730Sjfvstruct em_int_delay_info { 255163730Sjfv struct adapter *adapter; /* Back-pointer to the adapter struct */ 256163730Sjfv int offset; /* Register offset to read/write */ 257163730Sjfv int value; /* Current value in usecs */ 258118314Sjdp}; 259118314Sjdp 260155709Sglebius/* 261155709Sglebius * Bus dma allocation structure used by 262163730Sjfv * em_dma_malloc() and em_dma_free(). 263155709Sglebius */ 264155709Sglebiusstruct em_dma_alloc { 265163730Sjfv bus_addr_t dma_paddr; 266163730Sjfv caddr_t dma_vaddr; 267163730Sjfv bus_dma_tag_t dma_tag; 268163730Sjfv bus_dmamap_t dma_map; 269163730Sjfv bus_dma_segment_t dma_seg; 270163730Sjfv int dma_nseg; 271155709Sglebius}; 272119509Spdeuskar 273163730Sjfv/* Driver softc. */ 274160956Spdeuskarstruct adapter { 275155709Sglebius struct ifnet *ifp; 276155709Sglebius struct em_hw hw; 277119509Spdeuskar 278155709Sglebius /* FreeBSD operating-system-specific structures. */ 27997785Spdeuskar struct em_osdep osdep; 280155709Sglebius struct device *dev; 28197785Spdeuskar struct resource *res_memory; 282160949Sglebius struct resource *flash_mem; 283155709Sglebius struct resource *res_ioport; 284155709Sglebius struct resource *res_interrupt; 285155709Sglebius void *int_handler_tag; 286155709Sglebius struct ifmedia media; 287120364Ssam struct callout timer; 288120364Ssam struct callout tx_fifo_timer; 289164126Sglebius int watchdog_timer; 290155709Sglebius int io_rid; 291164305Sjhb int msi; 292160519Syongari int if_flags; 293120364Ssam struct mtx mtx; 294137609Srwatson int em_insert_vlan_header; 295163730Sjfv struct task link_task; 296163730Sjfv struct task rxtx_task; 297163730Sjfv struct taskqueue *tq; /* private task queue */ 298163730Sjfv 29997785Spdeuskar /* Info about the board itself */ 300155709Sglebius uint32_t part_num; 301155709Sglebius uint8_t link_active; 302155709Sglebius uint16_t link_speed; 303155709Sglebius uint16_t link_duplex; 304155709Sglebius uint32_t smartspeed; 305118314Sjdp struct em_int_delay_info tx_int_delay; 306118314Sjdp struct em_int_delay_info tx_abs_int_delay; 307118314Sjdp struct em_int_delay_info rx_int_delay; 308118314Sjdp struct em_int_delay_info rx_abs_int_delay; 30987189Spdeuskar 31097785Spdeuskar XSUM_CONTEXT_T active_checksum_context; 31187189Spdeuskar 312108229Spdeuskar /* 313155709Sglebius * Transmit definitions 314155709Sglebius * 315155709Sglebius * We have an array of num_tx_desc descriptors (handled 316155709Sglebius * by the controller) paired with an array of tx_buffers 317155709Sglebius * (at tx_buffer_area). 318155709Sglebius * The index of the next available descriptor is next_avail_tx_desc. 319155709Sglebius * The number of remaining tx_desc is num_tx_desc_avail. 320155709Sglebius */ 321155709Sglebius struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 322155709Sglebius struct em_tx_desc *tx_desc_base; 323155709Sglebius uint32_t next_avail_tx_desc; 324163826Sglebius uint32_t next_tx_to_clean; 325155709Sglebius volatile uint16_t num_tx_desc_avail; 326155709Sglebius uint16_t num_tx_desc; 327155709Sglebius uint32_t txd_cmd; 328155709Sglebius struct em_buffer *tx_buffer_area; 329155709Sglebius bus_dma_tag_t txtag; /* dma tag for tx */ 330163730Sjfv uint32_t tx_tso; /* last tx was tso */ 33187189Spdeuskar 332108229Spdeuskar /* 333108229Spdeuskar * Receive definitions 334155709Sglebius * 335155709Sglebius * we have an array of num_rx_desc rx_desc (handled by the 336155709Sglebius * controller), and paired with an array of rx_buffers 337155709Sglebius * (at rx_buffer_area). 338155709Sglebius * The next pair to check on receive is at offset next_rx_desc_to_check 339155709Sglebius */ 340155709Sglebius struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 341155709Sglebius struct em_rx_desc *rx_desc_base; 342155709Sglebius uint32_t next_rx_desc_to_check; 343155709Sglebius uint32_t rx_buffer_len; 344155709Sglebius uint16_t num_rx_desc; 345155709Sglebius int rx_process_limit; 346155709Sglebius struct em_buffer *rx_buffer_area; 347155709Sglebius bus_dma_tag_t rxtag; 348163730Sjfv bus_dmamap_t rx_sparemap; 34987189Spdeuskar 350163730Sjfv /* First/last mbuf pointers, for collecting multisegment RX packets. */ 351155709Sglebius struct mbuf *fmp; 352155709Sglebius struct mbuf *lmp; 35387189Spdeuskar 35497785Spdeuskar /* Misc stats maintained by the driver */ 355155709Sglebius unsigned long mbuf_alloc_failed; 356155709Sglebius unsigned long mbuf_cluster_failed; 357155709Sglebius unsigned long no_tx_desc_avail1; 358155709Sglebius unsigned long no_tx_desc_avail2; 359155709Sglebius unsigned long no_tx_map_avail; 360155709Sglebius unsigned long no_tx_dma_setup; 361152247Sglebius unsigned long watchdog_events; 362152247Sglebius unsigned long rx_overruns; 363112472Spdeuskar 364134619Spdeuskar /* Used in for 82547 10Mb Half workaround */ 365134619Spdeuskar #define EM_PBA_BYTES_SHIFT 0xA 366134619Spdeuskar #define EM_TX_HEAD_ADDR_SHIFT 7 367134619Spdeuskar #define EM_PBA_TX_MASK 0xFFFF0000 368155709Sglebius #define EM_FIFO_HDR 0x10 369134619Spdeuskar 370155709Sglebius #define EM_82547_PKT_THRESH 0x3e0 371134619Spdeuskar 372155709Sglebius uint32_t tx_fifo_size; 373155709Sglebius uint32_t tx_fifo_head; 374155709Sglebius uint32_t tx_fifo_head_addr; 375155709Sglebius uint64_t tx_fifo_reset_cnt; 376155709Sglebius uint64_t tx_fifo_wrk_cnt; 377155709Sglebius uint32_t tx_head_addr; 378134619Spdeuskar 379119509Spdeuskar /* For 82544 PCIX Workaround */ 380155709Sglebius boolean_t pcix_82544; 381122681Spdeuskar boolean_t in_detach; 382119509Spdeuskar 38397785Spdeuskar struct em_hw_stats stats; 38487189Spdeuskar}; 38587189Spdeuskar 386163730Sjfv/* ****************************************************************************** 387163730Sjfv * vendor_info_array 388163730Sjfv * 389163730Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 390163730Sjfv * should load. 391163730Sjfv * 392163730Sjfv * ******************************************************************************/ 393163730Sjfvtypedef struct _em_vendor_info_t { 394163730Sjfv unsigned int vendor_id; 395163730Sjfv unsigned int device_id; 396163730Sjfv unsigned int subvendor_id; 397163730Sjfv unsigned int subdevice_id; 398163730Sjfv unsigned int index; 399163730Sjfv} em_vendor_info_t; 400163730Sjfv 401163730Sjfv 402163730Sjfvstruct em_buffer { 403163826Sglebius int next_eop; /* Index of the desc to watch */ 404163730Sjfv struct mbuf *m_head; 405163730Sjfv bus_dmamap_t map; /* bus_dma map for packet */ 406163730Sjfv}; 407163730Sjfv 408163730Sjfv/* For 82544 PCIX Workaround */ 409163730Sjfvtypedef struct _ADDRESS_LENGTH_PAIR 410163730Sjfv{ 411163824Sglebius uint64_t address; 412163824Sglebius uint32_t length; 413163730Sjfv} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 414163730Sjfv 415163730Sjfvtypedef struct _DESCRIPTOR_PAIR 416163730Sjfv{ 417163730Sjfv ADDRESS_LENGTH_PAIR descriptor[4]; 418163824Sglebius uint32_t elements; 419163730Sjfv} DESC_ARRAY, *PDESC_ARRAY; 420163730Sjfv 421120989Ssam#define EM_LOCK_INIT(_sc, _name) \ 422120989Ssam mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 423120989Ssam#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 424120989Ssam#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx) 425120989Ssam#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 426120989Ssam#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 427120364Ssam 428155709Sglebius#endif /* _EM_H_DEFINED_ */ 429