1331722Seadler/****************************************************************************** 287189Spdeuskar 3283923Ssbruno Copyright (c) 2001-2015, Intel Corporation 4178523Sjfv All rights reserved. 5178523Sjfv 6178523Sjfv Redistribution and use in source and binary forms, with or without 7178523Sjfv modification, are permitted provided that the following conditions are met: 8178523Sjfv 9178523Sjfv 1. Redistributions of source code must retain the above copyright notice, 10178523Sjfv this list of conditions and the following disclaimer. 11178523Sjfv 12178523Sjfv 2. Redistributions in binary form must reproduce the above copyright 13178523Sjfv notice, this list of conditions and the following disclaimer in the 14178523Sjfv documentation and/or other materials provided with the distribution. 15178523Sjfv 16178523Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17178523Sjfv contributors may be used to endorse or promote products derived from 18178523Sjfv this software without specific prior written permission. 19178523Sjfv 20178523Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21178523Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22178523Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23178523Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24178523Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25178523Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26178523Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27178523Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28178523Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29178523Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30178523Sjfv POSSIBILITY OF SUCH DAMAGE. 3187189Spdeuskar 32178523Sjfv******************************************************************************/ 33178523Sjfv/*$FreeBSD: stable/11/sys/dev/e1000/if_em.h 342789 2019-01-05 19:32:48Z marius $*/ 3487189Spdeuskar 3587189Spdeuskar 3687189Spdeuskar#ifndef _EM_H_DEFINED_ 3787189Spdeuskar#define _EM_H_DEFINED_ 3887189Spdeuskar 39194865Sjfv 40108229Spdeuskar/* Tunables */ 41108229Spdeuskar 42108229Spdeuskar/* 43152276Sglebius * EM_TXD: Maximum number of Transmit Descriptors 44106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 45115878Spdeuskar * 80-4096 for others 46106649Spdeuskar * Default Value: 256 47106649Spdeuskar * This value is the number of transmit descriptors allocated by the driver. 48106649Spdeuskar * Increasing this value allows the driver to queue more transmits. Each 49108229Spdeuskar * descriptor is 16 bytes. 50152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 51152645Syongari * desscriptors should meet the following condition. 52169240Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53108229Spdeuskar */ 54152545Sglebius#define EM_MIN_TXD 80 55152545Sglebius#define EM_MAX_TXD 4096 56283959Ssbruno#ifdef EM_MULTIQUEUE 57283959Ssbruno#define EM_DEFAULT_TXD 4096 58283959Ssbruno#else 59203049Sjfv#define EM_DEFAULT_TXD 1024 60283959Ssbruno#endif 61106649Spdeuskar 62106649Spdeuskar/* 63152276Sglebius * EM_RXD - Maximum number of receive Descriptors 64106649Spdeuskar * Valid Range: 80-256 for 82542 and 82543-based adapters 65115878Spdeuskar * 80-4096 for others 66108229Spdeuskar * Default Value: 256 67106649Spdeuskar * This value is the number of receive descriptors allocated by the driver. 68106649Spdeuskar * Increasing this value allows the driver to buffer more incoming packets. 69106649Spdeuskar * Each descriptor is 16 bytes. A receive buffer is also allocated for each 70106649Spdeuskar * descriptor. The maximum MTU size is 16110. 71152645Syongari * Since TDLEN should be multiple of 128bytes, the number of transmit 72152645Syongari * desscriptors should meet the following condition. 73169240Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 74106649Spdeuskar */ 75152545Sglebius#define EM_MIN_RXD 80 76152545Sglebius#define EM_MAX_RXD 4096 77283959Ssbruno#ifdef EM_MULTIQUEUE 78283959Ssbruno#define EM_DEFAULT_RXD 4096 79283959Ssbruno#else 80203049Sjfv#define EM_DEFAULT_RXD 1024 81283959Ssbruno#endif 82106649Spdeuskar 83106649Spdeuskar/* 84119509Spdeuskar * EM_TIDV - Transmit Interrupt Delay Value 85106649Spdeuskar * Valid Range: 0-65535 (0=off) 86106649Spdeuskar * Default Value: 64 87106649Spdeuskar * This value delays the generation of transmit interrupts in units of 88106649Spdeuskar * 1.024 microseconds. Transmit interrupt reduction can improve CPU 89106649Spdeuskar * efficiency if properly tuned for specific network traffic. If the 90106649Spdeuskar * system is reporting dropped transmits, this value may be set too high 91106649Spdeuskar * causing the driver to run out of available transmit descriptors. 92106649Spdeuskar */ 93108229Spdeuskar#define EM_TIDV 64 94106649Spdeuskar 95106649Spdeuskar/* 96163824Sglebius * EM_TADV - Transmit Absolute Interrupt Delay Value 97163824Sglebius * (Not valid for 82542/82543/82544) 98108229Spdeuskar * Valid Range: 0-65535 (0=off) 99108229Spdeuskar * Default Value: 64 100108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 101119509Spdeuskar * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 102108229Spdeuskar * this value ensures that an interrupt is generated after the initial 103108229Spdeuskar * packet is sent on the wire within the set amount of time. Proper tuning, 104119509Spdeuskar * along with EM_TIDV, may improve traffic throughput in specific 105108229Spdeuskar * network conditions. 106108229Spdeuskar */ 107108229Spdeuskar#define EM_TADV 64 108108229Spdeuskar 109108229Spdeuskar/* 110119509Spdeuskar * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 111106649Spdeuskar * Valid Range: 0-65535 (0=off) 112106649Spdeuskar * Default Value: 0 113106649Spdeuskar * This value delays the generation of receive interrupts in units of 1.024 114106649Spdeuskar * microseconds. Receive interrupt reduction can improve CPU efficiency if 115106649Spdeuskar * properly tuned for specific network traffic. Increasing this value adds 116106649Spdeuskar * extra latency to frame reception and can end up decreasing the throughput 117106649Spdeuskar * of TCP traffic. If the system is reporting dropped receives, this value 118106649Spdeuskar * may be set too high, causing the driver to run out of available receive 119106649Spdeuskar * descriptors. 120106649Spdeuskar * 121119509Spdeuskar * CAUTION: When setting EM_RDTR to a value other than 0, adapters 122108229Spdeuskar * may hang (stop transmitting) under certain network conditions. 123163824Sglebius * If this occurs a WATCHDOG message is logged in the system 124163824Sglebius * event log. In addition, the controller is automatically reset, 125163824Sglebius * restoring the network connection. To eliminate the potential 126163824Sglebius * for the hang ensure that EM_RDTR is set to 0. 127106649Spdeuskar */ 128283959Ssbruno#ifdef EM_MULTIQUEUE 129283959Ssbruno#define EM_RDTR 64 130283959Ssbruno#else 131108229Spdeuskar#define EM_RDTR 0 132283959Ssbruno#endif 133106649Spdeuskar 134108229Spdeuskar/* 135119509Spdeuskar * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 136108229Spdeuskar * Valid Range: 0-65535 (0=off) 137108229Spdeuskar * Default Value: 64 138108229Spdeuskar * This value, in units of 1.024 microseconds, limits the delay in which a 139119509Spdeuskar * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 140108229Spdeuskar * this value ensures that an interrupt is generated after the initial 141108229Spdeuskar * packet is received within the set amount of time. Proper tuning, 142119509Spdeuskar * along with EM_RDTR, may improve traffic throughput in specific network 143108229Spdeuskar * conditions. 144108229Spdeuskar */ 145283959Ssbruno#ifdef EM_MULTIQUEUE 146283959Ssbruno#define EM_RADV 128 147283959Ssbruno#else 148108229Spdeuskar#define EM_RADV 64 149283959Ssbruno#endif 150106649Spdeuskar 151106649Spdeuskar/* 152203081Sjfv * This parameter controls the max duration of transmit watchdog. 153106649Spdeuskar */ 154203049Sjfv#define EM_WATCHDOG (10 * hz) 15587189Spdeuskar 156106649Spdeuskar/* 157106649Spdeuskar * This parameter controls when the driver calls the routine to reclaim 158106649Spdeuskar * transmit descriptors. 159106649Spdeuskar */ 160169240Sjfv#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 16187189Spdeuskar 162106649Spdeuskar/* 163106649Spdeuskar * This parameter controls whether or not autonegotation is enabled. 164106649Spdeuskar * 0 - Disable autonegotiation 165106649Spdeuskar * 1 - Enable autonegotiation 166106649Spdeuskar */ 167106649Spdeuskar#define DO_AUTO_NEG 1 168106649Spdeuskar 169106649Spdeuskar/* 170106649Spdeuskar * This parameter control whether or not the driver will wait for 171106649Spdeuskar * autonegotiation to complete. 172106649Spdeuskar * 1 - Wait for autonegotiation to complete 173106649Spdeuskar * 0 - Don't wait for autonegotiation to complete 174106649Spdeuskar */ 175115878Spdeuskar#define WAIT_FOR_AUTO_NEG_DEFAULT 0 176106649Spdeuskar 177169240Sjfv/* Tunables -- End */ 178106649Spdeuskar 179169240Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 180169240Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 181169240Sjfv ADVERTISE_1000_FULL) 182164546Skmacy 183169240Sjfv#define AUTO_ALL_MODES 0 184169240Sjfv 185169240Sjfv/* PHY master/slave setting */ 186169240Sjfv#define EM_MASTER_SLAVE e1000_ms_hw_default 187169240Sjfv 188164546Skmacy/* 189169240Sjfv * Micellaneous constants 190164546Skmacy */ 19187189Spdeuskar#define EM_VENDOR_ID 0x8086 192169240Sjfv#define EM_FLASH 0x0014 193112472Spdeuskar 19487189Spdeuskar#define EM_JUMBO_PBA 0x00000028 19587189Spdeuskar#define EM_DEFAULT_PBA 0x00000030 196112472Spdeuskar#define EM_SMARTSPEED_DOWNSHIFT 3 197112472Spdeuskar#define EM_SMARTSPEED_MAX 15 198205869Sjfv#define EM_MAX_LOOP 10 19987189Spdeuskar 20087189Spdeuskar#define MAX_NUM_MULTICAST_ADDRESSES 128 20187189Spdeuskar#define PCI_ANY_ID (~0U) 20287189Spdeuskar#define ETHER_ALIGN 2 203169240Sjfv#define EM_FC_PAUSE_TIME 0x0680 204169240Sjfv#define EM_EEPROM_APME 0x400; 205200243Sjfv#define EM_82544_APME 0x0004; 206108229Spdeuskar 207283923Ssbruno/* 208283923Ssbruno * Driver state logic for the detection of a hung state 209283923Ssbruno * in hardware. Set TX_HUNG whenever a TX packet is used 210283923Ssbruno * (data is sent) and clear it when txeof() is invoked if 211283923Ssbruno * any descriptors from the ring are cleaned/reclaimed. 212283923Ssbruno * Increment internal counter if no descriptors are cleaned 213283923Ssbruno * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 214283923Ssbruno * reset adapter. 215283923Ssbruno */ 216283923Ssbruno#define EM_TX_IDLE 0x00000000 217283923Ssbruno#define EM_TX_BUSY 0x00000001 218283923Ssbruno#define EM_TX_HUNG 0x80000000 219283923Ssbruno#define EM_TX_MAXTRIES 10 220214363Sjfv 221295323Serj#define PCICFG_DESC_RING_STATUS 0xe4 222295323Serj#define FLUSH_DESC_REQUIRED 0x100 223295323Serj 224160949Sglebius/* 225160949Sglebius * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 226160949Sglebius * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 227160949Sglebius * also optimize cache line size effect. H/W supports up to cache line size 128. 228160949Sglebius */ 229160949Sglebius#define EM_DBA_ALIGN 128 230160949Sglebius 231283959Ssbruno/* 232283959Ssbruno * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 233283959Ssbruno */ 234283959Ssbruno#define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 235283959Ssbruno#define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 236283959Ssbruno#define TARC_MQ_FIX (1 << 23) | \ 237283959Ssbruno (1 << 24) | \ 238283959Ssbruno (1 << 25) /* Handle errata in MQ mode */ 239283959Ssbruno#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 240160949Sglebius 241163824Sglebius/* PCI Config defines */ 242169240Sjfv#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 243169240Sjfv#define EM_BAR_TYPE_MASK 0x00000001 244169240Sjfv#define EM_BAR_TYPE_MMEM 0x00000000 245169240Sjfv#define EM_BAR_TYPE_FLASH 0x0014 246169240Sjfv#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 247169240Sjfv#define EM_BAR_MEM_TYPE_MASK 0x00000006 248169240Sjfv#define EM_BAR_MEM_TYPE_32BIT 0x00000000 249169240Sjfv#define EM_BAR_MEM_TYPE_64BIT 0x00000004 250169637Sjfv#define EM_MSIX_BAR 3 /* On 82575 */ 251163824Sglebius 252228387Sjfv/* More backward compatibility */ 253228387Sjfv#if __FreeBSD_version < 900000 254219753Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 255219753Sjfv#endif 256219753Sjfv 25787189Spdeuskar/* Defines for printing debug information */ 25887189Spdeuskar#define DEBUG_INIT 0 25987189Spdeuskar#define DEBUG_IOCTL 0 26087189Spdeuskar#define DEBUG_HW 0 26187189Spdeuskar 26287189Spdeuskar#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 26387189Spdeuskar#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 26487189Spdeuskar#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 26587189Spdeuskar#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 26687189Spdeuskar#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 26787189Spdeuskar#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 26887189Spdeuskar#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 26987189Spdeuskar#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 27087189Spdeuskar#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 27187189Spdeuskar 272295906Smarius#define EM_MAX_SCATTER 40 273194865Sjfv#define EM_VFTA_SIZE 128 274173788Sjfv#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 275169240Sjfv#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 276178523Sjfv#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 277205869Sjfv#define EM_MSIX_LINK 0x01000000 /* For 82574 use */ 278169240Sjfv#define ETH_ZLEN 60 279169240Sjfv#define ETH_ADDR_LEN 6 280342789Smarius#define CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP) /* Offload bits in mbuf flag */ 28187189Spdeuskar 282178523Sjfv/* 283178523Sjfv * 82574 has a nonstandard address for EIAC 284178523Sjfv * and since its only used in MSIX, and in 285178523Sjfv * the em driver only 82574 uses MSIX we can 286178523Sjfv * solve it just using this define. 287178523Sjfv */ 288178523Sjfv#define EM_EIAC 0x000DC 289283959Ssbruno/* 290283959Ssbruno * 82574 only reports 3 MSI-X vectors by default; 291283959Ssbruno * defines assisting with making it report 5 are 292283959Ssbruno * located here. 293283959Ssbruno */ 294283959Ssbruno#define EM_NVM_PCIE_CTRL 0x1B 295283959Ssbruno#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 296283959Ssbruno#define EM_NVM_MSIX_N_SHIFT 7 297178523Sjfv 298155709Sglebius/* 299155709Sglebius * Bus dma allocation structure used by 300169240Sjfv * e1000_dma_malloc and e1000_dma_free. 301155709Sglebius */ 302155709Sglebiusstruct em_dma_alloc { 303169240Sjfv bus_addr_t dma_paddr; 304169240Sjfv caddr_t dma_vaddr; 305169240Sjfv bus_dma_tag_t dma_tag; 306169240Sjfv bus_dmamap_t dma_map; 307169240Sjfv bus_dma_segment_t dma_seg; 308169240Sjfv int dma_nseg; 309155709Sglebius}; 310119509Spdeuskar 311194865Sjfvstruct adapter; 312194865Sjfv 313194865Sjfvstruct em_int_delay_info { 314194865Sjfv struct adapter *adapter; /* Back-pointer to the adapter struct */ 315194865Sjfv int offset; /* Register offset to read/write */ 316194865Sjfv int value; /* Current value in usecs */ 317194865Sjfv}; 318194865Sjfv 319205869Sjfv/* 320205869Sjfv * The transmit ring, one per tx queue 321205869Sjfv */ 322205869Sjfvstruct tx_ring { 323205869Sjfv struct adapter *adapter; 324205869Sjfv struct mtx tx_mtx; 325205869Sjfv char mtx_name[16]; 326205869Sjfv u32 me; 327205869Sjfv u32 msix; 328205869Sjfv u32 ims; 329283923Ssbruno int busy; 330205869Sjfv struct em_dma_alloc txdma; 331205869Sjfv struct e1000_tx_desc *tx_base; 332205869Sjfv struct task tx_task; 333205869Sjfv struct taskqueue *tq; 334205869Sjfv u32 next_avail_desc; 335205869Sjfv u32 next_to_clean; 336293331Ssbruno struct em_txbuffer *tx_buffers; 337205869Sjfv volatile u16 tx_avail; 338205869Sjfv u32 tx_tso; /* last tx was tso */ 339205869Sjfv u16 last_hw_offload; 340213234Sjfv u8 last_hw_ipcso; 341213234Sjfv u8 last_hw_ipcss; 342213234Sjfv u8 last_hw_tucso; 343213234Sjfv u8 last_hw_tucss; 344205869Sjfv#if __FreeBSD_version >= 800000 345205869Sjfv struct buf_ring *br; 346205869Sjfv#endif 347205869Sjfv /* Interrupt resources */ 348205869Sjfv bus_dma_tag_t txtag; 349205869Sjfv void *tag; 350205869Sjfv struct resource *res; 351205884Sjfv unsigned long tx_irq; 352205884Sjfv unsigned long no_desc_avail; 353205869Sjfv}; 354205869Sjfv 355205869Sjfv/* 356205869Sjfv * The Receive ring, one per rx queue 357205869Sjfv */ 358205869Sjfvstruct rx_ring { 359205869Sjfv struct adapter *adapter; 360205869Sjfv u32 me; 361205869Sjfv u32 msix; 362205869Sjfv u32 ims; 363205869Sjfv struct mtx rx_mtx; 364205869Sjfv char mtx_name[16]; 365205869Sjfv u32 payload; 366205869Sjfv struct task rx_task; 367205869Sjfv struct taskqueue *tq; 368293331Ssbruno union e1000_rx_desc_extended *rx_base; 369205869Sjfv struct em_dma_alloc rxdma; 370205884Sjfv u32 next_to_refresh; 371205884Sjfv u32 next_to_check; 372293331Ssbruno struct em_rxbuffer *rx_buffers; 373205869Sjfv struct mbuf *fmp; 374205869Sjfv struct mbuf *lmp; 375205869Sjfv 376205869Sjfv /* Interrupt resources */ 377205869Sjfv void *tag; 378205869Sjfv struct resource *res; 379205869Sjfv bus_dma_tag_t rxtag; 380212303Sjfv bool discard; 381205869Sjfv 382205869Sjfv /* Soft stats */ 383205884Sjfv unsigned long rx_irq; 384212303Sjfv unsigned long rx_discarded; 385205884Sjfv unsigned long rx_packets; 386205884Sjfv unsigned long rx_bytes; 387205869Sjfv}; 388205869Sjfv 389205869Sjfv 390203081Sjfv/* Our adapter structure */ 391203081Sjfvstruct adapter { 392266978Smarcel if_t ifp; 393169240Sjfv struct e1000_hw hw; 394119509Spdeuskar 395203081Sjfv /* FreeBSD operating-system-specific structures. */ 396169240Sjfv struct e1000_osdep osdep; 397155709Sglebius struct device *dev; 398206001Smarius struct cdev *led_dev; 399176667Sjfv 400203081Sjfv struct resource *memory; 401203081Sjfv struct resource *flash; 402205869Sjfv struct resource *msix_mem; 403316540Ssbruno int memrid; 404176667Sjfv 405205869Sjfv struct resource *res; 406205869Sjfv void *tag; 407205869Sjfv u32 linkvec; 408205869Sjfv u32 ivars; 409176667Sjfv 410155709Sglebius struct ifmedia media; 411120364Ssam struct callout timer; 412205869Sjfv int msix; 413160519Syongari int if_flags; 414173788Sjfv int max_frame_size; 415173788Sjfv int min_frame_size; 416173788Sjfv struct mtx core_mtx; 417137609Srwatson int em_insert_vlan_header; 418205869Sjfv u32 ims; 419205869Sjfv bool in_detach; 420203081Sjfv 421203081Sjfv /* Task for FAST handling */ 422203081Sjfv struct task link_task; 423205869Sjfv struct task que_task; 424169240Sjfv struct taskqueue *tq; /* private task queue */ 425176667Sjfv 426185353Sjfv eventhandler_tag vlan_attach; 427185353Sjfv eventhandler_tag vlan_detach; 428185353Sjfv 429205869Sjfv u16 num_vlans; 430283959Ssbruno u8 num_queues; 431205869Sjfv 432205869Sjfv /* 433205869Sjfv * Transmit rings: 434205869Sjfv * Allocated at run time, an array of rings. 435205869Sjfv */ 436205869Sjfv struct tx_ring *tx_rings; 437205869Sjfv int num_tx_desc; 438205869Sjfv u32 txd_cmd; 439205869Sjfv 440205869Sjfv /* 441205869Sjfv * Receive rings: 442205869Sjfv * Allocated at run time, an array of rings. 443205869Sjfv */ 444205869Sjfv struct rx_ring *rx_rings; 445205869Sjfv int num_rx_desc; 446205869Sjfv u32 rx_process_limit; 447214363Sjfv u32 rx_mbuf_sz; 448205869Sjfv 449169240Sjfv /* Management and WOL features */ 450203081Sjfv u32 wol; 451203081Sjfv bool has_manage; 452203081Sjfv bool has_amt; 453163730Sjfv 454211913Syongari /* Multicast array memory */ 455211913Syongari u8 *mta; 456212303Sjfv 457214363Sjfv /* 458214363Sjfv ** Shadow VFTA table, this is needed because 459214363Sjfv ** the real vlan filter table gets cleared during 460214363Sjfv ** a soft reset and the driver needs to be able 461214363Sjfv ** to repopulate it. 462214363Sjfv */ 463214363Sjfv u32 shadow_vfta[EM_VFTA_SIZE]; 464214363Sjfv 465214363Sjfv /* Info about the interface */ 466228387Sjfv u16 link_active; 467228387Sjfv u16 fc; 468214363Sjfv u16 link_speed; 469214363Sjfv u16 link_duplex; 470214363Sjfv u32 smartspeed; 471214363Sjfv 472203081Sjfv struct em_int_delay_info tx_int_delay; 473203081Sjfv struct em_int_delay_info tx_abs_int_delay; 474203081Sjfv struct em_int_delay_info rx_int_delay; 475203081Sjfv struct em_int_delay_info rx_abs_int_delay; 476250414Sluigi struct em_int_delay_info tx_itr; 47787189Spdeuskar 47897785Spdeuskar /* Misc stats maintained by the driver */ 479169240Sjfv unsigned long dropped_pkts; 480293854Smarius unsigned long link_irq; 481293854Smarius unsigned long mbuf_defrag_failed; 482293854Smarius unsigned long no_tx_dma_setup; 483155709Sglebius unsigned long no_tx_map_avail; 484205869Sjfv unsigned long rx_overruns; 485152247Sglebius unsigned long watchdog_events; 486112472Spdeuskar 487169240Sjfv struct e1000_hw_stats stats; 48887189Spdeuskar}; 48987189Spdeuskar 490205869Sjfv/******************************************************************************** 491163730Sjfv * vendor_info_array 492163730Sjfv * 493163730Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 494163730Sjfv * should load. 495163730Sjfv * 496205869Sjfv ********************************************************************************/ 497163730Sjfvtypedef struct _em_vendor_info_t { 498163730Sjfv unsigned int vendor_id; 499163730Sjfv unsigned int device_id; 500163730Sjfv unsigned int subvendor_id; 501163730Sjfv unsigned int subdevice_id; 502163730Sjfv unsigned int index; 503163730Sjfv} em_vendor_info_t; 504163730Sjfv 505293331Ssbrunostruct em_txbuffer { 506169240Sjfv int next_eop; /* Index of the desc to watch */ 507163730Sjfv struct mbuf *m_head; 508163730Sjfv bus_dmamap_t map; /* bus_dma map for packet */ 509163730Sjfv}; 510163730Sjfv 511293331Ssbrunostruct em_rxbuffer { 512293331Ssbruno int next_eop; /* Index of the desc to watch */ 513293331Ssbruno struct mbuf *m_head; 514293331Ssbruno bus_dmamap_t map; /* bus_dma map for packet */ 515293331Ssbruno bus_addr_t paddr; 516293331Ssbruno}; 517220251Sjfv 518293331Ssbruno 519220251Sjfv/* 520220251Sjfv** Find the number of unrefreshed RX descriptors 521220251Sjfv*/ 522220251Sjfvstatic inline u16 523220251Sjfve1000_rx_unrefreshed(struct rx_ring *rxr) 524220251Sjfv{ 525220251Sjfv struct adapter *adapter = rxr->adapter; 526220251Sjfv 527220251Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 528220251Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 529220251Sjfv else 530220251Sjfv return ((adapter->num_rx_desc + rxr->next_to_check) - 531220251Sjfv rxr->next_to_refresh - 1); 532220251Sjfv} 533220251Sjfv 534173788Sjfv#define EM_CORE_LOCK_INIT(_sc, _name) \ 535174029Sjfv mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 536173788Sjfv#define EM_TX_LOCK_INIT(_sc, _name) \ 537174029Sjfv mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 538178523Sjfv#define EM_RX_LOCK_INIT(_sc, _name) \ 539178523Sjfv mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 540173788Sjfv#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 541173788Sjfv#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 542178523Sjfv#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 543173788Sjfv#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 544173788Sjfv#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 545191038Skmacy#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 546178523Sjfv#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 547173788Sjfv#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 548173788Sjfv#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 549178523Sjfv#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 550173788Sjfv#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 551173788Sjfv#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 552206437Sjfv#define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 553120364Ssam 554293331Ssbruno#define EM_RSSRK_SIZE 4 555293331Ssbruno#define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ 556293331Ssbruno key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ 557293331Ssbruno key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ 558293331Ssbruno key[(i) * EM_RSSRK_SIZE + 3] << 24) 559155709Sglebius#endif /* _EM_H_DEFINED_ */ 560