e1000_ich8lan.c revision 213234
1177867Sjfv/****************************************************************************** 2169240Sjfv 3203049Sjfv Copyright (c) 2001-2010, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 213234 2010-09-28 00:13:15Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82562G 10/100 Network Connection 37185353Sjfv * 82562G-2 10/100 Network Connection 38185353Sjfv * 82562GT 10/100 Network Connection 39185353Sjfv * 82562GT-2 10/100 Network Connection 40185353Sjfv * 82562V 10/100 Network Connection 41185353Sjfv * 82562V-2 10/100 Network Connection 42185353Sjfv * 82566DC-2 Gigabit Network Connection 43185353Sjfv * 82566DC Gigabit Network Connection 44185353Sjfv * 82566DM-2 Gigabit Network Connection 45185353Sjfv * 82566DM Gigabit Network Connection 46185353Sjfv * 82566MC Gigabit Network Connection 47185353Sjfv * 82566MM Gigabit Network Connection 48185353Sjfv * 82567LM Gigabit Network Connection 49185353Sjfv * 82567LF Gigabit Network Connection 50185353Sjfv * 82567V Gigabit Network Connection 51185353Sjfv * 82567LM-2 Gigabit Network Connection 52185353Sjfv * 82567LF-2 Gigabit Network Connection 53185353Sjfv * 82567V-2 Gigabit Network Connection 54185353Sjfv * 82567LF-3 Gigabit Network Connection 55185353Sjfv * 82567LM-3 Gigabit Network Connection 56185353Sjfv * 82567LM-4 Gigabit Network Connection 57194865Sjfv * 82577LM Gigabit Network Connection 58194865Sjfv * 82577LC Gigabit Network Connection 59194865Sjfv * 82578DM Gigabit Network Connection 60194865Sjfv * 82578DC Gigabit Network Connection 61213234Sjfv * 82579LM Gigabit Network Connection 62213234Sjfv * 82579V Gigabit Network Connection 63169240Sjfv */ 64169240Sjfv 65169589Sjfv#include "e1000_api.h" 66169240Sjfv 67177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 68194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); 69177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 70177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 71177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 72177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 73200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw); 74200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw); 75177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 76213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 77213234Sjfvstatic void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 78177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 79177867Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 80200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 81177867Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 82173788Sjfv bool active); 83177867Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 84173788Sjfv bool active); 85177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 86173788Sjfv u16 words, u16 *data); 87177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 88173788Sjfv u16 words, u16 *data); 89177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 90177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 91177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 92173788Sjfv u16 *data); 93194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 94177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 95177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 96177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 97177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 98177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 99177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 100173788Sjfv u16 *speed, u16 *duplex); 101177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 102177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 103177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 104200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 105194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 106194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 107194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw); 108194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw); 109177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 110177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 111173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 112173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 113173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 114173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 115178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 116185353Sjfv u32 offset, u8 *data); 117173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 118185353Sjfv u8 size, u16 *data); 119177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 120173788Sjfv u32 offset, u16 *data); 121173788Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 122173788Sjfv u32 offset, u8 byte); 123177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 124173788Sjfv u32 offset, u8 data); 125173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 126173788Sjfv u8 size, u16 data); 127177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 128177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 129200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw); 130200243Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 131200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); 132203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 133213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 134213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 135169240Sjfv 136169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 137169240Sjfv/* Offset 04h HSFSTS */ 138169240Sjfvunion ich8_hws_flash_status { 139169240Sjfv struct ich8_hsfsts { 140169240Sjfv u16 flcdone :1; /* bit 0 Flash Cycle Done */ 141169240Sjfv u16 flcerr :1; /* bit 1 Flash Cycle Error */ 142169240Sjfv u16 dael :1; /* bit 2 Direct Access error Log */ 143169240Sjfv u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 144169240Sjfv u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 145169240Sjfv u16 reserved1 :2; /* bit 13:6 Reserved */ 146169240Sjfv u16 reserved2 :6; /* bit 13:6 Reserved */ 147169240Sjfv u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 148169240Sjfv u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 149169240Sjfv } hsf_status; 150169240Sjfv u16 regval; 151169240Sjfv}; 152169240Sjfv 153169240Sjfv/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 154169240Sjfv/* Offset 06h FLCTL */ 155169240Sjfvunion ich8_hws_flash_ctrl { 156169240Sjfv struct ich8_hsflctl { 157169240Sjfv u16 flcgo :1; /* 0 Flash Cycle Go */ 158169240Sjfv u16 flcycle :2; /* 2:1 Flash Cycle */ 159169240Sjfv u16 reserved :5; /* 7:3 Reserved */ 160169240Sjfv u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 161169240Sjfv u16 flockdn :6; /* 15:10 Reserved */ 162169240Sjfv } hsf_ctrl; 163169240Sjfv u16 regval; 164169240Sjfv}; 165169240Sjfv 166169240Sjfv/* ICH Flash Region Access Permissions */ 167169240Sjfvunion ich8_hws_flash_regacc { 168169240Sjfv struct ich8_flracc { 169169240Sjfv u32 grra :8; /* 0:7 GbE region Read Access */ 170169240Sjfv u32 grwa :8; /* 8:15 GbE region Write Access */ 171169240Sjfv u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 172169240Sjfv u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 173169240Sjfv } hsf_flregacc; 174169240Sjfv u16 regval; 175169240Sjfv}; 176169240Sjfv 177169240Sjfv/** 178194865Sjfv * e1000_init_phy_params_pchlan - Initialize PHY function pointers 179194865Sjfv * @hw: pointer to the HW structure 180194865Sjfv * 181194865Sjfv * Initialize family-specific PHY parameters and function pointers. 182194865Sjfv **/ 183194865Sjfvstatic s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 184194865Sjfv{ 185194865Sjfv struct e1000_phy_info *phy = &hw->phy; 186213234Sjfv u32 ctrl, fwsm; 187194865Sjfv s32 ret_val = E1000_SUCCESS; 188194865Sjfv 189194865Sjfv DEBUGFUNC("e1000_init_phy_params_pchlan"); 190194865Sjfv 191194865Sjfv phy->addr = 1; 192194865Sjfv phy->reset_delay_us = 100; 193194865Sjfv 194194865Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 195194865Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 196194865Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 197194865Sjfv phy->ops.read_reg = e1000_read_phy_reg_hv; 198200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 199194865Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 200194865Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 201200243Sjfv phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 202200243Sjfv phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 203194865Sjfv phy->ops.write_reg = e1000_write_phy_reg_hv; 204200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 205194865Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 206194865Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 207194865Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 208194865Sjfv 209213234Sjfv /* 210213234Sjfv * The MAC-PHY interconnect may still be in SMBus mode 211213234Sjfv * after Sx->S0. If the manageability engine (ME) is 212213234Sjfv * disabled, then toggle the LANPHYPC Value bit to force 213213234Sjfv * the interconnect to PCIe mode. 214213234Sjfv */ 215213234Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 216213234Sjfv if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) { 217205869Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 218205869Sjfv ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 219205869Sjfv ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 220205869Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 221205869Sjfv usec_delay(10); 222205869Sjfv ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 223205869Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 224205869Sjfv msec_delay(50); 225213234Sjfv 226213234Sjfv /* 227213234Sjfv * Gate automatic PHY configuration by hardware on 228213234Sjfv * non-managed 82579 229213234Sjfv */ 230213234Sjfv if (hw->mac.type == e1000_pch2lan) 231213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 232205869Sjfv } 233205869Sjfv 234205869Sjfv /* 235205869Sjfv * Reset the PHY before any acccess to it. Doing so, ensures that 236205869Sjfv * the PHY is in a known good state before we read/write PHY registers. 237205869Sjfv * The generic reset is sufficient here, because we haven't determined 238205869Sjfv * the PHY type yet. 239205869Sjfv */ 240205869Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 241205869Sjfv if (ret_val) 242205869Sjfv goto out; 243205869Sjfv 244213234Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 245213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 246213234Sjfv !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 247213234Sjfv msec_delay(10); 248213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 249213234Sjfv } 250213234Sjfv 251194865Sjfv phy->id = e1000_phy_unknown; 252213234Sjfv switch (hw->mac.type) { 253213234Sjfv default: 254213234Sjfv ret_val = e1000_get_phy_id(hw); 255213234Sjfv if (ret_val) 256213234Sjfv goto out; 257213234Sjfv if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 258213234Sjfv break; 259213234Sjfv /* fall-through */ 260213234Sjfv case e1000_pch2lan: 261203049Sjfv /* 262213234Sjfv * In case the PHY needs to be in mdio slow mode, 263203049Sjfv * set slow mode and try to get the PHY id again. 264203049Sjfv */ 265203049Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 266203049Sjfv if (ret_val) 267203049Sjfv goto out; 268203049Sjfv ret_val = e1000_get_phy_id(hw); 269203049Sjfv if (ret_val) 270203049Sjfv goto out; 271213234Sjfv break; 272203049Sjfv } 273194865Sjfv phy->type = e1000_get_phy_type_from_id(phy->id); 274194865Sjfv 275200243Sjfv switch (phy->type) { 276200243Sjfv case e1000_phy_82577: 277213234Sjfv case e1000_phy_82579: 278194865Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 279194865Sjfv phy->ops.force_speed_duplex = 280194865Sjfv e1000_phy_force_speed_duplex_82577; 281200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 282194865Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 283194865Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 284205869Sjfv break; 285200243Sjfv case e1000_phy_82578: 286200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 287200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 288200243Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 289200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 290200243Sjfv break; 291200243Sjfv default: 292200243Sjfv ret_val = -E1000_ERR_PHY; 293200243Sjfv break; 294194865Sjfv } 295194865Sjfv 296203049Sjfvout: 297194865Sjfv return ret_val; 298194865Sjfv} 299194865Sjfv 300194865Sjfv/** 301169240Sjfv * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 302169589Sjfv * @hw: pointer to the HW structure 303169240Sjfv * 304169240Sjfv * Initialize family-specific PHY parameters and function pointers. 305169240Sjfv **/ 306177867Sjfvstatic s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 307169240Sjfv{ 308169240Sjfv struct e1000_phy_info *phy = &hw->phy; 309169240Sjfv s32 ret_val = E1000_SUCCESS; 310169589Sjfv u16 i = 0; 311169240Sjfv 312169240Sjfv DEBUGFUNC("e1000_init_phy_params_ich8lan"); 313169240Sjfv 314177867Sjfv phy->addr = 1; 315177867Sjfv phy->reset_delay_us = 100; 316169240Sjfv 317177867Sjfv phy->ops.acquire = e1000_acquire_swflag_ich8lan; 318177867Sjfv phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 319177867Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 320177867Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 321177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 322177867Sjfv phy->ops.release = e1000_release_swflag_ich8lan; 323177867Sjfv phy->ops.reset = e1000_phy_hw_reset_ich8lan; 324177867Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 325177867Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 326177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 327177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 328177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 329169240Sjfv 330176667Sjfv /* 331176667Sjfv * We may need to do this twice - once for IGP and if that fails, 332176667Sjfv * we'll set BM func pointers and try again 333176667Sjfv */ 334176667Sjfv ret_val = e1000_determine_phy_address(hw); 335176667Sjfv if (ret_val) { 336177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 337177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 338176667Sjfv ret_val = e1000_determine_phy_address(hw); 339176667Sjfv if (ret_val) { 340190872Sjfv DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 341176667Sjfv goto out; 342176667Sjfv } 343176667Sjfv } 344169240Sjfv 345169589Sjfv phy->id = 0; 346169589Sjfv while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 347169589Sjfv (i++ < 100)) { 348169589Sjfv msec_delay(1); 349169589Sjfv ret_val = e1000_get_phy_id(hw); 350169589Sjfv if (ret_val) 351169589Sjfv goto out; 352169589Sjfv } 353169589Sjfv 354169240Sjfv /* Verify phy id */ 355169240Sjfv switch (phy->id) { 356169240Sjfv case IGP03E1000_E_PHY_ID: 357169240Sjfv phy->type = e1000_phy_igp_3; 358169240Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 359200243Sjfv phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; 360200243Sjfv phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; 361200243Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 362200243Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 363200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 364169240Sjfv break; 365169240Sjfv case IFE_E_PHY_ID: 366169240Sjfv case IFE_PLUS_E_PHY_ID: 367169240Sjfv case IFE_C_E_PHY_ID: 368169240Sjfv phy->type = e1000_phy_ife; 369169240Sjfv phy->autoneg_mask = E1000_ALL_NOT_GIG; 370200243Sjfv phy->ops.get_info = e1000_get_phy_info_ife; 371200243Sjfv phy->ops.check_polarity = e1000_check_polarity_ife; 372200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 373169240Sjfv break; 374176667Sjfv case BME1000_E_PHY_ID: 375176667Sjfv phy->type = e1000_phy_bm; 376176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 377177867Sjfv phy->ops.read_reg = e1000_read_phy_reg_bm; 378177867Sjfv phy->ops.write_reg = e1000_write_phy_reg_bm; 379177867Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 380200243Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 381200243Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 382200243Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 383176667Sjfv break; 384169240Sjfv default: 385169240Sjfv ret_val = -E1000_ERR_PHY; 386169240Sjfv goto out; 387169240Sjfv } 388169240Sjfv 389169240Sjfvout: 390169240Sjfv return ret_val; 391169240Sjfv} 392169240Sjfv 393169240Sjfv/** 394169240Sjfv * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 395169589Sjfv * @hw: pointer to the HW structure 396169240Sjfv * 397169240Sjfv * Initialize family-specific NVM parameters and function 398169240Sjfv * pointers. 399169240Sjfv **/ 400177867Sjfvstatic s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 401169240Sjfv{ 402169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 403185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 404169240Sjfv u32 gfpreg, sector_base_addr, sector_end_addr; 405173788Sjfv s32 ret_val = E1000_SUCCESS; 406169240Sjfv u16 i; 407169240Sjfv 408169240Sjfv DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 409169240Sjfv 410173788Sjfv /* Can't read flash registers if the register set isn't mapped. */ 411169240Sjfv if (!hw->flash_address) { 412169240Sjfv DEBUGOUT("ERROR: Flash registers not mapped\n"); 413169240Sjfv ret_val = -E1000_ERR_CONFIG; 414169240Sjfv goto out; 415169240Sjfv } 416169240Sjfv 417185353Sjfv nvm->type = e1000_nvm_flash_sw; 418169240Sjfv 419169240Sjfv gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 420169240Sjfv 421173788Sjfv /* 422173788Sjfv * sector_X_addr is a "sector"-aligned address (4096 bytes) 423169240Sjfv * Add 1 to sector_end_addr since this sector is included in 424173788Sjfv * the overall size. 425173788Sjfv */ 426169240Sjfv sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 427169240Sjfv sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 428169240Sjfv 429169240Sjfv /* flash_base_addr is byte-aligned */ 430185353Sjfv nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 431169240Sjfv 432173788Sjfv /* 433173788Sjfv * find total size of the NVM, then cut in half since the total 434173788Sjfv * size represents two separate NVM banks. 435173788Sjfv */ 436185353Sjfv nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 437169240Sjfv << FLASH_SECTOR_ADDR_SHIFT; 438185353Sjfv nvm->flash_bank_size /= 2; 439169240Sjfv /* Adjust to word count */ 440185353Sjfv nvm->flash_bank_size /= sizeof(u16); 441169240Sjfv 442185353Sjfv nvm->word_size = E1000_SHADOW_RAM_WORDS; 443169240Sjfv 444169240Sjfv /* Clear shadow ram */ 445169240Sjfv for (i = 0; i < nvm->word_size; i++) { 446169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 447169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 448169240Sjfv } 449169240Sjfv 450200243Sjfv E1000_MUTEX_INIT(&dev_spec->nvm_mutex); 451200243Sjfv E1000_MUTEX_INIT(&dev_spec->swflag_mutex); 452200243Sjfv 453169240Sjfv /* Function Pointers */ 454200243Sjfv nvm->ops.acquire = e1000_acquire_nvm_ich8lan; 455200243Sjfv nvm->ops.release = e1000_release_nvm_ich8lan; 456177867Sjfv nvm->ops.read = e1000_read_nvm_ich8lan; 457177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 458177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 459177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 460177867Sjfv nvm->ops.write = e1000_write_nvm_ich8lan; 461169240Sjfv 462169240Sjfvout: 463169240Sjfv return ret_val; 464169240Sjfv} 465169240Sjfv 466169240Sjfv/** 467169240Sjfv * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 468169589Sjfv * @hw: pointer to the HW structure 469169240Sjfv * 470169240Sjfv * Initialize family-specific MAC parameters and function 471169240Sjfv * pointers. 472169240Sjfv **/ 473177867Sjfvstatic s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 474169240Sjfv{ 475169240Sjfv struct e1000_mac_info *mac = &hw->mac; 476190872Sjfv u16 pci_cfg; 477169240Sjfv 478169240Sjfv DEBUGFUNC("e1000_init_mac_params_ich8lan"); 479169240Sjfv 480169240Sjfv /* Set media type function pointer */ 481173788Sjfv hw->phy.media_type = e1000_media_type_copper; 482169240Sjfv 483169240Sjfv /* Set mta register count */ 484169240Sjfv mac->mta_reg_count = 32; 485169240Sjfv /* Set rar entry count */ 486169240Sjfv mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 487169240Sjfv if (mac->type == e1000_ich8lan) 488169240Sjfv mac->rar_entry_count--; 489169240Sjfv /* Set if part includes ASF firmware */ 490169240Sjfv mac->asf_firmware_present = TRUE; 491205869Sjfv /* FWSM register */ 492205869Sjfv mac->has_fwsm = TRUE; 493205869Sjfv /* ARC subsystem not supported */ 494205869Sjfv mac->arc_subsystem_valid = FALSE; 495200243Sjfv /* Adaptive IFS supported */ 496200243Sjfv mac->adaptive_ifs = TRUE; 497169240Sjfv 498169240Sjfv /* Function pointers */ 499169240Sjfv 500169240Sjfv /* bus type/speed/width */ 501177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 502185353Sjfv /* function id */ 503185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_single_port; 504169240Sjfv /* reset */ 505177867Sjfv mac->ops.reset_hw = e1000_reset_hw_ich8lan; 506169240Sjfv /* hw initialization */ 507177867Sjfv mac->ops.init_hw = e1000_init_hw_ich8lan; 508169240Sjfv /* link setup */ 509177867Sjfv mac->ops.setup_link = e1000_setup_link_ich8lan; 510169240Sjfv /* physical interface setup */ 511177867Sjfv mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 512169240Sjfv /* check for link */ 513200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; 514169240Sjfv /* link info */ 515177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 516169240Sjfv /* multicast address update */ 517177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 518169240Sjfv /* clear hardware counters */ 519177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 520169240Sjfv 521190872Sjfv /* LED operations */ 522190872Sjfv switch (mac->type) { 523190872Sjfv case e1000_ich8lan: 524190872Sjfv case e1000_ich9lan: 525190872Sjfv case e1000_ich10lan: 526213234Sjfv /* check management mode */ 527213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 528190872Sjfv /* ID LED init */ 529190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 530190872Sjfv /* blink LED */ 531190872Sjfv mac->ops.blink_led = e1000_blink_led_generic; 532190872Sjfv /* setup LED */ 533190872Sjfv mac->ops.setup_led = e1000_setup_led_generic; 534190872Sjfv /* cleanup LED */ 535190872Sjfv mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 536190872Sjfv /* turn on/off LED */ 537190872Sjfv mac->ops.led_on = e1000_led_on_ich8lan; 538190872Sjfv mac->ops.led_off = e1000_led_off_ich8lan; 539190872Sjfv break; 540213234Sjfv case e1000_pch2lan: 541213234Sjfv mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 542213234Sjfv mac->ops.rar_set = e1000_rar_set_pch2lan; 543213234Sjfv /* fall-through */ 544194865Sjfv case e1000_pchlan: 545194865Sjfv /* save PCH revision_id */ 546194865Sjfv e1000_read_pci_cfg(hw, 0x2, &pci_cfg); 547194865Sjfv hw->revision_id = (u8)(pci_cfg &= 0x000F); 548213234Sjfv /* check management mode */ 549213234Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 550194865Sjfv /* ID LED init */ 551194865Sjfv mac->ops.id_led_init = e1000_id_led_init_pchlan; 552194865Sjfv /* setup LED */ 553194865Sjfv mac->ops.setup_led = e1000_setup_led_pchlan; 554194865Sjfv /* cleanup LED */ 555194865Sjfv mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 556194865Sjfv /* turn on/off LED */ 557194865Sjfv mac->ops.led_on = e1000_led_on_pchlan; 558194865Sjfv mac->ops.led_off = e1000_led_off_pchlan; 559194865Sjfv break; 560190872Sjfv default: 561190872Sjfv break; 562190872Sjfv } 563190872Sjfv 564169240Sjfv /* Enable PCS Lock-loss workaround for ICH8 */ 565169240Sjfv if (mac->type == e1000_ich8lan) 566169240Sjfv e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 567169240Sjfv 568213234Sjfv /* Gate automatic PHY configuration by hardware on managed 82579 */ 569213234Sjfv if ((mac->type == e1000_pch2lan) && 570213234Sjfv (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 571213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 572213234Sjfv 573185353Sjfv return E1000_SUCCESS; 574169240Sjfv} 575169240Sjfv 576169240Sjfv/** 577213234Sjfv * e1000_set_eee_pchlan - Enable/disable EEE support 578213234Sjfv * @hw: pointer to the HW structure 579213234Sjfv * 580213234Sjfv * Enable/disable EEE based on setting in dev_spec structure. The bits in 581213234Sjfv * the LPI Control register will remain set only if/when link is up. 582213234Sjfv **/ 583213234Sjfvstatic s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 584213234Sjfv{ 585213234Sjfv s32 ret_val = E1000_SUCCESS; 586213234Sjfv u16 phy_reg; 587213234Sjfv 588213234Sjfv DEBUGFUNC("e1000_set_eee_pchlan"); 589213234Sjfv 590213234Sjfv if (hw->phy.type != e1000_phy_82579) 591213234Sjfv goto out; 592213234Sjfv 593213234Sjfv ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg); 594213234Sjfv if (ret_val) 595213234Sjfv goto out; 596213234Sjfv 597213234Sjfv if (hw->dev_spec.ich8lan.eee_disable) 598213234Sjfv phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 599213234Sjfv else 600213234Sjfv phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 601213234Sjfv 602213234Sjfv ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg); 603213234Sjfvout: 604213234Sjfv return ret_val; 605213234Sjfv} 606213234Sjfv 607213234Sjfv/** 608200243Sjfv * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 609200243Sjfv * @hw: pointer to the HW structure 610200243Sjfv * 611200243Sjfv * Checks to see of the link status of the hardware has changed. If a 612200243Sjfv * change in link status has been detected, then we read the PHY registers 613200243Sjfv * to get the current speed/duplex if link exists. 614200243Sjfv **/ 615200243Sjfvstatic s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 616200243Sjfv{ 617200243Sjfv struct e1000_mac_info *mac = &hw->mac; 618200243Sjfv s32 ret_val; 619200243Sjfv bool link; 620200243Sjfv 621200243Sjfv DEBUGFUNC("e1000_check_for_copper_link_ich8lan"); 622200243Sjfv 623200243Sjfv /* 624200243Sjfv * We only want to go out to the PHY registers to see if Auto-Neg 625200243Sjfv * has completed and/or if our link status has changed. The 626200243Sjfv * get_link_status flag is set upon receiving a Link Status 627200243Sjfv * Change or Rx Sequence Error interrupt. 628200243Sjfv */ 629200243Sjfv if (!mac->get_link_status) { 630200243Sjfv ret_val = E1000_SUCCESS; 631200243Sjfv goto out; 632200243Sjfv } 633200243Sjfv 634200243Sjfv /* 635200243Sjfv * First we want to see if the MII Status Register reports 636200243Sjfv * link. If so, then we want to get the current speed/duplex 637200243Sjfv * of the PHY. 638200243Sjfv */ 639200243Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 640200243Sjfv if (ret_val) 641200243Sjfv goto out; 642200243Sjfv 643200243Sjfv if (hw->mac.type == e1000_pchlan) { 644200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, link); 645200243Sjfv if (ret_val) 646200243Sjfv goto out; 647200243Sjfv } 648200243Sjfv 649200243Sjfv if (!link) 650200243Sjfv goto out; /* No link detected */ 651200243Sjfv 652200243Sjfv mac->get_link_status = FALSE; 653200243Sjfv 654200243Sjfv if (hw->phy.type == e1000_phy_82578) { 655200243Sjfv ret_val = e1000_link_stall_workaround_hv(hw); 656200243Sjfv if (ret_val) 657200243Sjfv goto out; 658200243Sjfv } 659200243Sjfv 660213234Sjfv if (hw->mac.type == e1000_pch2lan) { 661213234Sjfv ret_val = e1000_k1_workaround_lv(hw); 662213234Sjfv if (ret_val) 663213234Sjfv goto out; 664213234Sjfv } 665213234Sjfv 666200243Sjfv /* 667200243Sjfv * Check if there was DownShift, must be checked 668200243Sjfv * immediately after link-up 669200243Sjfv */ 670200243Sjfv e1000_check_downshift_generic(hw); 671200243Sjfv 672213234Sjfv /* Enable/Disable EEE after link up */ 673213234Sjfv ret_val = e1000_set_eee_pchlan(hw); 674213234Sjfv if (ret_val) 675213234Sjfv goto out; 676213234Sjfv 677200243Sjfv /* 678200243Sjfv * If we are forcing speed/duplex, then we simply return since 679200243Sjfv * we have already determined whether we have link or not. 680200243Sjfv */ 681200243Sjfv if (!mac->autoneg) { 682200243Sjfv ret_val = -E1000_ERR_CONFIG; 683200243Sjfv goto out; 684200243Sjfv } 685200243Sjfv 686200243Sjfv /* 687200243Sjfv * Auto-Neg is enabled. Auto Speed Detection takes care 688200243Sjfv * of MAC speed/duplex configuration. So we only need to 689200243Sjfv * configure Collision Distance in the MAC. 690200243Sjfv */ 691200243Sjfv e1000_config_collision_dist_generic(hw); 692200243Sjfv 693200243Sjfv /* 694200243Sjfv * Configure Flow Control now that Auto-Neg has completed. 695200243Sjfv * First, we need to restore the desired flow control 696200243Sjfv * settings because we may have had to re-autoneg with a 697200243Sjfv * different link partner. 698200243Sjfv */ 699200243Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 700200243Sjfv if (ret_val) 701200243Sjfv DEBUGOUT("Error configuring flow control\n"); 702200243Sjfv 703200243Sjfvout: 704200243Sjfv return ret_val; 705200243Sjfv} 706200243Sjfv 707200243Sjfv/** 708169240Sjfv * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 709169589Sjfv * @hw: pointer to the HW structure 710169240Sjfv * 711169240Sjfv * Initialize family-specific function pointers for PHY, MAC, and NVM. 712169240Sjfv **/ 713173788Sjfvvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 714169240Sjfv{ 715169240Sjfv DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 716169240Sjfv 717177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 718177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 719194865Sjfv switch (hw->mac.type) { 720194865Sjfv case e1000_ich8lan: 721194865Sjfv case e1000_ich9lan: 722194865Sjfv case e1000_ich10lan: 723194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 724194865Sjfv break; 725194865Sjfv case e1000_pchlan: 726213234Sjfv case e1000_pch2lan: 727194865Sjfv hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 728194865Sjfv break; 729194865Sjfv default: 730194865Sjfv break; 731194865Sjfv } 732169240Sjfv} 733169240Sjfv 734169240Sjfv/** 735200243Sjfv * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 736200243Sjfv * @hw: pointer to the HW structure 737200243Sjfv * 738200243Sjfv * Acquires the mutex for performing NVM operations. 739200243Sjfv **/ 740200243Sjfvstatic s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) 741200243Sjfv{ 742200243Sjfv DEBUGFUNC("e1000_acquire_nvm_ich8lan"); 743200243Sjfv 744200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); 745200243Sjfv 746200243Sjfv return E1000_SUCCESS; 747200243Sjfv} 748200243Sjfv 749200243Sjfv/** 750200243Sjfv * e1000_release_nvm_ich8lan - Release NVM mutex 751200243Sjfv * @hw: pointer to the HW structure 752200243Sjfv * 753200243Sjfv * Releases the mutex used while performing NVM operations. 754200243Sjfv **/ 755200243Sjfvstatic void e1000_release_nvm_ich8lan(struct e1000_hw *hw) 756200243Sjfv{ 757200243Sjfv DEBUGFUNC("e1000_release_nvm_ich8lan"); 758200243Sjfv 759200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); 760200243Sjfv 761200243Sjfv return; 762200243Sjfv} 763200243Sjfv 764200243Sjfv/** 765169240Sjfv * e1000_acquire_swflag_ich8lan - Acquire software control flag 766169589Sjfv * @hw: pointer to the HW structure 767169240Sjfv * 768200243Sjfv * Acquires the software control flag for performing PHY and select 769200243Sjfv * MAC CSR accesses. 770169240Sjfv **/ 771177867Sjfvstatic s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 772169240Sjfv{ 773169240Sjfv u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 774169240Sjfv s32 ret_val = E1000_SUCCESS; 775169240Sjfv 776169240Sjfv DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 777169240Sjfv 778200243Sjfv E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); 779200243Sjfv 780169240Sjfv while (timeout) { 781169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 782200243Sjfv if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 783200243Sjfv break; 784169240Sjfv 785200243Sjfv msec_delay_irq(1); 786200243Sjfv timeout--; 787200243Sjfv } 788194865Sjfv 789200243Sjfv if (!timeout) { 790200243Sjfv DEBUGOUT("SW/FW/HW has locked the resource for too long.\n"); 791200243Sjfv ret_val = -E1000_ERR_CONFIG; 792200243Sjfv goto out; 793200243Sjfv } 794200243Sjfv 795200243Sjfv timeout = SW_FLAG_TIMEOUT; 796200243Sjfv 797200243Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 798200243Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 799200243Sjfv 800200243Sjfv while (timeout) { 801200243Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 802200243Sjfv if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 803200243Sjfv break; 804200243Sjfv 805169240Sjfv msec_delay_irq(1); 806169240Sjfv timeout--; 807169240Sjfv } 808169240Sjfv 809169240Sjfv if (!timeout) { 810200243Sjfv DEBUGOUT("Failed to acquire the semaphore.\n"); 811173788Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 812173788Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 813169240Sjfv ret_val = -E1000_ERR_CONFIG; 814169240Sjfv goto out; 815169240Sjfv } 816169240Sjfv 817169240Sjfvout: 818200243Sjfv if (ret_val) 819200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 820200243Sjfv 821169240Sjfv return ret_val; 822169240Sjfv} 823169240Sjfv 824169240Sjfv/** 825169240Sjfv * e1000_release_swflag_ich8lan - Release software control flag 826169589Sjfv * @hw: pointer to the HW structure 827169240Sjfv * 828200243Sjfv * Releases the software control flag for performing PHY and select 829200243Sjfv * MAC CSR accesses. 830169240Sjfv **/ 831177867Sjfvstatic void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 832169240Sjfv{ 833169240Sjfv u32 extcnf_ctrl; 834169240Sjfv 835169240Sjfv DEBUGFUNC("e1000_release_swflag_ich8lan"); 836169240Sjfv 837169240Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 838169240Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 839169240Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 840169240Sjfv 841200243Sjfv E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); 842200243Sjfv 843169240Sjfv return; 844169240Sjfv} 845169240Sjfv 846169240Sjfv/** 847169240Sjfv * e1000_check_mng_mode_ich8lan - Checks management mode 848169589Sjfv * @hw: pointer to the HW structure 849169240Sjfv * 850213234Sjfv * This checks if the adapter has any manageability enabled. 851169240Sjfv * This is a function pointer entry point only called by read/write 852169240Sjfv * routines for the PHY and NVM parts. 853169240Sjfv **/ 854177867Sjfvstatic bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 855169240Sjfv{ 856169240Sjfv u32 fwsm; 857169240Sjfv 858169240Sjfv DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 859169240Sjfv 860169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 861169240Sjfv 862213234Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 863213234Sjfv ((fwsm & E1000_FWSM_MODE_MASK) == 864213234Sjfv (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 865169240Sjfv} 866169240Sjfv 867169240Sjfv/** 868213234Sjfv * e1000_check_mng_mode_pchlan - Checks management mode 869213234Sjfv * @hw: pointer to the HW structure 870213234Sjfv * 871213234Sjfv * This checks if the adapter has iAMT enabled. 872213234Sjfv * This is a function pointer entry point only called by read/write 873213234Sjfv * routines for the PHY and NVM parts. 874213234Sjfv **/ 875213234Sjfvstatic bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 876213234Sjfv{ 877213234Sjfv u32 fwsm; 878213234Sjfv 879213234Sjfv DEBUGFUNC("e1000_check_mng_mode_pchlan"); 880213234Sjfv 881213234Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 882213234Sjfv 883213234Sjfv return (fwsm & E1000_ICH_FWSM_FW_VALID) && 884213234Sjfv (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 885213234Sjfv} 886213234Sjfv 887213234Sjfv/** 888213234Sjfv * e1000_rar_set_pch2lan - Set receive address register 889213234Sjfv * @hw: pointer to the HW structure 890213234Sjfv * @addr: pointer to the receive address 891213234Sjfv * @index: receive address array register 892213234Sjfv * 893213234Sjfv * Sets the receive address array register at index to the address passed 894213234Sjfv * in by addr. For 82579, RAR[0] is the base address register that is to 895213234Sjfv * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 896213234Sjfv * Use SHRA[0-3] in place of those reserved for ME. 897213234Sjfv **/ 898213234Sjfvstatic void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 899213234Sjfv{ 900213234Sjfv u32 rar_low, rar_high; 901213234Sjfv 902213234Sjfv DEBUGFUNC("e1000_rar_set_pch2lan"); 903213234Sjfv 904213234Sjfv /* 905213234Sjfv * HW expects these in little endian so we reverse the byte order 906213234Sjfv * from network order (big endian) to little endian 907213234Sjfv */ 908213234Sjfv rar_low = ((u32) addr[0] | 909213234Sjfv ((u32) addr[1] << 8) | 910213234Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 911213234Sjfv 912213234Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 913213234Sjfv 914213234Sjfv /* If MAC address zero, no need to set the AV bit */ 915213234Sjfv if (rar_low || rar_high) 916213234Sjfv rar_high |= E1000_RAH_AV; 917213234Sjfv 918213234Sjfv if (index == 0) { 919213234Sjfv E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 920213234Sjfv E1000_WRITE_FLUSH(hw); 921213234Sjfv E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 922213234Sjfv E1000_WRITE_FLUSH(hw); 923213234Sjfv return; 924213234Sjfv } 925213234Sjfv 926213234Sjfv if (index < hw->mac.rar_entry_count) { 927213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); 928213234Sjfv E1000_WRITE_FLUSH(hw); 929213234Sjfv E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); 930213234Sjfv E1000_WRITE_FLUSH(hw); 931213234Sjfv 932213234Sjfv /* verify the register updates */ 933213234Sjfv if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && 934213234Sjfv (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) 935213234Sjfv return; 936213234Sjfv 937213234Sjfv DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 938213234Sjfv (index - 1), E1000_READ_REG(hw, E1000_FWSM)); 939213234Sjfv } 940213234Sjfv 941213234Sjfv DEBUGOUT1("Failed to write receive address at index %d\n", index); 942213234Sjfv} 943213234Sjfv 944213234Sjfv/** 945169240Sjfv * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 946169589Sjfv * @hw: pointer to the HW structure 947169240Sjfv * 948169240Sjfv * Checks if firmware is blocking the reset of the PHY. 949169240Sjfv * This is a function pointer entry point only called by 950169240Sjfv * reset routines. 951169240Sjfv **/ 952177867Sjfvstatic s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 953169240Sjfv{ 954169240Sjfv u32 fwsm; 955169240Sjfv 956169240Sjfv DEBUGFUNC("e1000_check_reset_block_ich8lan"); 957169240Sjfv 958205869Sjfv if (hw->phy.reset_disable) 959205869Sjfv return E1000_BLK_PHY_RESET; 960205869Sjfv 961169240Sjfv fwsm = E1000_READ_REG(hw, E1000_FWSM); 962169240Sjfv 963169240Sjfv return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 964169240Sjfv : E1000_BLK_PHY_RESET; 965169240Sjfv} 966169240Sjfv 967169240Sjfv/** 968213234Sjfv * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 969213234Sjfv * @hw: pointer to the HW structure 970213234Sjfv * 971213234Sjfv * Assumes semaphore already acquired. 972213234Sjfv * 973213234Sjfv **/ 974213234Sjfvstatic s32 e1000_write_smbus_addr(struct e1000_hw *hw) 975213234Sjfv{ 976213234Sjfv u16 phy_data; 977213234Sjfv u32 strap = E1000_READ_REG(hw, E1000_STRAP); 978213234Sjfv s32 ret_val = E1000_SUCCESS; 979213234Sjfv 980213234Sjfv strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 981213234Sjfv 982213234Sjfv ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 983213234Sjfv if (ret_val) 984213234Sjfv goto out; 985213234Sjfv 986213234Sjfv phy_data &= ~HV_SMB_ADDR_MASK; 987213234Sjfv phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 988213234Sjfv phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 989213234Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 990213234Sjfv 991213234Sjfvout: 992213234Sjfv return ret_val; 993213234Sjfv} 994213234Sjfv 995213234Sjfv/** 996200243Sjfv * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 997200243Sjfv * @hw: pointer to the HW structure 998200243Sjfv * 999200243Sjfv * SW should configure the LCD from the NVM extended configuration region 1000200243Sjfv * as a workaround for certain parts. 1001200243Sjfv **/ 1002200243Sjfvstatic s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 1003200243Sjfv{ 1004200243Sjfv struct e1000_phy_info *phy = &hw->phy; 1005200243Sjfv u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 1006203049Sjfv s32 ret_val = E1000_SUCCESS; 1007200243Sjfv u16 word_addr, reg_data, reg_addr, phy_page = 0; 1008200243Sjfv 1009213234Sjfv DEBUGFUNC("e1000_sw_lcd_config_ich8lan"); 1010203049Sjfv 1011200243Sjfv /* 1012200243Sjfv * Initialize the PHY from the NVM on ICH platforms. This 1013200243Sjfv * is needed due to an issue where the NVM configuration is 1014200243Sjfv * not properly autoloaded after power transitions. 1015200243Sjfv * Therefore, after each PHY reset, we will load the 1016200243Sjfv * configuration data out of the NVM manually. 1017200243Sjfv */ 1018213234Sjfv switch (hw->mac.type) { 1019213234Sjfv case e1000_ich8lan: 1020213234Sjfv if (phy->type != e1000_phy_igp_3) 1021213234Sjfv return ret_val; 1022213234Sjfv 1023213234Sjfv if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || 1024213234Sjfv (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { 1025213234Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 1026213234Sjfv break; 1027213234Sjfv } 1028213234Sjfv /* Fall-thru */ 1029213234Sjfv case e1000_pchlan: 1030213234Sjfv case e1000_pch2lan: 1031203049Sjfv sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 1032213234Sjfv break; 1033213234Sjfv default: 1034213234Sjfv return ret_val; 1035213234Sjfv } 1036200243Sjfv 1037213234Sjfv ret_val = hw->phy.ops.acquire(hw); 1038213234Sjfv if (ret_val) 1039213234Sjfv return ret_val; 1040213234Sjfv 1041203049Sjfv data = E1000_READ_REG(hw, E1000_FEXTNVM); 1042203049Sjfv if (!(data & sw_cfg_mask)) 1043203049Sjfv goto out; 1044200243Sjfv 1045203049Sjfv /* 1046203049Sjfv * Make sure HW does not configure LCD from PHY 1047203049Sjfv * extended configuration before SW configuration 1048203049Sjfv */ 1049203049Sjfv data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1050213234Sjfv if (!(hw->mac.type == e1000_pch2lan)) { 1051213234Sjfv if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 1052213234Sjfv goto out; 1053213234Sjfv } 1054203049Sjfv 1055203049Sjfv cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 1056203049Sjfv cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 1057203049Sjfv cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 1058203049Sjfv if (!cnf_size) 1059203049Sjfv goto out; 1060203049Sjfv 1061203049Sjfv cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 1062203049Sjfv cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 1063203049Sjfv 1064213234Sjfv if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && 1065213234Sjfv (hw->mac.type == e1000_pchlan)) || 1066213234Sjfv (hw->mac.type == e1000_pch2lan)) { 1067200243Sjfv /* 1068203049Sjfv * HW configures the SMBus address and LEDs when the 1069203049Sjfv * OEM and LCD Write Enable bits are set in the NVM. 1070203049Sjfv * When both NVM bits are cleared, SW will configure 1071203049Sjfv * them instead. 1072200243Sjfv */ 1073213234Sjfv ret_val = e1000_write_smbus_addr(hw); 1074203049Sjfv if (ret_val) 1075200243Sjfv goto out; 1076200243Sjfv 1077203049Sjfv data = E1000_READ_REG(hw, E1000_LEDCTL); 1078203049Sjfv ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 1079203049Sjfv (u16)data); 1080203049Sjfv if (ret_val) 1081200243Sjfv goto out; 1082203049Sjfv } 1083200243Sjfv 1084203049Sjfv /* Configure LCD from extended configuration region. */ 1085200243Sjfv 1086203049Sjfv /* cnf_base_addr is in DWORD */ 1087203049Sjfv word_addr = (u16)(cnf_base_addr << 1); 1088200243Sjfv 1089203049Sjfv for (i = 0; i < cnf_size; i++) { 1090203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 1091203049Sjfv ®_data); 1092203049Sjfv if (ret_val) 1093203049Sjfv goto out; 1094200243Sjfv 1095203049Sjfv ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 1096203049Sjfv 1, ®_addr); 1097203049Sjfv if (ret_val) 1098203049Sjfv goto out; 1099200243Sjfv 1100203049Sjfv /* Save off the PHY page for future writes. */ 1101203049Sjfv if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 1102203049Sjfv phy_page = reg_data; 1103203049Sjfv continue; 1104203049Sjfv } 1105200243Sjfv 1106203049Sjfv reg_addr &= PHY_REG_MASK; 1107203049Sjfv reg_addr |= phy_page; 1108200243Sjfv 1109203049Sjfv ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 1110203049Sjfv reg_data); 1111203049Sjfv if (ret_val) 1112203049Sjfv goto out; 1113200243Sjfv } 1114200243Sjfv 1115200243Sjfvout: 1116200243Sjfv hw->phy.ops.release(hw); 1117200243Sjfv return ret_val; 1118200243Sjfv} 1119200243Sjfv 1120200243Sjfv/** 1121200243Sjfv * e1000_k1_gig_workaround_hv - K1 Si workaround 1122200243Sjfv * @hw: pointer to the HW structure 1123200243Sjfv * @link: link up bool flag 1124200243Sjfv * 1125200243Sjfv * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 1126200243Sjfv * from a lower speed. This workaround disables K1 whenever link is at 1Gig 1127200243Sjfv * If link is down, the function will restore the default K1 setting located 1128200243Sjfv * in the NVM. 1129200243Sjfv **/ 1130200243Sjfvstatic s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 1131200243Sjfv{ 1132200243Sjfv s32 ret_val = E1000_SUCCESS; 1133200243Sjfv u16 status_reg = 0; 1134200243Sjfv bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 1135200243Sjfv 1136200243Sjfv DEBUGFUNC("e1000_k1_gig_workaround_hv"); 1137200243Sjfv 1138200243Sjfv if (hw->mac.type != e1000_pchlan) 1139200243Sjfv goto out; 1140200243Sjfv 1141200243Sjfv /* Wrap the whole flow with the sw flag */ 1142200243Sjfv ret_val = hw->phy.ops.acquire(hw); 1143200243Sjfv if (ret_val) 1144200243Sjfv goto out; 1145200243Sjfv 1146200243Sjfv /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 1147200243Sjfv if (link) { 1148200243Sjfv if (hw->phy.type == e1000_phy_82578) { 1149200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 1150200243Sjfv &status_reg); 1151200243Sjfv if (ret_val) 1152200243Sjfv goto release; 1153200243Sjfv 1154200243Sjfv status_reg &= BM_CS_STATUS_LINK_UP | 1155200243Sjfv BM_CS_STATUS_RESOLVED | 1156200243Sjfv BM_CS_STATUS_SPEED_MASK; 1157200243Sjfv 1158200243Sjfv if (status_reg == (BM_CS_STATUS_LINK_UP | 1159200243Sjfv BM_CS_STATUS_RESOLVED | 1160200243Sjfv BM_CS_STATUS_SPEED_1000)) 1161200243Sjfv k1_enable = FALSE; 1162200243Sjfv } 1163200243Sjfv 1164200243Sjfv if (hw->phy.type == e1000_phy_82577) { 1165200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 1166200243Sjfv &status_reg); 1167200243Sjfv if (ret_val) 1168200243Sjfv goto release; 1169200243Sjfv 1170200243Sjfv status_reg &= HV_M_STATUS_LINK_UP | 1171200243Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 1172200243Sjfv HV_M_STATUS_SPEED_MASK; 1173200243Sjfv 1174200243Sjfv if (status_reg == (HV_M_STATUS_LINK_UP | 1175200243Sjfv HV_M_STATUS_AUTONEG_COMPLETE | 1176200243Sjfv HV_M_STATUS_SPEED_1000)) 1177200243Sjfv k1_enable = FALSE; 1178200243Sjfv } 1179200243Sjfv 1180200243Sjfv /* Link stall fix for link up */ 1181200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1182200243Sjfv 0x0100); 1183200243Sjfv if (ret_val) 1184200243Sjfv goto release; 1185200243Sjfv 1186200243Sjfv } else { 1187200243Sjfv /* Link stall fix for link down */ 1188200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 1189200243Sjfv 0x4100); 1190200243Sjfv if (ret_val) 1191200243Sjfv goto release; 1192200243Sjfv } 1193200243Sjfv 1194200243Sjfv ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1195200243Sjfv 1196200243Sjfvrelease: 1197200243Sjfv hw->phy.ops.release(hw); 1198200243Sjfvout: 1199200243Sjfv return ret_val; 1200200243Sjfv} 1201200243Sjfv 1202200243Sjfv/** 1203200243Sjfv * e1000_configure_k1_ich8lan - Configure K1 power state 1204200243Sjfv * @hw: pointer to the HW structure 1205200243Sjfv * @enable: K1 state to configure 1206200243Sjfv * 1207200243Sjfv * Configure the K1 power state based on the provided parameter. 1208200243Sjfv * Assumes semaphore already acquired. 1209200243Sjfv * 1210200243Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1211200243Sjfv **/ 1212200243Sjfvs32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 1213200243Sjfv{ 1214200243Sjfv s32 ret_val = E1000_SUCCESS; 1215200243Sjfv u32 ctrl_reg = 0; 1216200243Sjfv u32 ctrl_ext = 0; 1217200243Sjfv u32 reg = 0; 1218200243Sjfv u16 kmrn_reg = 0; 1219200243Sjfv 1220213234Sjfv DEBUGFUNC("e1000_configure_k1_ich8lan"); 1221213234Sjfv 1222200243Sjfv ret_val = e1000_read_kmrn_reg_locked(hw, 1223200243Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 1224200243Sjfv &kmrn_reg); 1225200243Sjfv if (ret_val) 1226200243Sjfv goto out; 1227200243Sjfv 1228200243Sjfv if (k1_enable) 1229200243Sjfv kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 1230200243Sjfv else 1231200243Sjfv kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 1232200243Sjfv 1233200243Sjfv ret_val = e1000_write_kmrn_reg_locked(hw, 1234200243Sjfv E1000_KMRNCTRLSTA_K1_CONFIG, 1235200243Sjfv kmrn_reg); 1236200243Sjfv if (ret_val) 1237200243Sjfv goto out; 1238200243Sjfv 1239200243Sjfv usec_delay(20); 1240200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1241200243Sjfv ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1242200243Sjfv 1243200243Sjfv reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1244200243Sjfv reg |= E1000_CTRL_FRCSPD; 1245200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1246200243Sjfv 1247200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1248200243Sjfv usec_delay(20); 1249200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1250200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1251200243Sjfv usec_delay(20); 1252200243Sjfv 1253200243Sjfvout: 1254200243Sjfv return ret_val; 1255200243Sjfv} 1256200243Sjfv 1257200243Sjfv/** 1258200243Sjfv * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 1259200243Sjfv * @hw: pointer to the HW structure 1260200243Sjfv * @d0_state: boolean if entering d0 or d3 device state 1261200243Sjfv * 1262200243Sjfv * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 1263200243Sjfv * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 1264200243Sjfv * in NVM determines whether HW should configure LPLU and Gbe Disable. 1265200243Sjfv **/ 1266200243Sjfvs32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 1267200243Sjfv{ 1268200243Sjfv s32 ret_val = 0; 1269200243Sjfv u32 mac_reg; 1270200243Sjfv u16 oem_reg; 1271200243Sjfv 1272213234Sjfv DEBUGFUNC("e1000_oem_bits_config_ich8lan"); 1273213234Sjfv 1274213234Sjfv if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan)) 1275200243Sjfv return ret_val; 1276200243Sjfv 1277200243Sjfv ret_val = hw->phy.ops.acquire(hw); 1278200243Sjfv if (ret_val) 1279200243Sjfv return ret_val; 1280200243Sjfv 1281213234Sjfv if (!(hw->mac.type == e1000_pch2lan)) { 1282213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1283213234Sjfv if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 1284213234Sjfv goto out; 1285213234Sjfv } 1286200243Sjfv 1287200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); 1288200243Sjfv if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 1289200243Sjfv goto out; 1290200243Sjfv 1291200243Sjfv mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 1292200243Sjfv 1293200243Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 1294200243Sjfv if (ret_val) 1295200243Sjfv goto out; 1296200243Sjfv 1297200243Sjfv oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 1298200243Sjfv 1299200243Sjfv if (d0_state) { 1300200243Sjfv if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 1301200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1302200243Sjfv 1303200243Sjfv if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 1304200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1305200243Sjfv } else { 1306200243Sjfv if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) 1307200243Sjfv oem_reg |= HV_OEM_BITS_GBE_DIS; 1308200243Sjfv 1309200243Sjfv if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) 1310200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1311200243Sjfv } 1312200243Sjfv /* Restart auto-neg to activate the bits */ 1313200243Sjfv if (!hw->phy.ops.check_reset_block(hw)) 1314200243Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 1315200243Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 1316200243Sjfv 1317200243Sjfvout: 1318200243Sjfv hw->phy.ops.release(hw); 1319200243Sjfv 1320200243Sjfv return ret_val; 1321200243Sjfv} 1322200243Sjfv 1323200243Sjfv 1324200243Sjfv/** 1325194865Sjfv * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx 1326169589Sjfv * @hw: pointer to the HW structure 1327169240Sjfv **/ 1328194865Sjfvs32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 1329169240Sjfv{ 1330213234Sjfv DEBUGFUNC("e1000_hv_phy_powerdown_workaround_ich8lan"); 1331213234Sjfv 1332194865Sjfv if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2)) 1333194865Sjfv return E1000_SUCCESS; 1334169240Sjfv 1335194865Sjfv return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444); 1336194865Sjfv} 1337169240Sjfv 1338194865Sjfv/** 1339203049Sjfv * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 1340203049Sjfv * @hw: pointer to the HW structure 1341203049Sjfv **/ 1342203049Sjfvstatic s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 1343203049Sjfv{ 1344203049Sjfv s32 ret_val; 1345203049Sjfv u16 data; 1346203049Sjfv 1347213234Sjfv DEBUGFUNC("e1000_set_mdio_slow_mode_hv"); 1348213234Sjfv 1349203049Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); 1350203049Sjfv if (ret_val) 1351203049Sjfv return ret_val; 1352203049Sjfv 1353203049Sjfv data |= HV_KMRN_MDIO_SLOW; 1354203049Sjfv 1355203049Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); 1356203049Sjfv 1357203049Sjfv return ret_val; 1358203049Sjfv} 1359203049Sjfv 1360203049Sjfv/** 1361194865Sjfv * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1362194865Sjfv * done after every PHY reset. 1363194865Sjfv **/ 1364194865Sjfvstatic s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1365194865Sjfv{ 1366194865Sjfv s32 ret_val = E1000_SUCCESS; 1367203049Sjfv u16 phy_data; 1368194865Sjfv 1369213234Sjfv DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan"); 1370213234Sjfv 1371194865Sjfv if (hw->mac.type != e1000_pchlan) 1372200243Sjfv goto out; 1373194865Sjfv 1374203049Sjfv /* Set MDIO slow mode before any other MDIO access */ 1375203049Sjfv if (hw->phy.type == e1000_phy_82577) { 1376203049Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 1377203049Sjfv if (ret_val) 1378203049Sjfv goto out; 1379203049Sjfv } 1380203049Sjfv 1381194865Sjfv /* Hanksville M Phy init for IEEE. */ 1382194865Sjfv if ((hw->revision_id == 2) && 1383194865Sjfv (hw->phy.type == e1000_phy_82577) && 1384194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 1385194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8823); 1386194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0018); 1387194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8824); 1388194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0016); 1389194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8825); 1390194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x001A); 1391194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888C); 1392194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1393194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888D); 1394194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1395194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x888E); 1396194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0007); 1397194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8827); 1398194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1399194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8835); 1400194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1401194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8834); 1402194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0001); 1403194865Sjfv hw->phy.ops.write_reg(hw, 0x10, 0x8833); 1404194865Sjfv hw->phy.ops.write_reg(hw, 0x11, 0x0002); 1405169240Sjfv } 1406169240Sjfv 1407194865Sjfv if (((hw->phy.type == e1000_phy_82577) && 1408194865Sjfv ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 1409194865Sjfv ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 1410194865Sjfv /* Disable generation of early preamble */ 1411194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 1412194865Sjfv if (ret_val) 1413200243Sjfv goto out; 1414169240Sjfv 1415194865Sjfv /* Preamble tuning for SSC */ 1416194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 1417194865Sjfv if (ret_val) 1418200243Sjfv goto out; 1419194865Sjfv } 1420169240Sjfv 1421194865Sjfv if (hw->phy.type == e1000_phy_82578) { 1422194865Sjfv if (hw->revision_id < 3) { 1423194865Sjfv /* PHY config */ 1424194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 1425194865Sjfv 0x66C0); 1426194865Sjfv if (ret_val) 1427200243Sjfv goto out; 1428169240Sjfv 1429194865Sjfv /* PHY config */ 1430194865Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 1431194865Sjfv 0xFFFF); 1432194865Sjfv if (ret_val) 1433200243Sjfv goto out; 1434194865Sjfv } 1435169240Sjfv 1436194865Sjfv /* 1437194865Sjfv * Return registers to default by doing a soft reset then 1438194865Sjfv * writing 0x3140 to the control register. 1439194865Sjfv */ 1440194865Sjfv if (hw->phy.revision < 2) { 1441194865Sjfv e1000_phy_sw_reset_generic(hw); 1442194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 1443194865Sjfv 0x3140); 1444194865Sjfv } 1445194865Sjfv } 1446169240Sjfv 1447194865Sjfv if ((hw->revision_id == 2) && 1448194865Sjfv (hw->phy.type == e1000_phy_82577) && 1449194865Sjfv ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 1450194865Sjfv /* 1451194865Sjfv * Workaround for OEM (GbE) not operating after reset - 1452194865Sjfv * restart AN (twice) 1453194865Sjfv */ 1454194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 1455194865Sjfv if (ret_val) 1456200243Sjfv goto out; 1457194865Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 1458194865Sjfv if (ret_val) 1459200243Sjfv goto out; 1460194865Sjfv } 1461194865Sjfv 1462194865Sjfv /* Select page 0 */ 1463194865Sjfv ret_val = hw->phy.ops.acquire(hw); 1464169240Sjfv if (ret_val) 1465200243Sjfv goto out; 1466200243Sjfv 1467194865Sjfv hw->phy.addr = 1; 1468200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1469203049Sjfv hw->phy.ops.release(hw); 1470200243Sjfv if (ret_val) 1471200243Sjfv goto out; 1472169240Sjfv 1473200243Sjfv /* 1474200243Sjfv * Configure the K1 Si workaround during phy reset assuming there is 1475200243Sjfv * link so that it disables K1 if link is in 1Gbps. 1476200243Sjfv */ 1477200243Sjfv ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); 1478203049Sjfv if (ret_val) 1479203049Sjfv goto out; 1480200243Sjfv 1481203049Sjfv /* Workaround for link disconnects on a busy hub in half duplex */ 1482203049Sjfv ret_val = hw->phy.ops.acquire(hw); 1483203049Sjfv if (ret_val) 1484203049Sjfv goto out; 1485203049Sjfv ret_val = hw->phy.ops.read_reg_locked(hw, 1486203049Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 17), 1487203049Sjfv &phy_data); 1488203049Sjfv if (ret_val) 1489203049Sjfv goto release; 1490203049Sjfv ret_val = hw->phy.ops.write_reg_locked(hw, 1491203049Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 17), 1492203049Sjfv phy_data & 0x00FF); 1493203049Sjfvrelease: 1494203049Sjfv hw->phy.ops.release(hw); 1495200243Sjfvout: 1496194865Sjfv return ret_val; 1497194865Sjfv} 1498169240Sjfv 1499194865Sjfv/** 1500213234Sjfv * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 1501213234Sjfv * @hw: pointer to the HW structure 1502213234Sjfv **/ 1503213234Sjfvvoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 1504213234Sjfv{ 1505213234Sjfv u32 mac_reg; 1506213234Sjfv u16 i; 1507213234Sjfv 1508213234Sjfv DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan"); 1509213234Sjfv 1510213234Sjfv /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ 1511213234Sjfv for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1512213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); 1513213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF)); 1514213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF)); 1515213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); 1516213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF)); 1517213234Sjfv hw->phy.ops.write_reg(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000)); 1518213234Sjfv } 1519213234Sjfv} 1520213234Sjfv 1521213234Sjfvstatic u32 e1000_calc_rx_da_crc(u8 mac[]) 1522213234Sjfv{ 1523213234Sjfv u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ 1524213234Sjfv u32 i, j, mask, crc; 1525213234Sjfv 1526213234Sjfv DEBUGFUNC("e1000_calc_rx_da_crc"); 1527213234Sjfv 1528213234Sjfv crc = 0xffffffff; 1529213234Sjfv for (i = 0; i < 6; i++) { 1530213234Sjfv crc = crc ^ mac[i]; 1531213234Sjfv for (j = 8; j > 0; j--) { 1532213234Sjfv mask = (crc & 1) * (-1); 1533213234Sjfv crc = (crc >> 1) ^ (poly & mask); 1534213234Sjfv } 1535213234Sjfv } 1536213234Sjfv return ~crc; 1537213234Sjfv} 1538213234Sjfv 1539213234Sjfv/** 1540213234Sjfv * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 1541213234Sjfv * with 82579 PHY 1542213234Sjfv * @hw: pointer to the HW structure 1543213234Sjfv * @enable: flag to enable/disable workaround when enabling/disabling jumbos 1544213234Sjfv **/ 1545213234Sjfvs32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 1546213234Sjfv{ 1547213234Sjfv s32 ret_val = E1000_SUCCESS; 1548213234Sjfv u16 phy_reg, data; 1549213234Sjfv u32 mac_reg; 1550213234Sjfv u16 i; 1551213234Sjfv 1552213234Sjfv DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan"); 1553213234Sjfv 1554213234Sjfv if (hw->mac.type != e1000_pch2lan) 1555213234Sjfv goto out; 1556213234Sjfv 1557213234Sjfv /* disable Rx path while enabling/disabling workaround */ 1558213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); 1559213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); 1560213234Sjfv if (ret_val) 1561213234Sjfv goto out; 1562213234Sjfv 1563213234Sjfv if (enable) { 1564213234Sjfv /* 1565213234Sjfv * Write Rx addresses (rar_entry_count for RAL/H, +4 for 1566213234Sjfv * SHRAL/H) and initial CRC values to the MAC 1567213234Sjfv */ 1568213234Sjfv for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1569213234Sjfv u8 mac_addr[ETH_ADDR_LEN] = {0}; 1570213234Sjfv u32 addr_high, addr_low; 1571213234Sjfv 1572213234Sjfv addr_high = E1000_READ_REG(hw, E1000_RAH(i)); 1573213234Sjfv if (!(addr_high & E1000_RAH_AV)) 1574213234Sjfv continue; 1575213234Sjfv addr_low = E1000_READ_REG(hw, E1000_RAL(i)); 1576213234Sjfv mac_addr[0] = (addr_low & 0xFF); 1577213234Sjfv mac_addr[1] = ((addr_low >> 8) & 0xFF); 1578213234Sjfv mac_addr[2] = ((addr_low >> 16) & 0xFF); 1579213234Sjfv mac_addr[3] = ((addr_low >> 24) & 0xFF); 1580213234Sjfv mac_addr[4] = (addr_high & 0xFF); 1581213234Sjfv mac_addr[5] = ((addr_high >> 8) & 0xFF); 1582213234Sjfv 1583213234Sjfv E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), 1584213234Sjfv e1000_calc_rx_da_crc(mac_addr)); 1585213234Sjfv } 1586213234Sjfv 1587213234Sjfv /* Write Rx addresses to the PHY */ 1588213234Sjfv e1000_copy_rx_addrs_to_phy_ich8lan(hw); 1589213234Sjfv 1590213234Sjfv /* Enable jumbo frame workaround in the MAC */ 1591213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 1592213234Sjfv mac_reg &= ~(1 << 14); 1593213234Sjfv mac_reg |= (7 << 15); 1594213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 1595213234Sjfv 1596213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 1597213234Sjfv mac_reg |= E1000_RCTL_SECRC; 1598213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 1599213234Sjfv 1600213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1601213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1602213234Sjfv &data); 1603213234Sjfv if (ret_val) 1604213234Sjfv goto out; 1605213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1606213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1607213234Sjfv data | (1 << 0)); 1608213234Sjfv if (ret_val) 1609213234Sjfv goto out; 1610213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1611213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1612213234Sjfv &data); 1613213234Sjfv if (ret_val) 1614213234Sjfv goto out; 1615213234Sjfv data &= ~(0xF << 8); 1616213234Sjfv data |= (0xB << 8); 1617213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1618213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1619213234Sjfv data); 1620213234Sjfv if (ret_val) 1621213234Sjfv goto out; 1622213234Sjfv 1623213234Sjfv /* Enable jumbo frame workaround in the PHY */ 1624213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 1625213234Sjfv data &= ~(0x7F << 5); 1626213234Sjfv data |= (0x37 << 5); 1627213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 1628213234Sjfv if (ret_val) 1629213234Sjfv goto out; 1630213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 1631213234Sjfv data &= ~(1 << 13); 1632213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 1633213234Sjfv if (ret_val) 1634213234Sjfv goto out; 1635213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 1636213234Sjfv data &= ~(0x3FF << 2); 1637213234Sjfv data |= (0x1A << 2); 1638213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 1639213234Sjfv if (ret_val) 1640213234Sjfv goto out; 1641213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xFE00); 1642213234Sjfv if (ret_val) 1643213234Sjfv goto out; 1644213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 1645213234Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10)); 1646213234Sjfv if (ret_val) 1647213234Sjfv goto out; 1648213234Sjfv } else { 1649213234Sjfv /* Write MAC register values back to h/w defaults */ 1650213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); 1651213234Sjfv mac_reg &= ~(0xF << 14); 1652213234Sjfv E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); 1653213234Sjfv 1654213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_RCTL); 1655213234Sjfv mac_reg &= ~E1000_RCTL_SECRC; 1656213234Sjfv E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); 1657213234Sjfv 1658213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1659213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1660213234Sjfv &data); 1661213234Sjfv if (ret_val) 1662213234Sjfv goto out; 1663213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1664213234Sjfv E1000_KMRNCTRLSTA_CTRL_OFFSET, 1665213234Sjfv data & ~(1 << 0)); 1666213234Sjfv if (ret_val) 1667213234Sjfv goto out; 1668213234Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 1669213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1670213234Sjfv &data); 1671213234Sjfv if (ret_val) 1672213234Sjfv goto out; 1673213234Sjfv data &= ~(0xF << 8); 1674213234Sjfv data |= (0xB << 8); 1675213234Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 1676213234Sjfv E1000_KMRNCTRLSTA_HD_CTRL, 1677213234Sjfv data); 1678213234Sjfv if (ret_val) 1679213234Sjfv goto out; 1680213234Sjfv 1681213234Sjfv /* Write PHY register values back to h/w defaults */ 1682213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); 1683213234Sjfv data &= ~(0x7F << 5); 1684213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); 1685213234Sjfv if (ret_val) 1686213234Sjfv goto out; 1687213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); 1688213234Sjfv data |= (1 << 13); 1689213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); 1690213234Sjfv if (ret_val) 1691213234Sjfv goto out; 1692213234Sjfv hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); 1693213234Sjfv data &= ~(0x3FF << 2); 1694213234Sjfv data |= (0x8 << 2); 1695213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); 1696213234Sjfv if (ret_val) 1697213234Sjfv goto out; 1698213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); 1699213234Sjfv if (ret_val) 1700213234Sjfv goto out; 1701213234Sjfv hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); 1702213234Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & ~(1 << 10)); 1703213234Sjfv if (ret_val) 1704213234Sjfv goto out; 1705213234Sjfv } 1706213234Sjfv 1707213234Sjfv /* re-enable Rx path after enabling/disabling workaround */ 1708213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); 1709213234Sjfv 1710213234Sjfvout: 1711213234Sjfv return ret_val; 1712213234Sjfv} 1713213234Sjfv 1714213234Sjfv/** 1715213234Sjfv * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1716213234Sjfv * done after every PHY reset. 1717213234Sjfv **/ 1718213234Sjfvstatic s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1719213234Sjfv{ 1720213234Sjfv s32 ret_val = E1000_SUCCESS; 1721213234Sjfv 1722213234Sjfv DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 1723213234Sjfv 1724213234Sjfv if (hw->mac.type != e1000_pch2lan) 1725213234Sjfv goto out; 1726213234Sjfv 1727213234Sjfv /* Set MDIO slow mode before any other MDIO access */ 1728213234Sjfv ret_val = e1000_set_mdio_slow_mode_hv(hw); 1729213234Sjfv 1730213234Sjfvout: 1731213234Sjfv return ret_val; 1732213234Sjfv} 1733213234Sjfv 1734213234Sjfv/** 1735213234Sjfv * e1000_k1_gig_workaround_lv - K1 Si workaround 1736213234Sjfv * @hw: pointer to the HW structure 1737213234Sjfv * 1738213234Sjfv * Workaround to set the K1 beacon duration for 82579 parts 1739213234Sjfv **/ 1740213234Sjfvstatic s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 1741213234Sjfv{ 1742213234Sjfv s32 ret_val = E1000_SUCCESS; 1743213234Sjfv u16 status_reg = 0; 1744213234Sjfv u32 mac_reg; 1745213234Sjfv 1746213234Sjfv DEBUGFUNC("e1000_k1_workaround_lv"); 1747213234Sjfv 1748213234Sjfv if (hw->mac.type != e1000_pch2lan) 1749213234Sjfv goto out; 1750213234Sjfv 1751213234Sjfv /* Set K1 beacon duration based on 1Gbps speed or otherwise */ 1752213234Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); 1753213234Sjfv if (ret_val) 1754213234Sjfv goto out; 1755213234Sjfv 1756213234Sjfv if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 1757213234Sjfv == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 1758213234Sjfv mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); 1759213234Sjfv mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1760213234Sjfv 1761213234Sjfv if (status_reg & HV_M_STATUS_SPEED_1000) 1762213234Sjfv mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1763213234Sjfv else 1764213234Sjfv mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 1765213234Sjfv 1766213234Sjfv E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); 1767213234Sjfv } 1768213234Sjfv 1769213234Sjfvout: 1770213234Sjfv return ret_val; 1771213234Sjfv} 1772213234Sjfv 1773213234Sjfv/** 1774213234Sjfv * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 1775213234Sjfv * @hw: pointer to the HW structure 1776213234Sjfv * @gate: boolean set to TRUE to gate, FALSE to un-gate 1777213234Sjfv * 1778213234Sjfv * Gate/ungate the automatic PHY configuration via hardware; perform 1779213234Sjfv * the configuration via software instead. 1780213234Sjfv **/ 1781213234Sjfvstatic void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 1782213234Sjfv{ 1783213234Sjfv u32 extcnf_ctrl; 1784213234Sjfv 1785213234Sjfv DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan"); 1786213234Sjfv 1787213234Sjfv if (hw->mac.type != e1000_pch2lan) 1788213234Sjfv return; 1789213234Sjfv 1790213234Sjfv extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 1791213234Sjfv 1792213234Sjfv if (gate) 1793213234Sjfv extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 1794213234Sjfv else 1795213234Sjfv extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 1796213234Sjfv 1797213234Sjfv E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 1798213234Sjfv return; 1799213234Sjfv} 1800213234Sjfv 1801213234Sjfv/** 1802213234Sjfv * e1000_hv_phy_tuning_workaround_ich8lan - This is a Phy tuning work around 1803213234Sjfv * needed for Nahum3 + Hanksville testing, requested by HW team 1804213234Sjfv **/ 1805213234Sjfvstatic s32 e1000_hv_phy_tuning_workaround_ich8lan(struct e1000_hw *hw) 1806213234Sjfv{ 1807213234Sjfv s32 ret_val = E1000_SUCCESS; 1808213234Sjfv 1809213234Sjfv DEBUGFUNC("e1000_hv_phy_tuning_workaround_ich8lan"); 1810213234Sjfv 1811213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 1812213234Sjfv if (ret_val) 1813213234Sjfv goto out; 1814213234Sjfv 1815213234Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 1816213234Sjfv if (ret_val) 1817213234Sjfv goto out; 1818213234Sjfv 1819213234Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 0x66C0); 1820213234Sjfv if (ret_val) 1821213234Sjfv goto out; 1822213234Sjfv 1823213234Sjfv ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 0xFFFF); 1824213234Sjfv 1825213234Sjfvout: 1826213234Sjfv return ret_val; 1827213234Sjfv} 1828213234Sjfv 1829213234Sjfv/** 1830194865Sjfv * e1000_lan_init_done_ich8lan - Check for PHY config completion 1831194865Sjfv * @hw: pointer to the HW structure 1832194865Sjfv * 1833194865Sjfv * Check the appropriate indication the MAC has finished configuring the 1834194865Sjfv * PHY after a software reset. 1835194865Sjfv **/ 1836194865Sjfvstatic void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 1837194865Sjfv{ 1838194865Sjfv u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 1839169240Sjfv 1840194865Sjfv DEBUGFUNC("e1000_lan_init_done_ich8lan"); 1841169240Sjfv 1842194865Sjfv /* Wait for basic configuration completes before proceeding */ 1843194865Sjfv do { 1844194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 1845194865Sjfv data &= E1000_STATUS_LAN_INIT_DONE; 1846194865Sjfv usec_delay(100); 1847194865Sjfv } while ((!data) && --loop); 1848169240Sjfv 1849194865Sjfv /* 1850194865Sjfv * If basic configuration is incomplete before the above loop 1851194865Sjfv * count reaches 0, loading the configuration from NVM will 1852194865Sjfv * leave the PHY in a bad state possibly resulting in no link. 1853194865Sjfv */ 1854194865Sjfv if (loop == 0) 1855194865Sjfv DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 1856169240Sjfv 1857194865Sjfv /* Clear the Init Done bit for the next init event */ 1858194865Sjfv data = E1000_READ_REG(hw, E1000_STATUS); 1859194865Sjfv data &= ~E1000_STATUS_LAN_INIT_DONE; 1860194865Sjfv E1000_WRITE_REG(hw, E1000_STATUS, data); 1861169240Sjfv} 1862169240Sjfv 1863169240Sjfv/** 1864213234Sjfv * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 1865169589Sjfv * @hw: pointer to the HW structure 1866169240Sjfv **/ 1867213234Sjfvstatic s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 1868169240Sjfv{ 1869200243Sjfv s32 ret_val = E1000_SUCCESS; 1870200243Sjfv u16 reg; 1871169240Sjfv 1872213234Sjfv DEBUGFUNC("e1000_post_phy_reset_ich8lan"); 1873169240Sjfv 1874213234Sjfv if (hw->phy.ops.check_reset_block(hw)) 1875169240Sjfv goto out; 1876169240Sjfv 1877213234Sjfv /* Allow time for h/w to get to quiescent state after reset */ 1878194865Sjfv msec_delay(10); 1879194865Sjfv 1880203049Sjfv /* Perform any necessary post-reset workarounds */ 1881203049Sjfv switch (hw->mac.type) { 1882203049Sjfv case e1000_pchlan: 1883194865Sjfv ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 1884194865Sjfv if (ret_val) 1885194865Sjfv goto out; 1886203049Sjfv break; 1887213234Sjfv case e1000_pch2lan: 1888213234Sjfv ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 1889213234Sjfv if (ret_val) 1890213234Sjfv goto out; 1891213234Sjfv break; 1892203049Sjfv default: 1893203049Sjfv break; 1894194865Sjfv } 1895194865Sjfv 1896213234Sjfv if (hw->device_id == E1000_DEV_ID_ICH10_HANKSVILLE) { 1897213234Sjfv ret_val = e1000_hv_phy_tuning_workaround_ich8lan(hw); 1898213234Sjfv if (ret_val) 1899213234Sjfv goto out; 1900213234Sjfv } 1901213234Sjfv 1902200243Sjfv /* Dummy read to clear the phy wakeup bit after lcd reset */ 1903213234Sjfv if (hw->mac.type >= e1000_pchlan) 1904200243Sjfv hw->phy.ops.read_reg(hw, BM_WUC, ®); 1905169240Sjfv 1906200243Sjfv /* Configure the LCD with the extended configuration region in NVM */ 1907200243Sjfv ret_val = e1000_sw_lcd_config_ich8lan(hw); 1908200243Sjfv if (ret_val) 1909200243Sjfv goto out; 1910169240Sjfv 1911200243Sjfv /* Configure the LCD with the OEM bits in NVM */ 1912203049Sjfv ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); 1913169240Sjfv 1914213234Sjfv /* Ungate automatic PHY configuration on non-managed 82579 */ 1915213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 1916213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) { 1917213234Sjfv msec_delay(10); 1918213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, FALSE); 1919213234Sjfv } 1920213234Sjfv 1921169240Sjfvout: 1922169240Sjfv return ret_val; 1923169240Sjfv} 1924169240Sjfv 1925169240Sjfv/** 1926213234Sjfv * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 1927213234Sjfv * @hw: pointer to the HW structure 1928213234Sjfv * 1929213234Sjfv * Resets the PHY 1930213234Sjfv * This is a function pointer entry point called by drivers 1931213234Sjfv * or other shared routines. 1932213234Sjfv **/ 1933213234Sjfvstatic s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 1934213234Sjfv{ 1935213234Sjfv s32 ret_val = E1000_SUCCESS; 1936213234Sjfv 1937213234Sjfv DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 1938213234Sjfv 1939213234Sjfv /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 1940213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 1941213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 1942213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 1943213234Sjfv 1944213234Sjfv ret_val = e1000_phy_hw_reset_generic(hw); 1945213234Sjfv if (ret_val) 1946213234Sjfv goto out; 1947213234Sjfv 1948213234Sjfv ret_val = e1000_post_phy_reset_ich8lan(hw); 1949213234Sjfv 1950213234Sjfvout: 1951213234Sjfv return ret_val; 1952213234Sjfv} 1953213234Sjfv 1954213234Sjfv/** 1955200243Sjfv * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 1956169589Sjfv * @hw: pointer to the HW structure 1957200243Sjfv * @active: TRUE to enable LPLU, FALSE to disable 1958169240Sjfv * 1959200243Sjfv * Sets the LPLU state according to the active flag. For PCH, if OEM write 1960200243Sjfv * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 1961200243Sjfv * the phy speed. This function will manually set the LPLU bit and restart 1962200243Sjfv * auto-neg as hw would do. D3 and D0 LPLU will call the same function 1963200243Sjfv * since it configures the same bit. 1964169240Sjfv **/ 1965200243Sjfvstatic s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 1966169240Sjfv{ 1967200243Sjfv s32 ret_val = E1000_SUCCESS; 1968200243Sjfv u16 oem_reg; 1969169240Sjfv 1970200243Sjfv DEBUGFUNC("e1000_set_lplu_state_pchlan"); 1971169240Sjfv 1972200243Sjfv ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); 1973169240Sjfv if (ret_val) 1974169240Sjfv goto out; 1975169240Sjfv 1976200243Sjfv if (active) 1977200243Sjfv oem_reg |= HV_OEM_BITS_LPLU; 1978200243Sjfv else 1979200243Sjfv oem_reg &= ~HV_OEM_BITS_LPLU; 1980169240Sjfv 1981200243Sjfv oem_reg |= HV_OEM_BITS_RESTART_AN; 1982200243Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); 1983169240Sjfv 1984169240Sjfvout: 1985169240Sjfv return ret_val; 1986169240Sjfv} 1987169240Sjfv 1988169240Sjfv/** 1989169240Sjfv * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 1990169589Sjfv * @hw: pointer to the HW structure 1991169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 1992169240Sjfv * 1993169240Sjfv * Sets the LPLU D0 state according to the active flag. When 1994169240Sjfv * activating LPLU this function also disables smart speed 1995169240Sjfv * and vice versa. LPLU will not be activated unless the 1996169240Sjfv * device autonegotiation advertisement meets standards of 1997169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 1998169240Sjfv * This is a function pointer entry point only called by 1999169240Sjfv * PHY setup routines. 2000169240Sjfv **/ 2001185353Sjfvstatic s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2002169240Sjfv{ 2003169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2004169240Sjfv u32 phy_ctrl; 2005169240Sjfv s32 ret_val = E1000_SUCCESS; 2006169240Sjfv u16 data; 2007169240Sjfv 2008169240Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 2009169240Sjfv 2010173788Sjfv if (phy->type == e1000_phy_ife) 2011169240Sjfv goto out; 2012169240Sjfv 2013169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2014169240Sjfv 2015169240Sjfv if (active) { 2016169240Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2017169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2018169240Sjfv 2019194865Sjfv if (phy->type != e1000_phy_igp_3) 2020194865Sjfv goto out; 2021194865Sjfv 2022173788Sjfv /* 2023173788Sjfv * Call gig speed drop workaround on LPLU before accessing 2024173788Sjfv * any PHY registers 2025173788Sjfv */ 2026194865Sjfv if (hw->mac.type == e1000_ich8lan) 2027169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2028169240Sjfv 2029169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 2030177867Sjfv ret_val = phy->ops.read_reg(hw, 2031169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2032169240Sjfv &data); 2033169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2034177867Sjfv ret_val = phy->ops.write_reg(hw, 2035169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2036169240Sjfv data); 2037169240Sjfv if (ret_val) 2038169240Sjfv goto out; 2039169240Sjfv } else { 2040169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2041169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2042169240Sjfv 2043194865Sjfv if (phy->type != e1000_phy_igp_3) 2044194865Sjfv goto out; 2045194865Sjfv 2046173788Sjfv /* 2047173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 2048169240Sjfv * during Dx states where the power conservation is most 2049169240Sjfv * important. During driver activity we should enable 2050173788Sjfv * SmartSpeed, so performance is maintained. 2051173788Sjfv */ 2052169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 2053177867Sjfv ret_val = phy->ops.read_reg(hw, 2054169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2055169240Sjfv &data); 2056169240Sjfv if (ret_val) 2057169240Sjfv goto out; 2058169240Sjfv 2059169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 2060177867Sjfv ret_val = phy->ops.write_reg(hw, 2061169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2062169240Sjfv data); 2063169240Sjfv if (ret_val) 2064169240Sjfv goto out; 2065169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 2066177867Sjfv ret_val = phy->ops.read_reg(hw, 2067169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2068169240Sjfv &data); 2069169240Sjfv if (ret_val) 2070169240Sjfv goto out; 2071169240Sjfv 2072169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2073177867Sjfv ret_val = phy->ops.write_reg(hw, 2074169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2075169240Sjfv data); 2076169240Sjfv if (ret_val) 2077169240Sjfv goto out; 2078169240Sjfv } 2079169240Sjfv } 2080169240Sjfv 2081169240Sjfvout: 2082169240Sjfv return ret_val; 2083169240Sjfv} 2084169240Sjfv 2085169240Sjfv/** 2086169240Sjfv * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 2087169589Sjfv * @hw: pointer to the HW structure 2088169589Sjfv * @active: TRUE to enable LPLU, FALSE to disable 2089169240Sjfv * 2090169240Sjfv * Sets the LPLU D3 state according to the active flag. When 2091169240Sjfv * activating LPLU this function also disables smart speed 2092169240Sjfv * and vice versa. LPLU will not be activated unless the 2093169240Sjfv * device autonegotiation advertisement meets standards of 2094169240Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 2095169240Sjfv * This is a function pointer entry point only called by 2096169240Sjfv * PHY setup routines. 2097169240Sjfv **/ 2098185353Sjfvstatic s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2099169240Sjfv{ 2100169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2101169240Sjfv u32 phy_ctrl; 2102169240Sjfv s32 ret_val = E1000_SUCCESS; 2103169240Sjfv u16 data; 2104169240Sjfv 2105169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 2106169240Sjfv 2107169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2108169240Sjfv 2109169240Sjfv if (!active) { 2110169240Sjfv phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2111169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2112194865Sjfv 2113194865Sjfv if (phy->type != e1000_phy_igp_3) 2114194865Sjfv goto out; 2115194865Sjfv 2116173788Sjfv /* 2117173788Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 2118169240Sjfv * during Dx states where the power conservation is most 2119169240Sjfv * important. During driver activity we should enable 2120173788Sjfv * SmartSpeed, so performance is maintained. 2121173788Sjfv */ 2122169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 2123177867Sjfv ret_val = phy->ops.read_reg(hw, 2124169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2125169240Sjfv &data); 2126169240Sjfv if (ret_val) 2127169240Sjfv goto out; 2128169240Sjfv 2129169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 2130177867Sjfv ret_val = phy->ops.write_reg(hw, 2131169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2132169240Sjfv data); 2133169240Sjfv if (ret_val) 2134169240Sjfv goto out; 2135169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 2136177867Sjfv ret_val = phy->ops.read_reg(hw, 2137169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2138169240Sjfv &data); 2139169240Sjfv if (ret_val) 2140169240Sjfv goto out; 2141169240Sjfv 2142169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2143177867Sjfv ret_val = phy->ops.write_reg(hw, 2144169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2145169240Sjfv data); 2146169240Sjfv if (ret_val) 2147169240Sjfv goto out; 2148169240Sjfv } 2149169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2150169240Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2151169240Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2152169240Sjfv phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2153169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2154169240Sjfv 2155194865Sjfv if (phy->type != e1000_phy_igp_3) 2156194865Sjfv goto out; 2157194865Sjfv 2158173788Sjfv /* 2159173788Sjfv * Call gig speed drop workaround on LPLU before accessing 2160173788Sjfv * any PHY registers 2161173788Sjfv */ 2162194865Sjfv if (hw->mac.type == e1000_ich8lan) 2163169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 2164169240Sjfv 2165169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 2166177867Sjfv ret_val = phy->ops.read_reg(hw, 2167169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2168169240Sjfv &data); 2169169240Sjfv if (ret_val) 2170169240Sjfv goto out; 2171169240Sjfv 2172169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2173177867Sjfv ret_val = phy->ops.write_reg(hw, 2174169240Sjfv IGP01E1000_PHY_PORT_CONFIG, 2175169240Sjfv data); 2176169240Sjfv } 2177169240Sjfv 2178169240Sjfvout: 2179169240Sjfv return ret_val; 2180169240Sjfv} 2181169240Sjfv 2182169240Sjfv/** 2183173788Sjfv * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 2184173788Sjfv * @hw: pointer to the HW structure 2185173788Sjfv * @bank: pointer to the variable that returns the active bank 2186173788Sjfv * 2187173788Sjfv * Reads signature byte from the NVM using the flash access registers. 2188190872Sjfv * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 2189173788Sjfv **/ 2190177867Sjfvstatic s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 2191173788Sjfv{ 2192190872Sjfv u32 eecd; 2193178523Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2194178523Sjfv u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 2195178523Sjfv u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 2196190872Sjfv u8 sig_byte = 0; 2197190872Sjfv s32 ret_val = E1000_SUCCESS; 2198178523Sjfv 2199213234Sjfv DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan"); 2200213234Sjfv 2201190872Sjfv switch (hw->mac.type) { 2202190872Sjfv case e1000_ich8lan: 2203190872Sjfv case e1000_ich9lan: 2204190872Sjfv eecd = E1000_READ_REG(hw, E1000_EECD); 2205190872Sjfv if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 2206190872Sjfv E1000_EECD_SEC1VAL_VALID_MASK) { 2207190872Sjfv if (eecd & E1000_EECD_SEC1VAL) 2208190872Sjfv *bank = 1; 2209190872Sjfv else 2210190872Sjfv *bank = 0; 2211190872Sjfv 2212190872Sjfv goto out; 2213190872Sjfv } 2214190872Sjfv DEBUGOUT("Unable to determine valid NVM bank via EEC - " 2215190872Sjfv "reading flash signature\n"); 2216190872Sjfv /* fall-thru */ 2217190872Sjfv default: 2218190872Sjfv /* set bank to 0 in case flash read fails */ 2219190872Sjfv *bank = 0; 2220190872Sjfv 2221190872Sjfv /* Check bank 0 */ 2222190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 2223190872Sjfv &sig_byte); 2224190872Sjfv if (ret_val) 2225190872Sjfv goto out; 2226190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2227200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 2228178523Sjfv *bank = 0; 2229190872Sjfv goto out; 2230190872Sjfv } 2231185353Sjfv 2232190872Sjfv /* Check bank 1 */ 2233190872Sjfv ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 2234190872Sjfv bank1_offset, 2235200243Sjfv &sig_byte); 2236190872Sjfv if (ret_val) 2237190872Sjfv goto out; 2238190872Sjfv if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2239200243Sjfv E1000_ICH_NVM_SIG_VALUE) { 2240190872Sjfv *bank = 1; 2241190872Sjfv goto out; 2242178523Sjfv } 2243190872Sjfv 2244190872Sjfv DEBUGOUT("ERROR: No valid NVM bank present\n"); 2245190872Sjfv ret_val = -E1000_ERR_NVM; 2246190872Sjfv break; 2247178523Sjfv } 2248190872Sjfvout: 2249173788Sjfv return ret_val; 2250173788Sjfv} 2251173788Sjfv 2252173788Sjfv/** 2253169240Sjfv * e1000_read_nvm_ich8lan - Read word(s) from the NVM 2254169589Sjfv * @hw: pointer to the HW structure 2255169589Sjfv * @offset: The offset (in bytes) of the word(s) to read. 2256169589Sjfv * @words: Size of data to read in words 2257169589Sjfv * @data: Pointer to the word(s) to read at offset. 2258169240Sjfv * 2259169240Sjfv * Reads a word(s) from the NVM using the flash access registers. 2260169240Sjfv **/ 2261177867Sjfvstatic s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2262173788Sjfv u16 *data) 2263169240Sjfv{ 2264169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2265185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2266169240Sjfv u32 act_offset; 2267169240Sjfv s32 ret_val = E1000_SUCCESS; 2268173788Sjfv u32 bank = 0; 2269169240Sjfv u16 i, word; 2270169240Sjfv 2271169240Sjfv DEBUGFUNC("e1000_read_nvm_ich8lan"); 2272169240Sjfv 2273169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2274169240Sjfv (words == 0)) { 2275169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 2276169240Sjfv ret_val = -E1000_ERR_NVM; 2277169240Sjfv goto out; 2278169240Sjfv } 2279169240Sjfv 2280200243Sjfv nvm->ops.acquire(hw); 2281169240Sjfv 2282173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2283200243Sjfv if (ret_val != E1000_SUCCESS) { 2284200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 2285200243Sjfv bank = 0; 2286200243Sjfv } 2287173788Sjfv 2288173788Sjfv act_offset = (bank) ? nvm->flash_bank_size : 0; 2289169240Sjfv act_offset += offset; 2290169240Sjfv 2291200243Sjfv ret_val = E1000_SUCCESS; 2292169240Sjfv for (i = 0; i < words; i++) { 2293173788Sjfv if ((dev_spec->shadow_ram) && 2294173788Sjfv (dev_spec->shadow_ram[offset+i].modified)) { 2295169240Sjfv data[i] = dev_spec->shadow_ram[offset+i].value; 2296169240Sjfv } else { 2297169240Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, 2298169240Sjfv act_offset + i, 2299169240Sjfv &word); 2300169240Sjfv if (ret_val) 2301169240Sjfv break; 2302169240Sjfv data[i] = word; 2303169240Sjfv } 2304169240Sjfv } 2305169240Sjfv 2306177867Sjfv nvm->ops.release(hw); 2307169240Sjfv 2308169240Sjfvout: 2309190872Sjfv if (ret_val) 2310190872Sjfv DEBUGOUT1("NVM read error: %d\n", ret_val); 2311190872Sjfv 2312169240Sjfv return ret_val; 2313169240Sjfv} 2314169240Sjfv 2315169240Sjfv/** 2316169240Sjfv * e1000_flash_cycle_init_ich8lan - Initialize flash 2317169589Sjfv * @hw: pointer to the HW structure 2318169240Sjfv * 2319169240Sjfv * This function does initial flash setup so that a new read/write/erase cycle 2320169240Sjfv * can be started. 2321169240Sjfv **/ 2322173788Sjfvstatic s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 2323169240Sjfv{ 2324169240Sjfv union ich8_hws_flash_status hsfsts; 2325169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2326169240Sjfv s32 i = 0; 2327169240Sjfv 2328169240Sjfv DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 2329169240Sjfv 2330169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2331169240Sjfv 2332169240Sjfv /* Check if the flash descriptor is valid */ 2333169240Sjfv if (hsfsts.hsf_status.fldesvalid == 0) { 2334169240Sjfv DEBUGOUT("Flash descriptor invalid. " 2335169240Sjfv "SW Sequencing must be used."); 2336169240Sjfv goto out; 2337169240Sjfv } 2338169240Sjfv 2339169240Sjfv /* Clear FCERR and DAEL in hw status by writing 1 */ 2340169240Sjfv hsfsts.hsf_status.flcerr = 1; 2341169240Sjfv hsfsts.hsf_status.dael = 1; 2342169240Sjfv 2343169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 2344169240Sjfv 2345173788Sjfv /* 2346173788Sjfv * Either we should have a hardware SPI cycle in progress 2347169240Sjfv * bit to check against, in order to start a new cycle or 2348169240Sjfv * FDONE bit should be changed in the hardware so that it 2349176667Sjfv * is 1 after hardware reset, which can then be used as an 2350169240Sjfv * indication whether a cycle is in progress or has been 2351169240Sjfv * completed. 2352169240Sjfv */ 2353169240Sjfv 2354169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 2355173788Sjfv /* 2356173788Sjfv * There is no cycle running at present, 2357173788Sjfv * so we can start a cycle. 2358173788Sjfv * Begin by setting Flash Cycle Done. 2359173788Sjfv */ 2360169240Sjfv hsfsts.hsf_status.flcdone = 1; 2361169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 2362169240Sjfv ret_val = E1000_SUCCESS; 2363169240Sjfv } else { 2364173788Sjfv /* 2365173788Sjfv * Otherwise poll for sometime so the current 2366173788Sjfv * cycle has a chance to end before giving up. 2367173788Sjfv */ 2368169240Sjfv for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 2369169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2370169240Sjfv ICH_FLASH_HSFSTS); 2371169240Sjfv if (hsfsts.hsf_status.flcinprog == 0) { 2372169240Sjfv ret_val = E1000_SUCCESS; 2373169240Sjfv break; 2374169240Sjfv } 2375169240Sjfv usec_delay(1); 2376169240Sjfv } 2377169240Sjfv if (ret_val == E1000_SUCCESS) { 2378173788Sjfv /* 2379173788Sjfv * Successful in waiting for previous cycle to timeout, 2380173788Sjfv * now set the Flash Cycle Done. 2381173788Sjfv */ 2382169240Sjfv hsfsts.hsf_status.flcdone = 1; 2383185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 2384169240Sjfv hsfsts.regval); 2385169240Sjfv } else { 2386169240Sjfv DEBUGOUT("Flash controller busy, cannot get access"); 2387169240Sjfv } 2388169240Sjfv } 2389169240Sjfv 2390169240Sjfvout: 2391169240Sjfv return ret_val; 2392169240Sjfv} 2393169240Sjfv 2394169240Sjfv/** 2395169240Sjfv * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 2396169589Sjfv * @hw: pointer to the HW structure 2397169589Sjfv * @timeout: maximum time to wait for completion 2398169240Sjfv * 2399169240Sjfv * This function starts a flash cycle and waits for its completion. 2400169240Sjfv **/ 2401173788Sjfvstatic s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 2402169240Sjfv{ 2403169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2404169240Sjfv union ich8_hws_flash_status hsfsts; 2405169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2406169240Sjfv u32 i = 0; 2407169240Sjfv 2408169240Sjfv DEBUGFUNC("e1000_flash_cycle_ich8lan"); 2409169240Sjfv 2410169240Sjfv /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 2411169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 2412169240Sjfv hsflctl.hsf_ctrl.flcgo = 1; 2413169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 2414169240Sjfv 2415169240Sjfv /* wait till FDONE bit is set to 1 */ 2416169240Sjfv do { 2417169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2418169240Sjfv if (hsfsts.hsf_status.flcdone == 1) 2419169240Sjfv break; 2420169240Sjfv usec_delay(1); 2421169240Sjfv } while (i++ < timeout); 2422169240Sjfv 2423169240Sjfv if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 2424169240Sjfv ret_val = E1000_SUCCESS; 2425169240Sjfv 2426169240Sjfv return ret_val; 2427169240Sjfv} 2428169240Sjfv 2429169240Sjfv/** 2430169240Sjfv * e1000_read_flash_word_ich8lan - Read word from flash 2431169589Sjfv * @hw: pointer to the HW structure 2432169589Sjfv * @offset: offset to data location 2433169589Sjfv * @data: pointer to the location for storing the data 2434169240Sjfv * 2435169240Sjfv * Reads the flash word at offset into data. Offset is converted 2436169240Sjfv * to bytes before read. 2437169240Sjfv **/ 2438177867Sjfvstatic s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 2439173788Sjfv u16 *data) 2440169240Sjfv{ 2441169240Sjfv s32 ret_val; 2442169240Sjfv 2443169240Sjfv DEBUGFUNC("e1000_read_flash_word_ich8lan"); 2444169240Sjfv 2445173788Sjfv if (!data) { 2446169240Sjfv ret_val = -E1000_ERR_NVM; 2447169240Sjfv goto out; 2448169240Sjfv } 2449169240Sjfv 2450169240Sjfv /* Must convert offset into bytes. */ 2451169240Sjfv offset <<= 1; 2452169240Sjfv 2453169240Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 2454169240Sjfv 2455169240Sjfvout: 2456169240Sjfv return ret_val; 2457169240Sjfv} 2458169240Sjfv 2459169240Sjfv/** 2460178523Sjfv * e1000_read_flash_byte_ich8lan - Read byte from flash 2461178523Sjfv * @hw: pointer to the HW structure 2462178523Sjfv * @offset: The offset of the byte to read. 2463178523Sjfv * @data: Pointer to a byte to store the value read. 2464178523Sjfv * 2465178523Sjfv * Reads a single byte from the NVM using the flash access registers. 2466178523Sjfv **/ 2467178523Sjfvstatic s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2468185353Sjfv u8 *data) 2469178523Sjfv{ 2470178523Sjfv s32 ret_val = E1000_SUCCESS; 2471178523Sjfv u16 word = 0; 2472178523Sjfv 2473178523Sjfv ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 2474178523Sjfv if (ret_val) 2475178523Sjfv goto out; 2476178523Sjfv 2477178523Sjfv *data = (u8)word; 2478178523Sjfv 2479178523Sjfvout: 2480178523Sjfv return ret_val; 2481178523Sjfv} 2482178523Sjfv 2483178523Sjfv/** 2484169240Sjfv * e1000_read_flash_data_ich8lan - Read byte or word from NVM 2485169589Sjfv * @hw: pointer to the HW structure 2486169589Sjfv * @offset: The offset (in bytes) of the byte or word to read. 2487169589Sjfv * @size: Size of data to read, 1=byte 2=word 2488169589Sjfv * @data: Pointer to the word to store the value read. 2489169240Sjfv * 2490169240Sjfv * Reads a byte or word from the NVM using the flash access registers. 2491169240Sjfv **/ 2492173788Sjfvstatic s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2493185353Sjfv u8 size, u16 *data) 2494169240Sjfv{ 2495169240Sjfv union ich8_hws_flash_status hsfsts; 2496169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2497169240Sjfv u32 flash_linear_addr; 2498169240Sjfv u32 flash_data = 0; 2499169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2500169240Sjfv u8 count = 0; 2501169240Sjfv 2502169240Sjfv DEBUGFUNC("e1000_read_flash_data_ich8lan"); 2503169240Sjfv 2504173788Sjfv if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 2505169240Sjfv goto out; 2506169240Sjfv 2507169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2508169240Sjfv hw->nvm.flash_base_addr; 2509169240Sjfv 2510169240Sjfv do { 2511169240Sjfv usec_delay(1); 2512169240Sjfv /* Steps */ 2513169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 2514169240Sjfv if (ret_val != E1000_SUCCESS) 2515169240Sjfv break; 2516169240Sjfv 2517169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 2518169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2519169240Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 2520169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 2521169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 2522169240Sjfv 2523169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 2524169240Sjfv 2525169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 2526169240Sjfv ICH_FLASH_READ_COMMAND_TIMEOUT); 2527169240Sjfv 2528173788Sjfv /* 2529173788Sjfv * Check if FCERR is set to 1, if set to 1, clear it 2530169240Sjfv * and try the whole sequence a few more times, else 2531169240Sjfv * read in (shift in) the Flash Data0, the order is 2532173788Sjfv * least significant byte first msb to lsb 2533173788Sjfv */ 2534169240Sjfv if (ret_val == E1000_SUCCESS) { 2535169240Sjfv flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 2536185353Sjfv if (size == 1) 2537169240Sjfv *data = (u8)(flash_data & 0x000000FF); 2538185353Sjfv else if (size == 2) 2539169240Sjfv *data = (u16)(flash_data & 0x0000FFFF); 2540169240Sjfv break; 2541169240Sjfv } else { 2542173788Sjfv /* 2543173788Sjfv * If we've gotten here, then things are probably 2544169240Sjfv * completely hosed, but if the error condition is 2545169240Sjfv * detected, it won't hurt to give it another try... 2546169240Sjfv * ICH_FLASH_CYCLE_REPEAT_COUNT times. 2547169240Sjfv */ 2548169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2549169240Sjfv ICH_FLASH_HSFSTS); 2550169240Sjfv if (hsfsts.hsf_status.flcerr == 1) { 2551169240Sjfv /* Repeat for some time before giving up. */ 2552169240Sjfv continue; 2553169240Sjfv } else if (hsfsts.hsf_status.flcdone == 0) { 2554169240Sjfv DEBUGOUT("Timeout error - flash cycle " 2555169240Sjfv "did not complete."); 2556169240Sjfv break; 2557169240Sjfv } 2558169240Sjfv } 2559169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2560169240Sjfv 2561169240Sjfvout: 2562169240Sjfv return ret_val; 2563169240Sjfv} 2564169240Sjfv 2565169240Sjfv/** 2566169240Sjfv * e1000_write_nvm_ich8lan - Write word(s) to the NVM 2567169589Sjfv * @hw: pointer to the HW structure 2568169589Sjfv * @offset: The offset (in bytes) of the word(s) to write. 2569169589Sjfv * @words: Size of data to write in words 2570169589Sjfv * @data: Pointer to the word(s) to write at offset. 2571169240Sjfv * 2572169240Sjfv * Writes a byte or word to the NVM using the flash access registers. 2573169240Sjfv **/ 2574177867Sjfvstatic s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2575173788Sjfv u16 *data) 2576169240Sjfv{ 2577169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2578185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2579169240Sjfv s32 ret_val = E1000_SUCCESS; 2580169240Sjfv u16 i; 2581169240Sjfv 2582169240Sjfv DEBUGFUNC("e1000_write_nvm_ich8lan"); 2583169240Sjfv 2584169240Sjfv if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2585169240Sjfv (words == 0)) { 2586169240Sjfv DEBUGOUT("nvm parameter(s) out of bounds\n"); 2587169240Sjfv ret_val = -E1000_ERR_NVM; 2588169240Sjfv goto out; 2589169240Sjfv } 2590169240Sjfv 2591200243Sjfv nvm->ops.acquire(hw); 2592169240Sjfv 2593169240Sjfv for (i = 0; i < words; i++) { 2594169240Sjfv dev_spec->shadow_ram[offset+i].modified = TRUE; 2595169240Sjfv dev_spec->shadow_ram[offset+i].value = data[i]; 2596169240Sjfv } 2597169240Sjfv 2598177867Sjfv nvm->ops.release(hw); 2599169240Sjfv 2600169240Sjfvout: 2601169240Sjfv return ret_val; 2602169240Sjfv} 2603169240Sjfv 2604169240Sjfv/** 2605169240Sjfv * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 2606169589Sjfv * @hw: pointer to the HW structure 2607169240Sjfv * 2608169240Sjfv * The NVM checksum is updated by calling the generic update_nvm_checksum, 2609169240Sjfv * which writes the checksum to the shadow ram. The changes in the shadow 2610169240Sjfv * ram are then committed to the EEPROM by processing each bank at a time 2611169240Sjfv * checking for the modified bit and writing only the pending changes. 2612176667Sjfv * After a successful commit, the shadow ram is cleared and is ready for 2613169240Sjfv * future writes. 2614169240Sjfv **/ 2615177867Sjfvstatic s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 2616169240Sjfv{ 2617169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2618185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2619173788Sjfv u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 2620169240Sjfv s32 ret_val; 2621169240Sjfv u16 data; 2622169240Sjfv 2623169240Sjfv DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 2624169240Sjfv 2625169240Sjfv ret_val = e1000_update_nvm_checksum_generic(hw); 2626169240Sjfv if (ret_val) 2627169240Sjfv goto out; 2628169240Sjfv 2629169240Sjfv if (nvm->type != e1000_nvm_flash_sw) 2630169240Sjfv goto out; 2631169240Sjfv 2632200243Sjfv nvm->ops.acquire(hw); 2633169240Sjfv 2634173788Sjfv /* 2635173788Sjfv * We're writing to the opposite bank so if we're on bank 1, 2636169240Sjfv * write to bank 0 etc. We also need to erase the segment that 2637173788Sjfv * is going to be written 2638173788Sjfv */ 2639173788Sjfv ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2640190872Sjfv if (ret_val != E1000_SUCCESS) { 2641200243Sjfv DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 2642200243Sjfv bank = 0; 2643190872Sjfv } 2644173788Sjfv 2645173788Sjfv if (bank == 0) { 2646169240Sjfv new_bank_offset = nvm->flash_bank_size; 2647169240Sjfv old_bank_offset = 0; 2648190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 2649203049Sjfv if (ret_val) 2650203049Sjfv goto release; 2651169240Sjfv } else { 2652169240Sjfv old_bank_offset = nvm->flash_bank_size; 2653169240Sjfv new_bank_offset = 0; 2654190872Sjfv ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 2655203049Sjfv if (ret_val) 2656203049Sjfv goto release; 2657169240Sjfv } 2658169240Sjfv 2659169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 2660173788Sjfv /* 2661173788Sjfv * Determine whether to write the value stored 2662169240Sjfv * in the other NVM bank or a modified value stored 2663173788Sjfv * in the shadow RAM 2664173788Sjfv */ 2665173788Sjfv if (dev_spec->shadow_ram[i].modified) { 2666169240Sjfv data = dev_spec->shadow_ram[i].value; 2667169240Sjfv } else { 2668190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, i + 2669190872Sjfv old_bank_offset, 2670190872Sjfv &data); 2671190872Sjfv if (ret_val) 2672190872Sjfv break; 2673169240Sjfv } 2674169240Sjfv 2675173788Sjfv /* 2676173788Sjfv * If the word is 0x13, then make sure the signature bits 2677169240Sjfv * (15:14) are 11b until the commit has completed. 2678169240Sjfv * This will allow us to write 10b which indicates the 2679169240Sjfv * signature is valid. We want to do this after the write 2680169240Sjfv * has completed so that we don't mark the segment valid 2681173788Sjfv * while the write is still in progress 2682173788Sjfv */ 2683169240Sjfv if (i == E1000_ICH_NVM_SIG_WORD) 2684169240Sjfv data |= E1000_ICH_NVM_SIG_MASK; 2685169240Sjfv 2686169240Sjfv /* Convert offset to bytes. */ 2687169240Sjfv act_offset = (i + new_bank_offset) << 1; 2688169240Sjfv 2689169240Sjfv usec_delay(100); 2690169240Sjfv /* Write the bytes to the new bank. */ 2691169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2692169240Sjfv act_offset, 2693169240Sjfv (u8)data); 2694169240Sjfv if (ret_val) 2695169240Sjfv break; 2696169240Sjfv 2697169240Sjfv usec_delay(100); 2698169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2699169240Sjfv act_offset + 1, 2700169240Sjfv (u8)(data >> 8)); 2701169240Sjfv if (ret_val) 2702169240Sjfv break; 2703169240Sjfv } 2704169240Sjfv 2705173788Sjfv /* 2706173788Sjfv * Don't bother writing the segment valid bits if sector 2707173788Sjfv * programming failed. 2708173788Sjfv */ 2709169240Sjfv if (ret_val) { 2710169240Sjfv DEBUGOUT("Flash commit failed.\n"); 2711203049Sjfv goto release; 2712169240Sjfv } 2713169240Sjfv 2714173788Sjfv /* 2715173788Sjfv * Finally validate the new segment by setting bit 15:14 2716169240Sjfv * to 10b in word 0x13 , this can be done without an 2717169240Sjfv * erase as well since these bits are 11 to start with 2718173788Sjfv * and we need to change bit 14 to 0b 2719173788Sjfv */ 2720169240Sjfv act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 2721190872Sjfv ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 2722203049Sjfv if (ret_val) 2723203049Sjfv goto release; 2724200243Sjfv 2725169240Sjfv data &= 0xBFFF; 2726169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2727169240Sjfv act_offset * 2 + 1, 2728169240Sjfv (u8)(data >> 8)); 2729203049Sjfv if (ret_val) 2730203049Sjfv goto release; 2731169240Sjfv 2732173788Sjfv /* 2733173788Sjfv * And invalidate the previously valid segment by setting 2734169240Sjfv * its signature word (0x13) high_byte to 0b. This can be 2735169240Sjfv * done without an erase because flash erase sets all bits 2736173788Sjfv * to 1's. We can write 1's to 0's without an erase 2737173788Sjfv */ 2738169240Sjfv act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 2739169240Sjfv ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 2740203049Sjfv if (ret_val) 2741203049Sjfv goto release; 2742169240Sjfv 2743169240Sjfv /* Great! Everything worked, we can now clear the cached entries. */ 2744169240Sjfv for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 2745169240Sjfv dev_spec->shadow_ram[i].modified = FALSE; 2746169240Sjfv dev_spec->shadow_ram[i].value = 0xFFFF; 2747169240Sjfv } 2748169240Sjfv 2749203049Sjfvrelease: 2750177867Sjfv nvm->ops.release(hw); 2751169240Sjfv 2752173788Sjfv /* 2753173788Sjfv * Reload the EEPROM, or else modifications will not appear 2754169240Sjfv * until after the next adapter reset. 2755169240Sjfv */ 2756203049Sjfv if (!ret_val) { 2757203049Sjfv nvm->ops.reload(hw); 2758203049Sjfv msec_delay(10); 2759203049Sjfv } 2760169240Sjfv 2761169240Sjfvout: 2762190872Sjfv if (ret_val) 2763190872Sjfv DEBUGOUT1("NVM update error: %d\n", ret_val); 2764190872Sjfv 2765169240Sjfv return ret_val; 2766169240Sjfv} 2767169240Sjfv 2768169240Sjfv/** 2769169240Sjfv * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 2770169589Sjfv * @hw: pointer to the HW structure 2771169240Sjfv * 2772169240Sjfv * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 2773185353Sjfv * If the bit is 0, that the EEPROM had been modified, but the checksum was not 2774185353Sjfv * calculated, in which case we need to calculate the checksum and set bit 6. 2775169240Sjfv **/ 2776177867Sjfvstatic s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 2777169240Sjfv{ 2778169240Sjfv s32 ret_val = E1000_SUCCESS; 2779169240Sjfv u16 data; 2780169240Sjfv 2781169240Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 2782169240Sjfv 2783173788Sjfv /* 2784173788Sjfv * Read 0x19 and check bit 6. If this bit is 0, the checksum 2785169240Sjfv * needs to be fixed. This bit is an indication that the NVM 2786169240Sjfv * was prepared by OEM software and did not calculate the 2787169240Sjfv * checksum...a likely scenario. 2788169240Sjfv */ 2789177867Sjfv ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 2790169240Sjfv if (ret_val) 2791169240Sjfv goto out; 2792169240Sjfv 2793169240Sjfv if ((data & 0x40) == 0) { 2794169240Sjfv data |= 0x40; 2795177867Sjfv ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 2796169240Sjfv if (ret_val) 2797169240Sjfv goto out; 2798177867Sjfv ret_val = hw->nvm.ops.update(hw); 2799169240Sjfv if (ret_val) 2800169240Sjfv goto out; 2801169240Sjfv } 2802169240Sjfv 2803169240Sjfv ret_val = e1000_validate_nvm_checksum_generic(hw); 2804169240Sjfv 2805169240Sjfvout: 2806169240Sjfv return ret_val; 2807169240Sjfv} 2808169240Sjfv 2809169240Sjfv/** 2810169240Sjfv * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 2811169589Sjfv * @hw: pointer to the HW structure 2812169589Sjfv * @offset: The offset (in bytes) of the byte/word to read. 2813169589Sjfv * @size: Size of data to read, 1=byte 2=word 2814169589Sjfv * @data: The byte(s) to write to the NVM. 2815169240Sjfv * 2816169240Sjfv * Writes one/two bytes to the NVM using the flash access registers. 2817169240Sjfv **/ 2818173788Sjfvstatic s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2819173788Sjfv u8 size, u16 data) 2820169240Sjfv{ 2821169240Sjfv union ich8_hws_flash_status hsfsts; 2822169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2823169240Sjfv u32 flash_linear_addr; 2824169240Sjfv u32 flash_data = 0; 2825169240Sjfv s32 ret_val = -E1000_ERR_NVM; 2826169240Sjfv u8 count = 0; 2827169240Sjfv 2828169240Sjfv DEBUGFUNC("e1000_write_ich8_data"); 2829169240Sjfv 2830169240Sjfv if (size < 1 || size > 2 || data > size * 0xff || 2831169240Sjfv offset > ICH_FLASH_LINEAR_ADDR_MASK) 2832169240Sjfv goto out; 2833169240Sjfv 2834169240Sjfv flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2835169240Sjfv hw->nvm.flash_base_addr; 2836169240Sjfv 2837169240Sjfv do { 2838169240Sjfv usec_delay(1); 2839169240Sjfv /* Steps */ 2840169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 2841169240Sjfv if (ret_val != E1000_SUCCESS) 2842169240Sjfv break; 2843169240Sjfv 2844169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 2845169240Sjfv /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2846185353Sjfv hsflctl.hsf_ctrl.fldbcount = size - 1; 2847169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 2848169240Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 2849169240Sjfv 2850169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 2851169240Sjfv 2852169240Sjfv if (size == 1) 2853169240Sjfv flash_data = (u32)data & 0x00FF; 2854169240Sjfv else 2855169240Sjfv flash_data = (u32)data; 2856169240Sjfv 2857169240Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 2858169240Sjfv 2859173788Sjfv /* 2860173788Sjfv * check if FCERR is set to 1 , if set to 1, clear it 2861173788Sjfv * and try the whole sequence a few more times else done 2862173788Sjfv */ 2863169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 2864169240Sjfv ICH_FLASH_WRITE_COMMAND_TIMEOUT); 2865185353Sjfv if (ret_val == E1000_SUCCESS) 2866169240Sjfv break; 2867185353Sjfv 2868185353Sjfv /* 2869185353Sjfv * If we're here, then things are most likely 2870185353Sjfv * completely hosed, but if the error condition 2871185353Sjfv * is detected, it won't hurt to give it another 2872185353Sjfv * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 2873185353Sjfv */ 2874185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2875200243Sjfv if (hsfsts.hsf_status.flcerr == 1) 2876185353Sjfv /* Repeat for some time before giving up. */ 2877185353Sjfv continue; 2878200243Sjfv if (hsfsts.hsf_status.flcdone == 0) { 2879185353Sjfv DEBUGOUT("Timeout error - flash cycle " 2880185353Sjfv "did not complete."); 2881185353Sjfv break; 2882169240Sjfv } 2883169240Sjfv } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2884169240Sjfv 2885169240Sjfvout: 2886169240Sjfv return ret_val; 2887169240Sjfv} 2888169240Sjfv 2889169240Sjfv/** 2890169240Sjfv * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 2891169589Sjfv * @hw: pointer to the HW structure 2892169589Sjfv * @offset: The index of the byte to read. 2893169589Sjfv * @data: The byte to write to the NVM. 2894169240Sjfv * 2895169240Sjfv * Writes a single byte to the NVM using the flash access registers. 2896169240Sjfv **/ 2897177867Sjfvstatic s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2898173788Sjfv u8 data) 2899169240Sjfv{ 2900169240Sjfv u16 word = (u16)data; 2901169240Sjfv 2902169240Sjfv DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 2903169240Sjfv 2904169240Sjfv return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 2905169240Sjfv} 2906169240Sjfv 2907169240Sjfv/** 2908169240Sjfv * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 2909169589Sjfv * @hw: pointer to the HW structure 2910169589Sjfv * @offset: The offset of the byte to write. 2911169589Sjfv * @byte: The byte to write to the NVM. 2912169240Sjfv * 2913169240Sjfv * Writes a single byte to the NVM using the flash access registers. 2914169240Sjfv * Goes through a retry algorithm before giving up. 2915169240Sjfv **/ 2916176667Sjfvstatic s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 2917176667Sjfv u32 offset, u8 byte) 2918169240Sjfv{ 2919169240Sjfv s32 ret_val; 2920169240Sjfv u16 program_retries; 2921169240Sjfv 2922169240Sjfv DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 2923169240Sjfv 2924169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2925173788Sjfv if (ret_val == E1000_SUCCESS) 2926169240Sjfv goto out; 2927169240Sjfv 2928169240Sjfv for (program_retries = 0; program_retries < 100; program_retries++) { 2929169240Sjfv DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 2930169240Sjfv usec_delay(100); 2931169240Sjfv ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 2932169240Sjfv if (ret_val == E1000_SUCCESS) 2933169240Sjfv break; 2934169240Sjfv } 2935169240Sjfv if (program_retries == 100) { 2936169240Sjfv ret_val = -E1000_ERR_NVM; 2937169240Sjfv goto out; 2938169240Sjfv } 2939169240Sjfv 2940169240Sjfvout: 2941169240Sjfv return ret_val; 2942169240Sjfv} 2943169240Sjfv 2944169240Sjfv/** 2945169240Sjfv * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 2946169589Sjfv * @hw: pointer to the HW structure 2947169589Sjfv * @bank: 0 for first bank, 1 for second bank, etc. 2948169240Sjfv * 2949169240Sjfv * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 2950169240Sjfv * bank N is 4096 * N + flash_reg_addr. 2951169240Sjfv **/ 2952177867Sjfvstatic s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 2953169240Sjfv{ 2954169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 2955169240Sjfv union ich8_hws_flash_status hsfsts; 2956169240Sjfv union ich8_hws_flash_ctrl hsflctl; 2957169240Sjfv u32 flash_linear_addr; 2958173788Sjfv /* bank size is in 16bit words - adjust to bytes */ 2959173788Sjfv u32 flash_bank_size = nvm->flash_bank_size * 2; 2960185353Sjfv s32 ret_val = E1000_SUCCESS; 2961185353Sjfv s32 count = 0; 2962185353Sjfv s32 j, iteration, sector_size; 2963169240Sjfv 2964169240Sjfv DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 2965169240Sjfv 2966169240Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 2967169240Sjfv 2968173788Sjfv /* 2969173788Sjfv * Determine HW Sector size: Read BERASE bits of hw flash status 2970173788Sjfv * register 2971173788Sjfv * 00: The Hw sector is 256 bytes, hence we need to erase 16 2972169240Sjfv * consecutive sectors. The start index for the nth Hw sector 2973169240Sjfv * can be calculated as = bank * 4096 + n * 256 2974169240Sjfv * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 2975169240Sjfv * The start index for the nth Hw sector can be calculated 2976169240Sjfv * as = bank * 4096 2977169240Sjfv * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 2978169240Sjfv * (ich9 only, otherwise error condition) 2979169240Sjfv * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 2980169240Sjfv */ 2981169240Sjfv switch (hsfsts.hsf_status.berasesz) { 2982169240Sjfv case 0: 2983169240Sjfv /* Hw sector size 256 */ 2984169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_256; 2985169240Sjfv iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 2986169240Sjfv break; 2987169240Sjfv case 1: 2988169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_4K; 2989194865Sjfv iteration = 1; 2990169240Sjfv break; 2991169240Sjfv case 2: 2992195850Sjfv sector_size = ICH_FLASH_SEG_SIZE_8K; 2993195850Sjfv iteration = 1; 2994169240Sjfv break; 2995169240Sjfv case 3: 2996169240Sjfv sector_size = ICH_FLASH_SEG_SIZE_64K; 2997194865Sjfv iteration = 1; 2998169240Sjfv break; 2999169240Sjfv default: 3000169240Sjfv ret_val = -E1000_ERR_NVM; 3001169240Sjfv goto out; 3002169240Sjfv } 3003169240Sjfv 3004169240Sjfv /* Start with the base address, then add the sector offset. */ 3005169240Sjfv flash_linear_addr = hw->nvm.flash_base_addr; 3006200243Sjfv flash_linear_addr += (bank) ? flash_bank_size : 0; 3007169240Sjfv 3008169240Sjfv for (j = 0; j < iteration ; j++) { 3009169240Sjfv do { 3010169240Sjfv /* Steps */ 3011169240Sjfv ret_val = e1000_flash_cycle_init_ich8lan(hw); 3012169240Sjfv if (ret_val) 3013169240Sjfv goto out; 3014169240Sjfv 3015173788Sjfv /* 3016173788Sjfv * Write a value 11 (block Erase) in Flash 3017173788Sjfv * Cycle field in hw flash control 3018173788Sjfv */ 3019169240Sjfv hsflctl.regval = E1000_READ_FLASH_REG16(hw, 3020169240Sjfv ICH_FLASH_HSFCTL); 3021169240Sjfv hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 3022185353Sjfv E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 3023169240Sjfv hsflctl.regval); 3024169240Sjfv 3025173788Sjfv /* 3026173788Sjfv * Write the last 24 bits of an index within the 3027169240Sjfv * block into Flash Linear address field in Flash 3028169240Sjfv * Address. 3029169240Sjfv */ 3030169240Sjfv flash_linear_addr += (j * sector_size); 3031185353Sjfv E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 3032169240Sjfv flash_linear_addr); 3033169240Sjfv 3034169240Sjfv ret_val = e1000_flash_cycle_ich8lan(hw, 3035169240Sjfv ICH_FLASH_ERASE_COMMAND_TIMEOUT); 3036185353Sjfv if (ret_val == E1000_SUCCESS) 3037169240Sjfv break; 3038185353Sjfv 3039185353Sjfv /* 3040185353Sjfv * Check if FCERR is set to 1. If 1, 3041185353Sjfv * clear it and try the whole sequence 3042185353Sjfv * a few more times else Done 3043185353Sjfv */ 3044185353Sjfv hsfsts.regval = E1000_READ_FLASH_REG16(hw, 3045185353Sjfv ICH_FLASH_HSFSTS); 3046185353Sjfv if (hsfsts.hsf_status.flcerr == 1) 3047185353Sjfv /* repeat for some time before giving up */ 3048185353Sjfv continue; 3049185353Sjfv else if (hsfsts.hsf_status.flcdone == 0) 3050185353Sjfv goto out; 3051169240Sjfv } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 3052169240Sjfv } 3053169240Sjfv 3054169240Sjfvout: 3055169240Sjfv return ret_val; 3056169240Sjfv} 3057169240Sjfv 3058169240Sjfv/** 3059169240Sjfv * e1000_valid_led_default_ich8lan - Set the default LED settings 3060169589Sjfv * @hw: pointer to the HW structure 3061169589Sjfv * @data: Pointer to the LED settings 3062169240Sjfv * 3063169240Sjfv * Reads the LED default settings from the NVM to data. If the NVM LED 3064169240Sjfv * settings is all 0's or F's, set the LED default to a valid LED default 3065169240Sjfv * setting. 3066169240Sjfv **/ 3067177867Sjfvstatic s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 3068169240Sjfv{ 3069169240Sjfv s32 ret_val; 3070169240Sjfv 3071169240Sjfv DEBUGFUNC("e1000_valid_led_default_ich8lan"); 3072169240Sjfv 3073177867Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 3074169240Sjfv if (ret_val) { 3075169240Sjfv DEBUGOUT("NVM Read Error\n"); 3076169240Sjfv goto out; 3077169240Sjfv } 3078169240Sjfv 3079169240Sjfv if (*data == ID_LED_RESERVED_0000 || 3080169240Sjfv *data == ID_LED_RESERVED_FFFF) 3081169240Sjfv *data = ID_LED_DEFAULT_ICH8LAN; 3082169240Sjfv 3083169240Sjfvout: 3084169240Sjfv return ret_val; 3085169240Sjfv} 3086169240Sjfv 3087169240Sjfv/** 3088194865Sjfv * e1000_id_led_init_pchlan - store LED configurations 3089194865Sjfv * @hw: pointer to the HW structure 3090194865Sjfv * 3091194865Sjfv * PCH does not control LEDs via the LEDCTL register, rather it uses 3092194865Sjfv * the PHY LED configuration register. 3093194865Sjfv * 3094194865Sjfv * PCH also does not have an "always on" or "always off" mode which 3095194865Sjfv * complicates the ID feature. Instead of using the "on" mode to indicate 3096194865Sjfv * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 3097194865Sjfv * use "link_up" mode. The LEDs will still ID on request if there is no 3098194865Sjfv * link based on logic in e1000_led_[on|off]_pchlan(). 3099194865Sjfv **/ 3100194865Sjfvstatic s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 3101194865Sjfv{ 3102194865Sjfv struct e1000_mac_info *mac = &hw->mac; 3103194865Sjfv s32 ret_val; 3104194865Sjfv const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 3105194865Sjfv const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 3106194865Sjfv u16 data, i, temp, shift; 3107194865Sjfv 3108194865Sjfv DEBUGFUNC("e1000_id_led_init_pchlan"); 3109194865Sjfv 3110194865Sjfv /* Get default ID LED modes */ 3111194865Sjfv ret_val = hw->nvm.ops.valid_led_default(hw, &data); 3112194865Sjfv if (ret_val) 3113194865Sjfv goto out; 3114194865Sjfv 3115194865Sjfv mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 3116194865Sjfv mac->ledctl_mode1 = mac->ledctl_default; 3117194865Sjfv mac->ledctl_mode2 = mac->ledctl_default; 3118194865Sjfv 3119194865Sjfv for (i = 0; i < 4; i++) { 3120194865Sjfv temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 3121194865Sjfv shift = (i * 5); 3122194865Sjfv switch (temp) { 3123194865Sjfv case ID_LED_ON1_DEF2: 3124194865Sjfv case ID_LED_ON1_ON2: 3125194865Sjfv case ID_LED_ON1_OFF2: 3126194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3127194865Sjfv mac->ledctl_mode1 |= (ledctl_on << shift); 3128194865Sjfv break; 3129194865Sjfv case ID_LED_OFF1_DEF2: 3130194865Sjfv case ID_LED_OFF1_ON2: 3131194865Sjfv case ID_LED_OFF1_OFF2: 3132194865Sjfv mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3133194865Sjfv mac->ledctl_mode1 |= (ledctl_off << shift); 3134194865Sjfv break; 3135194865Sjfv default: 3136194865Sjfv /* Do nothing */ 3137194865Sjfv break; 3138194865Sjfv } 3139194865Sjfv switch (temp) { 3140194865Sjfv case ID_LED_DEF1_ON2: 3141194865Sjfv case ID_LED_ON1_ON2: 3142194865Sjfv case ID_LED_OFF1_ON2: 3143194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3144194865Sjfv mac->ledctl_mode2 |= (ledctl_on << shift); 3145194865Sjfv break; 3146194865Sjfv case ID_LED_DEF1_OFF2: 3147194865Sjfv case ID_LED_ON1_OFF2: 3148194865Sjfv case ID_LED_OFF1_OFF2: 3149194865Sjfv mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3150194865Sjfv mac->ledctl_mode2 |= (ledctl_off << shift); 3151194865Sjfv break; 3152194865Sjfv default: 3153194865Sjfv /* Do nothing */ 3154194865Sjfv break; 3155194865Sjfv } 3156194865Sjfv } 3157194865Sjfv 3158194865Sjfvout: 3159194865Sjfv return ret_val; 3160194865Sjfv} 3161194865Sjfv 3162194865Sjfv/** 3163169240Sjfv * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 3164169589Sjfv * @hw: pointer to the HW structure 3165169240Sjfv * 3166169240Sjfv * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 3167169240Sjfv * register, so the the bus width is hard coded. 3168169240Sjfv **/ 3169177867Sjfvstatic s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 3170169240Sjfv{ 3171169240Sjfv struct e1000_bus_info *bus = &hw->bus; 3172169240Sjfv s32 ret_val; 3173169240Sjfv 3174169240Sjfv DEBUGFUNC("e1000_get_bus_info_ich8lan"); 3175169240Sjfv 3176169240Sjfv ret_val = e1000_get_bus_info_pcie_generic(hw); 3177169240Sjfv 3178173788Sjfv /* 3179173788Sjfv * ICH devices are "PCI Express"-ish. They have 3180169240Sjfv * a configuration space, but do not contain 3181169240Sjfv * PCI Express Capability registers, so bus width 3182169240Sjfv * must be hardcoded. 3183169240Sjfv */ 3184169240Sjfv if (bus->width == e1000_bus_width_unknown) 3185169240Sjfv bus->width = e1000_bus_width_pcie_x1; 3186169240Sjfv 3187169240Sjfv return ret_val; 3188169240Sjfv} 3189169240Sjfv 3190169240Sjfv/** 3191169240Sjfv * e1000_reset_hw_ich8lan - Reset the hardware 3192169589Sjfv * @hw: pointer to the HW structure 3193169240Sjfv * 3194169240Sjfv * Does a full reset of the hardware which includes a reset of the PHY and 3195169240Sjfv * MAC. 3196169240Sjfv **/ 3197177867Sjfvstatic s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 3198169240Sjfv{ 3199200243Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3200200243Sjfv u16 reg; 3201169240Sjfv u32 ctrl, icr, kab; 3202169240Sjfv s32 ret_val; 3203169240Sjfv 3204169240Sjfv DEBUGFUNC("e1000_reset_hw_ich8lan"); 3205169240Sjfv 3206173788Sjfv /* 3207173788Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 3208169240Sjfv * on the last TLP read/write transaction when MAC is reset. 3209169240Sjfv */ 3210169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 3211185353Sjfv if (ret_val) 3212169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 3213169240Sjfv 3214169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 3215169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3216169240Sjfv 3217173788Sjfv /* 3218173788Sjfv * Disable the Transmit and Receive units. Then delay to allow 3219169240Sjfv * any pending transactions to complete before we hit the MAC 3220169240Sjfv * with the global reset. 3221169240Sjfv */ 3222169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 3223169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 3224169240Sjfv E1000_WRITE_FLUSH(hw); 3225169240Sjfv 3226169240Sjfv msec_delay(10); 3227169240Sjfv 3228169240Sjfv /* Workaround for ICH8 bit corruption issue in FIFO memory */ 3229169240Sjfv if (hw->mac.type == e1000_ich8lan) { 3230169240Sjfv /* Set Tx and Rx buffer allocation to 8k apiece. */ 3231169240Sjfv E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 3232169240Sjfv /* Set Packet Buffer Size to 16k. */ 3233169240Sjfv E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 3234169240Sjfv } 3235169240Sjfv 3236200243Sjfv if (hw->mac.type == e1000_pchlan) { 3237200243Sjfv /* Save the NVM K1 bit setting*/ 3238200243Sjfv ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); 3239200243Sjfv if (ret_val) 3240200243Sjfv return ret_val; 3241200243Sjfv 3242200243Sjfv if (reg & E1000_NVM_K1_ENABLE) 3243200243Sjfv dev_spec->nvm_k1_enabled = TRUE; 3244200243Sjfv else 3245200243Sjfv dev_spec->nvm_k1_enabled = FALSE; 3246200243Sjfv } 3247200243Sjfv 3248169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 3249169240Sjfv 3250213234Sjfv if (!hw->phy.ops.check_reset_block(hw)) { 3251173788Sjfv /* 3252213234Sjfv * Full-chip reset requires MAC and PHY reset at the same 3253169240Sjfv * time to make sure the interface between MAC and the 3254169240Sjfv * external PHY is reset. 3255169240Sjfv */ 3256169240Sjfv ctrl |= E1000_CTRL_PHY_RST; 3257213234Sjfv 3258213234Sjfv /* 3259213234Sjfv * Gate automatic PHY configuration by hardware on 3260213234Sjfv * non-managed 82579 3261213234Sjfv */ 3262213234Sjfv if ((hw->mac.type == e1000_pch2lan) && 3263213234Sjfv !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) 3264213234Sjfv e1000_gate_hw_phy_config_ich8lan(hw, TRUE); 3265169240Sjfv } 3266169240Sjfv ret_val = e1000_acquire_swflag_ich8lan(hw); 3267185353Sjfv DEBUGOUT("Issuing a global reset to ich8lan\n"); 3268169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 3269169240Sjfv msec_delay(20); 3270169240Sjfv 3271194865Sjfv if (!ret_val) 3272194865Sjfv e1000_release_swflag_ich8lan(hw); 3273194865Sjfv 3274213234Sjfv if (ctrl & E1000_CTRL_PHY_RST) { 3275213234Sjfv ret_val = hw->phy.ops.get_cfg_done(hw); 3276203049Sjfv if (ret_val) 3277203049Sjfv goto out; 3278203049Sjfv 3279213234Sjfv ret_val = e1000_post_phy_reset_ich8lan(hw); 3280213234Sjfv if (ret_val) 3281213234Sjfv goto out; 3282169240Sjfv } 3283169240Sjfv 3284200243Sjfv /* 3285200243Sjfv * For PCH, this write will make sure that any noise 3286200243Sjfv * will be detected as a CRC error and be dropped rather than show up 3287200243Sjfv * as a bad packet to the DMA engine. 3288200243Sjfv */ 3289200243Sjfv if (hw->mac.type == e1000_pchlan) 3290200243Sjfv E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); 3291200243Sjfv 3292169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3293169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 3294169240Sjfv 3295169240Sjfv kab = E1000_READ_REG(hw, E1000_KABGTXD); 3296169240Sjfv kab |= E1000_KABGTXD_BGSQLBIAS; 3297169240Sjfv E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 3298169240Sjfv 3299200243Sjfvout: 3300169240Sjfv return ret_val; 3301169240Sjfv} 3302169240Sjfv 3303169240Sjfv/** 3304169240Sjfv * e1000_init_hw_ich8lan - Initialize the hardware 3305169589Sjfv * @hw: pointer to the HW structure 3306169240Sjfv * 3307169240Sjfv * Prepares the hardware for transmit and receive by doing the following: 3308169240Sjfv * - initialize hardware bits 3309169240Sjfv * - initialize LED identification 3310169240Sjfv * - setup receive address registers 3311169240Sjfv * - setup flow control 3312176667Sjfv * - setup transmit descriptors 3313169240Sjfv * - clear statistics 3314169240Sjfv **/ 3315177867Sjfvstatic s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 3316169240Sjfv{ 3317169240Sjfv struct e1000_mac_info *mac = &hw->mac; 3318169240Sjfv u32 ctrl_ext, txdctl, snoop; 3319169240Sjfv s32 ret_val; 3320169240Sjfv u16 i; 3321169240Sjfv 3322169240Sjfv DEBUGFUNC("e1000_init_hw_ich8lan"); 3323169240Sjfv 3324169240Sjfv e1000_initialize_hw_bits_ich8lan(hw); 3325169240Sjfv 3326169240Sjfv /* Initialize identification LED */ 3327190872Sjfv ret_val = mac->ops.id_led_init(hw); 3328190872Sjfv if (ret_val) 3329200243Sjfv DEBUGOUT("Error initializing identification LED\n"); 3330190872Sjfv /* This is not fatal and we should not stop init due to this */ 3331169240Sjfv 3332169240Sjfv /* Setup the receive address. */ 3333169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 3334169240Sjfv 3335169240Sjfv /* Zero out the Multicast HASH table */ 3336169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 3337169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 3338169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 3339169240Sjfv 3340194865Sjfv /* 3341194865Sjfv * The 82578 Rx buffer will stall if wakeup is enabled in host and 3342194865Sjfv * the ME. Reading the BM_WUC register will clear the host wakeup bit. 3343194865Sjfv * Reset the phy after disabling host wakeup to reset the Rx buffer. 3344194865Sjfv */ 3345194865Sjfv if (hw->phy.type == e1000_phy_82578) { 3346194865Sjfv hw->phy.ops.read_reg(hw, BM_WUC, &i); 3347194865Sjfv ret_val = e1000_phy_hw_reset_ich8lan(hw); 3348194865Sjfv if (ret_val) 3349194865Sjfv return ret_val; 3350194865Sjfv } 3351194865Sjfv 3352169240Sjfv /* Setup link and flow control */ 3353177867Sjfv ret_val = mac->ops.setup_link(hw); 3354169240Sjfv 3355169240Sjfv /* Set the transmit descriptor write-back policy for both queues */ 3356173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 3357169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3358169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 3359169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3360169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3361173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 3362173788Sjfv txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 3363169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3364169240Sjfv E1000_TXDCTL_FULL_TX_DESC_WB; 3365169240Sjfv txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3366169240Sjfv E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3367173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 3368169240Sjfv 3369173788Sjfv /* 3370173788Sjfv * ICH8 has opposite polarity of no_snoop bits. 3371173788Sjfv * By default, we should use snoop behavior. 3372173788Sjfv */ 3373169240Sjfv if (mac->type == e1000_ich8lan) 3374169240Sjfv snoop = PCIE_ICH8_SNOOP_ALL; 3375169240Sjfv else 3376200243Sjfv snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 3377169240Sjfv e1000_set_pcie_no_snoop_generic(hw, snoop); 3378169240Sjfv 3379169240Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3380169240Sjfv ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 3381169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3382169240Sjfv 3383173788Sjfv /* 3384173788Sjfv * Clear all of the statistics registers (clear on read). It is 3385169240Sjfv * important that we do this after we have tried to establish link 3386169240Sjfv * because the symbol error count will increment wildly if there 3387169240Sjfv * is no link. 3388169240Sjfv */ 3389169240Sjfv e1000_clear_hw_cntrs_ich8lan(hw); 3390169240Sjfv 3391169240Sjfv return ret_val; 3392169240Sjfv} 3393169240Sjfv/** 3394169240Sjfv * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 3395169589Sjfv * @hw: pointer to the HW structure 3396169240Sjfv * 3397169240Sjfv * Sets/Clears required hardware bits necessary for correctly setting up the 3398169240Sjfv * hardware for transmit and receive. 3399169240Sjfv **/ 3400173788Sjfvstatic void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 3401169240Sjfv{ 3402169240Sjfv u32 reg; 3403169240Sjfv 3404169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 3405169240Sjfv 3406169240Sjfv /* Extended Device Control */ 3407169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3408169240Sjfv reg |= (1 << 22); 3409194865Sjfv /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 3410194865Sjfv if (hw->mac.type >= e1000_pchlan) 3411194865Sjfv reg |= E1000_CTRL_EXT_PHYPDEN; 3412169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3413169240Sjfv 3414169240Sjfv /* Transmit Descriptor Control 0 */ 3415173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 3416169240Sjfv reg |= (1 << 22); 3417173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 3418169240Sjfv 3419169240Sjfv /* Transmit Descriptor Control 1 */ 3420173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 3421169240Sjfv reg |= (1 << 22); 3422173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 3423169240Sjfv 3424169240Sjfv /* Transmit Arbitration Control 0 */ 3425173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 3426169240Sjfv if (hw->mac.type == e1000_ich8lan) 3427169240Sjfv reg |= (1 << 28) | (1 << 29); 3428169240Sjfv reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 3429173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3430169240Sjfv 3431169240Sjfv /* Transmit Arbitration Control 1 */ 3432173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 3433169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 3434169240Sjfv reg &= ~(1 << 28); 3435169240Sjfv else 3436169240Sjfv reg |= (1 << 28); 3437169240Sjfv reg |= (1 << 24) | (1 << 26) | (1 << 30); 3438173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 3439169240Sjfv 3440169240Sjfv /* Device Status */ 3441169240Sjfv if (hw->mac.type == e1000_ich8lan) { 3442169240Sjfv reg = E1000_READ_REG(hw, E1000_STATUS); 3443169240Sjfv reg &= ~(1 << 31); 3444169240Sjfv E1000_WRITE_REG(hw, E1000_STATUS, reg); 3445169240Sjfv } 3446169240Sjfv 3447205869Sjfv /* 3448205869Sjfv * work-around descriptor data corruption issue during nfs v2 udp 3449205869Sjfv * traffic, just disable the nfs filtering capability 3450205869Sjfv */ 3451205869Sjfv reg = E1000_READ_REG(hw, E1000_RFCTL); 3452205869Sjfv reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 3453205869Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, reg); 3454205869Sjfv 3455169240Sjfv return; 3456169240Sjfv} 3457169240Sjfv 3458169240Sjfv/** 3459169240Sjfv * e1000_setup_link_ich8lan - Setup flow control and link settings 3460169589Sjfv * @hw: pointer to the HW structure 3461169240Sjfv * 3462169240Sjfv * Determines which flow control settings to use, then configures flow 3463169240Sjfv * control. Calls the appropriate media-specific link configuration 3464169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 3465169240Sjfv * should be established. Assumes the hardware has previously been reset 3466169240Sjfv * and the transmitter and receiver are not enabled. 3467169240Sjfv **/ 3468177867Sjfvstatic s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 3469169240Sjfv{ 3470169240Sjfv s32 ret_val = E1000_SUCCESS; 3471169240Sjfv 3472169240Sjfv DEBUGFUNC("e1000_setup_link_ich8lan"); 3473169240Sjfv 3474177867Sjfv if (hw->phy.ops.check_reset_block(hw)) 3475169240Sjfv goto out; 3476169240Sjfv 3477173788Sjfv /* 3478173788Sjfv * ICH parts do not have a word in the NVM to determine 3479169240Sjfv * the default flow control setting, so we explicitly 3480169240Sjfv * set it to full. 3481169240Sjfv */ 3482185353Sjfv if (hw->fc.requested_mode == e1000_fc_default) 3483185353Sjfv hw->fc.requested_mode = e1000_fc_full; 3484169240Sjfv 3485185353Sjfv /* 3486185353Sjfv * Save off the requested flow control mode for use later. Depending 3487185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 3488185353Sjfv */ 3489185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 3490169240Sjfv 3491185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 3492190872Sjfv hw->fc.current_mode); 3493169240Sjfv 3494169240Sjfv /* Continue to configure the copper link. */ 3495177867Sjfv ret_val = hw->mac.ops.setup_physical_interface(hw); 3496169240Sjfv if (ret_val) 3497169240Sjfv goto out; 3498169240Sjfv 3499173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 3500194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 3501213234Sjfv (hw->phy.type == e1000_phy_82579) || 3502194865Sjfv (hw->phy.type == e1000_phy_82577)) { 3503213234Sjfv E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); 3504213234Sjfv 3505194865Sjfv ret_val = hw->phy.ops.write_reg(hw, 3506194865Sjfv PHY_REG(BM_PORT_CTRL_PAGE, 27), 3507194865Sjfv hw->fc.pause_time); 3508194865Sjfv if (ret_val) 3509194865Sjfv goto out; 3510194865Sjfv } 3511169240Sjfv 3512169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 3513169240Sjfv 3514169240Sjfvout: 3515169240Sjfv return ret_val; 3516169240Sjfv} 3517169240Sjfv 3518169240Sjfv/** 3519169240Sjfv * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 3520169589Sjfv * @hw: pointer to the HW structure 3521169240Sjfv * 3522169240Sjfv * Configures the kumeran interface to the PHY to wait the appropriate time 3523169240Sjfv * when polling the PHY, then call the generic setup_copper_link to finish 3524169240Sjfv * configuring the copper link. 3525169240Sjfv **/ 3526177867Sjfvstatic s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 3527169240Sjfv{ 3528169240Sjfv u32 ctrl; 3529169240Sjfv s32 ret_val; 3530169240Sjfv u16 reg_data; 3531169240Sjfv 3532169240Sjfv DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 3533169240Sjfv 3534169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 3535169240Sjfv ctrl |= E1000_CTRL_SLU; 3536169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3537169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3538169240Sjfv 3539173788Sjfv /* 3540173788Sjfv * Set the mac to wait the maximum time between each iteration 3541169240Sjfv * and increase the max iterations when polling the phy; 3542173788Sjfv * this fixes erroneous timeouts at 10Mbps. 3543173788Sjfv */ 3544200243Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 3545181027Sjfv 0xFFFF); 3546169240Sjfv if (ret_val) 3547169240Sjfv goto out; 3548194865Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, 3549194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 3550181027Sjfv ®_data); 3551169240Sjfv if (ret_val) 3552169240Sjfv goto out; 3553169240Sjfv reg_data |= 0x3F; 3554194865Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3555194865Sjfv E1000_KMRNCTRLSTA_INBAND_PARAM, 3556181027Sjfv reg_data); 3557169240Sjfv if (ret_val) 3558169240Sjfv goto out; 3559169240Sjfv 3560190872Sjfv switch (hw->phy.type) { 3561190872Sjfv case e1000_phy_igp_3: 3562169240Sjfv ret_val = e1000_copper_link_setup_igp(hw); 3563169240Sjfv if (ret_val) 3564169240Sjfv goto out; 3565190872Sjfv break; 3566190872Sjfv case e1000_phy_bm: 3567194865Sjfv case e1000_phy_82578: 3568176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 3569176667Sjfv if (ret_val) 3570176667Sjfv goto out; 3571190872Sjfv break; 3572194865Sjfv case e1000_phy_82577: 3573213234Sjfv case e1000_phy_82579: 3574194865Sjfv ret_val = e1000_copper_link_setup_82577(hw); 3575194865Sjfv if (ret_val) 3576194865Sjfv goto out; 3577194865Sjfv break; 3578190872Sjfv case e1000_phy_ife: 3579177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 3580177867Sjfv ®_data); 3581173788Sjfv if (ret_val) 3582173788Sjfv goto out; 3583173788Sjfv 3584173788Sjfv reg_data &= ~IFE_PMC_AUTO_MDIX; 3585173788Sjfv 3586173788Sjfv switch (hw->phy.mdix) { 3587173788Sjfv case 1: 3588173788Sjfv reg_data &= ~IFE_PMC_FORCE_MDIX; 3589173788Sjfv break; 3590173788Sjfv case 2: 3591173788Sjfv reg_data |= IFE_PMC_FORCE_MDIX; 3592173788Sjfv break; 3593173788Sjfv case 0: 3594173788Sjfv default: 3595173788Sjfv reg_data |= IFE_PMC_AUTO_MDIX; 3596173788Sjfv break; 3597173788Sjfv } 3598177867Sjfv ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 3599177867Sjfv reg_data); 3600173788Sjfv if (ret_val) 3601173788Sjfv goto out; 3602190872Sjfv break; 3603190872Sjfv default: 3604190872Sjfv break; 3605173788Sjfv } 3606169240Sjfv ret_val = e1000_setup_copper_link_generic(hw); 3607169240Sjfv 3608169240Sjfvout: 3609169240Sjfv return ret_val; 3610169240Sjfv} 3611169240Sjfv 3612169240Sjfv/** 3613169240Sjfv * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 3614169589Sjfv * @hw: pointer to the HW structure 3615169589Sjfv * @speed: pointer to store current link speed 3616169589Sjfv * @duplex: pointer to store the current link duplex 3617169240Sjfv * 3618176667Sjfv * Calls the generic get_speed_and_duplex to retrieve the current link 3619169240Sjfv * information and then calls the Kumeran lock loss workaround for links at 3620169240Sjfv * gigabit speeds. 3621169240Sjfv **/ 3622177867Sjfvstatic s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 3623173788Sjfv u16 *duplex) 3624169240Sjfv{ 3625169240Sjfv s32 ret_val; 3626169240Sjfv 3627169240Sjfv DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 3628169240Sjfv 3629169240Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 3630169240Sjfv if (ret_val) 3631169240Sjfv goto out; 3632169240Sjfv 3633169240Sjfv if ((hw->mac.type == e1000_ich8lan) && 3634169240Sjfv (hw->phy.type == e1000_phy_igp_3) && 3635169240Sjfv (*speed == SPEED_1000)) { 3636169240Sjfv ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 3637169240Sjfv } 3638169240Sjfv 3639169240Sjfvout: 3640169240Sjfv return ret_val; 3641169240Sjfv} 3642169240Sjfv 3643169240Sjfv/** 3644169240Sjfv * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 3645169589Sjfv * @hw: pointer to the HW structure 3646169240Sjfv * 3647169240Sjfv * Work-around for 82566 Kumeran PCS lock loss: 3648169240Sjfv * On link status change (i.e. PCI reset, speed change) and link is up and 3649169240Sjfv * speed is gigabit- 3650169240Sjfv * 0) if workaround is optionally disabled do nothing 3651169240Sjfv * 1) wait 1ms for Kumeran link to come up 3652169240Sjfv * 2) check Kumeran Diagnostic register PCS lock loss bit 3653169240Sjfv * 3) if not set the link is locked (all is good), otherwise... 3654169240Sjfv * 4) reset the PHY 3655169240Sjfv * 5) repeat up to 10 times 3656169240Sjfv * Note: this is only called for IGP3 copper when speed is 1gb. 3657169240Sjfv **/ 3658173788Sjfvstatic s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 3659169240Sjfv{ 3660185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3661169240Sjfv u32 phy_ctrl; 3662169240Sjfv s32 ret_val = E1000_SUCCESS; 3663169240Sjfv u16 i, data; 3664173788Sjfv bool link; 3665169240Sjfv 3666169240Sjfv DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 3667169240Sjfv 3668173788Sjfv if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 3669169240Sjfv goto out; 3670169240Sjfv 3671173788Sjfv /* 3672173788Sjfv * Make sure link is up before proceeding. If not just return. 3673169240Sjfv * Attempting this while link is negotiating fouled up link 3674173788Sjfv * stability 3675173788Sjfv */ 3676169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3677169240Sjfv if (!link) { 3678169240Sjfv ret_val = E1000_SUCCESS; 3679169240Sjfv goto out; 3680169240Sjfv } 3681169240Sjfv 3682169240Sjfv for (i = 0; i < 10; i++) { 3683169240Sjfv /* read once to clear */ 3684177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 3685169240Sjfv if (ret_val) 3686169240Sjfv goto out; 3687169240Sjfv /* and again to get new status */ 3688177867Sjfv ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 3689169240Sjfv if (ret_val) 3690169240Sjfv goto out; 3691169240Sjfv 3692169240Sjfv /* check for PCS lock */ 3693169240Sjfv if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 3694169240Sjfv ret_val = E1000_SUCCESS; 3695169240Sjfv goto out; 3696169240Sjfv } 3697169240Sjfv 3698169240Sjfv /* Issue PHY reset */ 3699177867Sjfv hw->phy.ops.reset(hw); 3700169240Sjfv msec_delay_irq(5); 3701169240Sjfv } 3702169240Sjfv /* Disable GigE link negotiation */ 3703169240Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3704169240Sjfv phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 3705169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3706169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3707169240Sjfv 3708173788Sjfv /* 3709176667Sjfv * Call gig speed drop workaround on Gig disable before accessing 3710173788Sjfv * any PHY registers 3711173788Sjfv */ 3712169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3713169240Sjfv 3714169240Sjfv /* unable to acquire PCS lock */ 3715169240Sjfv ret_val = -E1000_ERR_PHY; 3716169240Sjfv 3717169240Sjfvout: 3718169240Sjfv return ret_val; 3719169240Sjfv} 3720169240Sjfv 3721169240Sjfv/** 3722176667Sjfv * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 3723169589Sjfv * @hw: pointer to the HW structure 3724176667Sjfv * @state: boolean value used to set the current Kumeran workaround state 3725169240Sjfv * 3726169240Sjfv * If ICH8, set the current Kumeran workaround state (enabled - TRUE 3727169240Sjfv * /disabled - FALSE). 3728169240Sjfv **/ 3729173788Sjfvvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 3730173788Sjfv bool state) 3731169240Sjfv{ 3732185353Sjfv struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3733169240Sjfv 3734169240Sjfv DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 3735169240Sjfv 3736169240Sjfv if (hw->mac.type != e1000_ich8lan) { 3737169240Sjfv DEBUGOUT("Workaround applies to ICH8 only.\n"); 3738185353Sjfv return; 3739169240Sjfv } 3740169240Sjfv 3741169240Sjfv dev_spec->kmrn_lock_loss_workaround_enabled = state; 3742169240Sjfv 3743169240Sjfv return; 3744169240Sjfv} 3745169240Sjfv 3746169240Sjfv/** 3747169240Sjfv * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 3748169589Sjfv * @hw: pointer to the HW structure 3749169240Sjfv * 3750169240Sjfv * Workaround for 82566 power-down on D3 entry: 3751169240Sjfv * 1) disable gigabit link 3752169240Sjfv * 2) write VR power-down enable 3753169240Sjfv * 3) read it back 3754169240Sjfv * Continue if successful, else issue LCD reset and repeat 3755169240Sjfv **/ 3756173788Sjfvvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 3757169240Sjfv{ 3758169240Sjfv u32 reg; 3759169240Sjfv u16 data; 3760169240Sjfv u8 retry = 0; 3761169240Sjfv 3762169240Sjfv DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 3763169240Sjfv 3764169240Sjfv if (hw->phy.type != e1000_phy_igp_3) 3765169240Sjfv goto out; 3766169240Sjfv 3767169240Sjfv /* Try the workaround twice (if needed) */ 3768169240Sjfv do { 3769169240Sjfv /* Disable link */ 3770169240Sjfv reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 3771169240Sjfv reg |= (E1000_PHY_CTRL_GBE_DISABLE | 3772169240Sjfv E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3773169240Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 3774169240Sjfv 3775173788Sjfv /* 3776176667Sjfv * Call gig speed drop workaround on Gig disable before 3777173788Sjfv * accessing any PHY registers 3778173788Sjfv */ 3779169240Sjfv if (hw->mac.type == e1000_ich8lan) 3780169240Sjfv e1000_gig_downshift_workaround_ich8lan(hw); 3781169240Sjfv 3782169240Sjfv /* Write VR power-down enable */ 3783177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 3784169240Sjfv data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3785185353Sjfv hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 3786169240Sjfv data | IGP3_VR_CTRL_MODE_SHUTDOWN); 3787169240Sjfv 3788169240Sjfv /* Read it back and test */ 3789177867Sjfv hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 3790169589Sjfv data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3791169589Sjfv if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 3792169240Sjfv break; 3793169240Sjfv 3794169240Sjfv /* Issue PHY reset and repeat at most one more time */ 3795169240Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 3796169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 3797169240Sjfv retry++; 3798169240Sjfv } while (retry); 3799169240Sjfv 3800169240Sjfvout: 3801169240Sjfv return; 3802169240Sjfv} 3803169240Sjfv 3804169240Sjfv/** 3805169240Sjfv * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 3806169589Sjfv * @hw: pointer to the HW structure 3807169240Sjfv * 3808169240Sjfv * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 3809176667Sjfv * LPLU, Gig disable, MDIC PHY reset): 3810169240Sjfv * 1) Set Kumeran Near-end loopback 3811169240Sjfv * 2) Clear Kumeran Near-end loopback 3812169240Sjfv * Should only be called for ICH8[m] devices with IGP_3 Phy. 3813169240Sjfv **/ 3814173788Sjfvvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 3815169240Sjfv{ 3816169240Sjfv s32 ret_val = E1000_SUCCESS; 3817169240Sjfv u16 reg_data; 3818169240Sjfv 3819169240Sjfv DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 3820169240Sjfv 3821169240Sjfv if ((hw->mac.type != e1000_ich8lan) || 3822169240Sjfv (hw->phy.type != e1000_phy_igp_3)) 3823169240Sjfv goto out; 3824169240Sjfv 3825181027Sjfv ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3826181027Sjfv ®_data); 3827169240Sjfv if (ret_val) 3828169240Sjfv goto out; 3829169240Sjfv reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 3830181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3831181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 3832181027Sjfv reg_data); 3833169240Sjfv if (ret_val) 3834169240Sjfv goto out; 3835169240Sjfv reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 3836181027Sjfv ret_val = e1000_write_kmrn_reg_generic(hw, 3837181027Sjfv E1000_KMRNCTRLSTA_DIAG_OFFSET, 3838181027Sjfv reg_data); 3839169240Sjfvout: 3840169240Sjfv return; 3841169240Sjfv} 3842169240Sjfv 3843169240Sjfv/** 3844176667Sjfv * e1000_disable_gig_wol_ich8lan - disable gig during WoL 3845176667Sjfv * @hw: pointer to the HW structure 3846176667Sjfv * 3847176667Sjfv * During S0 to Sx transition, it is possible the link remains at gig 3848176667Sjfv * instead of negotiating to a lower speed. Before going to Sx, set 3849176667Sjfv * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 3850176667Sjfv * to a lower speed. 3851176667Sjfv * 3852190872Sjfv * Should only be called for applicable parts. 3853176667Sjfv **/ 3854176667Sjfvvoid e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 3855176667Sjfv{ 3856176667Sjfv u32 phy_ctrl; 3857213234Sjfv s32 ret_val; 3858176667Sjfv 3859213234Sjfv DEBUGFUNC("e1000_disable_gig_wol_ich8lan"); 3860194865Sjfv 3861213234Sjfv phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 3862213234Sjfv phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE; 3863213234Sjfv E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 3864213234Sjfv 3865213234Sjfv if (hw->mac.type >= e1000_pchlan) { 3866213234Sjfv e1000_oem_bits_config_ich8lan(hw, FALSE); 3867213234Sjfv ret_val = hw->phy.ops.acquire(hw); 3868213234Sjfv if (ret_val) 3869213234Sjfv return; 3870213234Sjfv e1000_write_smbus_addr(hw); 3871213234Sjfv hw->phy.ops.release(hw); 3872176667Sjfv } 3873176667Sjfv 3874176667Sjfv return; 3875176667Sjfv} 3876176667Sjfv 3877176667Sjfv/** 3878169240Sjfv * e1000_cleanup_led_ich8lan - Restore the default LED operation 3879169589Sjfv * @hw: pointer to the HW structure 3880169240Sjfv * 3881169240Sjfv * Return the LED back to the default configuration. 3882169240Sjfv **/ 3883177867Sjfvstatic s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 3884169240Sjfv{ 3885169240Sjfv DEBUGFUNC("e1000_cleanup_led_ich8lan"); 3886169240Sjfv 3887169240Sjfv if (hw->phy.type == e1000_phy_ife) 3888203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3889203049Sjfv 0); 3890169240Sjfv 3891203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 3892203049Sjfv return E1000_SUCCESS; 3893169240Sjfv} 3894169240Sjfv 3895169240Sjfv/** 3896176667Sjfv * e1000_led_on_ich8lan - Turn LEDs on 3897169589Sjfv * @hw: pointer to the HW structure 3898169240Sjfv * 3899176667Sjfv * Turn on the LEDs. 3900169240Sjfv **/ 3901177867Sjfvstatic s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 3902169240Sjfv{ 3903169240Sjfv DEBUGFUNC("e1000_led_on_ich8lan"); 3904169240Sjfv 3905169240Sjfv if (hw->phy.type == e1000_phy_ife) 3906203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3907169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 3908169240Sjfv 3909203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 3910203049Sjfv return E1000_SUCCESS; 3911169240Sjfv} 3912169240Sjfv 3913169240Sjfv/** 3914176667Sjfv * e1000_led_off_ich8lan - Turn LEDs off 3915169589Sjfv * @hw: pointer to the HW structure 3916169240Sjfv * 3917176667Sjfv * Turn off the LEDs. 3918169240Sjfv **/ 3919177867Sjfvstatic s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 3920169240Sjfv{ 3921169240Sjfv DEBUGFUNC("e1000_led_off_ich8lan"); 3922169240Sjfv 3923169240Sjfv if (hw->phy.type == e1000_phy_ife) 3924203049Sjfv return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3925169240Sjfv (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 3926169240Sjfv 3927203049Sjfv E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 3928203049Sjfv return E1000_SUCCESS; 3929169240Sjfv} 3930169240Sjfv 3931169240Sjfv/** 3932194865Sjfv * e1000_setup_led_pchlan - Configures SW controllable LED 3933194865Sjfv * @hw: pointer to the HW structure 3934194865Sjfv * 3935194865Sjfv * This prepares the SW controllable LED for use. 3936194865Sjfv **/ 3937194865Sjfvstatic s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3938194865Sjfv{ 3939194865Sjfv DEBUGFUNC("e1000_setup_led_pchlan"); 3940194865Sjfv 3941194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3942194865Sjfv (u16)hw->mac.ledctl_mode1); 3943194865Sjfv} 3944194865Sjfv 3945194865Sjfv/** 3946194865Sjfv * e1000_cleanup_led_pchlan - Restore the default LED operation 3947194865Sjfv * @hw: pointer to the HW structure 3948194865Sjfv * 3949194865Sjfv * Return the LED back to the default configuration. 3950194865Sjfv **/ 3951194865Sjfvstatic s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 3952194865Sjfv{ 3953194865Sjfv DEBUGFUNC("e1000_cleanup_led_pchlan"); 3954194865Sjfv 3955194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3956194865Sjfv (u16)hw->mac.ledctl_default); 3957194865Sjfv} 3958194865Sjfv 3959194865Sjfv/** 3960194865Sjfv * e1000_led_on_pchlan - Turn LEDs on 3961194865Sjfv * @hw: pointer to the HW structure 3962194865Sjfv * 3963194865Sjfv * Turn on the LEDs. 3964194865Sjfv **/ 3965194865Sjfvstatic s32 e1000_led_on_pchlan(struct e1000_hw *hw) 3966194865Sjfv{ 3967194865Sjfv u16 data = (u16)hw->mac.ledctl_mode2; 3968194865Sjfv u32 i, led; 3969194865Sjfv 3970194865Sjfv DEBUGFUNC("e1000_led_on_pchlan"); 3971194865Sjfv 3972194865Sjfv /* 3973194865Sjfv * If no link, then turn LED on by setting the invert bit 3974194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode2. 3975194865Sjfv */ 3976194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 3977194865Sjfv for (i = 0; i < 3; i++) { 3978194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 3979194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 3980194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 3981194865Sjfv continue; 3982194865Sjfv if (led & E1000_PHY_LED0_IVRT) 3983194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 3984194865Sjfv else 3985194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 3986194865Sjfv } 3987194865Sjfv } 3988194865Sjfv 3989194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3990194865Sjfv} 3991194865Sjfv 3992194865Sjfv/** 3993194865Sjfv * e1000_led_off_pchlan - Turn LEDs off 3994194865Sjfv * @hw: pointer to the HW structure 3995194865Sjfv * 3996194865Sjfv * Turn off the LEDs. 3997194865Sjfv **/ 3998194865Sjfvstatic s32 e1000_led_off_pchlan(struct e1000_hw *hw) 3999194865Sjfv{ 4000194865Sjfv u16 data = (u16)hw->mac.ledctl_mode1; 4001194865Sjfv u32 i, led; 4002194865Sjfv 4003194865Sjfv DEBUGFUNC("e1000_led_off_pchlan"); 4004194865Sjfv 4005194865Sjfv /* 4006194865Sjfv * If no link, then turn LED off by clearing the invert bit 4007194865Sjfv * for each LED that's mode is "link_up" in ledctl_mode1. 4008194865Sjfv */ 4009194865Sjfv if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 4010194865Sjfv for (i = 0; i < 3; i++) { 4011194865Sjfv led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4012194865Sjfv if ((led & E1000_PHY_LED0_MODE_MASK) != 4013194865Sjfv E1000_LEDCTL_MODE_LINK_UP) 4014194865Sjfv continue; 4015194865Sjfv if (led & E1000_PHY_LED0_IVRT) 4016194865Sjfv data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4017194865Sjfv else 4018194865Sjfv data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4019194865Sjfv } 4020194865Sjfv } 4021194865Sjfv 4022194865Sjfv return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 4023194865Sjfv} 4024194865Sjfv 4025194865Sjfv/** 4026213234Sjfv * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 4027169589Sjfv * @hw: pointer to the HW structure 4028169240Sjfv * 4029213234Sjfv * Read appropriate register for the config done bit for completion status 4030213234Sjfv * and configure the PHY through s/w for EEPROM-less parts. 4031213234Sjfv * 4032213234Sjfv * NOTE: some silicon which is EEPROM-less will fail trying to read the 4033213234Sjfv * config done bit, so only an error is logged and continues. If we were 4034213234Sjfv * to return with error, EEPROM-less silicon would not be able to be reset 4035213234Sjfv * or change link. 4036169240Sjfv **/ 4037177867Sjfvstatic s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 4038169240Sjfv{ 4039173788Sjfv s32 ret_val = E1000_SUCCESS; 4040178523Sjfv u32 bank = 0; 4041213234Sjfv u32 status; 4042173788Sjfv 4043213234Sjfv DEBUGFUNC("e1000_get_cfg_done_ich8lan"); 4044194865Sjfv 4045213234Sjfv e1000_get_cfg_done_generic(hw); 4046213234Sjfv 4047213234Sjfv /* Wait for indication from h/w that it has completed basic config */ 4048213234Sjfv if (hw->mac.type >= e1000_ich10lan) { 4049213234Sjfv e1000_lan_init_done_ich8lan(hw); 4050213234Sjfv } else { 4051213234Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 4052213234Sjfv if (ret_val) { 4053213234Sjfv /* 4054213234Sjfv * When auto config read does not complete, do not 4055213234Sjfv * return with an error. This can happen in situations 4056213234Sjfv * where there is no eeprom and prevents getting link. 4057213234Sjfv */ 4058213234Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 4059213234Sjfv ret_val = E1000_SUCCESS; 4060213234Sjfv } 4061194865Sjfv } 4062194865Sjfv 4063213234Sjfv /* Clear PHY Reset Asserted bit */ 4064213234Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 4065213234Sjfv if (status & E1000_STATUS_PHYRA) 4066213234Sjfv E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); 4067213234Sjfv else 4068213234Sjfv DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 4069169240Sjfv 4070169240Sjfv /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 4071200243Sjfv if (hw->mac.type <= e1000_ich9lan) { 4072178523Sjfv if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 4073185353Sjfv (hw->phy.type == e1000_phy_igp_3)) { 4074178523Sjfv e1000_phy_init_script_igp3(hw); 4075178523Sjfv } 4076178523Sjfv } else { 4077178523Sjfv if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 4078185353Sjfv /* Maybe we should do a basic PHY config */ 4079178523Sjfv DEBUGOUT("EEPROM not present\n"); 4080178523Sjfv ret_val = -E1000_ERR_CONFIG; 4081178523Sjfv } 4082169240Sjfv } 4083169240Sjfv 4084173788Sjfv return ret_val; 4085169240Sjfv} 4086169240Sjfv 4087169240Sjfv/** 4088173788Sjfv * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 4089173788Sjfv * @hw: pointer to the HW structure 4090173788Sjfv * 4091173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 4092173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 4093173788Sjfv **/ 4094177867Sjfvstatic void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 4095173788Sjfv{ 4096173788Sjfv /* If the management interface is not enabled, then power down */ 4097185353Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 4098185353Sjfv hw->phy.ops.check_reset_block(hw))) 4099173788Sjfv e1000_power_down_phy_copper(hw); 4100173788Sjfv 4101173788Sjfv return; 4102173788Sjfv} 4103173788Sjfv 4104173788Sjfv/** 4105169240Sjfv * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 4106169589Sjfv * @hw: pointer to the HW structure 4107169240Sjfv * 4108169240Sjfv * Clears hardware counters specific to the silicon family and calls 4109169240Sjfv * clear_hw_cntrs_generic to clear all general purpose counters. 4110169240Sjfv **/ 4111177867Sjfvstatic void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 4112169240Sjfv{ 4113194865Sjfv u16 phy_data; 4114194865Sjfv 4115169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 4116169240Sjfv 4117169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 4118169240Sjfv 4119185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 4120185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 4121185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 4122185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 4123185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 4124185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 4125169240Sjfv 4126185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 4127185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 4128185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 4129169240Sjfv 4130185353Sjfv E1000_READ_REG(hw, E1000_IAC); 4131185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 4132194865Sjfv 4133194865Sjfv /* Clear PHY statistics registers */ 4134194865Sjfv if ((hw->phy.type == e1000_phy_82578) || 4135213234Sjfv (hw->phy.type == e1000_phy_82579) || 4136194865Sjfv (hw->phy.type == e1000_phy_82577)) { 4137194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 4138194865Sjfv hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 4139194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 4140194865Sjfv hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 4141194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 4142194865Sjfv hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 4143194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 4144194865Sjfv hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 4145194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 4146194865Sjfv hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 4147194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 4148194865Sjfv hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 4149194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 4150194865Sjfv hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 4151194865Sjfv } 4152169240Sjfv} 4153169240Sjfv 4154