e1000_ich8lan.c revision 194865
1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 194865 2009-06-24 17:41:29Z jfv $*/ 34 35/* 36 * 82562G 10/100 Network Connection 37 * 82562G-2 10/100 Network Connection 38 * 82562GT 10/100 Network Connection 39 * 82562GT-2 10/100 Network Connection 40 * 82562V 10/100 Network Connection 41 * 82562V-2 10/100 Network Connection 42 * 82566DC-2 Gigabit Network Connection 43 * 82566DC Gigabit Network Connection 44 * 82566DM-2 Gigabit Network Connection 45 * 82566DM Gigabit Network Connection 46 * 82566MC Gigabit Network Connection 47 * 82566MM Gigabit Network Connection 48 * 82567LM Gigabit Network Connection 49 * 82567LF Gigabit Network Connection 50 * 82567V Gigabit Network Connection 51 * 82567LM-2 Gigabit Network Connection 52 * 82567LF-2 Gigabit Network Connection 53 * 82567V-2 Gigabit Network Connection 54 * 82567LF-3 Gigabit Network Connection 55 * 82567LM-3 Gigabit Network Connection 56 * 82567LM-4 Gigabit Network Connection 57 * 82577LM Gigabit Network Connection 58 * 82577LC Gigabit Network Connection 59 * 82578DM Gigabit Network Connection 60 * 82578DC Gigabit Network Connection 61 */ 62 63#include "e1000_api.h" 64 65static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw); 66static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw); 67static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw); 68static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw); 69static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw); 70static void e1000_release_swflag_ich8lan(struct e1000_hw *hw); 71static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 72static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); 73static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); 74static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw); 75static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, 76 bool active); 77static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, 78 bool active); 79static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 80 u16 words, u16 *data); 81static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, 82 u16 words, u16 *data); 83static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw); 84static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw); 85static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, 86 u16 *data); 87static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 88static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw); 89static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw); 90static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw); 91static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); 92static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); 93static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, 94 u16 *speed, u16 *duplex); 95static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 96static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 97static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 98static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 99static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 100static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 101static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 102static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 103static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 104static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout); 105static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw); 106static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw); 107static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 108static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 109static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, 110 u32 offset, u8 *data); 111static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 112 u8 size, u16 *data); 113static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, 114 u32 offset, u16 *data); 115static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 116 u32 offset, u8 byte); 117static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, 118 u32 offset, u8 data); 119static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 120 u8 size, u16 data); 121static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); 122static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 123 124/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 125/* Offset 04h HSFSTS */ 126union ich8_hws_flash_status { 127 struct ich8_hsfsts { 128 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 129 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 130 u16 dael :1; /* bit 2 Direct Access error Log */ 131 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 132 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 133 u16 reserved1 :2; /* bit 13:6 Reserved */ 134 u16 reserved2 :6; /* bit 13:6 Reserved */ 135 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 136 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 137 } hsf_status; 138 u16 regval; 139}; 140 141/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 142/* Offset 06h FLCTL */ 143union ich8_hws_flash_ctrl { 144 struct ich8_hsflctl { 145 u16 flcgo :1; /* 0 Flash Cycle Go */ 146 u16 flcycle :2; /* 2:1 Flash Cycle */ 147 u16 reserved :5; /* 7:3 Reserved */ 148 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 149 u16 flockdn :6; /* 15:10 Reserved */ 150 } hsf_ctrl; 151 u16 regval; 152}; 153 154/* ICH Flash Region Access Permissions */ 155union ich8_hws_flash_regacc { 156 struct ich8_flracc { 157 u32 grra :8; /* 0:7 GbE region Read Access */ 158 u32 grwa :8; /* 8:15 GbE region Write Access */ 159 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 160 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 161 } hsf_flregacc; 162 u16 regval; 163}; 164 165/** 166 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 167 * @hw: pointer to the HW structure 168 * 169 * Initialize family-specific PHY parameters and function pointers. 170 **/ 171static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 172{ 173 struct e1000_phy_info *phy = &hw->phy; 174 s32 ret_val = E1000_SUCCESS; 175 176 DEBUGFUNC("e1000_init_phy_params_pchlan"); 177 178 phy->addr = 1; 179 phy->reset_delay_us = 100; 180 181 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 182 phy->ops.check_polarity = e1000_check_polarity_ife; 183 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 184 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 185 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 186 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 187 phy->ops.get_info = e1000_get_phy_info_ich8lan; 188 phy->ops.read_reg = e1000_read_phy_reg_hv; 189 phy->ops.release = e1000_release_swflag_ich8lan; 190 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 191 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 192 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 193 phy->ops.write_reg = e1000_write_phy_reg_hv; 194 phy->ops.power_up = e1000_power_up_phy_copper; 195 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 196 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 197 198 phy->id = e1000_phy_unknown; 199 e1000_get_phy_id(hw); 200 phy->type = e1000_get_phy_type_from_id(phy->id); 201 202 if (phy->type == e1000_phy_82577) { 203 phy->ops.check_polarity = e1000_check_polarity_82577; 204 phy->ops.force_speed_duplex = 205 e1000_phy_force_speed_duplex_82577; 206 phy->ops.get_cable_length = e1000_get_cable_length_82577; 207 phy->ops.get_info = e1000_get_phy_info_82577; 208 phy->ops.commit = e1000_phy_sw_reset_generic; 209 } 210 211 return ret_val; 212} 213 214/** 215 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 216 * @hw: pointer to the HW structure 217 * 218 * Initialize family-specific PHY parameters and function pointers. 219 **/ 220static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 221{ 222 struct e1000_phy_info *phy = &hw->phy; 223 s32 ret_val = E1000_SUCCESS; 224 u16 i = 0; 225 226 DEBUGFUNC("e1000_init_phy_params_ich8lan"); 227 228 phy->addr = 1; 229 phy->reset_delay_us = 100; 230 231 phy->ops.acquire = e1000_acquire_swflag_ich8lan; 232 phy->ops.check_polarity = e1000_check_polarity_ife; 233 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; 234 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 235 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 236 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; 237 phy->ops.get_info = e1000_get_phy_info_ich8lan; 238 phy->ops.read_reg = e1000_read_phy_reg_igp; 239 phy->ops.release = e1000_release_swflag_ich8lan; 240 phy->ops.reset = e1000_phy_hw_reset_ich8lan; 241 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; 242 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; 243 phy->ops.write_reg = e1000_write_phy_reg_igp; 244 phy->ops.power_up = e1000_power_up_phy_copper; 245 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 246 247 /* 248 * We may need to do this twice - once for IGP and if that fails, 249 * we'll set BM func pointers and try again 250 */ 251 ret_val = e1000_determine_phy_address(hw); 252 if (ret_val) { 253 phy->ops.write_reg = e1000_write_phy_reg_bm; 254 phy->ops.read_reg = e1000_read_phy_reg_bm; 255 ret_val = e1000_determine_phy_address(hw); 256 if (ret_val) { 257 DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); 258 goto out; 259 } 260 } 261 262 phy->id = 0; 263 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && 264 (i++ < 100)) { 265 msec_delay(1); 266 ret_val = e1000_get_phy_id(hw); 267 if (ret_val) 268 goto out; 269 } 270 271 /* Verify phy id */ 272 switch (phy->id) { 273 case IGP03E1000_E_PHY_ID: 274 phy->type = e1000_phy_igp_3; 275 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 276 break; 277 case IFE_E_PHY_ID: 278 case IFE_PLUS_E_PHY_ID: 279 case IFE_C_E_PHY_ID: 280 phy->type = e1000_phy_ife; 281 phy->autoneg_mask = E1000_ALL_NOT_GIG; 282 break; 283 case BME1000_E_PHY_ID: 284 phy->type = e1000_phy_bm; 285 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 286 phy->ops.read_reg = e1000_read_phy_reg_bm; 287 phy->ops.write_reg = e1000_write_phy_reg_bm; 288 phy->ops.commit = e1000_phy_sw_reset_generic; 289 break; 290 default: 291 ret_val = -E1000_ERR_PHY; 292 goto out; 293 } 294 295out: 296 return ret_val; 297} 298 299/** 300 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 301 * @hw: pointer to the HW structure 302 * 303 * Initialize family-specific NVM parameters and function 304 * pointers. 305 **/ 306static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 307{ 308 struct e1000_nvm_info *nvm = &hw->nvm; 309 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 310 union ich8_hws_flash_status hsfsts; 311 u32 gfpreg, sector_base_addr, sector_end_addr; 312 s32 ret_val = E1000_SUCCESS; 313 u16 i; 314 315 DEBUGFUNC("e1000_init_nvm_params_ich8lan"); 316 317 /* Can't read flash registers if the register set isn't mapped. */ 318 if (!hw->flash_address) { 319 DEBUGOUT("ERROR: Flash registers not mapped\n"); 320 ret_val = -E1000_ERR_CONFIG; 321 goto out; 322 } 323 324 nvm->type = e1000_nvm_flash_sw; 325 326 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); 327 328 /* 329 * sector_X_addr is a "sector"-aligned address (4096 bytes) 330 * Add 1 to sector_end_addr since this sector is included in 331 * the overall size. 332 */ 333 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 334 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 335 336 /* flash_base_addr is byte-aligned */ 337 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 338 339 /* 340 * find total size of the NVM, then cut in half since the total 341 * size represents two separate NVM banks. 342 */ 343 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 344 << FLASH_SECTOR_ADDR_SHIFT; 345 nvm->flash_bank_size /= 2; 346 /* Adjust to word count */ 347 nvm->flash_bank_size /= sizeof(u16); 348 349 /* 350 * Make sure the flash bank size does not overwrite the 4k 351 * sector ranges. We may have 64k allotted to us but we only care 352 * about the first 2 4k sectors. Therefore, if we have anything less 353 * than 64k set in the HSFSTS register, we will reduce the bank size 354 * down to 4k and let the rest remain unused. If berasesz == 3, then 355 * we are working in 64k mode. Otherwise we are not. 356 */ 357 if (nvm->flash_bank_size > E1000_SHADOW_RAM_WORDS) { 358 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 359 if (hsfsts.hsf_status.berasesz != 3) 360 nvm->flash_bank_size = E1000_SHADOW_RAM_WORDS; 361 } 362 363 nvm->word_size = E1000_SHADOW_RAM_WORDS; 364 365 /* Clear shadow ram */ 366 for (i = 0; i < nvm->word_size; i++) { 367 dev_spec->shadow_ram[i].modified = FALSE; 368 dev_spec->shadow_ram[i].value = 0xFFFF; 369 } 370 371 /* Function Pointers */ 372 nvm->ops.acquire = e1000_acquire_swflag_ich8lan; 373 nvm->ops.read = e1000_read_nvm_ich8lan; 374 nvm->ops.release = e1000_release_swflag_ich8lan; 375 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; 376 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; 377 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; 378 nvm->ops.write = e1000_write_nvm_ich8lan; 379 380out: 381 return ret_val; 382} 383 384/** 385 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 386 * @hw: pointer to the HW structure 387 * 388 * Initialize family-specific MAC parameters and function 389 * pointers. 390 **/ 391static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 392{ 393 struct e1000_mac_info *mac = &hw->mac; 394 u16 pci_cfg; 395 396 DEBUGFUNC("e1000_init_mac_params_ich8lan"); 397 398 /* Set media type function pointer */ 399 hw->phy.media_type = e1000_media_type_copper; 400 401 /* Set mta register count */ 402 mac->mta_reg_count = 32; 403 /* Set rar entry count */ 404 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 405 if (mac->type == e1000_ich8lan) 406 mac->rar_entry_count--; 407 /* Set if part includes ASF firmware */ 408 mac->asf_firmware_present = TRUE; 409 /* Set if manageability features are enabled. */ 410 mac->arc_subsystem_valid = TRUE; 411 412 /* Function pointers */ 413 414 /* bus type/speed/width */ 415 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; 416 /* function id */ 417 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 418 /* reset */ 419 mac->ops.reset_hw = e1000_reset_hw_ich8lan; 420 /* hw initialization */ 421 mac->ops.init_hw = e1000_init_hw_ich8lan; 422 /* link setup */ 423 mac->ops.setup_link = e1000_setup_link_ich8lan; 424 /* physical interface setup */ 425 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; 426 /* check for link */ 427 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 428 /* check management mode */ 429 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 430 /* link info */ 431 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; 432 /* multicast address update */ 433 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 434 /* setting MTA */ 435 mac->ops.mta_set = e1000_mta_set_generic; 436 /* clear hardware counters */ 437 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; 438 439 /* LED operations */ 440 switch (mac->type) { 441 case e1000_ich8lan: 442 case e1000_ich9lan: 443 case e1000_ich10lan: 444 /* ID LED init */ 445 mac->ops.id_led_init = e1000_id_led_init_generic; 446 /* blink LED */ 447 mac->ops.blink_led = e1000_blink_led_generic; 448 /* setup LED */ 449 mac->ops.setup_led = e1000_setup_led_generic; 450 /* cleanup LED */ 451 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 452 /* turn on/off LED */ 453 mac->ops.led_on = e1000_led_on_ich8lan; 454 mac->ops.led_off = e1000_led_off_ich8lan; 455 break; 456 case e1000_pchlan: 457 /* save PCH revision_id */ 458 e1000_read_pci_cfg(hw, 0x2, &pci_cfg); 459 hw->revision_id = (u8)(pci_cfg &= 0x000F); 460 /* ID LED init */ 461 mac->ops.id_led_init = e1000_id_led_init_pchlan; 462 /* setup LED */ 463 mac->ops.setup_led = e1000_setup_led_pchlan; 464 /* cleanup LED */ 465 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 466 /* turn on/off LED */ 467 mac->ops.led_on = e1000_led_on_pchlan; 468 mac->ops.led_off = e1000_led_off_pchlan; 469 break; 470 default: 471 break; 472 } 473 474 /* Enable PCS Lock-loss workaround for ICH8 */ 475 if (mac->type == e1000_ich8lan) 476 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); 477 478 479 return E1000_SUCCESS; 480} 481 482/** 483 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers 484 * @hw: pointer to the HW structure 485 * 486 * Initialize family-specific function pointers for PHY, MAC, and NVM. 487 **/ 488void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) 489{ 490 DEBUGFUNC("e1000_init_function_pointers_ich8lan"); 491 492 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; 493 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; 494 switch (hw->mac.type) { 495 case e1000_ich8lan: 496 case e1000_ich9lan: 497 case e1000_ich10lan: 498 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; 499 break; 500 case e1000_pchlan: 501 hw->phy.ops.init_params = e1000_init_phy_params_pchlan; 502 break; 503 default: 504 break; 505 } 506} 507 508/** 509 * e1000_acquire_swflag_ich8lan - Acquire software control flag 510 * @hw: pointer to the HW structure 511 * 512 * Acquires the software control flag for performing NVM and PHY 513 * operations. This is a function pointer entry point only called by 514 * read/write routines for the PHY and NVM parts. 515 **/ 516static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 517{ 518 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 519 s32 ret_val = E1000_SUCCESS; 520 521 DEBUGFUNC("e1000_acquire_swflag_ich8lan"); 522 523 while (timeout) { 524 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 525 526 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) { 527 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 528 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 529 530 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 531 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 532 break; 533 } 534 msec_delay_irq(1); 535 timeout--; 536 } 537 538 if (!timeout) { 539 DEBUGOUT("SW/FW/HW has locked the resource for too long.\n"); 540 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 541 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 542 ret_val = -E1000_ERR_CONFIG; 543 goto out; 544 } 545 546out: 547 return ret_val; 548} 549 550/** 551 * e1000_release_swflag_ich8lan - Release software control flag 552 * @hw: pointer to the HW structure 553 * 554 * Releases the software control flag for performing NVM and PHY operations. 555 * This is a function pointer entry point only called by read/write 556 * routines for the PHY and NVM parts. 557 **/ 558static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 559{ 560 u32 extcnf_ctrl; 561 562 DEBUGFUNC("e1000_release_swflag_ich8lan"); 563 564 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 565 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 566 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 567 568 return; 569} 570 571/** 572 * e1000_check_mng_mode_ich8lan - Checks management mode 573 * @hw: pointer to the HW structure 574 * 575 * This checks if the adapter has manageability enabled. 576 * This is a function pointer entry point only called by read/write 577 * routines for the PHY and NVM parts. 578 **/ 579static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 580{ 581 u32 fwsm; 582 583 DEBUGFUNC("e1000_check_mng_mode_ich8lan"); 584 585 fwsm = E1000_READ_REG(hw, E1000_FWSM); 586 587 return (fwsm & E1000_FWSM_MODE_MASK) == 588 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 589} 590 591/** 592 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 593 * @hw: pointer to the HW structure 594 * 595 * Checks if firmware is blocking the reset of the PHY. 596 * This is a function pointer entry point only called by 597 * reset routines. 598 **/ 599static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 600{ 601 u32 fwsm; 602 603 DEBUGFUNC("e1000_check_reset_block_ich8lan"); 604 605 fwsm = E1000_READ_REG(hw, E1000_FWSM); 606 607 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 608 : E1000_BLK_PHY_RESET; 609} 610 611/** 612 * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx 613 * @hw: pointer to the HW structure 614 **/ 615s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 616{ 617 if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2)) 618 return E1000_SUCCESS; 619 620 return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444); 621} 622 623/** 624 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 625 * done after every PHY reset. 626 **/ 627static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 628{ 629 s32 ret_val = E1000_SUCCESS; 630 631 if (hw->mac.type != e1000_pchlan) 632 return ret_val; 633 634 /* Hanksville M Phy init for IEEE. */ 635 if ((hw->revision_id == 2) && 636 (hw->phy.type == e1000_phy_82577) && 637 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 638 hw->phy.ops.write_reg(hw, 0x10, 0x8823); 639 hw->phy.ops.write_reg(hw, 0x11, 0x0018); 640 hw->phy.ops.write_reg(hw, 0x10, 0x8824); 641 hw->phy.ops.write_reg(hw, 0x11, 0x0016); 642 hw->phy.ops.write_reg(hw, 0x10, 0x8825); 643 hw->phy.ops.write_reg(hw, 0x11, 0x001A); 644 hw->phy.ops.write_reg(hw, 0x10, 0x888C); 645 hw->phy.ops.write_reg(hw, 0x11, 0x0007); 646 hw->phy.ops.write_reg(hw, 0x10, 0x888D); 647 hw->phy.ops.write_reg(hw, 0x11, 0x0007); 648 hw->phy.ops.write_reg(hw, 0x10, 0x888E); 649 hw->phy.ops.write_reg(hw, 0x11, 0x0007); 650 hw->phy.ops.write_reg(hw, 0x10, 0x8827); 651 hw->phy.ops.write_reg(hw, 0x11, 0x0001); 652 hw->phy.ops.write_reg(hw, 0x10, 0x8835); 653 hw->phy.ops.write_reg(hw, 0x11, 0x0001); 654 hw->phy.ops.write_reg(hw, 0x10, 0x8834); 655 hw->phy.ops.write_reg(hw, 0x11, 0x0001); 656 hw->phy.ops.write_reg(hw, 0x10, 0x8833); 657 hw->phy.ops.write_reg(hw, 0x11, 0x0002); 658 } 659 660 if (((hw->phy.type == e1000_phy_82577) && 661 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 662 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 663 /* Disable generation of early preamble */ 664 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); 665 if (ret_val) 666 return ret_val; 667 668 /* Preamble tuning for SSC */ 669 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204); 670 if (ret_val) 671 return ret_val; 672 } 673 674 if (hw->phy.type == e1000_phy_82578) { 675 if (hw->revision_id < 3) { 676 /* PHY config */ 677 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 678 0x66C0); 679 if (ret_val) 680 return ret_val; 681 682 /* PHY config */ 683 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 684 0xFFFF); 685 if (ret_val) 686 return ret_val; 687 } 688 689 /* 690 * Return registers to default by doing a soft reset then 691 * writing 0x3140 to the control register. 692 */ 693 if (hw->phy.revision < 2) { 694 e1000_phy_sw_reset_generic(hw); 695 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, 696 0x3140); 697 } 698 } 699 700 if ((hw->revision_id == 2) && 701 (hw->phy.type == e1000_phy_82577) && 702 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) { 703 /* 704 * Workaround for OEM (GbE) not operating after reset - 705 * restart AN (twice) 706 */ 707 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 708 if (ret_val) 709 return ret_val; 710 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400); 711 if (ret_val) 712 return ret_val; 713 } 714 715 /* Select page 0 */ 716 ret_val = hw->phy.ops.acquire(hw); 717 if (ret_val) 718 return ret_val; 719 hw->phy.addr = 1; 720 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 721 hw->phy.ops.release(hw); 722 723 return ret_val; 724} 725 726/** 727 * e1000_lan_init_done_ich8lan - Check for PHY config completion 728 * @hw: pointer to the HW structure 729 * 730 * Check the appropriate indication the MAC has finished configuring the 731 * PHY after a software reset. 732 **/ 733static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 734{ 735 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 736 737 DEBUGFUNC("e1000_lan_init_done_ich8lan"); 738 739 /* Wait for basic configuration completes before proceeding */ 740 do { 741 data = E1000_READ_REG(hw, E1000_STATUS); 742 data &= E1000_STATUS_LAN_INIT_DONE; 743 usec_delay(100); 744 } while ((!data) && --loop); 745 746 /* 747 * If basic configuration is incomplete before the above loop 748 * count reaches 0, loading the configuration from NVM will 749 * leave the PHY in a bad state possibly resulting in no link. 750 */ 751 if (loop == 0) 752 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n"); 753 754 /* Clear the Init Done bit for the next init event */ 755 data = E1000_READ_REG(hw, E1000_STATUS); 756 data &= ~E1000_STATUS_LAN_INIT_DONE; 757 E1000_WRITE_REG(hw, E1000_STATUS, data); 758} 759 760/** 761 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 762 * @hw: pointer to the HW structure 763 * 764 * Resets the PHY 765 * This is a function pointer entry point called by drivers 766 * or other shared routines. 767 **/ 768static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 769{ 770 struct e1000_phy_info *phy = &hw->phy; 771 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 772 s32 ret_val; 773 u16 word_addr, reg_data, reg_addr, phy_page = 0; 774 775 DEBUGFUNC("e1000_phy_hw_reset_ich8lan"); 776 777 ret_val = e1000_phy_hw_reset_generic(hw); 778 if (ret_val) 779 goto out; 780 781 /* Allow time for h/w to get to a quiescent state after reset */ 782 msec_delay(10); 783 784 if (hw->mac.type == e1000_pchlan) { 785 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 786 if (ret_val) 787 goto out; 788 } 789 790 /* 791 * Initialize the PHY from the NVM on ICH platforms. This 792 * is needed due to an issue where the NVM configuration is 793 * not properly autoloaded after power transitions. 794 * Therefore, after each PHY reset, we will load the 795 * configuration data out of the NVM manually. 796 */ 797 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { 798 /* Check if SW needs configure the PHY */ 799 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 800 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 801 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 802 else 803 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 804 805 data = E1000_READ_REG(hw, E1000_FEXTNVM); 806 if (!(data & sw_cfg_mask)) 807 goto out; 808 809 /* Wait for basic configuration completes before proceeding */ 810 e1000_lan_init_done_ich8lan(hw); 811 812 /* 813 * Make sure HW does not configure LCD from PHY 814 * extended configuration before SW configuration 815 */ 816 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 817 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 818 goto out; 819 820 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); 821 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 822 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 823 if (!cnf_size) 824 goto out; 825 826 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 827 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 828 829 /* Configure LCD from extended configuration region. */ 830 831 /* cnf_base_addr is in DWORD */ 832 word_addr = (u16)(cnf_base_addr << 1); 833 834 for (i = 0; i < cnf_size; i++) { 835 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, 836 ®_data); 837 if (ret_val) 838 goto out; 839 840 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), 841 1, ®_addr); 842 if (ret_val) 843 goto out; 844 845 /* Save off the PHY page for future writes. */ 846 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 847 phy_page = reg_data; 848 continue; 849 } 850 851 reg_addr |= phy_page; 852 853 ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data); 854 if (ret_val) 855 goto out; 856 } 857 } 858 859out: 860 return ret_val; 861} 862 863/** 864 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info 865 * @hw: pointer to the HW structure 866 * 867 * Wrapper for calling the get_phy_info routines for the appropriate phy type. 868 **/ 869static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) 870{ 871 s32 ret_val = -E1000_ERR_PHY_TYPE; 872 873 DEBUGFUNC("e1000_get_phy_info_ich8lan"); 874 875 switch (hw->phy.type) { 876 case e1000_phy_ife: 877 ret_val = e1000_get_phy_info_ife_ich8lan(hw); 878 break; 879 case e1000_phy_igp_3: 880 case e1000_phy_bm: 881 case e1000_phy_82578: 882 case e1000_phy_82577: 883 ret_val = e1000_get_phy_info_igp(hw); 884 break; 885 default: 886 break; 887 } 888 889 return ret_val; 890} 891 892/** 893 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states 894 * @hw: pointer to the HW structure 895 * 896 * Populates "phy" structure with various feature states. 897 * This function is only called by other family-specific 898 * routines. 899 **/ 900static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) 901{ 902 struct e1000_phy_info *phy = &hw->phy; 903 s32 ret_val; 904 u16 data; 905 bool link; 906 907 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan"); 908 909 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 910 if (ret_val) 911 goto out; 912 913 if (!link) { 914 DEBUGOUT("Phy info is only valid if link is up\n"); 915 ret_val = -E1000_ERR_CONFIG; 916 goto out; 917 } 918 919 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 920 if (ret_val) 921 goto out; 922 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 923 ? FALSE : TRUE; 924 925 if (phy->polarity_correction) { 926 ret_val = e1000_check_polarity_ife(hw); 927 if (ret_val) 928 goto out; 929 } else { 930 /* Polarity is forced */ 931 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 932 ? e1000_rev_polarity_reversed 933 : e1000_rev_polarity_normal; 934 } 935 936 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 937 if (ret_val) 938 goto out; 939 940 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 941 942 /* The following parameters are undefined for 10/100 operation. */ 943 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 944 phy->local_rx = e1000_1000t_rx_status_undefined; 945 phy->remote_rx = e1000_1000t_rx_status_undefined; 946 947out: 948 return ret_val; 949} 950 951/** 952 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 953 * @hw: pointer to the HW structure 954 * @active: TRUE to enable LPLU, FALSE to disable 955 * 956 * Sets the LPLU D0 state according to the active flag. When 957 * activating LPLU this function also disables smart speed 958 * and vice versa. LPLU will not be activated unless the 959 * device autonegotiation advertisement meets standards of 960 * either 10 or 10/100 or 10/100/1000 at all duplexes. 961 * This is a function pointer entry point only called by 962 * PHY setup routines. 963 **/ 964static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 965{ 966 struct e1000_phy_info *phy = &hw->phy; 967 u32 phy_ctrl; 968 s32 ret_val = E1000_SUCCESS; 969 u16 data; 970 971 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan"); 972 973 if (phy->type == e1000_phy_ife) 974 goto out; 975 976 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 977 978 if (active) { 979 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 980 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 981 982 if (phy->type != e1000_phy_igp_3) 983 goto out; 984 985 /* 986 * Call gig speed drop workaround on LPLU before accessing 987 * any PHY registers 988 */ 989 if (hw->mac.type == e1000_ich8lan) 990 e1000_gig_downshift_workaround_ich8lan(hw); 991 992 /* When LPLU is enabled, we should disable SmartSpeed */ 993 ret_val = phy->ops.read_reg(hw, 994 IGP01E1000_PHY_PORT_CONFIG, 995 &data); 996 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 997 ret_val = phy->ops.write_reg(hw, 998 IGP01E1000_PHY_PORT_CONFIG, 999 data); 1000 if (ret_val) 1001 goto out; 1002 } else { 1003 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 1004 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1005 1006 if (phy->type != e1000_phy_igp_3) 1007 goto out; 1008 1009 /* 1010 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1011 * during Dx states where the power conservation is most 1012 * important. During driver activity we should enable 1013 * SmartSpeed, so performance is maintained. 1014 */ 1015 if (phy->smart_speed == e1000_smart_speed_on) { 1016 ret_val = phy->ops.read_reg(hw, 1017 IGP01E1000_PHY_PORT_CONFIG, 1018 &data); 1019 if (ret_val) 1020 goto out; 1021 1022 data |= IGP01E1000_PSCFR_SMART_SPEED; 1023 ret_val = phy->ops.write_reg(hw, 1024 IGP01E1000_PHY_PORT_CONFIG, 1025 data); 1026 if (ret_val) 1027 goto out; 1028 } else if (phy->smart_speed == e1000_smart_speed_off) { 1029 ret_val = phy->ops.read_reg(hw, 1030 IGP01E1000_PHY_PORT_CONFIG, 1031 &data); 1032 if (ret_val) 1033 goto out; 1034 1035 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1036 ret_val = phy->ops.write_reg(hw, 1037 IGP01E1000_PHY_PORT_CONFIG, 1038 data); 1039 if (ret_val) 1040 goto out; 1041 } 1042 } 1043 1044out: 1045 return ret_val; 1046} 1047 1048/** 1049 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 1050 * @hw: pointer to the HW structure 1051 * @active: TRUE to enable LPLU, FALSE to disable 1052 * 1053 * Sets the LPLU D3 state according to the active flag. When 1054 * activating LPLU this function also disables smart speed 1055 * and vice versa. LPLU will not be activated unless the 1056 * device autonegotiation advertisement meets standards of 1057 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1058 * This is a function pointer entry point only called by 1059 * PHY setup routines. 1060 **/ 1061static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 1062{ 1063 struct e1000_phy_info *phy = &hw->phy; 1064 u32 phy_ctrl; 1065 s32 ret_val = E1000_SUCCESS; 1066 u16 data; 1067 1068 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan"); 1069 1070 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 1071 1072 if (!active) { 1073 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 1074 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1075 1076 if (phy->type != e1000_phy_igp_3) 1077 goto out; 1078 1079 /* 1080 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1081 * during Dx states where the power conservation is most 1082 * important. During driver activity we should enable 1083 * SmartSpeed, so performance is maintained. 1084 */ 1085 if (phy->smart_speed == e1000_smart_speed_on) { 1086 ret_val = phy->ops.read_reg(hw, 1087 IGP01E1000_PHY_PORT_CONFIG, 1088 &data); 1089 if (ret_val) 1090 goto out; 1091 1092 data |= IGP01E1000_PSCFR_SMART_SPEED; 1093 ret_val = phy->ops.write_reg(hw, 1094 IGP01E1000_PHY_PORT_CONFIG, 1095 data); 1096 if (ret_val) 1097 goto out; 1098 } else if (phy->smart_speed == e1000_smart_speed_off) { 1099 ret_val = phy->ops.read_reg(hw, 1100 IGP01E1000_PHY_PORT_CONFIG, 1101 &data); 1102 if (ret_val) 1103 goto out; 1104 1105 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1106 ret_val = phy->ops.write_reg(hw, 1107 IGP01E1000_PHY_PORT_CONFIG, 1108 data); 1109 if (ret_val) 1110 goto out; 1111 } 1112 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1113 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1114 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1115 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 1116 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 1117 1118 if (phy->type != e1000_phy_igp_3) 1119 goto out; 1120 1121 /* 1122 * Call gig speed drop workaround on LPLU before accessing 1123 * any PHY registers 1124 */ 1125 if (hw->mac.type == e1000_ich8lan) 1126 e1000_gig_downshift_workaround_ich8lan(hw); 1127 1128 /* When LPLU is enabled, we should disable SmartSpeed */ 1129 ret_val = phy->ops.read_reg(hw, 1130 IGP01E1000_PHY_PORT_CONFIG, 1131 &data); 1132 if (ret_val) 1133 goto out; 1134 1135 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1136 ret_val = phy->ops.write_reg(hw, 1137 IGP01E1000_PHY_PORT_CONFIG, 1138 data); 1139 } 1140 1141out: 1142 return ret_val; 1143} 1144 1145/** 1146 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 1147 * @hw: pointer to the HW structure 1148 * @bank: pointer to the variable that returns the active bank 1149 * 1150 * Reads signature byte from the NVM using the flash access registers. 1151 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 1152 **/ 1153static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 1154{ 1155 u32 eecd; 1156 struct e1000_nvm_info *nvm = &hw->nvm; 1157 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 1158 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 1159 u8 sig_byte = 0; 1160 s32 ret_val = E1000_SUCCESS; 1161 1162 switch (hw->mac.type) { 1163 case e1000_ich8lan: 1164 case e1000_ich9lan: 1165 eecd = E1000_READ_REG(hw, E1000_EECD); 1166 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 1167 E1000_EECD_SEC1VAL_VALID_MASK) { 1168 if (eecd & E1000_EECD_SEC1VAL) 1169 *bank = 1; 1170 else 1171 *bank = 0; 1172 1173 goto out; 1174 } 1175 DEBUGOUT("Unable to determine valid NVM bank via EEC - " 1176 "reading flash signature\n"); 1177 /* fall-thru */ 1178 default: 1179 /* set bank to 0 in case flash read fails */ 1180 *bank = 0; 1181 1182 /* Check bank 0 */ 1183 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 1184 &sig_byte); 1185 if (ret_val) 1186 goto out; 1187 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1188 E1000_ICH_NVM_SIG_VALUE) { 1189 *bank = 0; 1190 goto out; 1191 } 1192 1193 /* Check bank 1 */ 1194 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 1195 bank1_offset, 1196 &sig_byte); 1197 if (ret_val) 1198 goto out; 1199 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 1200 E1000_ICH_NVM_SIG_VALUE) { 1201 *bank = 1; 1202 goto out; 1203 } 1204 1205 DEBUGOUT("ERROR: No valid NVM bank present\n"); 1206 ret_val = -E1000_ERR_NVM; 1207 break; 1208 } 1209out: 1210 return ret_val; 1211} 1212 1213/** 1214 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 1215 * @hw: pointer to the HW structure 1216 * @offset: The offset (in bytes) of the word(s) to read. 1217 * @words: Size of data to read in words 1218 * @data: Pointer to the word(s) to read at offset. 1219 * 1220 * Reads a word(s) from the NVM using the flash access registers. 1221 **/ 1222static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1223 u16 *data) 1224{ 1225 struct e1000_nvm_info *nvm = &hw->nvm; 1226 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1227 u32 act_offset; 1228 s32 ret_val = E1000_SUCCESS; 1229 u32 bank = 0; 1230 u16 i, word; 1231 1232 DEBUGFUNC("e1000_read_nvm_ich8lan"); 1233 1234 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1235 (words == 0)) { 1236 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1237 ret_val = -E1000_ERR_NVM; 1238 goto out; 1239 } 1240 1241 ret_val = nvm->ops.acquire(hw); 1242 if (ret_val) 1243 goto out; 1244 1245 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1246 if (ret_val != E1000_SUCCESS) 1247 goto release; 1248 1249 act_offset = (bank) ? nvm->flash_bank_size : 0; 1250 act_offset += offset; 1251 1252 for (i = 0; i < words; i++) { 1253 if ((dev_spec->shadow_ram) && 1254 (dev_spec->shadow_ram[offset+i].modified)) { 1255 data[i] = dev_spec->shadow_ram[offset+i].value; 1256 } else { 1257 ret_val = e1000_read_flash_word_ich8lan(hw, 1258 act_offset + i, 1259 &word); 1260 if (ret_val) 1261 break; 1262 data[i] = word; 1263 } 1264 } 1265 1266release: 1267 nvm->ops.release(hw); 1268 1269out: 1270 if (ret_val) 1271 DEBUGOUT1("NVM read error: %d\n", ret_val); 1272 1273 return ret_val; 1274} 1275 1276/** 1277 * e1000_flash_cycle_init_ich8lan - Initialize flash 1278 * @hw: pointer to the HW structure 1279 * 1280 * This function does initial flash setup so that a new read/write/erase cycle 1281 * can be started. 1282 **/ 1283static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 1284{ 1285 union ich8_hws_flash_status hsfsts; 1286 s32 ret_val = -E1000_ERR_NVM; 1287 s32 i = 0; 1288 1289 DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); 1290 1291 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1292 1293 /* Check if the flash descriptor is valid */ 1294 if (hsfsts.hsf_status.fldesvalid == 0) { 1295 DEBUGOUT("Flash descriptor invalid. " 1296 "SW Sequencing must be used."); 1297 goto out; 1298 } 1299 1300 /* Clear FCERR and DAEL in hw status by writing 1 */ 1301 hsfsts.hsf_status.flcerr = 1; 1302 hsfsts.hsf_status.dael = 1; 1303 1304 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1305 1306 /* 1307 * Either we should have a hardware SPI cycle in progress 1308 * bit to check against, in order to start a new cycle or 1309 * FDONE bit should be changed in the hardware so that it 1310 * is 1 after hardware reset, which can then be used as an 1311 * indication whether a cycle is in progress or has been 1312 * completed. 1313 */ 1314 1315 if (hsfsts.hsf_status.flcinprog == 0) { 1316 /* 1317 * There is no cycle running at present, 1318 * so we can start a cycle. 1319 * Begin by setting Flash Cycle Done. 1320 */ 1321 hsfsts.hsf_status.flcdone = 1; 1322 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 1323 ret_val = E1000_SUCCESS; 1324 } else { 1325 /* 1326 * Otherwise poll for sometime so the current 1327 * cycle has a chance to end before giving up. 1328 */ 1329 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 1330 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1331 ICH_FLASH_HSFSTS); 1332 if (hsfsts.hsf_status.flcinprog == 0) { 1333 ret_val = E1000_SUCCESS; 1334 break; 1335 } 1336 usec_delay(1); 1337 } 1338 if (ret_val == E1000_SUCCESS) { 1339 /* 1340 * Successful in waiting for previous cycle to timeout, 1341 * now set the Flash Cycle Done. 1342 */ 1343 hsfsts.hsf_status.flcdone = 1; 1344 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 1345 hsfsts.regval); 1346 } else { 1347 DEBUGOUT("Flash controller busy, cannot get access"); 1348 } 1349 } 1350 1351out: 1352 return ret_val; 1353} 1354 1355/** 1356 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 1357 * @hw: pointer to the HW structure 1358 * @timeout: maximum time to wait for completion 1359 * 1360 * This function starts a flash cycle and waits for its completion. 1361 **/ 1362static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 1363{ 1364 union ich8_hws_flash_ctrl hsflctl; 1365 union ich8_hws_flash_status hsfsts; 1366 s32 ret_val = -E1000_ERR_NVM; 1367 u32 i = 0; 1368 1369 DEBUGFUNC("e1000_flash_cycle_ich8lan"); 1370 1371 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 1372 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1373 hsflctl.hsf_ctrl.flcgo = 1; 1374 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1375 1376 /* wait till FDONE bit is set to 1 */ 1377 do { 1378 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1379 if (hsfsts.hsf_status.flcdone == 1) 1380 break; 1381 usec_delay(1); 1382 } while (i++ < timeout); 1383 1384 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 1385 ret_val = E1000_SUCCESS; 1386 1387 return ret_val; 1388} 1389 1390/** 1391 * e1000_read_flash_word_ich8lan - Read word from flash 1392 * @hw: pointer to the HW structure 1393 * @offset: offset to data location 1394 * @data: pointer to the location for storing the data 1395 * 1396 * Reads the flash word at offset into data. Offset is converted 1397 * to bytes before read. 1398 **/ 1399static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 1400 u16 *data) 1401{ 1402 s32 ret_val; 1403 1404 DEBUGFUNC("e1000_read_flash_word_ich8lan"); 1405 1406 if (!data) { 1407 ret_val = -E1000_ERR_NVM; 1408 goto out; 1409 } 1410 1411 /* Must convert offset into bytes. */ 1412 offset <<= 1; 1413 1414 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data); 1415 1416out: 1417 return ret_val; 1418} 1419 1420/** 1421 * e1000_read_flash_byte_ich8lan - Read byte from flash 1422 * @hw: pointer to the HW structure 1423 * @offset: The offset of the byte to read. 1424 * @data: Pointer to a byte to store the value read. 1425 * 1426 * Reads a single byte from the NVM using the flash access registers. 1427 **/ 1428static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1429 u8 *data) 1430{ 1431 s32 ret_val = E1000_SUCCESS; 1432 u16 word = 0; 1433 1434 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 1435 if (ret_val) 1436 goto out; 1437 1438 *data = (u8)word; 1439 1440out: 1441 return ret_val; 1442} 1443 1444/** 1445 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 1446 * @hw: pointer to the HW structure 1447 * @offset: The offset (in bytes) of the byte or word to read. 1448 * @size: Size of data to read, 1=byte 2=word 1449 * @data: Pointer to the word to store the value read. 1450 * 1451 * Reads a byte or word from the NVM using the flash access registers. 1452 **/ 1453static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1454 u8 size, u16 *data) 1455{ 1456 union ich8_hws_flash_status hsfsts; 1457 union ich8_hws_flash_ctrl hsflctl; 1458 u32 flash_linear_addr; 1459 u32 flash_data = 0; 1460 s32 ret_val = -E1000_ERR_NVM; 1461 u8 count = 0; 1462 1463 DEBUGFUNC("e1000_read_flash_data_ich8lan"); 1464 1465 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 1466 goto out; 1467 1468 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1469 hw->nvm.flash_base_addr; 1470 1471 do { 1472 usec_delay(1); 1473 /* Steps */ 1474 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1475 if (ret_val != E1000_SUCCESS) 1476 break; 1477 1478 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1479 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1480 hsflctl.hsf_ctrl.fldbcount = size - 1; 1481 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 1482 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1483 1484 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1485 1486 ret_val = e1000_flash_cycle_ich8lan(hw, 1487 ICH_FLASH_READ_COMMAND_TIMEOUT); 1488 1489 /* 1490 * Check if FCERR is set to 1, if set to 1, clear it 1491 * and try the whole sequence a few more times, else 1492 * read in (shift in) the Flash Data0, the order is 1493 * least significant byte first msb to lsb 1494 */ 1495 if (ret_val == E1000_SUCCESS) { 1496 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); 1497 if (size == 1) 1498 *data = (u8)(flash_data & 0x000000FF); 1499 else if (size == 2) 1500 *data = (u16)(flash_data & 0x0000FFFF); 1501 break; 1502 } else { 1503 /* 1504 * If we've gotten here, then things are probably 1505 * completely hosed, but if the error condition is 1506 * detected, it won't hurt to give it another try... 1507 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 1508 */ 1509 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 1510 ICH_FLASH_HSFSTS); 1511 if (hsfsts.hsf_status.flcerr == 1) { 1512 /* Repeat for some time before giving up. */ 1513 continue; 1514 } else if (hsfsts.hsf_status.flcdone == 0) { 1515 DEBUGOUT("Timeout error - flash cycle " 1516 "did not complete."); 1517 break; 1518 } 1519 } 1520 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1521 1522out: 1523 return ret_val; 1524} 1525 1526/** 1527 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 1528 * @hw: pointer to the HW structure 1529 * @offset: The offset (in bytes) of the word(s) to write. 1530 * @words: Size of data to write in words 1531 * @data: Pointer to the word(s) to write at offset. 1532 * 1533 * Writes a byte or word to the NVM using the flash access registers. 1534 **/ 1535static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 1536 u16 *data) 1537{ 1538 struct e1000_nvm_info *nvm = &hw->nvm; 1539 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1540 s32 ret_val = E1000_SUCCESS; 1541 u16 i; 1542 1543 DEBUGFUNC("e1000_write_nvm_ich8lan"); 1544 1545 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 1546 (words == 0)) { 1547 DEBUGOUT("nvm parameter(s) out of bounds\n"); 1548 ret_val = -E1000_ERR_NVM; 1549 goto out; 1550 } 1551 1552 ret_val = nvm->ops.acquire(hw); 1553 if (ret_val) 1554 goto out; 1555 1556 for (i = 0; i < words; i++) { 1557 dev_spec->shadow_ram[offset+i].modified = TRUE; 1558 dev_spec->shadow_ram[offset+i].value = data[i]; 1559 } 1560 1561 nvm->ops.release(hw); 1562 1563out: 1564 return ret_val; 1565} 1566 1567/** 1568 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 1569 * @hw: pointer to the HW structure 1570 * 1571 * The NVM checksum is updated by calling the generic update_nvm_checksum, 1572 * which writes the checksum to the shadow ram. The changes in the shadow 1573 * ram are then committed to the EEPROM by processing each bank at a time 1574 * checking for the modified bit and writing only the pending changes. 1575 * After a successful commit, the shadow ram is cleared and is ready for 1576 * future writes. 1577 **/ 1578static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 1579{ 1580 struct e1000_nvm_info *nvm = &hw->nvm; 1581 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 1582 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 1583 s32 ret_val; 1584 u16 data; 1585 1586 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan"); 1587 1588 ret_val = e1000_update_nvm_checksum_generic(hw); 1589 if (ret_val) 1590 goto out; 1591 1592 if (nvm->type != e1000_nvm_flash_sw) 1593 goto out; 1594 1595 ret_val = nvm->ops.acquire(hw); 1596 if (ret_val) 1597 goto out; 1598 1599 /* 1600 * We're writing to the opposite bank so if we're on bank 1, 1601 * write to bank 0 etc. We also need to erase the segment that 1602 * is going to be written 1603 */ 1604 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1605 if (ret_val != E1000_SUCCESS) { 1606 nvm->ops.release(hw); 1607 goto out; 1608 } 1609 1610 if (bank == 0) { 1611 new_bank_offset = nvm->flash_bank_size; 1612 old_bank_offset = 0; 1613 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 1614 if (ret_val) { 1615 nvm->ops.release(hw); 1616 goto out; 1617 } 1618 } else { 1619 old_bank_offset = nvm->flash_bank_size; 1620 new_bank_offset = 0; 1621 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 1622 if (ret_val) { 1623 nvm->ops.release(hw); 1624 goto out; 1625 } 1626 } 1627 1628 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1629 /* 1630 * Determine whether to write the value stored 1631 * in the other NVM bank or a modified value stored 1632 * in the shadow RAM 1633 */ 1634 if (dev_spec->shadow_ram[i].modified) { 1635 data = dev_spec->shadow_ram[i].value; 1636 } else { 1637 ret_val = e1000_read_flash_word_ich8lan(hw, i + 1638 old_bank_offset, 1639 &data); 1640 if (ret_val) 1641 break; 1642 } 1643 1644 /* 1645 * If the word is 0x13, then make sure the signature bits 1646 * (15:14) are 11b until the commit has completed. 1647 * This will allow us to write 10b which indicates the 1648 * signature is valid. We want to do this after the write 1649 * has completed so that we don't mark the segment valid 1650 * while the write is still in progress 1651 */ 1652 if (i == E1000_ICH_NVM_SIG_WORD) 1653 data |= E1000_ICH_NVM_SIG_MASK; 1654 1655 /* Convert offset to bytes. */ 1656 act_offset = (i + new_bank_offset) << 1; 1657 1658 usec_delay(100); 1659 /* Write the bytes to the new bank. */ 1660 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1661 act_offset, 1662 (u8)data); 1663 if (ret_val) 1664 break; 1665 1666 usec_delay(100); 1667 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1668 act_offset + 1, 1669 (u8)(data >> 8)); 1670 if (ret_val) 1671 break; 1672 } 1673 1674 /* 1675 * Don't bother writing the segment valid bits if sector 1676 * programming failed. 1677 */ 1678 if (ret_val) { 1679 DEBUGOUT("Flash commit failed.\n"); 1680 nvm->ops.release(hw); 1681 goto out; 1682 } 1683 1684 /* 1685 * Finally validate the new segment by setting bit 15:14 1686 * to 10b in word 0x13 , this can be done without an 1687 * erase as well since these bits are 11 to start with 1688 * and we need to change bit 14 to 0b 1689 */ 1690 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 1691 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 1692 if (ret_val) { 1693 nvm->ops.release(hw); 1694 goto out; 1695 } 1696 data &= 0xBFFF; 1697 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 1698 act_offset * 2 + 1, 1699 (u8)(data >> 8)); 1700 if (ret_val) { 1701 nvm->ops.release(hw); 1702 goto out; 1703 } 1704 1705 /* 1706 * And invalidate the previously valid segment by setting 1707 * its signature word (0x13) high_byte to 0b. This can be 1708 * done without an erase because flash erase sets all bits 1709 * to 1's. We can write 1's to 0's without an erase 1710 */ 1711 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 1712 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 1713 if (ret_val) { 1714 nvm->ops.release(hw); 1715 goto out; 1716 } 1717 1718 /* Great! Everything worked, we can now clear the cached entries. */ 1719 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 1720 dev_spec->shadow_ram[i].modified = FALSE; 1721 dev_spec->shadow_ram[i].value = 0xFFFF; 1722 } 1723 1724 nvm->ops.release(hw); 1725 1726 /* 1727 * Reload the EEPROM, or else modifications will not appear 1728 * until after the next adapter reset. 1729 */ 1730 nvm->ops.reload(hw); 1731 msec_delay(10); 1732 1733out: 1734 if (ret_val) 1735 DEBUGOUT1("NVM update error: %d\n", ret_val); 1736 1737 return ret_val; 1738} 1739 1740/** 1741 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 1742 * @hw: pointer to the HW structure 1743 * 1744 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 1745 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 1746 * calculated, in which case we need to calculate the checksum and set bit 6. 1747 **/ 1748static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 1749{ 1750 s32 ret_val = E1000_SUCCESS; 1751 u16 data; 1752 1753 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan"); 1754 1755 /* 1756 * Read 0x19 and check bit 6. If this bit is 0, the checksum 1757 * needs to be fixed. This bit is an indication that the NVM 1758 * was prepared by OEM software and did not calculate the 1759 * checksum...a likely scenario. 1760 */ 1761 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data); 1762 if (ret_val) 1763 goto out; 1764 1765 if ((data & 0x40) == 0) { 1766 data |= 0x40; 1767 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data); 1768 if (ret_val) 1769 goto out; 1770 ret_val = hw->nvm.ops.update(hw); 1771 if (ret_val) 1772 goto out; 1773 } 1774 1775 ret_val = e1000_validate_nvm_checksum_generic(hw); 1776 1777out: 1778 return ret_val; 1779} 1780 1781/** 1782 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 1783 * @hw: pointer to the HW structure 1784 * @offset: The offset (in bytes) of the byte/word to read. 1785 * @size: Size of data to read, 1=byte 2=word 1786 * @data: The byte(s) to write to the NVM. 1787 * 1788 * Writes one/two bytes to the NVM using the flash access registers. 1789 **/ 1790static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 1791 u8 size, u16 data) 1792{ 1793 union ich8_hws_flash_status hsfsts; 1794 union ich8_hws_flash_ctrl hsflctl; 1795 u32 flash_linear_addr; 1796 u32 flash_data = 0; 1797 s32 ret_val = -E1000_ERR_NVM; 1798 u8 count = 0; 1799 1800 DEBUGFUNC("e1000_write_ich8_data"); 1801 1802 if (size < 1 || size > 2 || data > size * 0xff || 1803 offset > ICH_FLASH_LINEAR_ADDR_MASK) 1804 goto out; 1805 1806 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 1807 hw->nvm.flash_base_addr; 1808 1809 do { 1810 usec_delay(1); 1811 /* Steps */ 1812 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1813 if (ret_val != E1000_SUCCESS) 1814 break; 1815 1816 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 1817 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 1818 hsflctl.hsf_ctrl.fldbcount = size - 1; 1819 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 1820 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 1821 1822 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); 1823 1824 if (size == 1) 1825 flash_data = (u32)data & 0x00FF; 1826 else 1827 flash_data = (u32)data; 1828 1829 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 1830 1831 /* 1832 * check if FCERR is set to 1 , if set to 1, clear it 1833 * and try the whole sequence a few more times else done 1834 */ 1835 ret_val = e1000_flash_cycle_ich8lan(hw, 1836 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 1837 if (ret_val == E1000_SUCCESS) 1838 break; 1839 1840 /* 1841 * If we're here, then things are most likely 1842 * completely hosed, but if the error condition 1843 * is detected, it won't hurt to give it another 1844 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 1845 */ 1846 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1847 if (hsfsts.hsf_status.flcerr == 1) { 1848 /* Repeat for some time before giving up. */ 1849 continue; 1850 } else if (hsfsts.hsf_status.flcdone == 0) { 1851 DEBUGOUT("Timeout error - flash cycle " 1852 "did not complete."); 1853 break; 1854 } 1855 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 1856 1857out: 1858 return ret_val; 1859} 1860 1861/** 1862 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 1863 * @hw: pointer to the HW structure 1864 * @offset: The index of the byte to read. 1865 * @data: The byte to write to the NVM. 1866 * 1867 * Writes a single byte to the NVM using the flash access registers. 1868 **/ 1869static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 1870 u8 data) 1871{ 1872 u16 word = (u16)data; 1873 1874 DEBUGFUNC("e1000_write_flash_byte_ich8lan"); 1875 1876 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 1877} 1878 1879/** 1880 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 1881 * @hw: pointer to the HW structure 1882 * @offset: The offset of the byte to write. 1883 * @byte: The byte to write to the NVM. 1884 * 1885 * Writes a single byte to the NVM using the flash access registers. 1886 * Goes through a retry algorithm before giving up. 1887 **/ 1888static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 1889 u32 offset, u8 byte) 1890{ 1891 s32 ret_val; 1892 u16 program_retries; 1893 1894 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan"); 1895 1896 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1897 if (ret_val == E1000_SUCCESS) 1898 goto out; 1899 1900 for (program_retries = 0; program_retries < 100; program_retries++) { 1901 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset); 1902 usec_delay(100); 1903 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 1904 if (ret_val == E1000_SUCCESS) 1905 break; 1906 } 1907 if (program_retries == 100) { 1908 ret_val = -E1000_ERR_NVM; 1909 goto out; 1910 } 1911 1912out: 1913 return ret_val; 1914} 1915 1916/** 1917 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 1918 * @hw: pointer to the HW structure 1919 * @bank: 0 for first bank, 1 for second bank, etc. 1920 * 1921 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 1922 * bank N is 4096 * N + flash_reg_addr. 1923 **/ 1924static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 1925{ 1926 struct e1000_nvm_info *nvm = &hw->nvm; 1927 union ich8_hws_flash_status hsfsts; 1928 union ich8_hws_flash_ctrl hsflctl; 1929 u32 flash_linear_addr; 1930 /* bank size is in 16bit words - adjust to bytes */ 1931 u32 flash_bank_size = nvm->flash_bank_size * 2; 1932 s32 ret_val = E1000_SUCCESS; 1933 s32 count = 0; 1934 s32 j, iteration, sector_size; 1935 1936 DEBUGFUNC("e1000_erase_flash_bank_ich8lan"); 1937 1938 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 1939 1940 /* 1941 * Determine HW Sector size: Read BERASE bits of hw flash status 1942 * register 1943 * 00: The Hw sector is 256 bytes, hence we need to erase 16 1944 * consecutive sectors. The start index for the nth Hw sector 1945 * can be calculated as = bank * 4096 + n * 256 1946 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 1947 * The start index for the nth Hw sector can be calculated 1948 * as = bank * 4096 1949 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 1950 * (ich9 only, otherwise error condition) 1951 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 1952 */ 1953 switch (hsfsts.hsf_status.berasesz) { 1954 case 0: 1955 /* Hw sector size 256 */ 1956 sector_size = ICH_FLASH_SEG_SIZE_256; 1957 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 1958 break; 1959 case 1: 1960 sector_size = ICH_FLASH_SEG_SIZE_4K; 1961 iteration = 1; 1962 break; 1963 case 2: 1964 if (hw->mac.type == e1000_ich9lan) { 1965 sector_size = ICH_FLASH_SEG_SIZE_8K; 1966 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; 1967 } else { 1968 ret_val = -E1000_ERR_NVM; 1969 goto out; 1970 } 1971 break; 1972 case 3: 1973 sector_size = ICH_FLASH_SEG_SIZE_64K; 1974 iteration = 1; 1975 break; 1976 default: 1977 ret_val = -E1000_ERR_NVM; 1978 goto out; 1979 } 1980 1981 /* Start with the base address, then add the sector offset. */ 1982 flash_linear_addr = hw->nvm.flash_base_addr; 1983 flash_linear_addr += (bank) ? (sector_size * iteration) : 0; 1984 1985 for (j = 0; j < iteration ; j++) { 1986 do { 1987 /* Steps */ 1988 ret_val = e1000_flash_cycle_init_ich8lan(hw); 1989 if (ret_val) 1990 goto out; 1991 1992 /* 1993 * Write a value 11 (block Erase) in Flash 1994 * Cycle field in hw flash control 1995 */ 1996 hsflctl.regval = E1000_READ_FLASH_REG16(hw, 1997 ICH_FLASH_HSFCTL); 1998 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 1999 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 2000 hsflctl.regval); 2001 2002 /* 2003 * Write the last 24 bits of an index within the 2004 * block into Flash Linear address field in Flash 2005 * Address. 2006 */ 2007 flash_linear_addr += (j * sector_size); 2008 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, 2009 flash_linear_addr); 2010 2011 ret_val = e1000_flash_cycle_ich8lan(hw, 2012 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 2013 if (ret_val == E1000_SUCCESS) 2014 break; 2015 2016 /* 2017 * Check if FCERR is set to 1. If 1, 2018 * clear it and try the whole sequence 2019 * a few more times else Done 2020 */ 2021 hsfsts.regval = E1000_READ_FLASH_REG16(hw, 2022 ICH_FLASH_HSFSTS); 2023 if (hsfsts.hsf_status.flcerr == 1) 2024 /* repeat for some time before giving up */ 2025 continue; 2026 else if (hsfsts.hsf_status.flcdone == 0) 2027 goto out; 2028 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 2029 } 2030 2031out: 2032 return ret_val; 2033} 2034 2035/** 2036 * e1000_valid_led_default_ich8lan - Set the default LED settings 2037 * @hw: pointer to the HW structure 2038 * @data: Pointer to the LED settings 2039 * 2040 * Reads the LED default settings from the NVM to data. If the NVM LED 2041 * settings is all 0's or F's, set the LED default to a valid LED default 2042 * setting. 2043 **/ 2044static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 2045{ 2046 s32 ret_val; 2047 2048 DEBUGFUNC("e1000_valid_led_default_ich8lan"); 2049 2050 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 2051 if (ret_val) { 2052 DEBUGOUT("NVM Read Error\n"); 2053 goto out; 2054 } 2055 2056 if (*data == ID_LED_RESERVED_0000 || 2057 *data == ID_LED_RESERVED_FFFF) 2058 *data = ID_LED_DEFAULT_ICH8LAN; 2059 2060out: 2061 return ret_val; 2062} 2063 2064/** 2065 * e1000_id_led_init_pchlan - store LED configurations 2066 * @hw: pointer to the HW structure 2067 * 2068 * PCH does not control LEDs via the LEDCTL register, rather it uses 2069 * the PHY LED configuration register. 2070 * 2071 * PCH also does not have an "always on" or "always off" mode which 2072 * complicates the ID feature. Instead of using the "on" mode to indicate 2073 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()), 2074 * use "link_up" mode. The LEDs will still ID on request if there is no 2075 * link based on logic in e1000_led_[on|off]_pchlan(). 2076 **/ 2077static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 2078{ 2079 struct e1000_mac_info *mac = &hw->mac; 2080 s32 ret_val; 2081 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 2082 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 2083 u16 data, i, temp, shift; 2084 2085 DEBUGFUNC("e1000_id_led_init_pchlan"); 2086 2087 /* Get default ID LED modes */ 2088 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 2089 if (ret_val) 2090 goto out; 2091 2092 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 2093 mac->ledctl_mode1 = mac->ledctl_default; 2094 mac->ledctl_mode2 = mac->ledctl_default; 2095 2096 for (i = 0; i < 4; i++) { 2097 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 2098 shift = (i * 5); 2099 switch (temp) { 2100 case ID_LED_ON1_DEF2: 2101 case ID_LED_ON1_ON2: 2102 case ID_LED_ON1_OFF2: 2103 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2104 mac->ledctl_mode1 |= (ledctl_on << shift); 2105 break; 2106 case ID_LED_OFF1_DEF2: 2107 case ID_LED_OFF1_ON2: 2108 case ID_LED_OFF1_OFF2: 2109 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 2110 mac->ledctl_mode1 |= (ledctl_off << shift); 2111 break; 2112 default: 2113 /* Do nothing */ 2114 break; 2115 } 2116 switch (temp) { 2117 case ID_LED_DEF1_ON2: 2118 case ID_LED_ON1_ON2: 2119 case ID_LED_OFF1_ON2: 2120 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2121 mac->ledctl_mode2 |= (ledctl_on << shift); 2122 break; 2123 case ID_LED_DEF1_OFF2: 2124 case ID_LED_ON1_OFF2: 2125 case ID_LED_OFF1_OFF2: 2126 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 2127 mac->ledctl_mode2 |= (ledctl_off << shift); 2128 break; 2129 default: 2130 /* Do nothing */ 2131 break; 2132 } 2133 } 2134 2135out: 2136 return ret_val; 2137} 2138 2139/** 2140 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 2141 * @hw: pointer to the HW structure 2142 * 2143 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 2144 * register, so the the bus width is hard coded. 2145 **/ 2146static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 2147{ 2148 struct e1000_bus_info *bus = &hw->bus; 2149 s32 ret_val; 2150 2151 DEBUGFUNC("e1000_get_bus_info_ich8lan"); 2152 2153 ret_val = e1000_get_bus_info_pcie_generic(hw); 2154 2155 /* 2156 * ICH devices are "PCI Express"-ish. They have 2157 * a configuration space, but do not contain 2158 * PCI Express Capability registers, so bus width 2159 * must be hardcoded. 2160 */ 2161 if (bus->width == e1000_bus_width_unknown) 2162 bus->width = e1000_bus_width_pcie_x1; 2163 2164 return ret_val; 2165} 2166 2167/** 2168 * e1000_reset_hw_ich8lan - Reset the hardware 2169 * @hw: pointer to the HW structure 2170 * 2171 * Does a full reset of the hardware which includes a reset of the PHY and 2172 * MAC. 2173 **/ 2174static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 2175{ 2176 u32 ctrl, icr, kab; 2177 s32 ret_val; 2178 2179 DEBUGFUNC("e1000_reset_hw_ich8lan"); 2180 2181 /* 2182 * Prevent the PCI-E bus from sticking if there is no TLP connection 2183 * on the last TLP read/write transaction when MAC is reset. 2184 */ 2185 ret_val = e1000_disable_pcie_master_generic(hw); 2186 if (ret_val) 2187 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2188 2189 DEBUGOUT("Masking off all interrupts\n"); 2190 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2191 2192 /* 2193 * Disable the Transmit and Receive units. Then delay to allow 2194 * any pending transactions to complete before we hit the MAC 2195 * with the global reset. 2196 */ 2197 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2198 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2199 E1000_WRITE_FLUSH(hw); 2200 2201 msec_delay(10); 2202 2203 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 2204 if (hw->mac.type == e1000_ich8lan) { 2205 /* Set Tx and Rx buffer allocation to 8k apiece. */ 2206 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); 2207 /* Set Packet Buffer Size to 16k. */ 2208 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); 2209 } 2210 2211 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2212 2213 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) { 2214 /* Clear PHY Reset Asserted bit */ 2215 if (hw->mac.type >= e1000_pchlan) { 2216 u32 status = E1000_READ_REG(hw, E1000_STATUS); 2217 E1000_WRITE_REG(hw, E1000_STATUS, status & 2218 ~E1000_STATUS_PHYRA); 2219 } 2220 2221 /* 2222 * PHY HW reset requires MAC CORE reset at the same 2223 * time to make sure the interface between MAC and the 2224 * external PHY is reset. 2225 */ 2226 ctrl |= E1000_CTRL_PHY_RST; 2227 } 2228 ret_val = e1000_acquire_swflag_ich8lan(hw); 2229 DEBUGOUT("Issuing a global reset to ich8lan\n"); 2230 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); 2231 msec_delay(20); 2232 2233 if (!ret_val) 2234 e1000_release_swflag_ich8lan(hw); 2235 2236 if (ctrl & E1000_CTRL_PHY_RST) 2237 ret_val = hw->phy.ops.get_cfg_done(hw); 2238 2239 if (hw->mac.type >= e1000_ich10lan) { 2240 e1000_lan_init_done_ich8lan(hw); 2241 } else { 2242 ret_val = e1000_get_auto_rd_done_generic(hw); 2243 if (ret_val) { 2244 /* 2245 * When auto config read does not complete, do not 2246 * return with an error. This can happen in situations 2247 * where there is no eeprom and prevents getting link. 2248 */ 2249 DEBUGOUT("Auto Read Done did not complete\n"); 2250 } 2251 } 2252 2253 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2254 icr = E1000_READ_REG(hw, E1000_ICR); 2255 2256 kab = E1000_READ_REG(hw, E1000_KABGTXD); 2257 kab |= E1000_KABGTXD_BGSQLBIAS; 2258 E1000_WRITE_REG(hw, E1000_KABGTXD, kab); 2259 2260 if (hw->mac.type == e1000_pchlan) 2261 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2262 2263 return ret_val; 2264} 2265 2266/** 2267 * e1000_init_hw_ich8lan - Initialize the hardware 2268 * @hw: pointer to the HW structure 2269 * 2270 * Prepares the hardware for transmit and receive by doing the following: 2271 * - initialize hardware bits 2272 * - initialize LED identification 2273 * - setup receive address registers 2274 * - setup flow control 2275 * - setup transmit descriptors 2276 * - clear statistics 2277 **/ 2278static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 2279{ 2280 struct e1000_mac_info *mac = &hw->mac; 2281 u32 ctrl_ext, txdctl, snoop; 2282 s32 ret_val; 2283 u16 i; 2284 2285 DEBUGFUNC("e1000_init_hw_ich8lan"); 2286 2287 e1000_initialize_hw_bits_ich8lan(hw); 2288 2289 /* Initialize identification LED */ 2290 ret_val = mac->ops.id_led_init(hw); 2291 if (ret_val) 2292 /* This is not fatal and we should not stop init due to this */ 2293 DEBUGOUT("Error initializing identification LED\n"); 2294 2295 /* Setup the receive address. */ 2296 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 2297 2298 /* Zero out the Multicast HASH table */ 2299 DEBUGOUT("Zeroing the MTA\n"); 2300 for (i = 0; i < mac->mta_reg_count; i++) 2301 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2302 2303 /* 2304 * The 82578 Rx buffer will stall if wakeup is enabled in host and 2305 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 2306 * Reset the phy after disabling host wakeup to reset the Rx buffer. 2307 */ 2308 if (hw->phy.type == e1000_phy_82578) { 2309 hw->phy.ops.read_reg(hw, BM_WUC, &i); 2310 ret_val = e1000_phy_hw_reset_ich8lan(hw); 2311 if (ret_val) 2312 return ret_val; 2313 } 2314 2315 /* Setup link and flow control */ 2316 ret_val = mac->ops.setup_link(hw); 2317 2318 /* Set the transmit descriptor write-back policy for both queues */ 2319 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2320 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2321 E1000_TXDCTL_FULL_TX_DESC_WB; 2322 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2323 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2324 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 2325 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2326 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 2327 E1000_TXDCTL_FULL_TX_DESC_WB; 2328 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 2329 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 2330 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); 2331 2332 /* 2333 * ICH8 has opposite polarity of no_snoop bits. 2334 * By default, we should use snoop behavior. 2335 */ 2336 if (mac->type == e1000_ich8lan) 2337 snoop = PCIE_ICH8_SNOOP_ALL; 2338 else 2339 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 2340 e1000_set_pcie_no_snoop_generic(hw, snoop); 2341 2342 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2343 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2344 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2345 2346 /* 2347 * Clear all of the statistics registers (clear on read). It is 2348 * important that we do this after we have tried to establish link 2349 * because the symbol error count will increment wildly if there 2350 * is no link. 2351 */ 2352 e1000_clear_hw_cntrs_ich8lan(hw); 2353 2354 return ret_val; 2355} 2356/** 2357 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 2358 * @hw: pointer to the HW structure 2359 * 2360 * Sets/Clears required hardware bits necessary for correctly setting up the 2361 * hardware for transmit and receive. 2362 **/ 2363static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 2364{ 2365 u32 reg; 2366 2367 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan"); 2368 2369 /* Extended Device Control */ 2370 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2371 reg |= (1 << 22); 2372 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 2373 if (hw->mac.type >= e1000_pchlan) 2374 reg |= E1000_CTRL_EXT_PHYPDEN; 2375 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2376 2377 /* Transmit Descriptor Control 0 */ 2378 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 2379 reg |= (1 << 22); 2380 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 2381 2382 /* Transmit Descriptor Control 1 */ 2383 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 2384 reg |= (1 << 22); 2385 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 2386 2387 /* Transmit Arbitration Control 0 */ 2388 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2389 if (hw->mac.type == e1000_ich8lan) 2390 reg |= (1 << 28) | (1 << 29); 2391 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 2392 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2393 2394 /* Transmit Arbitration Control 1 */ 2395 reg = E1000_READ_REG(hw, E1000_TARC(1)); 2396 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 2397 reg &= ~(1 << 28); 2398 else 2399 reg |= (1 << 28); 2400 reg |= (1 << 24) | (1 << 26) | (1 << 30); 2401 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 2402 2403 /* Device Status */ 2404 if (hw->mac.type == e1000_ich8lan) { 2405 reg = E1000_READ_REG(hw, E1000_STATUS); 2406 reg &= ~(1 << 31); 2407 E1000_WRITE_REG(hw, E1000_STATUS, reg); 2408 } 2409 2410 return; 2411} 2412 2413/** 2414 * e1000_setup_link_ich8lan - Setup flow control and link settings 2415 * @hw: pointer to the HW structure 2416 * 2417 * Determines which flow control settings to use, then configures flow 2418 * control. Calls the appropriate media-specific link configuration 2419 * function. Assuming the adapter has a valid link partner, a valid link 2420 * should be established. Assumes the hardware has previously been reset 2421 * and the transmitter and receiver are not enabled. 2422 **/ 2423static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 2424{ 2425 s32 ret_val = E1000_SUCCESS; 2426 2427 DEBUGFUNC("e1000_setup_link_ich8lan"); 2428 2429 if (hw->phy.ops.check_reset_block(hw)) 2430 goto out; 2431 2432 /* 2433 * ICH parts do not have a word in the NVM to determine 2434 * the default flow control setting, so we explicitly 2435 * set it to full. 2436 */ 2437 if (hw->fc.requested_mode == e1000_fc_default) 2438 hw->fc.requested_mode = e1000_fc_full; 2439 2440 /* 2441 * Save off the requested flow control mode for use later. Depending 2442 * on the link partner's capabilities, we may or may not use this mode. 2443 */ 2444 hw->fc.current_mode = hw->fc.requested_mode; 2445 2446 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 2447 hw->fc.current_mode); 2448 2449 /* Continue to configure the copper link. */ 2450 ret_val = hw->mac.ops.setup_physical_interface(hw); 2451 if (ret_val) 2452 goto out; 2453 2454 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 2455 if ((hw->phy.type == e1000_phy_82578) || 2456 (hw->phy.type == e1000_phy_82577)) { 2457 ret_val = hw->phy.ops.write_reg(hw, 2458 PHY_REG(BM_PORT_CTRL_PAGE, 27), 2459 hw->fc.pause_time); 2460 if (ret_val) 2461 goto out; 2462 } 2463 2464 ret_val = e1000_set_fc_watermarks_generic(hw); 2465 2466out: 2467 return ret_val; 2468} 2469 2470/** 2471 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 2472 * @hw: pointer to the HW structure 2473 * 2474 * Configures the kumeran interface to the PHY to wait the appropriate time 2475 * when polling the PHY, then call the generic setup_copper_link to finish 2476 * configuring the copper link. 2477 **/ 2478static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 2479{ 2480 u32 ctrl; 2481 s32 ret_val; 2482 u16 reg_data; 2483 2484 DEBUGFUNC("e1000_setup_copper_link_ich8lan"); 2485 2486 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2487 ctrl |= E1000_CTRL_SLU; 2488 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2489 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2490 2491 /* 2492 * Set the mac to wait the maximum time between each iteration 2493 * and increase the max iterations when polling the phy; 2494 * this fixes erroneous timeouts at 10Mbps. 2495 */ 2496 ret_val = e1000_write_kmrn_reg_generic(hw, 2497 E1000_KMRNCTRLSTA_TIMEOUTS, 2498 0xFFFF); 2499 if (ret_val) 2500 goto out; 2501 ret_val = e1000_read_kmrn_reg_generic(hw, 2502 E1000_KMRNCTRLSTA_INBAND_PARAM, 2503 ®_data); 2504 if (ret_val) 2505 goto out; 2506 reg_data |= 0x3F; 2507 ret_val = e1000_write_kmrn_reg_generic(hw, 2508 E1000_KMRNCTRLSTA_INBAND_PARAM, 2509 reg_data); 2510 if (ret_val) 2511 goto out; 2512 2513 switch (hw->phy.type) { 2514 case e1000_phy_igp_3: 2515 ret_val = e1000_copper_link_setup_igp(hw); 2516 if (ret_val) 2517 goto out; 2518 break; 2519 case e1000_phy_bm: 2520 case e1000_phy_82578: 2521 ret_val = e1000_copper_link_setup_m88(hw); 2522 if (ret_val) 2523 goto out; 2524 break; 2525 case e1000_phy_82577: 2526 ret_val = e1000_copper_link_setup_82577(hw); 2527 if (ret_val) 2528 goto out; 2529 break; 2530 case e1000_phy_ife: 2531 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 2532 ®_data); 2533 if (ret_val) 2534 goto out; 2535 2536 reg_data &= ~IFE_PMC_AUTO_MDIX; 2537 2538 switch (hw->phy.mdix) { 2539 case 1: 2540 reg_data &= ~IFE_PMC_FORCE_MDIX; 2541 break; 2542 case 2: 2543 reg_data |= IFE_PMC_FORCE_MDIX; 2544 break; 2545 case 0: 2546 default: 2547 reg_data |= IFE_PMC_AUTO_MDIX; 2548 break; 2549 } 2550 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 2551 reg_data); 2552 if (ret_val) 2553 goto out; 2554 break; 2555 default: 2556 break; 2557 } 2558 ret_val = e1000_setup_copper_link_generic(hw); 2559 2560out: 2561 return ret_val; 2562} 2563 2564/** 2565 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 2566 * @hw: pointer to the HW structure 2567 * @speed: pointer to store current link speed 2568 * @duplex: pointer to store the current link duplex 2569 * 2570 * Calls the generic get_speed_and_duplex to retrieve the current link 2571 * information and then calls the Kumeran lock loss workaround for links at 2572 * gigabit speeds. 2573 **/ 2574static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 2575 u16 *duplex) 2576{ 2577 s32 ret_val; 2578 2579 DEBUGFUNC("e1000_get_link_up_info_ich8lan"); 2580 2581 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 2582 if (ret_val) 2583 goto out; 2584 2585 if ((hw->mac.type == e1000_ich8lan) && 2586 (hw->phy.type == e1000_phy_igp_3) && 2587 (*speed == SPEED_1000)) { 2588 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 2589 } 2590 2591out: 2592 return ret_val; 2593} 2594 2595/** 2596 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 2597 * @hw: pointer to the HW structure 2598 * 2599 * Work-around for 82566 Kumeran PCS lock loss: 2600 * On link status change (i.e. PCI reset, speed change) and link is up and 2601 * speed is gigabit- 2602 * 0) if workaround is optionally disabled do nothing 2603 * 1) wait 1ms for Kumeran link to come up 2604 * 2) check Kumeran Diagnostic register PCS lock loss bit 2605 * 3) if not set the link is locked (all is good), otherwise... 2606 * 4) reset the PHY 2607 * 5) repeat up to 10 times 2608 * Note: this is only called for IGP3 copper when speed is 1gb. 2609 **/ 2610static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 2611{ 2612 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2613 u32 phy_ctrl; 2614 s32 ret_val = E1000_SUCCESS; 2615 u16 i, data; 2616 bool link; 2617 2618 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); 2619 2620 if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 2621 goto out; 2622 2623 /* 2624 * Make sure link is up before proceeding. If not just return. 2625 * Attempting this while link is negotiating fouled up link 2626 * stability 2627 */ 2628 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2629 if (!link) { 2630 ret_val = E1000_SUCCESS; 2631 goto out; 2632 } 2633 2634 for (i = 0; i < 10; i++) { 2635 /* read once to clear */ 2636 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2637 if (ret_val) 2638 goto out; 2639 /* and again to get new status */ 2640 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); 2641 if (ret_val) 2642 goto out; 2643 2644 /* check for PCS lock */ 2645 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 2646 ret_val = E1000_SUCCESS; 2647 goto out; 2648 } 2649 2650 /* Issue PHY reset */ 2651 hw->phy.ops.reset(hw); 2652 msec_delay_irq(5); 2653 } 2654 /* Disable GigE link negotiation */ 2655 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2656 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 2657 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2658 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2659 2660 /* 2661 * Call gig speed drop workaround on Gig disable before accessing 2662 * any PHY registers 2663 */ 2664 e1000_gig_downshift_workaround_ich8lan(hw); 2665 2666 /* unable to acquire PCS lock */ 2667 ret_val = -E1000_ERR_PHY; 2668 2669out: 2670 return ret_val; 2671} 2672 2673/** 2674 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 2675 * @hw: pointer to the HW structure 2676 * @state: boolean value used to set the current Kumeran workaround state 2677 * 2678 * If ICH8, set the current Kumeran workaround state (enabled - TRUE 2679 * /disabled - FALSE). 2680 **/ 2681void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 2682 bool state) 2683{ 2684 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2685 2686 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan"); 2687 2688 if (hw->mac.type != e1000_ich8lan) { 2689 DEBUGOUT("Workaround applies to ICH8 only.\n"); 2690 return; 2691 } 2692 2693 dev_spec->kmrn_lock_loss_workaround_enabled = state; 2694 2695 return; 2696} 2697 2698/** 2699 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 2700 * @hw: pointer to the HW structure 2701 * 2702 * Workaround for 82566 power-down on D3 entry: 2703 * 1) disable gigabit link 2704 * 2) write VR power-down enable 2705 * 3) read it back 2706 * Continue if successful, else issue LCD reset and repeat 2707 **/ 2708void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 2709{ 2710 u32 reg; 2711 u16 data; 2712 u8 retry = 0; 2713 2714 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan"); 2715 2716 if (hw->phy.type != e1000_phy_igp_3) 2717 goto out; 2718 2719 /* Try the workaround twice (if needed) */ 2720 do { 2721 /* Disable link */ 2722 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); 2723 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 2724 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 2725 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); 2726 2727 /* 2728 * Call gig speed drop workaround on Gig disable before 2729 * accessing any PHY registers 2730 */ 2731 if (hw->mac.type == e1000_ich8lan) 2732 e1000_gig_downshift_workaround_ich8lan(hw); 2733 2734 /* Write VR power-down enable */ 2735 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2736 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2737 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, 2738 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 2739 2740 /* Read it back and test */ 2741 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); 2742 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 2743 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 2744 break; 2745 2746 /* Issue PHY reset and repeat at most one more time */ 2747 reg = E1000_READ_REG(hw, E1000_CTRL); 2748 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); 2749 retry++; 2750 } while (retry); 2751 2752out: 2753 return; 2754} 2755 2756/** 2757 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working 2758 * @hw: pointer to the HW structure 2759 * 2760 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 2761 * LPLU, Gig disable, MDIC PHY reset): 2762 * 1) Set Kumeran Near-end loopback 2763 * 2) Clear Kumeran Near-end loopback 2764 * Should only be called for ICH8[m] devices with IGP_3 Phy. 2765 **/ 2766void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 2767{ 2768 s32 ret_val = E1000_SUCCESS; 2769 u16 reg_data; 2770 2771 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan"); 2772 2773 if ((hw->mac.type != e1000_ich8lan) || 2774 (hw->phy.type != e1000_phy_igp_3)) 2775 goto out; 2776 2777 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 2778 ®_data); 2779 if (ret_val) 2780 goto out; 2781 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 2782 ret_val = e1000_write_kmrn_reg_generic(hw, 2783 E1000_KMRNCTRLSTA_DIAG_OFFSET, 2784 reg_data); 2785 if (ret_val) 2786 goto out; 2787 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 2788 ret_val = e1000_write_kmrn_reg_generic(hw, 2789 E1000_KMRNCTRLSTA_DIAG_OFFSET, 2790 reg_data); 2791out: 2792 return; 2793} 2794 2795/** 2796 * e1000_disable_gig_wol_ich8lan - disable gig during WoL 2797 * @hw: pointer to the HW structure 2798 * 2799 * During S0 to Sx transition, it is possible the link remains at gig 2800 * instead of negotiating to a lower speed. Before going to Sx, set 2801 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation 2802 * to a lower speed. 2803 * 2804 * Should only be called for applicable parts. 2805 **/ 2806void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw) 2807{ 2808 u32 phy_ctrl; 2809 2810 switch (hw->mac.type) { 2811 case e1000_ich9lan: 2812 case e1000_ich10lan: 2813 case e1000_pchlan: 2814 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); 2815 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 2816 E1000_PHY_CTRL_GBE_DISABLE; 2817 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); 2818 2819 /* Workaround SWFLAG unexpectedly set during S0->Sx */ 2820 if (hw->mac.type == e1000_pchlan) 2821 usec_delay(500); 2822 default: 2823 break; 2824 } 2825 2826 return; 2827} 2828 2829/** 2830 * e1000_cleanup_led_ich8lan - Restore the default LED operation 2831 * @hw: pointer to the HW structure 2832 * 2833 * Return the LED back to the default configuration. 2834 **/ 2835static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 2836{ 2837 s32 ret_val = E1000_SUCCESS; 2838 2839 DEBUGFUNC("e1000_cleanup_led_ich8lan"); 2840 2841 if (hw->phy.type == e1000_phy_ife) 2842 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2843 0); 2844 else 2845 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 2846 2847 return ret_val; 2848} 2849 2850/** 2851 * e1000_led_on_ich8lan - Turn LEDs on 2852 * @hw: pointer to the HW structure 2853 * 2854 * Turn on the LEDs. 2855 **/ 2856static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 2857{ 2858 s32 ret_val = E1000_SUCCESS; 2859 2860 DEBUGFUNC("e1000_led_on_ich8lan"); 2861 2862 if (hw->phy.type == e1000_phy_ife) 2863 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 2864 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 2865 else 2866 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2867 2868 return ret_val; 2869} 2870 2871/** 2872 * e1000_led_off_ich8lan - Turn LEDs off 2873 * @hw: pointer to the HW structure 2874 * 2875 * Turn off the LEDs. 2876 **/ 2877static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 2878{ 2879 s32 ret_val = E1000_SUCCESS; 2880 2881 DEBUGFUNC("e1000_led_off_ich8lan"); 2882 2883 if (hw->phy.type == e1000_phy_ife) 2884 ret_val = hw->phy.ops.write_reg(hw, 2885 IFE_PHY_SPECIAL_CONTROL_LED, 2886 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 2887 else 2888 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2889 2890 return ret_val; 2891} 2892 2893/** 2894 * e1000_setup_led_pchlan - Configures SW controllable LED 2895 * @hw: pointer to the HW structure 2896 * 2897 * This prepares the SW controllable LED for use. 2898 **/ 2899static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 2900{ 2901 DEBUGFUNC("e1000_setup_led_pchlan"); 2902 2903 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 2904 (u16)hw->mac.ledctl_mode1); 2905} 2906 2907/** 2908 * e1000_cleanup_led_pchlan - Restore the default LED operation 2909 * @hw: pointer to the HW structure 2910 * 2911 * Return the LED back to the default configuration. 2912 **/ 2913static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 2914{ 2915 DEBUGFUNC("e1000_cleanup_led_pchlan"); 2916 2917 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 2918 (u16)hw->mac.ledctl_default); 2919} 2920 2921/** 2922 * e1000_led_on_pchlan - Turn LEDs on 2923 * @hw: pointer to the HW structure 2924 * 2925 * Turn on the LEDs. 2926 **/ 2927static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 2928{ 2929 u16 data = (u16)hw->mac.ledctl_mode2; 2930 u32 i, led; 2931 2932 DEBUGFUNC("e1000_led_on_pchlan"); 2933 2934 /* 2935 * If no link, then turn LED on by setting the invert bit 2936 * for each LED that's mode is "link_up" in ledctl_mode2. 2937 */ 2938 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 2939 for (i = 0; i < 3; i++) { 2940 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 2941 if ((led & E1000_PHY_LED0_MODE_MASK) != 2942 E1000_LEDCTL_MODE_LINK_UP) 2943 continue; 2944 if (led & E1000_PHY_LED0_IVRT) 2945 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 2946 else 2947 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 2948 } 2949 } 2950 2951 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 2952} 2953 2954/** 2955 * e1000_led_off_pchlan - Turn LEDs off 2956 * @hw: pointer to the HW structure 2957 * 2958 * Turn off the LEDs. 2959 **/ 2960static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 2961{ 2962 u16 data = (u16)hw->mac.ledctl_mode1; 2963 u32 i, led; 2964 2965 DEBUGFUNC("e1000_led_off_pchlan"); 2966 2967 /* 2968 * If no link, then turn LED off by clearing the invert bit 2969 * for each LED that's mode is "link_up" in ledctl_mode1. 2970 */ 2971 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 2972 for (i = 0; i < 3; i++) { 2973 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 2974 if ((led & E1000_PHY_LED0_MODE_MASK) != 2975 E1000_LEDCTL_MODE_LINK_UP) 2976 continue; 2977 if (led & E1000_PHY_LED0_IVRT) 2978 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 2979 else 2980 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 2981 } 2982 } 2983 2984 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 2985} 2986 2987/** 2988 * e1000_get_cfg_done_ich8lan - Read config done bit 2989 * @hw: pointer to the HW structure 2990 * 2991 * Read the management control register for the config done bit for 2992 * completion status. NOTE: silicon which is EEPROM-less will fail trying 2993 * to read the config done bit, so an error is *ONLY* logged and returns 2994 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 2995 * would not be able to be reset or change link. 2996 **/ 2997static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 2998{ 2999 s32 ret_val = E1000_SUCCESS; 3000 u32 bank = 0; 3001 3002 if (hw->mac.type >= e1000_pchlan) { 3003 u32 status = E1000_READ_REG(hw, E1000_STATUS); 3004 3005 if (status & E1000_STATUS_PHYRA) { 3006 E1000_WRITE_REG(hw, E1000_STATUS, status & 3007 ~E1000_STATUS_PHYRA); 3008 } else 3009 DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); 3010 } 3011 3012 e1000_get_cfg_done_generic(hw); 3013 3014 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 3015 if ((hw->mac.type != e1000_ich10lan) && 3016 (hw->mac.type != e1000_pchlan)) { 3017 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 3018 (hw->phy.type == e1000_phy_igp_3)) { 3019 e1000_phy_init_script_igp3(hw); 3020 } 3021 } else { 3022 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 3023 /* Maybe we should do a basic PHY config */ 3024 DEBUGOUT("EEPROM not present\n"); 3025 ret_val = -E1000_ERR_CONFIG; 3026 } 3027 } 3028 3029 return ret_val; 3030} 3031 3032/** 3033 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 3034 * @hw: pointer to the HW structure 3035 * 3036 * In the case of a PHY power down to save power, or to turn off link during a 3037 * driver unload, or wake on lan is not enabled, remove the link. 3038 **/ 3039static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 3040{ 3041 /* If the management interface is not enabled, then power down */ 3042 if (!(hw->mac.ops.check_mng_mode(hw) || 3043 hw->phy.ops.check_reset_block(hw))) 3044 e1000_power_down_phy_copper(hw); 3045 3046 return; 3047} 3048 3049/** 3050 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 3051 * @hw: pointer to the HW structure 3052 * 3053 * Clears hardware counters specific to the silicon family and calls 3054 * clear_hw_cntrs_generic to clear all general purpose counters. 3055 **/ 3056static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 3057{ 3058 u16 phy_data; 3059 3060 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan"); 3061 3062 e1000_clear_hw_cntrs_base_generic(hw); 3063 3064 E1000_READ_REG(hw, E1000_ALGNERRC); 3065 E1000_READ_REG(hw, E1000_RXERRC); 3066 E1000_READ_REG(hw, E1000_TNCRS); 3067 E1000_READ_REG(hw, E1000_CEXTERR); 3068 E1000_READ_REG(hw, E1000_TSCTC); 3069 E1000_READ_REG(hw, E1000_TSCTFC); 3070 3071 E1000_READ_REG(hw, E1000_MGTPRC); 3072 E1000_READ_REG(hw, E1000_MGTPDC); 3073 E1000_READ_REG(hw, E1000_MGTPTC); 3074 3075 E1000_READ_REG(hw, E1000_IAC); 3076 E1000_READ_REG(hw, E1000_ICRXOC); 3077 3078 /* Clear PHY statistics registers */ 3079 if ((hw->phy.type == e1000_phy_82578) || 3080 (hw->phy.type == e1000_phy_82577)) { 3081 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 3082 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 3083 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 3084 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 3085 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 3086 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 3087 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 3088 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 3089 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 3090 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 3091 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 3092 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 3093 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 3094 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 3095 } 3096} 3097 3098