e1000_82575.c revision 218909
11558Srgrimes/****************************************************************************** 21558Srgrimes 31558Srgrimes Copyright (c) 2001-2010, Intel Corporation 41558Srgrimes All rights reserved. 51558Srgrimes 61558Srgrimes Redistribution and use in source and binary forms, with or without 71558Srgrimes modification, are permitted provided that the following conditions are met: 81558Srgrimes 91558Srgrimes 1. Redistributions of source code must retain the above copyright notice, 101558Srgrimes this list of conditions and the following disclaimer. 111558Srgrimes 121558Srgrimes 2. Redistributions in binary form must reproduce the above copyright 131558Srgrimes notice, this list of conditions and the following disclaimer in the 141558Srgrimes documentation and/or other materials provided with the distribution. 151558Srgrimes 161558Srgrimes 3. Neither the name of the Intel Corporation nor the names of its 171558Srgrimes contributors may be used to endorse or promote products derived from 181558Srgrimes this software without specific prior written permission. 191558Srgrimes 201558Srgrimes THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 211558Srgrimes AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221558Srgrimes IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231558Srgrimes ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 241558Srgrimes LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251558Srgrimes CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261558Srgrimes SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271558Srgrimes INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281558Srgrimes CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291558Srgrimes ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 301558Srgrimes POSSIBILITY OF SUCH DAMAGE. 311558Srgrimes 321558Srgrimes******************************************************************************/ 331558Srgrimes/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 218909 2011-02-21 09:01:34Z brucec $*/ 3437663Scharnier 351558Srgrimes/* 361558Srgrimes * 82575EB Gigabit Network Connection 372999Swollman * 82575EB Gigabit Backplane Connection 381558Srgrimes * 82575GB Gigabit Network Connection 39105267Scharnier * 82575GB Gigabit Network Connection 401558Srgrimes * 82576 Gigabit Network Connection 4137663Scharnier * 82576 Quad Port Gigabit Mezzanine Adapter 42105267Scharnier */ 4337663Scharnier 441558Srgrimes#include "e1000_api.h" 45105267Scharnier 46105267Scharnierstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 47105267Scharnierstatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 481558Srgrimesstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 49192934Srmacklemstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 50192934Srmacklemstatic void e1000_release_phy_82575(struct e1000_hw *hw); 51192934Srmacklemstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 521558Srgrimesstatic void e1000_release_nvm_82575(struct e1000_hw *hw); 531558Srgrimesstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw); 54192934Srmacklemstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 551558Srgrimesstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 561558Srgrimes u16 *duplex); 571558Srgrimesstatic s32 e1000_init_hw_82575(struct e1000_hw *hw); 58109363Smbrstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 591558Srgrimesstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 6074462Salfred u16 *data); 6174462Salfredstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw); 629336Sdfrstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw); 63192934Srmacklemstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 6483653Speter u32 offset, u16 *data); 651558Srgrimesstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 66192934Srmacklem u32 offset, u16 data); 67192934Srmacklemstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 681558Srgrimes bool active); 691558Srgrimesstatic s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 701558Srgrimes bool active); 7137663Scharnierstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 721558Srgrimes bool active); 731558Srgrimesstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 74149433Spjdstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 75103949Smikestatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 761558Srgrimesstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 771558Srgrimes u32 offset, u16 data); 781558Srgrimesstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 791558Srgrimesstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 801558Srgrimesstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 811558Srgrimes u16 *speed, u16 *duplex); 821558Srgrimesstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 831558Srgrimesstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 84158857Srodrigcstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw); 851558Srgrimesstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 861558Srgrimesstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 871558Srgrimesstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw); 881558Srgrimesstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 891558Srgrimesstatic void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 901558Srgrimesstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 911558Srgrimesstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 921558Srgrimesstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 931558Srgrimesstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 941558Srgrimesstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 95194880Sdfrstatic s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 96194880Sdfr u16 offset); 971558Srgrimesstatic s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 981558Srgrimes u16 offset); 991558Srgrimesstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 1001558Srgrimesstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 1011558Srgrimes 1021558Srgrimesstatic const u16 e1000_82580_rxpbs_table[] = 1031558Srgrimes { 36, 72, 144, 1, 2, 4, 8, 16, 1041558Srgrimes 35, 70, 140 }; 1051558Srgrimes#define E1000_82580_RXPBS_TABLE_SIZE \ 1061558Srgrimes (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 1071558Srgrimes 1089336Sdfr 1091558Srgrimes/** 1101558Srgrimes * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 1111558Srgrimes * @hw: pointer to the HW structure 1121558Srgrimes * 1131558Srgrimes * Called to determine if the I2C pins are being used for I2C or as an 1141558Srgrimes * external MDIO interface since the two options are mutually exclusive. 1151558Srgrimes **/ 1161558Srgrimesstatic bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 11727447Sdfr{ 118184588Sdfr u32 reg = 0; 119184588Sdfr bool ext_mdio = FALSE; 1201558Srgrimes 1211558Srgrimes DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 1221558Srgrimes 1231558Srgrimes switch (hw->mac.type) { 1241558Srgrimes case e1000_82575: 12574462Salfred case e1000_82576: 12675801Siedowse reg = E1000_READ_REG(hw, E1000_MDIC); 12742144Sdfr ext_mdio = !!(reg & E1000_MDIC_DEST); 1281558Srgrimes break; 1291558Srgrimes case e1000_82580: 1301558Srgrimes case e1000_i350: 13174462Salfred reg = E1000_READ_REG(hw, E1000_MDICNFG); 1321558Srgrimes ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 1331558Srgrimes break; 1341558Srgrimes default: 1351558Srgrimes break; 1361558Srgrimes } 1371558Srgrimes return ext_mdio; 1381558Srgrimes} 1391558Srgrimes 1401558Srgrimes/** 1411558Srgrimes * e1000_init_phy_params_82575 - Init PHY func ptrs. 1421558Srgrimes * @hw: pointer to the HW structure 1431558Srgrimes **/ 14475641Siedowsestatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 1457401Swpaul{ 1461558Srgrimes struct e1000_phy_info *phy = &hw->phy; 1471558Srgrimes s32 ret_val = E1000_SUCCESS; 1489336Sdfr u32 ctrl_ext; 1491558Srgrimes 1501558Srgrimes DEBUGFUNC("e1000_init_phy_params_82575"); 1511558Srgrimes 1521558Srgrimes if (hw->phy.media_type != e1000_media_type_copper) { 1539336Sdfr phy->type = e1000_phy_none; 1549336Sdfr goto out; 1559336Sdfr } 1569336Sdfr 157184588Sdfr phy->ops.power_up = e1000_power_up_phy_copper; 158184588Sdfr phy->ops.power_down = e1000_power_down_phy_copper_82575; 1599336Sdfr 1609336Sdfr phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1611558Srgrimes phy->reset_delay_us = 100; 16292882Simp 16392882Simp phy->ops.acquire = e1000_acquire_phy_82575; 16492882Simp phy->ops.check_reset_block = e1000_check_reset_block_generic; 16592882Simp phy->ops.commit = e1000_phy_sw_reset_generic; 16692882Simp phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 16792882Simp phy->ops.release = e1000_release_phy_82575; 16875801Siedowse 16992882Simp ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 170172827Smatteo 17175635Siedowse if (e1000_sgmii_active_82575(hw)) { 17292882Simp phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 17392882Simp ctrl_ext |= E1000_CTRL_I2C_ENA; 17492882Simp } else { 17592882Simp phy->ops.reset = e1000_phy_hw_reset_generic; 17692882Simp ctrl_ext &= ~E1000_CTRL_I2C_ENA; 17792882Simp } 17892882Simp 17992882Simp E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 18092882Simp e1000_reset_mdicnfg_82580(hw); 18192882Simp 18292882Simp if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 18392882Simp phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 18492882Simp phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 18592882Simp } else if (hw->mac.type >= e1000_82580) { 18692882Simp phy->ops.read_reg = e1000_read_phy_reg_82580; 18792882Simp phy->ops.write_reg = e1000_write_phy_reg_82580; 18892882Simp } else { 18992882Simp phy->ops.read_reg = e1000_read_phy_reg_igp; 19092882Simp phy->ops.write_reg = e1000_write_phy_reg_igp; 19192882Simp } 19292882Simp 19375754Siedowse /* Set phy->phy_addr and phy->id. */ 19475801Siedowse ret_val = e1000_get_phy_id_82575(hw); 19592882Simp 19692882Simp /* Verify phy id and set remaining function pointers */ 19792882Simp switch (phy->id) { 19892882Simp case I347AT4_E_PHY_ID: 199216587Scharnier case M88E1112_E_PHY_ID: 200100117Salfred case M88E1111_I_PHY_ID: 20175801Siedowse phy->type = e1000_phy_m88; 20275801Siedowse phy->ops.check_polarity = e1000_check_polarity_m88; 20375801Siedowse phy->ops.get_info = e1000_get_phy_info_m88; 20492882Simp if (phy->id == I347AT4_E_PHY_ID || 20592882Simp phy->id == M88E1112_E_PHY_ID) 20692882Simp phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 20792882Simp else 208100117Salfred phy->ops.get_cable_length = e1000_get_cable_length_m88; 209216587Scharnier phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 21092882Simp break; 21192882Simp case IGP03E1000_E_PHY_ID: 21292882Simp case IGP04E1000_E_PHY_ID: 2131558Srgrimes phy->type = e1000_phy_igp_3; 2141558Srgrimes phy->ops.check_polarity = e1000_check_polarity_igp; 2151558Srgrimes phy->ops.get_info = e1000_get_phy_info_igp; 2161558Srgrimes phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 217166440Spjd phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 218166440Spjd phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 219172827Smatteo phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 22072650Sgreen break; 22191354Sdd case I82580_I_PHY_ID: 22272650Sgreen case I350_I_PHY_ID: 2231558Srgrimes phy->type = e1000_phy_82580; 22472650Sgreen phy->ops.check_polarity = e1000_check_polarity_82577; 22572650Sgreen phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; 2261558Srgrimes phy->ops.get_cable_length = e1000_get_cable_length_82577; 22725087Sdfr phy->ops.get_info = e1000_get_phy_info_82577; 2289336Sdfr phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 229172827Smatteo phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 2309336Sdfr break; 231121767Speter default: 23275754Siedowse ret_val = -E1000_ERR_PHY; 233172827Smatteo goto out; 23474462Salfred } 235172827Smatteo 236172827Smatteoout: 2371558Srgrimes return ret_val; 23874462Salfred} 23974462Salfred 240192934Srmacklem/** 241192934Srmacklem * e1000_init_nvm_params_82575 - Init NVM func ptrs. 242192934Srmacklem * @hw: pointer to the HW structure 243192934Srmacklem **/ 244192934Srmacklemstatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 245149433Spjd{ 24675801Siedowse struct e1000_nvm_info *nvm = &hw->nvm; 2471558Srgrimes u32 eecd = E1000_READ_REG(hw, E1000_EECD); 2481558Srgrimes u16 size; 24983653Speter 2501558Srgrimes DEBUGFUNC("e1000_init_nvm_params_82575"); 2511558Srgrimes 2521558Srgrimes size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 25375801Siedowse E1000_EECD_SIZE_EX_SHIFT); 254100336Sjoerg /* 25574462Salfred * Added to a constant, "size" becomes the left-shift value 256184588Sdfr * for setting word_size. 2571558Srgrimes */ 2581558Srgrimes size += NVM_WORD_SIZE_BASE_SHIFT; 2591558Srgrimes 26092882Simp nvm->word_size = 1 << size; 2611558Srgrimes 2621558Srgrimes nvm->opcode_bits = 8; 2631558Srgrimes nvm->delay_usec = 1; 2641558Srgrimes switch (nvm->override) { 2651558Srgrimes case e1000_nvm_override_spi_large: 2661558Srgrimes nvm->page_size = 32; 2671558Srgrimes nvm->address_bits = 16; 2681558Srgrimes break; 2691558Srgrimes case e1000_nvm_override_spi_small: 2701558Srgrimes nvm->page_size = 8; 2711558Srgrimes nvm->address_bits = 8; 2721558Srgrimes break; 2731558Srgrimes default: 274216587Scharnier nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 2751558Srgrimes nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 27675754Siedowse break; 277172827Smatteo } 278172827Smatteo 279172827Smatteo nvm->type = e1000_nvm_eeprom_spi; 280149433Spjd 281172827Smatteo if (nvm->word_size == (1 << 15)) { 282172827Smatteo nvm->page_size = 128; 283109363Smbr } 2841558Srgrimes 28574462Salfred 286150214Spjd /* Function Pointers */ 287149433Spjd nvm->ops.acquire = e1000_acquire_nvm_82575; 288149433Spjd if (nvm->word_size < (1 << 15)) { 289149433Spjd nvm->ops.read = e1000_read_nvm_eerd; 290149433Spjd } else { 291149433Spjd nvm->ops.read = e1000_read_nvm_spi; 29274462Salfred } 29374462Salfred nvm->ops.release = e1000_release_nvm_82575; 29474462Salfred nvm->ops.valid_led_default = e1000_valid_led_default_82575; 29574462Salfred switch (hw->mac.type) { 29674462Salfred case e1000_82580: 29774462Salfred nvm->ops.validate = e1000_validate_nvm_checksum_82580; 2982999Swollman nvm->ops.update = e1000_update_nvm_checksum_82580; 299192993Srmacklem break; 3001558Srgrimes case e1000_i350: 30125087Sdfr nvm->ops.validate = e1000_validate_nvm_checksum_i350; 30225087Sdfr nvm->ops.update = e1000_update_nvm_checksum_i350; 30325087Sdfr break; 304192993Srmacklem default: 305192934Srmacklem nvm->ops.validate = e1000_validate_nvm_checksum_generic; 306192934Srmacklem nvm->ops.update = e1000_update_nvm_checksum_generic; 3079336Sdfr } 3089336Sdfr nvm->ops.write = e1000_write_nvm_spi; 3099336Sdfr 3109336Sdfr return E1000_SUCCESS; 3119336Sdfr} 3129336Sdfr 3138688Sphk/** 3148688Sphk * e1000_init_mac_params_82575 - Init MAC func ptrs. 3158688Sphk * @hw: pointer to the HW structure 31631656Sguido **/ 317121767Speterstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 31831656Sguido{ 319126572Sbms struct e1000_mac_info *mac = &hw->mac; 320126572Sbms struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 321126572Sbms u32 ctrl_ext = 0; 322126572Sbms 323126572Sbms DEBUGFUNC("e1000_init_mac_params_82575"); 324126572Sbms 325172827Smatteo /* Set media type */ 326126572Sbms /* 327172827Smatteo * The 82575 uses bits 22:23 for link mode. The mode can be changed 328172827Smatteo * based on the EEPROM. We cannot rely upon device ID. There 329172827Smatteo * is no distinguishable difference between fiber and internal 330172827Smatteo * SerDes mode on the 82575. There can be an external PHY attached 331172827Smatteo * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 332172827Smatteo */ 333172827Smatteo hw->phy.media_type = e1000_media_type_copper; 334172827Smatteo dev_spec->sgmii_active = FALSE; 335172827Smatteo 336172827Smatteo ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 337172827Smatteo switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 338172827Smatteo case E1000_CTRL_EXT_LINK_MODE_SGMII: 339172827Smatteo dev_spec->sgmii_active = TRUE; 340172827Smatteo break; 341172827Smatteo case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 342172827Smatteo case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 343172827Smatteo hw->phy.media_type = e1000_media_type_internal_serdes; 344172827Smatteo break; 345172827Smatteo default: 346172827Smatteo break; 347172827Smatteo } 3481558Srgrimes 34937663Scharnier /* Set mta register count */ 3501558Srgrimes mac->mta_reg_count = 128; 351192934Srmacklem /* Set uta register count */ 352192934Srmacklem mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 353192993Srmacklem /* Set rar entry count */ 354192934Srmacklem mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 355192934Srmacklem if (mac->type == e1000_82576) 356192934Srmacklem mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 357192934Srmacklem if (mac->type == e1000_82580) 358192934Srmacklem mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 359192934Srmacklem if (mac->type == e1000_i350) { 360192934Srmacklem mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 361192934Srmacklem /* Enable EEE default settings for i350 */ 362192934Srmacklem dev_spec->eee_disable = FALSE; 363192934Srmacklem } 364192934Srmacklem 365192934Srmacklem /* Set if part includes ASF firmware */ 366192934Srmacklem mac->asf_firmware_present = TRUE; 367192934Srmacklem /* FWSM register */ 368192934Srmacklem mac->has_fwsm = TRUE; 369192934Srmacklem /* ARC supported; valid only if manageability features are enabled. */ 370192934Srmacklem mac->arc_subsystem_valid = 3711558Srgrimes (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 3721558Srgrimes ? TRUE : FALSE; 3731558Srgrimes 3741558Srgrimes /* Function pointers */ 3751558Srgrimes 376166440Spjd /* bus type/speed/width */ 377166440Spjd mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 378166440Spjd /* reset */ 379166440Spjd if (mac->type >= e1000_82580) 3801558Srgrimes mac->ops.reset_hw = e1000_reset_hw_82580; 3811558Srgrimes else 38237663Scharnier mac->ops.reset_hw = e1000_reset_hw_82575; 3831558Srgrimes /* hw initialization */ 3841558Srgrimes mac->ops.init_hw = e1000_init_hw_82575; 38537663Scharnier /* link setup */ 3861558Srgrimes mac->ops.setup_link = e1000_setup_link_generic; 3871558Srgrimes /* physical interface link setup */ 38837663Scharnier mac->ops.setup_physical_interface = 3891558Srgrimes (hw->phy.media_type == e1000_media_type_copper) 3901558Srgrimes ? e1000_setup_copper_link_82575 3911558Srgrimes : e1000_setup_serdes_link_82575; 3921558Srgrimes /* physical interface shutdown */ 3931558Srgrimes mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 39475754Siedowse /* physical interface power up */ 39574462Salfred mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 396164394Srodrigc /* check for link */ 397149433Spjd mac->ops.check_for_link = e1000_check_for_link_82575; 398149433Spjd /* receive address register setting */ 399149433Spjd mac->ops.rar_set = e1000_rar_set_generic; 400194880Sdfr /* read mac address */ 401194880Sdfr mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 402109363Smbr /* configure collision distance */ 403109363Smbr mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 40424759Sguido /* multicast address update */ 40583687Speter mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 40683687Speter /* writing VFTA */ 40783687Speter mac->ops.write_vfta = e1000_write_vfta_generic; 40824759Sguido /* clearing VFTA */ 40924759Sguido mac->ops.clear_vfta = e1000_clear_vfta_generic; 41024759Sguido /* ID LED init */ 41124330Sguido mac->ops.id_led_init = e1000_id_led_init_generic; 412126572Sbms /* blink LED */ 413172827Smatteo mac->ops.blink_led = e1000_blink_led_generic; 414172827Smatteo /* setup LED */ 415172827Smatteo mac->ops.setup_led = e1000_setup_led_generic; 416172827Smatteo /* cleanup LED */ 417172827Smatteo mac->ops.cleanup_led = e1000_cleanup_led_generic; 418172827Smatteo /* turn on/off LED */ 419172827Smatteo mac->ops.led_on = e1000_led_on_generic; 420172827Smatteo mac->ops.led_off = e1000_led_off_generic; 421172827Smatteo /* clear hardware counters */ 422172827Smatteo mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 423172827Smatteo /* link info */ 424172827Smatteo mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 425172827Smatteo 426172827Smatteo /* set lan id for port to determine which phy lock to use */ 427172827Smatteo hw->mac.ops.set_lan_id(hw); 428172827Smatteo 429172827Smatteo return E1000_SUCCESS; 430172827Smatteo} 431172827Smatteo 432172827Smatteo/** 433172827Smatteo * e1000_init_function_pointers_82575 - Init func ptrs. 434172827Smatteo * @hw: pointer to the HW structure 435172827Smatteo * 436172827Smatteo * Called to initialize all function pointers and parameters. 437172827Smatteo **/ 438172827Smatteovoid e1000_init_function_pointers_82575(struct e1000_hw *hw) 439172827Smatteo{ 440172827Smatteo DEBUGFUNC("e1000_init_function_pointers_82575"); 441172827Smatteo 442172827Smatteo hw->mac.ops.init_params = e1000_init_mac_params_82575; 443172827Smatteo hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 444172827Smatteo hw->phy.ops.init_params = e1000_init_phy_params_82575; 445172827Smatteo hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 446172827Smatteo} 447172827Smatteo 448126572Sbms/** 449172827Smatteo * e1000_acquire_phy_82575 - Acquire rights to access PHY 45074462Salfred * @hw: pointer to the HW structure 451172827Smatteo * 45274462Salfred * Acquire access rights to the correct PHY. 45374462Salfred **/ 454172827Smatteostatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 455172827Smatteo{ 456172827Smatteo u16 mask = E1000_SWFW_PHY0_SM; 457172827Smatteo 458172827Smatteo DEBUGFUNC("e1000_acquire_phy_82575"); 459172827Smatteo 460172827Smatteo if (hw->bus.func == E1000_FUNC_1) 461172827Smatteo mask = E1000_SWFW_PHY1_SM; 462172827Smatteo else if (hw->bus.func == E1000_FUNC_2) 46374462Salfred mask = E1000_SWFW_PHY2_SM; 464172827Smatteo else if (hw->bus.func == E1000_FUNC_3) 46574462Salfred mask = E1000_SWFW_PHY3_SM; 46674462Salfred 46774462Salfred return e1000_acquire_swfw_sync_82575(hw, mask); 4681558Srgrimes} 4691558Srgrimes 47075754Siedowse/** 47175754Siedowse * e1000_release_phy_82575 - Release rights to access PHY 47275754Siedowse * @hw: pointer to the HW structure 47375754Siedowse * 47475754Siedowse * A wrapper to release access rights to the correct PHY. 47575754Siedowse **/ 47675754Siedowsestatic void e1000_release_phy_82575(struct e1000_hw *hw) 47775754Siedowse{ 47875754Siedowse u16 mask = E1000_SWFW_PHY0_SM; 47975754Siedowse 48075754Siedowse DEBUGFUNC("e1000_release_phy_82575"); 48175754Siedowse 48275754Siedowse if (hw->bus.func == E1000_FUNC_1) 48375754Siedowse mask = E1000_SWFW_PHY1_SM; 48475754Siedowse else if (hw->bus.func == E1000_FUNC_2) 48575754Siedowse mask = E1000_SWFW_PHY2_SM; 48675754Siedowse else if (hw->bus.func == E1000_FUNC_3) 48775754Siedowse mask = E1000_SWFW_PHY3_SM; 48875754Siedowse 48975754Siedowse e1000_release_swfw_sync_82575(hw, mask); 490172827Smatteo} 491172827Smatteo 492172827Smatteo/** 493172827Smatteo * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 494172827Smatteo * @hw: pointer to the HW structure 495172827Smatteo * @offset: register offset to be read 496172827Smatteo * @data: pointer to the read data 497172827Smatteo * 498172827Smatteo * Reads the PHY register at offset using the serial gigabit media independent 499172827Smatteo * interface and stores the retrieved information in data. 500172827Smatteo **/ 501172827Smatteostatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 502172827Smatteo u16 *data) 503172827Smatteo{ 504172827Smatteo s32 ret_val = -E1000_ERR_PARAM; 505172827Smatteo 506172827Smatteo DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 507172827Smatteo 508172827Smatteo if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 509172827Smatteo DEBUGOUT1("PHY Address %u is out of range\n", offset); 510172827Smatteo goto out; 511172827Smatteo } 512172827Smatteo 513172827Smatteo ret_val = hw->phy.ops.acquire(hw); 514172827Smatteo if (ret_val) 515172827Smatteo goto out; 516172827Smatteo 517172827Smatteo ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 518172827Smatteo 519172827Smatteo hw->phy.ops.release(hw); 520172827Smatteo 521172827Smatteoout: 522172827Smatteo return ret_val; 523172827Smatteo} 524172827Smatteo 525172827Smatteo/** 526172827Smatteo * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 527172827Smatteo * @hw: pointer to the HW structure 528172827Smatteo * @offset: register offset to write to 529172827Smatteo * @data: data to write at register offset 530172827Smatteo * 531172827Smatteo * Writes the data to PHY register at the offset using the serial gigabit 532172827Smatteo * media independent interface. 533172827Smatteo **/ 534172827Smatteostatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 535172827Smatteo u16 data) 536172827Smatteo{ 537172827Smatteo s32 ret_val = -E1000_ERR_PARAM; 538172827Smatteo 539172827Smatteo DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 540172827Smatteo 541172827Smatteo if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 542172827Smatteo DEBUGOUT1("PHY Address %d is out of range\n", offset); 543172827Smatteo goto out; 544172827Smatteo } 545172827Smatteo 546172827Smatteo ret_val = hw->phy.ops.acquire(hw); 547172827Smatteo if (ret_val) 548172827Smatteo goto out; 549172827Smatteo 550172827Smatteo ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 551172827Smatteo 552172827Smatteo hw->phy.ops.release(hw); 553172827Smatteo 554172827Smatteoout: 555172827Smatteo return ret_val; 556172827Smatteo} 557172827Smatteo 558172827Smatteo/** 559172827Smatteo * e1000_get_phy_id_82575 - Retrieve PHY addr and id 560172827Smatteo * @hw: pointer to the HW structure 561172827Smatteo * 562172827Smatteo * Retrieves the PHY address and ID for both PHY's which do and do not use 563172827Smatteo * sgmi interface. 564172827Smatteo **/ 565172827Smatteostatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 566172827Smatteo{ 567172827Smatteo struct e1000_phy_info *phy = &hw->phy; 568172827Smatteo s32 ret_val = E1000_SUCCESS; 569172827Smatteo u16 phy_id; 570172827Smatteo u32 ctrl_ext; 571172827Smatteo u32 mdic; 572172827Smatteo 573172827Smatteo DEBUGFUNC("e1000_get_phy_id_82575"); 574172827Smatteo 575172827Smatteo /* 576172827Smatteo * For SGMII PHYs, we try the list of possible addresses until 577172827Smatteo * we find one that works. For non-SGMII PHYs 578172827Smatteo * (e.g. integrated copper PHYs), an address of 1 should 579172827Smatteo * work. The result of this function should mean phy->phy_addr 580172827Smatteo * and phy->id are set correctly. 581172827Smatteo */ 582172827Smatteo if (!e1000_sgmii_active_82575(hw)) { 583172827Smatteo phy->addr = 1; 584172827Smatteo ret_val = e1000_get_phy_id(hw); 585172827Smatteo goto out; 586172827Smatteo } 587172827Smatteo 588172827Smatteo if (e1000_sgmii_uses_mdio_82575(hw)) { 589172827Smatteo switch (hw->mac.type) { 590172827Smatteo case e1000_82575: 591172827Smatteo case e1000_82576: 592172827Smatteo mdic = E1000_READ_REG(hw, E1000_MDIC); 593172827Smatteo mdic &= E1000_MDIC_PHY_MASK; 594172827Smatteo phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 595172827Smatteo break; 596172827Smatteo case e1000_82580: 597172827Smatteo case e1000_i350: 598172827Smatteo mdic = E1000_READ_REG(hw, E1000_MDICNFG); 599172827Smatteo mdic &= E1000_MDICNFG_PHY_MASK; 600172827Smatteo phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 601172827Smatteo break; 602172827Smatteo default: 603172827Smatteo ret_val = -E1000_ERR_PHY; 604172827Smatteo goto out; 605172827Smatteo break; 606172827Smatteo } 607172827Smatteo ret_val = e1000_get_phy_id(hw); 608172827Smatteo goto out; 609172827Smatteo } 610172827Smatteo 611172827Smatteo /* Power on sgmii phy if it is disabled */ 612172827Smatteo ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 613172827Smatteo E1000_WRITE_REG(hw, E1000_CTRL_EXT, 614172827Smatteo ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 615172827Smatteo E1000_WRITE_FLUSH(hw); 616172827Smatteo msec_delay(300); 617172827Smatteo 618172827Smatteo /* 619172827Smatteo * The address field in the I2CCMD register is 3 bits and 0 is invalid. 620172827Smatteo * Therefore, we need to test 1-7 621172827Smatteo */ 622172827Smatteo for (phy->addr = 1; phy->addr < 8; phy->addr++) { 623172827Smatteo ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 624172827Smatteo if (ret_val == E1000_SUCCESS) { 625172827Smatteo DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 626172827Smatteo phy_id, 627173056Ssimon phy->addr); 628172827Smatteo /* 629172827Smatteo * At the time of this writing, The M88 part is 630172827Smatteo * the only supported SGMII PHY product. 631172827Smatteo */ 632172827Smatteo if (phy_id == M88_VENDOR) 633172827Smatteo break; 634172827Smatteo } else { 635172827Smatteo DEBUGOUT1("PHY address %u was unreadable\n", 636172827Smatteo phy->addr); 637172827Smatteo } 638172827Smatteo } 639172827Smatteo 640172827Smatteo /* A valid PHY type couldn't be found. */ 641172827Smatteo if (phy->addr == 8) { 642172827Smatteo phy->addr = 0; 643172827Smatteo ret_val = -E1000_ERR_PHY; 644172827Smatteo } else { 645172827Smatteo ret_val = e1000_get_phy_id(hw); 646172827Smatteo } 647172827Smatteo 648172827Smatteo /* restore previous sfp cage power state */ 649172827Smatteo E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 650172827Smatteo 651172827Smatteoout: 652172827Smatteo return ret_val; 653172827Smatteo} 654172827Smatteo 655172827Smatteo/** 656172827Smatteo * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 657172827Smatteo * @hw: pointer to the HW structure 658172827Smatteo * 659172827Smatteo * Resets the PHY using the serial gigabit media independent interface. 660172827Smatteo **/ 661172827Smatteostatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 662172827Smatteo{ 663172827Smatteo s32 ret_val = E1000_SUCCESS; 664172827Smatteo 665172827Smatteo DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 666172827Smatteo 667172827Smatteo /* 668172827Smatteo * This isn't a TRUE "hard" reset, but is the only reset 669172827Smatteo * available to us at this time. 670172827Smatteo */ 671172827Smatteo 672172827Smatteo DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 673172827Smatteo 674172827Smatteo if (!(hw->phy.ops.write_reg)) 675194880Sdfr goto out; 676172827Smatteo 677172827Smatteo /* 678194880Sdfr * SFP documentation requires the following to configure the SPF module 679172827Smatteo * to work on SGMII. No further documentation is given. 680172827Smatteo */ 681194880Sdfr ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 682172827Smatteo if (ret_val) 683172827Smatteo goto out; 684194880Sdfr 685172827Smatteo ret_val = hw->phy.ops.commit(hw); 686172827Smatteo 687172827Smatteoout: 688172827Smatteo return ret_val; 689172827Smatteo} 690172827Smatteo 691172827Smatteo/** 692172827Smatteo * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 693172827Smatteo * @hw: pointer to the HW structure 694172827Smatteo * @active: TRUE to enable LPLU, FALSE to disable 695172827Smatteo * 696172827Smatteo * Sets the LPLU D0 state according to the active flag. When 697172827Smatteo * activating LPLU this function also disables smart speed 698172827Smatteo * and vice versa. LPLU will not be activated unless the 699172827Smatteo * device autonegotiation advertisement meets standards of 700172827Smatteo * either 10 or 10/100 or 10/100/1000 at all duplexes. 701172827Smatteo * This is a function pointer entry point only called by 702172827Smatteo * PHY setup routines. 703172827Smatteo **/ 704172827Smatteostatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 705172827Smatteo{ 706172827Smatteo struct e1000_phy_info *phy = &hw->phy; 707172827Smatteo s32 ret_val = E1000_SUCCESS; 708172827Smatteo u16 data; 709172827Smatteo 710172827Smatteo DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 711172827Smatteo 712172827Smatteo if (!(hw->phy.ops.read_reg)) 713172827Smatteo goto out; 714172827Smatteo 715172827Smatteo ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 716172827Smatteo if (ret_val) 717172827Smatteo goto out; 718172827Smatteo 719172827Smatteo if (active) { 720172827Smatteo data |= IGP02E1000_PM_D0_LPLU; 721172827Smatteo ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 722194880Sdfr data); 723194880Sdfr if (ret_val) 724172827Smatteo goto out; 725172827Smatteo 726172827Smatteo /* When LPLU is enabled, we should disable SmartSpeed */ 727172827Smatteo ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 728172827Smatteo &data); 7291558Srgrimes data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7301558Srgrimes ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 73137663Scharnier data); 732216587Scharnier if (ret_val) 73337663Scharnier goto out; 73437663Scharnier } else { 735192993Srmacklem data &= ~IGP02E1000_PM_D0_LPLU; 736172827Smatteo ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 73737663Scharnier data); 73837663Scharnier /* 73937663Scharnier * LPLU and SmartSpeed are mutually exclusive. LPLU is used 7401558Srgrimes * during Dx states where the power conservation is most 7411558Srgrimes * important. During driver activity we should enable 7421558Srgrimes * SmartSpeed, so performance is maintained. 7431558Srgrimes */ 744216587Scharnier if (phy->smart_speed == e1000_smart_speed_on) { 7451558Srgrimes ret_val = phy->ops.read_reg(hw, 7461558Srgrimes IGP01E1000_PHY_PORT_CONFIG, 7471558Srgrimes &data); 7489336Sdfr if (ret_val) 7491558Srgrimes goto out; 7501558Srgrimes 75174462Salfred data |= IGP01E1000_PSCFR_SMART_SPEED; 75274462Salfred ret_val = phy->ops.write_reg(hw, 75374462Salfred IGP01E1000_PHY_PORT_CONFIG, 7549336Sdfr data); 755194880Sdfr if (ret_val) 75628911Sguido goto out; 7579336Sdfr } else if (phy->smart_speed == e1000_smart_speed_off) { 7581558Srgrimes ret_val = phy->ops.read_reg(hw, 7599336Sdfr IGP01E1000_PHY_PORT_CONFIG, 7609336Sdfr &data); 76174462Salfred if (ret_val) 76274462Salfred goto out; 76374462Salfred 76475635Siedowse data &= ~IGP01E1000_PSCFR_SMART_SPEED; 76574462Salfred ret_val = phy->ops.write_reg(hw, 76674462Salfred IGP01E1000_PHY_PORT_CONFIG, 76775635Siedowse data); 76874462Salfred if (ret_val) 76974462Salfred goto out; 77074462Salfred } 77174462Salfred } 77274462Salfred 77374462Salfredout: 77474462Salfred return ret_val; 77574462Salfred} 77674462Salfred 7771558Srgrimes/** 7781558Srgrimes * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 779121556Speter * @hw: pointer to the HW structure 78037663Scharnier * @active: TRUE to enable LPLU, FALSE to disable 7811558Srgrimes * 782194880Sdfr * Sets the LPLU D0 state according to the active flag. When 7839336Sdfr * activating LPLU this function also disables smart speed 78431656Sguido * and vice versa. LPLU will not be activated unless the 78531656Sguido * device autonegotiation advertisement meets standards of 78674462Salfred * either 10 or 10/100 or 10/100/1000 at all duplexes. 7871558Srgrimes * This is a function pointer entry point only called by 7881558Srgrimes * PHY setup routines. 7891558Srgrimes **/ 790121556Speterstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 79131656Sguido{ 79274462Salfred struct e1000_phy_info *phy = &hw->phy; 7931558Srgrimes s32 ret_val = E1000_SUCCESS; 7941558Srgrimes u16 data; 7951558Srgrimes 7961558Srgrimes DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 7971558Srgrimes 7981558Srgrimes data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 7999336Sdfr 8009336Sdfr if (active) { 8011558Srgrimes data |= E1000_82580_PM_D0_LPLU; 80251968Salfred 8031558Srgrimes /* When LPLU is enabled, we should disable SmartSpeed */ 8049336Sdfr data &= ~E1000_82580_PM_SPD; 80574462Salfred } else { 8061558Srgrimes data &= ~E1000_82580_PM_D0_LPLU; 8071558Srgrimes 80831656Sguido /* 80937663Scharnier * LPLU and SmartSpeed are mutually exclusive. LPLU is used 81074462Salfred * during Dx states where the power conservation is most 8111558Srgrimes * important. During driver activity we should enable 81237663Scharnier * SmartSpeed, so performance is maintained. 81328911Sguido */ 8141558Srgrimes if (phy->smart_speed == e1000_smart_speed_on) { 8151558Srgrimes data |= E1000_82580_PM_SPD; 8161558Srgrimes } else if (phy->smart_speed == e1000_smart_speed_off) { 8179336Sdfr data &= ~E1000_82580_PM_SPD; 8181558Srgrimes } 8199336Sdfr } 8209336Sdfr 8211558Srgrimes E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 82274462Salfred return ret_val; 82374462Salfred} 82474462Salfred 82528911Sguido/** 826121556Speter * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 82728911Sguido * @hw: pointer to the HW structure 82837663Scharnier * @active: boolean used to enable/disable lplu 82928911Sguido * 83028911Sguido * Success returns 0, Failure returns 1 83128911Sguido * 8329336Sdfr * The low power link up (lplu) state is set to the power management level D3 8339336Sdfr * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 8349336Sdfr * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 8359336Sdfr * is used during Dx states where the power conservation is most important. 8369336Sdfr * During driver activity, SmartSpeed should be enabled so performance is 8371558Srgrimes * maintained. 83823681Speter **/ 8399336Sdfrs32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 8401558Srgrimes{ 84137663Scharnier struct e1000_phy_info *phy = &hw->phy; 842121556Speter s32 ret_val = E1000_SUCCESS; 8431558Srgrimes u16 data; 84437663Scharnier 8459336Sdfr DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 8461558Srgrimes 8471558Srgrimes data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 848184588Sdfr 849184588Sdfr if (!active) { 850121556Speter data &= ~E1000_82580_PM_D3_LPLU; 851121556Speter /* 85237663Scharnier * LPLU and SmartSpeed are mutually exclusive. LPLU is used 85374462Salfred * during Dx states where the power conservation is most 85474462Salfred * important. During driver activity we should enable 8551558Srgrimes * SmartSpeed, so performance is maintained. 85674462Salfred */ 8571558Srgrimes if (phy->smart_speed == e1000_smart_speed_on) { 85837663Scharnier data |= E1000_82580_PM_SPD; 859121767Speter } else if (phy->smart_speed == e1000_smart_speed_off) { 86031656Sguido data &= ~E1000_82580_PM_SPD; 86131656Sguido } 86274462Salfred } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 86331656Sguido (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 8641558Srgrimes (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 86531656Sguido data |= E1000_82580_PM_D3_LPLU; 86631656Sguido /* When LPLU is enabled, we should disable SmartSpeed */ 86774462Salfred data &= ~E1000_82580_PM_SPD; 86831656Sguido } 86928911Sguido 870121556Speter E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 871121556Speter return ret_val; 87237663Scharnier} 8739336Sdfr 8741558Srgrimes/** 875194880Sdfr * e1000_acquire_nvm_82575 - Request for access to EEPROM 876121556Speter * @hw: pointer to the HW structure 87737663Scharnier * 878121767Speter * Acquire the necessary semaphores for exclusive access to the EEPROM. 87931656Sguido * Set the EEPROM access request bit and wait for EEPROM access grant bit. 88031656Sguido * Return successful if access grant bit set, else clear the request for 88174462Salfred * EEPROM access and return -E1000_ERR_NVM (-1). 8821558Srgrimes **/ 883194880Sdfrstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 8849336Sdfr{ 88531656Sguido s32 ret_val; 88631656Sguido 88774462Salfred DEBUGFUNC("e1000_acquire_nvm_82575"); 8881558Srgrimes 8891558Srgrimes ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 8901558Srgrimes if (ret_val) 891121556Speter goto out; 89231656Sguido 89374462Salfred ret_val = e1000_acquire_nvm_generic(hw); 8941558Srgrimes 8951558Srgrimes if (ret_val) 8961558Srgrimes e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 89751968Salfred 89851968Salfredout: 89951968Salfred return ret_val; 90074462Salfred} 90151968Salfred 902121556Speter/** 90337663Scharnier * e1000_release_nvm_82575 - Release exclusive access to EEPROM 90474462Salfred * @hw: pointer to the HW structure 90575635Siedowse * 90675635Siedowse * Stop any current commands to the EEPROM and clear the EEPROM request bit, 907121767Speter * then release the semaphores acquired. 90831656Sguido **/ 90931656Sguidostatic void e1000_release_nvm_82575(struct e1000_hw *hw) 91074462Salfred{ 9111558Srgrimes DEBUGFUNC("e1000_release_nvm_82575"); 912194880Sdfr 9139336Sdfr e1000_release_nvm_generic(hw); 91431656Sguido e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 91531656Sguido} 91674462Salfred 9171558Srgrimes/** 9181558Srgrimes * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 9191558Srgrimes * @hw: pointer to the HW structure 920121556Speter * @mask: specifies which semaphore to acquire 92137663Scharnier * 92274462Salfred * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 92375635Siedowse * will also specify which port we're acquiring the lock for. 92475635Siedowse **/ 925121767Speterstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 92631656Sguido{ 92731656Sguido u32 swfw_sync; 92874462Salfred u32 swmask = mask; 9291558Srgrimes u32 fwmask = mask << 16; 930194880Sdfr s32 ret_val = E1000_SUCCESS; 931121556Speter s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 932121556Speter 933121556Speter DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 934100117Salfred 935121767Speter while (i < timeout) { 93631656Sguido if (e1000_get_hw_semaphore_generic(hw)) { 93731656Sguido ret_val = -E1000_ERR_SWFW_SYNC; 93874462Salfred goto out; 9391558Srgrimes } 9401558Srgrimes 9411558Srgrimes swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 9421558Srgrimes if (!(swfw_sync & (fwmask | swmask))) 9431558Srgrimes break; 9441558Srgrimes 9451558Srgrimes /* 9461558Srgrimes * Firmware currently using resource (fwmask) 9471558Srgrimes * or other software thread using resource (swmask) 9481558Srgrimes */ 9491558Srgrimes e1000_put_hw_semaphore_generic(hw); 950216587Scharnier msec_delay_irq(5); 9511558Srgrimes i++; 952194880Sdfr } 9531558Srgrimes 9541558Srgrimes if (i == timeout) { 9551558Srgrimes DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 9569336Sdfr ret_val = -E1000_ERR_SWFW_SYNC; 9571558Srgrimes goto out; 9581558Srgrimes } 959216587Scharnier 9601558Srgrimes swfw_sync |= swmask; 96192806Sobrien E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 9629336Sdfr 963184588Sdfr e1000_put_hw_semaphore_generic(hw); 9641558Srgrimes 9651558Srgrimesout: 9661558Srgrimes return ret_val; 9679336Sdfr} 9689336Sdfr 9699336Sdfr/** 9709336Sdfr * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 9719336Sdfr * @hw: pointer to the HW structure 9729336Sdfr * @mask: specifies which semaphore to acquire 9739336Sdfr * 9749336Sdfr * Release the SW/FW semaphore used to access the PHY or NVM. The mask 9759336Sdfr * will also specify which port we're releasing the lock for. 976184588Sdfr **/ 977184588Sdfrstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 978184588Sdfr{ 979184588Sdfr u32 swfw_sync; 980184588Sdfr 981184588Sdfr DEBUGFUNC("e1000_release_swfw_sync_82575"); 982184588Sdfr 983184588Sdfr while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 984184588Sdfr /* Empty */ 985184588Sdfr 986184588Sdfr swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 987184588Sdfr swfw_sync &= ~mask; 988184588Sdfr E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 989184588Sdfr 9909336Sdfr e1000_put_hw_semaphore_generic(hw); 9919336Sdfr} 9921558Srgrimes 9931558Srgrimes/** 9941558Srgrimes * e1000_get_cfg_done_82575 - Read config done bit 995216587Scharnier * @hw: pointer to the HW structure 9961558Srgrimes * 9971558Srgrimes * Read the management control register for the config done bit for 9981558Srgrimes * completion status. NOTE: silicon which is EEPROM-less will fail trying 9991558Srgrimes * to read the config done bit, so an error is *ONLY* logged and returns 10001558Srgrimes * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 10011558Srgrimes * would not be able to be reset or change link. 10021558Srgrimes **/ 10031558Srgrimesstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 10041558Srgrimes{ 10051558Srgrimes s32 timeout = PHY_CFG_TIMEOUT; 10061558Srgrimes s32 ret_val = E1000_SUCCESS; 1007194880Sdfr u32 mask = E1000_NVM_CFG_DONE_PORT_0; 10081558Srgrimes 10091558Srgrimes DEBUGFUNC("e1000_get_cfg_done_82575"); 1010194880Sdfr 10111558Srgrimes if (hw->bus.func == E1000_FUNC_1) 10121558Srgrimes mask = E1000_NVM_CFG_DONE_PORT_1; 10131558Srgrimes else if (hw->bus.func == E1000_FUNC_2) 10141558Srgrimes mask = E1000_NVM_CFG_DONE_PORT_2; 10151558Srgrimes else if (hw->bus.func == E1000_FUNC_3) 10161558Srgrimes mask = E1000_NVM_CFG_DONE_PORT_3; 10171558Srgrimes while (timeout) { 10181558Srgrimes if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 10191558Srgrimes break; 10201558Srgrimes msec_delay(1); 10211558Srgrimes timeout--; 10221558Srgrimes } 1023216587Scharnier if (!timeout) 10241558Srgrimes DEBUGOUT("MNG configuration cycle has not completed.\n"); 10251558Srgrimes 10261558Srgrimes /* If EEPROM is not marked present, init the PHY manually */ 10279336Sdfr if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 10289336Sdfr (hw->phy.type == e1000_phy_igp_3)) 10291558Srgrimes e1000_phy_init_script_igp3(hw); 10309336Sdfr 10319336Sdfr return ret_val; 10329336Sdfr} 10331558Srgrimes 10341558Srgrimes/** 10351558Srgrimes * e1000_get_link_up_info_82575 - Get link speed/duplex info 1036100117Salfred * @hw: pointer to the HW structure 1037100117Salfred * @speed: stores the current speed 10381558Srgrimes * @duplex: stores the current duplex 10391558Srgrimes * 10401558Srgrimes * This is a wrapper function, if using the serial gigabit media independent 1041100117Salfred * interface, use PCS to retrieve the link speed and duplex information. 10421558Srgrimes * Otherwise, use the generic function to get the link speed and duplex info. 10431558Srgrimes **/ 10441558Srgrimesstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 10459336Sdfr u16 *duplex) 10461558Srgrimes{ 10471558Srgrimes s32 ret_val; 10481558Srgrimes 10491558Srgrimes DEBUGFUNC("e1000_get_link_up_info_82575"); 10509336Sdfr 10511558Srgrimes if (hw->phy.media_type != e1000_media_type_copper) 10521558Srgrimes ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 10531558Srgrimes duplex); 10541558Srgrimes else 10551558Srgrimes ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 10561558Srgrimes duplex); 10571558Srgrimes 10581558Srgrimes return ret_val; 1059216587Scharnier} 1060216587Scharnier 10611558Srgrimes/** 10621558Srgrimes * e1000_check_for_link_82575 - Check for link 10631558Srgrimes * @hw: pointer to the HW structure 10641558Srgrimes * 10651558Srgrimes * If sgmii is enabled, then use the pcs register to determine link, otherwise 10661558Srgrimes * use the generic interface for determining link. 10671558Srgrimes **/ 10681558Srgrimesstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw) 10691558Srgrimes{ 1070100117Salfred s32 ret_val; 10711558Srgrimes u16 speed, duplex; 10721558Srgrimes 10731558Srgrimes DEBUGFUNC("e1000_check_for_link_82575"); 10741558Srgrimes 1075194880Sdfr if (hw->phy.media_type != e1000_media_type_copper) { 10761558Srgrimes ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 10771558Srgrimes &duplex); 10781558Srgrimes /* 10791558Srgrimes * Use this flag to determine if link needs to be checked or 10801558Srgrimes * not. If we have link clear the flag so that we do not 1081100117Salfred * continue to check for link. 1082100117Salfred */ 1083100117Salfred hw->mac.get_link_status = !hw->mac.serdes_has_link; 1084100117Salfred } else { 1085194880Sdfr ret_val = e1000_check_for_copper_link_generic(hw); 1086100117Salfred } 1087100117Salfred 10881558Srgrimes return ret_val; 10891558Srgrimes} 10901558Srgrimes 10911558Srgrimes/** 10921558Srgrimes * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 10931558Srgrimes * @hw: pointer to the HW structure 10941558Srgrimes **/ 109574462Salfredstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 10968871Srgrimes{ 1097194880Sdfr u32 reg; 10981558Srgrimes 10991558Srgrimes DEBUGFUNC("e1000_power_up_serdes_link_82575"); 11001558Srgrimes 11011558Srgrimes if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 11021558Srgrimes !e1000_sgmii_active_82575(hw)) 11038871Srgrimes return; 1104194880Sdfr 11051558Srgrimes /* Enable PCS to turn on link */ 11061558Srgrimes reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 11071558Srgrimes reg |= E1000_PCS_CFG_PCS_EN; 11081558Srgrimes E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 11091558Srgrimes 11101558Srgrimes /* Power up the laser */ 11111558Srgrimes reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 11121558Srgrimes reg &= ~E1000_CTRL_EXT_SDP3_DATA; 11131558Srgrimes E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 11141558Srgrimes 11151558Srgrimes /* flush the write to verify completion */ 1116100117Salfred E1000_WRITE_FLUSH(hw); 11171558Srgrimes msec_delay(1); 11181558Srgrimes} 11191558Srgrimes 11201558Srgrimes/** 11211558Srgrimes * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1122100117Salfred * @hw: pointer to the HW structure 1123216587Scharnier * @speed: stores the current speed 1124100117Salfred * @duplex: stores the current duplex 1125100117Salfred * 1126100117Salfred * Using the physical coding sub-layer (PCS), retrieve the current speed and 1127100117Salfred * duplex, then store the values in the pointers provided. 1128100117Salfred **/ 1129100117Salfredstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1130216587Scharnier u16 *speed, u16 *duplex) 1131100117Salfred{ 1132100117Salfred struct e1000_mac_info *mac = &hw->mac; 1133100117Salfred u32 pcs; 1134100117Salfred 1135100117Salfred DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 113696622Siedowse 113796622Siedowse /* Set up defaults for the return values of this function */ 11381558Srgrimes mac->serdes_has_link = FALSE; 11391558Srgrimes *speed = 0; 11401558Srgrimes *duplex = 0; 1141166440Spjd 11421558Srgrimes /* 1143166440Spjd * Read the PCS Status register for link state. For non-copper mode, 1144216587Scharnier * the status register is not accurate. The PCS status register is 11451558Srgrimes * used instead. 11461558Srgrimes */ 11471558Srgrimes pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 11481558Srgrimes 11491558Srgrimes /* 1150166440Spjd * The link up bit determines when link is up on autoneg. The sync ok 115172650Sgreen * gets set once both sides sync up and agree upon link. Stable link 11521558Srgrimes * can be determined by checking for both link up and link sync ok 1153166440Spjd */ 11541558Srgrimes if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1155192934Srmacklem mac->serdes_has_link = TRUE; 11561558Srgrimes 11571558Srgrimes /* Detect and store PCS speed */ 11581558Srgrimes if (pcs & E1000_PCS_LSTS_SPEED_1000) { 115937663Scharnier *speed = SPEED_1000; 11601558Srgrimes } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 11611558Srgrimes *speed = SPEED_100; 11621558Srgrimes } else { 11631558Srgrimes *speed = SPEED_10; 11641558Srgrimes } 11651558Srgrimes 11661558Srgrimes /* Detect and store PCS duplex */ 11671558Srgrimes if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 11681558Srgrimes *duplex = FULL_DUPLEX; 11691558Srgrimes } else { 11701558Srgrimes *duplex = HALF_DUPLEX; 11711558Srgrimes } 11721558Srgrimes } 11731558Srgrimes 1174192934Srmacklem return E1000_SUCCESS; 11751558Srgrimes} 11761558Srgrimes 1177192934Srmacklem/** 1178192934Srmacklem * e1000_shutdown_serdes_link_82575 - Remove link during power down 1179192934Srmacklem * @hw: pointer to the HW structure 1180192934Srmacklem * 1181192934Srmacklem * In the case of serdes shut down sfp and PCS on driver unload 1182192934Srmacklem * when management pass thru is not enabled. 1183192934Srmacklem **/ 1184192934Srmacklemvoid e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1185192934Srmacklem{ 1186192934Srmacklem u32 reg; 1187192934Srmacklem 1188192934Srmacklem DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1189192934Srmacklem 1190192934Srmacklem if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1191192934Srmacklem !e1000_sgmii_active_82575(hw)) 1192192934Srmacklem return; 1193192934Srmacklem 11941558Srgrimes if (!e1000_enable_mng_pass_thru(hw)) { 11951558Srgrimes /* Disable PCS to turn off link */ 11961558Srgrimes reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 11971558Srgrimes reg &= ~E1000_PCS_CFG_PCS_EN; 11981558Srgrimes E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1199194880Sdfr 12001558Srgrimes /* shutdown the laser */ 12011558Srgrimes reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 12021558Srgrimes reg |= E1000_CTRL_EXT_SDP3_DATA; 12031558Srgrimes E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 12041558Srgrimes 12051558Srgrimes /* flush the write to verify completion */ 12061558Srgrimes E1000_WRITE_FLUSH(hw); 12071558Srgrimes msec_delay(1); 12081558Srgrimes } 120937663Scharnier 12101558Srgrimes return; 12111558Srgrimes} 12121558Srgrimes 12131558Srgrimes/** 12141558Srgrimes * e1000_reset_hw_82575 - Reset hardware 12151558Srgrimes * @hw: pointer to the HW structure 12161558Srgrimes * 12171558Srgrimes * This resets the hardware into a known state. 12181558Srgrimes **/ 1219192934Srmacklemstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1220192934Srmacklem{ 1221192934Srmacklem u32 ctrl; 1222192934Srmacklem s32 ret_val; 1223192934Srmacklem 1224192934Srmacklem DEBUGFUNC("e1000_reset_hw_82575"); 1225192934Srmacklem 12261558Srgrimes /* 12271558Srgrimes * Prevent the PCI-E bus from sticking if there is no TLP connection 12281558Srgrimes * on the last TLP read/write transaction when MAC is reset. 122937663Scharnier */ 12301558Srgrimes ret_val = e1000_disable_pcie_master_generic(hw); 12311558Srgrimes if (ret_val) { 12321558Srgrimes DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1233192934Srmacklem } 1234192934Srmacklem 1235192934Srmacklem /* set the completion timeout for interface */ 12361558Srgrimes ret_val = e1000_set_pcie_completion_timeout(hw); 12371558Srgrimes if (ret_val) { 12381558Srgrimes DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1239192934Srmacklem } 1240192934Srmacklem 1241192934Srmacklem DEBUGOUT("Masking off all interrupts\n"); 1242192934Srmacklem E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1243192934Srmacklem 1244192934Srmacklem E1000_WRITE_REG(hw, E1000_RCTL, 0); 1245192934Srmacklem E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1246192934Srmacklem E1000_WRITE_FLUSH(hw); 1247192934Srmacklem 1248192934Srmacklem msec_delay(10); 1249192934Srmacklem 1250192934Srmacklem ctrl = E1000_READ_REG(hw, E1000_CTRL); 1251192934Srmacklem 1252192934Srmacklem DEBUGOUT("Issuing a global reset to MAC\n"); 12531558Srgrimes E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1254192934Srmacklem 1255192934Srmacklem ret_val = e1000_get_auto_rd_done_generic(hw); 1256192934Srmacklem if (ret_val) { 1257192934Srmacklem /* 1258192934Srmacklem * When auto config read does not complete, do not 1259192934Srmacklem * return with an error. This can happen in situations 1260192934Srmacklem * where there is no eeprom and prevents getting link. 1261192934Srmacklem */ 1262192934Srmacklem DEBUGOUT("Auto Read Done did not complete\n"); 1263192934Srmacklem } 1264192934Srmacklem 1265192934Srmacklem /* If EEPROM is not present, run manual init scripts */ 1266192934Srmacklem if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1267192934Srmacklem e1000_reset_init_script_82575(hw); 1268192934Srmacklem 1269192934Srmacklem /* Clear any pending interrupt events. */ 1270192934Srmacklem E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1271192934Srmacklem E1000_READ_REG(hw, E1000_ICR); 1272192934Srmacklem 1273192934Srmacklem /* Install any alternate MAC address into RAR0 */ 1274192934Srmacklem ret_val = e1000_check_alt_mac_addr_generic(hw); 1275192934Srmacklem 1276192934Srmacklem return ret_val; 1277192934Srmacklem} 1278192934Srmacklem 1279192934Srmacklem/** 1280192934Srmacklem * e1000_init_hw_82575 - Initialize hardware 1281192934Srmacklem * @hw: pointer to the HW structure 1282192934Srmacklem * 1283192934Srmacklem * This inits the hardware readying it for operation. 1284192934Srmacklem **/ 1285192934Srmacklemstatic s32 e1000_init_hw_82575(struct e1000_hw *hw) 1286192934Srmacklem{ 1287192934Srmacklem struct e1000_mac_info *mac = &hw->mac; 1288192934Srmacklem s32 ret_val; 12891558Srgrimes u16 i, rar_count = mac->rar_entry_count; 1290192934Srmacklem 12911558Srgrimes DEBUGFUNC("e1000_init_hw_82575"); 1292192934Srmacklem 1293192934Srmacklem /* Initialize identification LED */ 12941558Srgrimes ret_val = mac->ops.id_led_init(hw); 12951558Srgrimes if (ret_val) { 12961558Srgrimes DEBUGOUT("Error initializing identification LED\n"); 12971558Srgrimes /* This is not fatal and we should not stop init due to this */ 12981558Srgrimes } 12991558Srgrimes 13001558Srgrimes /* Disabling VLAN filtering */ 13011558Srgrimes DEBUGOUT("Initializing the IEEE VLAN\n"); 13021558Srgrimes mac->ops.clear_vfta(hw); 13031558Srgrimes 13041558Srgrimes /* Setup the receive address */ 13051558Srgrimes e1000_init_rx_addrs_generic(hw, rar_count); 13061558Srgrimes 13071558Srgrimes /* Zero out the Multicast HASH table */ 13081558Srgrimes DEBUGOUT("Zeroing the MTA\n"); 13091558Srgrimes for (i = 0; i < mac->mta_reg_count; i++) 13101558Srgrimes E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 13111558Srgrimes 13121558Srgrimes /* Zero out the Unicast HASH table */ 13131558Srgrimes DEBUGOUT("Zeroing the UTA\n"); 13141558Srgrimes for (i = 0; i < mac->uta_reg_count; i++) 13151558Srgrimes E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 13161558Srgrimes 13171558Srgrimes /* Setup link and flow control */ 13181558Srgrimes ret_val = mac->ops.setup_link(hw); 13191558Srgrimes 132037003Sjoerg /* 132137663Scharnier * Clear all of the statistics registers (clear on read). It is 132237663Scharnier * important that we do this after we have tried to establish link 132337004Sjoerg * because the symbol error count will increment wildly if there 132437003Sjoerg * is no link. 132537663Scharnier */ 132637663Scharnier e1000_clear_hw_cntrs_82575(hw); 132729317Sjlemon 13281558Srgrimes return ret_val; 13297401Swpaul} 133037663Scharnier 133129317Sjlemon/** 13321558Srgrimes * e1000_setup_copper_link_82575 - Configure copper link settings 13331558Srgrimes * @hw: pointer to the HW structure 13341558Srgrimes * 13351558Srgrimes * Configures the link for auto-neg or forced speed and duplex. Then we check 13361558Srgrimes * for link, once link is established calls to configure collision distance 13371558Srgrimes * and flow control are called. 13381558Srgrimes **/ 13391558Srgrimesstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 13401558Srgrimes{ 13411558Srgrimes u32 ctrl; 13421558Srgrimes s32 ret_val; 13431558Srgrimes 13441558Srgrimes DEBUGFUNC("e1000_setup_copper_link_82575"); 13451558Srgrimes 13461558Srgrimes ctrl = E1000_READ_REG(hw, E1000_CTRL); 134775641Siedowse ctrl |= E1000_CTRL_SLU; 13481558Srgrimes ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 134937663Scharnier E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 13501558Srgrimes 13511558Srgrimes ret_val = e1000_setup_serdes_link_82575(hw); 13521558Srgrimes if (ret_val) 13531558Srgrimes goto out; 13541558Srgrimes 13551558Srgrimes if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 135675801Siedowse /* allow time for SFP cage time to power up phy */ 13571558Srgrimes msec_delay(300); 13581558Srgrimes 135929317Sjlemon ret_val = hw->phy.ops.reset(hw); 136074462Salfred if (ret_val) { 136174462Salfred DEBUGOUT("Error resetting the PHY.\n"); 136229317Sjlemon goto out; 136329317Sjlemon } 136429317Sjlemon } 136529317Sjlemon switch (hw->phy.type) { 136674462Salfred case e1000_phy_m88: 136729317Sjlemon if (hw->phy.id == I347AT4_E_PHY_ID || 136829317Sjlemon hw->phy.id == M88E1112_E_PHY_ID) 136929317Sjlemon ret_val = e1000_copper_link_setup_m88_gen2(hw); 137029317Sjlemon else 137129317Sjlemon ret_val = e1000_copper_link_setup_m88(hw); 13721558Srgrimes break; 13731558Srgrimes case e1000_phy_igp_3: 1374192934Srmacklem ret_val = e1000_copper_link_setup_igp(hw); 1375192934Srmacklem break; 1376192934Srmacklem case e1000_phy_82580: 1377192934Srmacklem ret_val = e1000_copper_link_setup_82577(hw); 1378192934Srmacklem break; 1379192934Srmacklem default: 13801558Srgrimes ret_val = -E1000_ERR_PHY; 13811558Srgrimes break; 13821558Srgrimes } 13831558Srgrimes 13841558Srgrimes if (ret_val) 13851558Srgrimes goto out; 13861558Srgrimes 138775635Siedowse ret_val = e1000_setup_copper_link_generic(hw); 138875635Siedowseout: 138975635Siedowse return ret_val; 139075635Siedowse} 139175635Siedowse 13921558Srgrimes/** 13931558Srgrimes * e1000_setup_serdes_link_82575 - Setup link for serdes 13941558Srgrimes * @hw: pointer to the HW structure 1395192934Srmacklem * 1396192934Srmacklem * Configure the physical coding sub-layer (PCS) link. The PCS link is 1397194773Srmacklem * used on copper connections where the serialized gigabit media independent 1398194773Srmacklem * interface (sgmii), or serdes fiber is being used. Configures the link 1399194773Srmacklem * for auto-negotiation or forces speed/duplex. 1400194773Srmacklem **/ 1401194773Srmacklemstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1402194773Srmacklem{ 1403194773Srmacklem u32 ctrl_ext, ctrl_reg, reg; 1404194773Srmacklem bool pcs_autoneg; 1405194773Srmacklem 1406194773Srmacklem DEBUGFUNC("e1000_setup_serdes_link_82575"); 1407194773Srmacklem 1408194773Srmacklem if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1409192934Srmacklem !e1000_sgmii_active_82575(hw)) 1410194773Srmacklem return E1000_SUCCESS; 1411192934Srmacklem 1412192934Srmacklem /* 14131558Srgrimes * On the 82575, SerDes loopback mode persists until it is 14141558Srgrimes * explicitly turned off or a power cycle is performed. A read to 14151558Srgrimes * the register does not indicate its status. Therefore, we ensure 14169336Sdfr * loopback mode is disabled during initialization. 14171558Srgrimes */ 14181558Srgrimes E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 14191558Srgrimes 14201558Srgrimes /* power on the sfp cage if present */ 14219336Sdfr ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 14221558Srgrimes ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 14231558Srgrimes E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 14241558Srgrimes 14251558Srgrimes ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 14261558Srgrimes ctrl_reg |= E1000_CTRL_SLU; 14271558Srgrimes 14281558Srgrimes /* set both sw defined pins on 82575/82576*/ 14291558Srgrimes if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 14301558Srgrimes ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 14311558Srgrimes 14321558Srgrimes reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 14331558Srgrimes 14341558Srgrimes /* default pcs_autoneg to the same setting as mac autoneg */ 14351558Srgrimes pcs_autoneg = hw->mac.autoneg; 14361558Srgrimes 14371558Srgrimes switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 14381558Srgrimes case E1000_CTRL_EXT_LINK_MODE_SGMII: 14391558Srgrimes /* sgmii mode lets the phy handle forcing speed/duplex */ 14401558Srgrimes pcs_autoneg = TRUE; 14411558Srgrimes /* autoneg time out should be disabled for SGMII mode */ 1442192934Srmacklem reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 14431558Srgrimes break; 14441558Srgrimes case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 14451558Srgrimes /* disable PCS autoneg and support parallel detect only */ 14461558Srgrimes pcs_autoneg = FALSE; 14471558Srgrimes /* fall through to default case */ 14481558Srgrimes default: 14491558Srgrimes /* 14501558Srgrimes * non-SGMII modes only supports a speed of 1000/Full for the 1451166440Spjd * link so it is best to just force the MAC and let the pcs 1452166440Spjd * link either autoneg or be forced to 1000/Full 1453166440Spjd */ 1454216587Scharnier ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1455166440Spjd E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1456166440Spjd 1457166440Spjd /* set speed of 1000/Full if speed/duplex is forced */ 1458166440Spjd reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1459166440Spjd break; 1460166440Spjd } 1461166440Spjd 1462166440Spjd E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1463166440Spjd 1464166440Spjd /* 1465166440Spjd * New SerDes mode allows for forcing speed or autonegotiating speed 1466168684Spjd * at 1gb. Autoneg should be default set by most drivers. This is the 1467192934Srmacklem * mode that will be compatible with older link partners and switches. 1468166440Spjd * However, both are supported by the hardware and some drivers/tools. 1469192934Srmacklem */ 1470166440Spjd reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1471166440Spjd E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1472166440Spjd 1473166440Spjd /* 1474166440Spjd * We force flow control to prevent the CTRL register values from being 1475166440Spjd * overwritten by the autonegotiated flow control values 1476166440Spjd */ 1477166440Spjd reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1478166440Spjd 1479166440Spjd if (pcs_autoneg) { 1480166440Spjd /* Set PCS register for autoneg */ 1481166440Spjd reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1482166440Spjd E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1483166440Spjd DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1484166440Spjd } else { 1485166440Spjd /* Set PCS register for forced link */ 1486166440Spjd reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1487166440Spjd DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1488166440Spjd } 1489166440Spjd 1490166440Spjd E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1491166440Spjd 1492166440Spjd if (!e1000_sgmii_active_82575(hw)) 1493166440Spjd e1000_force_mac_fc_generic(hw); 1494166440Spjd 1495166440Spjd return E1000_SUCCESS; 1496166440Spjd} 1497166440Spjd 1498192934Srmacklem/** 1499192934Srmacklem * e1000_valid_led_default_82575 - Verify a valid default LED config 1500192934Srmacklem * @hw: pointer to the HW structure 1501192934Srmacklem * @data: pointer to the NVM (EEPROM) 1502192934Srmacklem * 1503192934Srmacklem * Read the EEPROM for the current default LED configuration. If the 1504192934Srmacklem * LED configuration is not valid, set to a valid LED configuration. 1505192934Srmacklem **/ 1506192934Srmacklemstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1507192934Srmacklem{ 1508192934Srmacklem s32 ret_val; 1509192934Srmacklem 1510192934Srmacklem DEBUGFUNC("e1000_valid_led_default_82575"); 1511192934Srmacklem 1512192934Srmacklem ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1513166440Spjd if (ret_val) { 1514166440Spjd DEBUGOUT("NVM Read Error\n"); 1515166440Spjd goto out; 1516166440Spjd } 1517166440Spjd 1518166440Spjd if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1519166440Spjd switch(hw->phy.media_type) { 1520166440Spjd case e1000_media_type_internal_serdes: 1521166440Spjd *data = ID_LED_DEFAULT_82575_SERDES; 1522166440Spjd break; 1523166440Spjd case e1000_media_type_copper: 1524166440Spjd default: 1525166440Spjd *data = ID_LED_DEFAULT; 1526166440Spjd break; 1527166440Spjd } 1528166440Spjd } 1529166440Spjdout: 1530166440Spjd return ret_val; 1531166440Spjd} 1532166440Spjd 1533166440Spjd/** 1534166440Spjd * e1000_sgmii_active_82575 - Return sgmii state 1535166440Spjd * @hw: pointer to the HW structure 1536166440Spjd * 1537166440Spjd * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1538166440Spjd * which can be enabled for use in the embedded applications. Simply 1539166440Spjd * return the current state of the sgmii interface. 1540166440Spjd **/ 1541166440Spjdstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1542166440Spjd{ 1543166440Spjd struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1544166440Spjd return dev_spec->sgmii_active; 1545166440Spjd} 1546166440Spjd 1547166440Spjd/** 1548166440Spjd * e1000_reset_init_script_82575 - Inits HW defaults after reset 1549166440Spjd * @hw: pointer to the HW structure 1550166440Spjd * 1551166440Spjd * Inits recommended HW defaults after a reset when there is no EEPROM 1552166440Spjd * detected. This is only for the 82575. 1553166440Spjd **/ 1554166440Spjdstatic s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1555166440Spjd{ 1556166440Spjd DEBUGFUNC("e1000_reset_init_script_82575"); 1557166440Spjd 1558166440Spjd if (hw->mac.type == e1000_82575) { 1559166440Spjd DEBUGOUT("Running reset init script for 82575\n"); 1560166440Spjd /* SerDes configuration via SERDESCTRL */ 1561166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1562166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1563166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1564166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1565166440Spjd 1566166440Spjd /* CCM configuration via CCMCTL register */ 1567166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1568166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1569166440Spjd 1570166440Spjd /* PCIe lanes configuration */ 1571166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1572166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1573166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1574166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1575166440Spjd 1576166440Spjd /* PCIe PLL Configuration */ 1577168684Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1578166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1579166440Spjd e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1580166440Spjd } 1581166440Spjd 1582168684Spjd return E1000_SUCCESS; 1583168684Spjd} 1584166440Spjd 1585166440Spjd/** 1586166440Spjd * e1000_read_mac_addr_82575 - Read device MAC address 1587168684Spjd * @hw: pointer to the HW structure 1588166440Spjd **/ 1589168684Spjdstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1590168684Spjd{ 1591168684Spjd s32 ret_val = E1000_SUCCESS; 1592168684Spjd 1593192934Srmacklem DEBUGFUNC("e1000_read_mac_addr_82575"); 1594192934Srmacklem 1595192934Srmacklem /* 1596192934Srmacklem * If there's an alternate MAC address place it in RAR0 1597192934Srmacklem * so that it will override the Si installed default perm 1598192934Srmacklem * address. 1599166440Spjd */ 1600166440Spjd ret_val = e1000_check_alt_mac_addr_generic(hw); 1601166440Spjd if (ret_val) 16021558Srgrimes goto out; 16031558Srgrimes 16041558Srgrimes ret_val = e1000_read_mac_addr_generic(hw); 1605216587Scharnier 16061558Srgrimesout: 16071558Srgrimes return ret_val; 16081558Srgrimes} 16091558Srgrimes 16101558Srgrimes/** 16111558Srgrimes * e1000_config_collision_dist_82575 - Configure collision distance 161223681Speter * @hw: pointer to the HW structure 16131558Srgrimes * 16141558Srgrimes * Configures the collision distance to the default value and is used 16151558Srgrimes * during link setup. 16161558Srgrimes **/ 16171558Srgrimesstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw) 16181558Srgrimes{ 16191558Srgrimes u32 tctl_ext; 1620216587Scharnier 16211558Srgrimes DEBUGFUNC("e1000_config_collision_dist_82575"); 16221558Srgrimes 16231558Srgrimes tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 16241558Srgrimes 16251558Srgrimes tctl_ext &= ~E1000_TCTL_EXT_COLD; 16261558Srgrimes tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 162723681Speter 16281558Srgrimes E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 16291558Srgrimes E1000_WRITE_FLUSH(hw); 16301558Srgrimes} 16311558Srgrimes 16321558Srgrimes/** 16331558Srgrimes * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 16341558Srgrimes * @hw: pointer to the HW structure 1635216587Scharnier * 16361558Srgrimes * In the case of a PHY power down to save power, or to turn off link during a 16371558Srgrimes * driver unload, or wake on lan is not enabled, remove the link. 16381558Srgrimes **/ 1639100336Sjoergstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1640100336Sjoerg{ 16411558Srgrimes struct e1000_phy_info *phy = &hw->phy; 16421558Srgrimes 16431558Srgrimes if (!(phy->ops.check_reset_block)) 16441558Srgrimes return; 16451558Srgrimes 16461558Srgrimes /* If the management interface is not enabled, then power down */ 16471558Srgrimes if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 16481558Srgrimes e1000_power_down_phy_copper(hw); 16491558Srgrimes 16501558Srgrimes return; 16511558Srgrimes} 16521558Srgrimes 16531558Srgrimes/** 1654216587Scharnier * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 16551558Srgrimes * @hw: pointer to the HW structure 16561558Srgrimes * 16571558Srgrimes * Clears the hardware counters by reading the counter registers. 16581558Srgrimes **/ 16591558Srgrimesstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 16601558Srgrimes{ 16611558Srgrimes DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 16621558Srgrimes 16631558Srgrimes e1000_clear_hw_cntrs_base_generic(hw); 16641558Srgrimes 16651558Srgrimes E1000_READ_REG(hw, E1000_PRC64); 16661558Srgrimes E1000_READ_REG(hw, E1000_PRC127); 16671558Srgrimes E1000_READ_REG(hw, E1000_PRC255); 16681558Srgrimes E1000_READ_REG(hw, E1000_PRC511); 16691558Srgrimes E1000_READ_REG(hw, E1000_PRC1023); 16701558Srgrimes E1000_READ_REG(hw, E1000_PRC1522); 16711558Srgrimes E1000_READ_REG(hw, E1000_PTC64); 1672216587Scharnier E1000_READ_REG(hw, E1000_PTC127); 16731558Srgrimes E1000_READ_REG(hw, E1000_PTC255); 16741558Srgrimes E1000_READ_REG(hw, E1000_PTC511); 16751558Srgrimes E1000_READ_REG(hw, E1000_PTC1023); 16761558Srgrimes E1000_READ_REG(hw, E1000_PTC1522); 167737663Scharnier 167837663Scharnier E1000_READ_REG(hw, E1000_ALGNERRC); 16791558Srgrimes E1000_READ_REG(hw, E1000_RXERRC); 16801558Srgrimes E1000_READ_REG(hw, E1000_TNCRS); 16811558Srgrimes E1000_READ_REG(hw, E1000_CEXTERR); 16821558Srgrimes E1000_READ_REG(hw, E1000_TSCTC); 16831558Srgrimes E1000_READ_REG(hw, E1000_TSCTFC); 16841558Srgrimes 16851558Srgrimes E1000_READ_REG(hw, E1000_MGTPRC); 16861558Srgrimes E1000_READ_REG(hw, E1000_MGTPDC); 16871558Srgrimes E1000_READ_REG(hw, E1000_MGTPTC); 16881558Srgrimes 16891558Srgrimes E1000_READ_REG(hw, E1000_IAC); 16901558Srgrimes E1000_READ_REG(hw, E1000_ICRXOC); 16911558Srgrimes 16921558Srgrimes E1000_READ_REG(hw, E1000_ICRXPTC); 1693216587Scharnier E1000_READ_REG(hw, E1000_ICRXATC); 1694216587Scharnier E1000_READ_REG(hw, E1000_ICTXPTC); 16951558Srgrimes E1000_READ_REG(hw, E1000_ICTXATC); 16961558Srgrimes E1000_READ_REG(hw, E1000_ICTXQEC); 16971558Srgrimes E1000_READ_REG(hw, E1000_ICTXQMTC); 16981558Srgrimes E1000_READ_REG(hw, E1000_ICRXDMTC); 16999336Sdfr 17001558Srgrimes E1000_READ_REG(hw, E1000_CBTMPC); 17011558Srgrimes E1000_READ_REG(hw, E1000_HTDPMC); 17021558Srgrimes E1000_READ_REG(hw, E1000_CBRMPC); 17031558Srgrimes E1000_READ_REG(hw, E1000_RPTHC); 17049336Sdfr E1000_READ_REG(hw, E1000_HGPTC); 17051558Srgrimes E1000_READ_REG(hw, E1000_HTCBDPC); 17069336Sdfr E1000_READ_REG(hw, E1000_HGORCL); 17071558Srgrimes E1000_READ_REG(hw, E1000_HGORCH); 17081558Srgrimes E1000_READ_REG(hw, E1000_HGOTCL); 17091558Srgrimes E1000_READ_REG(hw, E1000_HGOTCH); 17101558Srgrimes E1000_READ_REG(hw, E1000_LENERRS); 17111558Srgrimes 17121558Srgrimes /* This register should not be read in copper configurations */ 17131558Srgrimes if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 17141558Srgrimes e1000_sgmii_active_82575(hw)) 17151558Srgrimes E1000_READ_REG(hw, E1000_SCVPC); 171637663Scharnier} 17171558Srgrimes 17181558Srgrimes/** 17191558Srgrimes * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 17209336Sdfr * @hw: pointer to the HW structure 17211558Srgrimes * 17221558Srgrimes * After rx enable if managability is enabled then there is likely some 17231558Srgrimes * bad data at the start of the fifo and possibly in the DMA fifo. This 17241558Srgrimes * function clears the fifos and flushes any packets that came in as rx was 17251558Srgrimes * being enabled. 17261558Srgrimes **/ 17271558Srgrimesvoid e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 17281558Srgrimes{ 17291558Srgrimes u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 17301558Srgrimes int i, ms_wait; 1731216587Scharnier 1732216587Scharnier DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 17331558Srgrimes if (hw->mac.type != e1000_82575 || 17341558Srgrimes !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 17351558Srgrimes return; 17361558Srgrimes 17371558Srgrimes /* Disable all Rx queues */ 17381558Srgrimes for (i = 0; i < 4; i++) { 17391558Srgrimes rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 17401558Srgrimes E1000_WRITE_REG(hw, E1000_RXDCTL(i), 17411558Srgrimes rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 17429336Sdfr } 17431558Srgrimes /* Poll all queues to verify they have shut down */ 17441558Srgrimes for (ms_wait = 0; ms_wait < 10; ms_wait++) { 17459336Sdfr msec_delay(1); 17461558Srgrimes rx_enabled = 0; 17471558Srgrimes for (i = 0; i < 4; i++) 17481558Srgrimes rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 17491558Srgrimes if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 17501558Srgrimes break; 17511558Srgrimes } 17521558Srgrimes 17531558Srgrimes if (ms_wait == 10) 17541558Srgrimes DEBUGOUT("Queue disable timed out after 10ms\n"); 17551558Srgrimes 17561558Srgrimes /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 17571558Srgrimes * incoming packets are rejected. Set enable and wait 2ms so that 17581558Srgrimes * any packet that was coming in as RCTL.EN was set is flushed 17591558Srgrimes */ 17601558Srgrimes rfctl = E1000_READ_REG(hw, E1000_RFCTL); 17611558Srgrimes E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 17621558Srgrimes 17631558Srgrimes rlpml = E1000_READ_REG(hw, E1000_RLPML); 17641558Srgrimes E1000_WRITE_REG(hw, E1000_RLPML, 0); 17651558Srgrimes 17669336Sdfr rctl = E1000_READ_REG(hw, E1000_RCTL); 17671558Srgrimes temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 17689336Sdfr temp_rctl |= E1000_RCTL_LPE; 17691558Srgrimes 17701558Srgrimes E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 17711558Srgrimes E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 17721558Srgrimes E1000_WRITE_FLUSH(hw); 17731558Srgrimes msec_delay(2); 17741558Srgrimes 1775216587Scharnier /* Enable Rx queues that were previously enabled and restore our 17761558Srgrimes * previous state 17771558Srgrimes */ 17781558Srgrimes for (i = 0; i < 4; i++) 17791558Srgrimes E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 178074462Salfred E1000_WRITE_REG(hw, E1000_RCTL, rctl); 17811558Srgrimes E1000_WRITE_FLUSH(hw); 178274462Salfred 17831558Srgrimes E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 178474462Salfred E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 17851558Srgrimes 17861558Srgrimes /* Flush receive errors generated by workaround */ 17871558Srgrimes E1000_READ_REG(hw, E1000_ROC); 17881558Srgrimes E1000_READ_REG(hw, E1000_RNBC); 17891558Srgrimes E1000_READ_REG(hw, E1000_MPC); 17901558Srgrimes} 17911558Srgrimes 17921558Srgrimes/** 17931558Srgrimes * e1000_set_pcie_completion_timeout - set pci-e completion timeout 17941558Srgrimes * @hw: pointer to the HW structure 1795216587Scharnier * 1796216587Scharnier * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 17971558Srgrimes * however the hardware default for these parts is 500us to 1ms which is less 17981558Srgrimes * than the 10ms recommended by the pci-e spec. To address this we need to 17991558Srgrimes * increase the value to either 10ms to 200ms for capability version 1 config, 180074462Salfred * or 16ms to 55ms for version 2. 18011558Srgrimes **/ 18021558Srgrimesstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 18031558Srgrimes{ 18049336Sdfr u32 gcr = E1000_READ_REG(hw, E1000_GCR); 18051558Srgrimes s32 ret_val = E1000_SUCCESS; 18061558Srgrimes u16 pcie_devctl2; 18071558Srgrimes 18081558Srgrimes /* only take action if timeout value is defaulted to 0 */ 18091558Srgrimes if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 181074462Salfred goto out; 181174462Salfred 181275801Siedowse /* 181374462Salfred * if capababilities version is type 1 we can write the 181474462Salfred * timeout of 10ms to 200ms through the GCR register 181574462Salfred */ 181674462Salfred if (!(gcr & E1000_GCR_CAP_VER2)) { 18179336Sdfr gcr |= E1000_GCR_CMPL_TMOUT_10ms; 181875801Siedowse goto out; 18191558Srgrimes } 182075801Siedowse 182175801Siedowse /* 182275801Siedowse * for version 2 capabilities we need to write the config space 182375801Siedowse * directly in order to set the completion timeout value for 182474462Salfred * 16ms to 55ms 182574462Salfred */ 182674462Salfred ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 182775801Siedowse &pcie_devctl2); 182875801Siedowse if (ret_val) 18291558Srgrimes goto out; 18301558Srgrimes 18311558Srgrimes pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 18321558Srgrimes 18331558Srgrimes ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 18341558Srgrimes &pcie_devctl2); 18351558Srgrimesout: 18361558Srgrimes /* disable completion timeout resend */ 18371558Srgrimes gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 18381558Srgrimes 1839216587Scharnier E1000_WRITE_REG(hw, E1000_GCR, gcr); 18401558Srgrimes return ret_val; 18419336Sdfr} 18421558Srgrimes 18431558Srgrimes 18441558Srgrimes/** 18451558Srgrimes * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 18469336Sdfr * @hw: pointer to the hardware struct 18471558Srgrimes * @enable: state to enter, either enabled or disabled 18481558Srgrimes * @pf: Physical Function pool - do not set anti-spoofing for the PF 18491558Srgrimes * 18501558Srgrimes * enables/disables L2 switch anti-spoofing functionality. 18511558Srgrimes **/ 18521558Srgrimesvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 18531558Srgrimes{ 18541558Srgrimes u32 dtxswc; 18551558Srgrimes 18561558Srgrimes switch (hw->mac.type) { 18571558Srgrimes case e1000_82576: 1858216587Scharnier case e1000_i350: 18591558Srgrimes dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 18601558Srgrimes if (enable) { 18611558Srgrimes dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 18621558Srgrimes E1000_DTXSWC_VLAN_SPOOF_MASK); 18631558Srgrimes /* The PF can spoof - it has to in order to 18641558Srgrimes * support emulation mode NICs */ 18651558Srgrimes dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 18661558Srgrimes } else { 18671558Srgrimes dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 18681558Srgrimes E1000_DTXSWC_VLAN_SPOOF_MASK); 18691558Srgrimes } 1870184588Sdfr E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1871184588Sdfr break; 1872184588Sdfr default: 1873216587Scharnier break; 1874184588Sdfr } 1875184588Sdfr} 1876184588Sdfr 1877184588Sdfr/** 1878184588Sdfr * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 1879184588Sdfr * @hw: pointer to the hardware struct 1880184588Sdfr * @enable: state to enter, either enabled or disabled 1881184588Sdfr * 1882184588Sdfr * enables/disables L2 switch loopback functionality. 1883184588Sdfr **/ 1884184588Sdfrvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1885184588Sdfr{ 1886184588Sdfr u32 dtxswc; 1887184588Sdfr 1888184588Sdfr switch (hw->mac.type) { 1889184588Sdfr case e1000_82576: 1890184588Sdfr dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1891184588Sdfr if (enable) 1892184588Sdfr dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1893184588Sdfr else 1894184588Sdfr dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1895184588Sdfr E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1896184588Sdfr break; 1897184588Sdfr case e1000_i350: 1898184588Sdfr dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 1899184588Sdfr if (enable) 1900184588Sdfr dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1901184588Sdfr else 1902184588Sdfr dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1903184588Sdfr E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 1904184588Sdfr break; 1905184588Sdfr default: 1906184588Sdfr /* Currently no other hardware supports loopback */ 1907184588Sdfr break; 1908184588Sdfr } 1909184588Sdfr 1910184588Sdfr 1911184588Sdfr} 1912184588Sdfr 1913184588Sdfr/** 1914184588Sdfr * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 1915184588Sdfr * @hw: pointer to the hardware struct 1916184588Sdfr * @enable: state to enter, either enabled or disabled 1917184588Sdfr * 1918184588Sdfr * enables/disables replication of packets across multiple pools. 19191558Srgrimes **/ 19201558Srgrimesvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 19211558Srgrimes{ 19221558Srgrimes u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 19231558Srgrimes 1924216587Scharnier if (enable) 1925216587Scharnier vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 19261558Srgrimes else 19271558Srgrimes vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 19281558Srgrimes 19291558Srgrimes E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 19301558Srgrimes} 193151968Salfred 19321558Srgrimes/** 19331558Srgrimes * e1000_read_phy_reg_82580 - Read 82580 MDI control register 19341558Srgrimes * @hw: pointer to the HW structure 19351558Srgrimes * @offset: register offset to be read 19361558Srgrimes * @data: pointer to the read data 19371558Srgrimes * 19381558Srgrimes * Reads the MDI control register in the PHY at offset and stores the 19391558Srgrimes * information read to data. 194037663Scharnier **/ 19411558Srgrimesstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 194237663Scharnier{ 19431558Srgrimes s32 ret_val; 19441558Srgrimes 194537663Scharnier DEBUGFUNC("e1000_read_phy_reg_82580"); 19461558Srgrimes 19471558Srgrimes ret_val = hw->phy.ops.acquire(hw); 19481558Srgrimes if (ret_val) 19491558Srgrimes goto out; 19501558Srgrimes 19511558Srgrimes ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 19521558Srgrimes 19531558Srgrimes hw->phy.ops.release(hw); 19541558Srgrimes 19551558Srgrimesout: 19561558Srgrimes return ret_val; 19571558Srgrimes} 19581558Srgrimes 19591558Srgrimes/** 19601558Srgrimes * e1000_write_phy_reg_82580 - Write 82580 MDI control register 19611558Srgrimes * @hw: pointer to the HW structure 19621558Srgrimes * @offset: register offset to write to 19631558Srgrimes * @data: data to write to register at offset 19641558Srgrimes * 19651558Srgrimes * Writes data to MDI control register in the PHY at offset. 19661558Srgrimes **/ 19671558Srgrimesstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 19681558Srgrimes{ 19691558Srgrimes s32 ret_val; 19701558Srgrimes 19711558Srgrimes DEBUGFUNC("e1000_write_phy_reg_82580"); 197275801Siedowse 19731558Srgrimes ret_val = hw->phy.ops.acquire(hw); 197437663Scharnier if (ret_val) 19751558Srgrimes goto out; 19761558Srgrimes 19771558Srgrimes ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 19781558Srgrimes 19791558Srgrimes hw->phy.ops.release(hw); 19801558Srgrimes 198174462Salfredout: 198274462Salfred return ret_val; 198374462Salfred} 198474462Salfred 198574462Salfred/** 19861558Srgrimes * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 198737663Scharnier * @hw: pointer to the HW structure 19881558Srgrimes * 19891558Srgrimes * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 199037663Scharnier * the values found in the EEPROM. This addresses an issue in which these 19911558Srgrimes * bits are not restored from EEPROM after reset. 19921558Srgrimes **/ 19931558Srgrimesstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 19941558Srgrimes{ 19951558Srgrimes s32 ret_val = E1000_SUCCESS; 19961558Srgrimes u32 mdicnfg; 19971558Srgrimes u16 nvm_data = 0; 19981558Srgrimes 199927447Sdfr DEBUGFUNC("e1000_reset_mdicnfg_82580"); 200027447Sdfr 200127447Sdfr if (hw->mac.type != e1000_82580) 200227447Sdfr goto out; 200327447Sdfr if (!e1000_sgmii_active_82575(hw)) 200427447Sdfr goto out; 200527447Sdfr 2006100336Sjoerg ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2007100336Sjoerg NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2008184588Sdfr &nvm_data); 2009184588Sdfr if (ret_val) { 2010184588Sdfr DEBUGOUT("NVM Read Error\n"); 2011184588Sdfr goto out; 2012184588Sdfr } 20131558Srgrimes 201437663Scharnier mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 20151558Srgrimes if (nvm_data & NVM_WORD24_EXT_MDIO) 20161558Srgrimes mdicnfg |= E1000_MDICNFG_EXT_MDIO; 20171558Srgrimes if (nvm_data & NVM_WORD24_COM_MDIO) 20181558Srgrimes mdicnfg |= E1000_MDICNFG_COM_MDIO; 20191558Srgrimes E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 20201558Srgrimesout: 20211558Srgrimes return ret_val; 20221558Srgrimes} 20231558Srgrimes 20241558Srgrimes/** 20251558Srgrimes * e1000_reset_hw_82580 - Reset hardware 20261558Srgrimes * @hw: pointer to the HW structure 20271558Srgrimes * 20281558Srgrimes * This resets function or entire device (all ports, etc.) 20291558Srgrimes * to a known state. 20301558Srgrimes **/ 20311558Srgrimesstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw) 20321558Srgrimes{ 20331558Srgrimes s32 ret_val = E1000_SUCCESS; 20341558Srgrimes /* BH SW mailbox bit in SW_FW_SYNC */ 20351558Srgrimes u16 swmbsw_mask = E1000_SW_SYNCH_MB; 20361558Srgrimes u32 ctrl; 2037216587Scharnier bool global_device_reset = hw->dev_spec._82575.global_device_reset; 20381558Srgrimes 20397401Swpaul DEBUGFUNC("e1000_reset_hw_82580"); 204075635Siedowse 204174462Salfred hw->dev_spec._82575.global_device_reset = FALSE; 204274462Salfred 20431558Srgrimes /* Get current control state. */ 204474462Salfred ctrl = E1000_READ_REG(hw, E1000_CTRL); 204574462Salfred 20461558Srgrimes /* 20471558Srgrimes * Prevent the PCI-E bus from sticking if there is no TLP connection 204874462Salfred * on the last TLP read/write transaction when MAC is reset. 204974462Salfred */ 205074462Salfred ret_val = e1000_disable_pcie_master_generic(hw); 205174462Salfred if (ret_val) 205274462Salfred DEBUGOUT("PCI-E Master disable polling has failed.\n"); 205375635Siedowse 205474462Salfred DEBUGOUT("Masking off all interrupts\n"); 205574462Salfred E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 205674462Salfred E1000_WRITE_REG(hw, E1000_RCTL, 0); 205774462Salfred E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 205874462Salfred E1000_WRITE_FLUSH(hw); 205974462Salfred 2060146187Sume msec_delay(10); 206174462Salfred 206274462Salfred /* Determine whether or not a global dev reset is requested */ 206374462Salfred if (global_device_reset && 206475641Siedowse e1000_acquire_swfw_sync_82575(hw, swmbsw_mask)) 206574462Salfred global_device_reset = FALSE; 206675635Siedowse 206775635Siedowse if (global_device_reset && 206875635Siedowse !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 206975635Siedowse ctrl |= E1000_CTRL_DEV_RST; 207075635Siedowse else 207175635Siedowse ctrl |= E1000_CTRL_RST; 207275635Siedowse 207375635Siedowse E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 207475635Siedowse 207575635Siedowse /* Add delay to insure DEV_RST has time to complete */ 207675635Siedowse if (global_device_reset) 207775801Siedowse msec_delay(5); 207875635Siedowse 207975635Siedowse ret_val = e1000_get_auto_rd_done_generic(hw); 208075635Siedowse if (ret_val) { 208175635Siedowse /* 208275635Siedowse * When auto config read does not complete, do not 208375635Siedowse * return with an error. This can happen in situations 208475635Siedowse * where there is no eeprom and prevents getting link. 208575635Siedowse */ 208675635Siedowse DEBUGOUT("Auto Read Done did not complete\n"); 208774462Salfred } 20881558Srgrimes 208975635Siedowse /* If EEPROM is not present, run manual init scripts */ 20901558Srgrimes if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 20911558Srgrimes e1000_reset_init_script_82575(hw); 20921558Srgrimes 20931558Srgrimes /* clear global device reset status bit */ 20941558Srgrimes E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 20951558Srgrimes 20961558Srgrimes /* Clear any pending interrupt events. */ 2097216587Scharnier E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 20981558Srgrimes E1000_READ_REG(hw, E1000_ICR); 20991558Srgrimes 21001558Srgrimes ret_val = e1000_reset_mdicnfg_82580(hw); 21011558Srgrimes if (ret_val) 21021558Srgrimes DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 21031558Srgrimes 21041558Srgrimes /* Install any alternate MAC address into RAR0 */ 21051558Srgrimes ret_val = e1000_check_alt_mac_addr_generic(hw); 210627447Sdfr 210727447Sdfr /* Release semaphore */ 21081558Srgrimes if (global_device_reset) 21091558Srgrimes e1000_release_swfw_sync_82575(hw, swmbsw_mask); 21101558Srgrimes 21111558Srgrimes return ret_val; 21121558Srgrimes} 21131558Srgrimes 21141558Srgrimes/** 21151558Srgrimes * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2116216587Scharnier * @data: data received by reading RXPBS register 21171558Srgrimes * 21181558Srgrimes * The 82580 uses a table based approach for packet buffer allocation sizes. 21191558Srgrimes * This function converts the retrieved value into the correct table value 21201558Srgrimes * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 21211558Srgrimes * 0x0 36 72 144 1 2 4 8 16 21221558Srgrimes * 0x8 35 70 140 rsv rsv rsv rsv rsv 21231558Srgrimes */ 21241558Srgrimesu16 e1000_rxpbs_adjust_82580(u32 data) 21251558Srgrimes{ 21261558Srgrimes u16 ret_val = 0; 21271558Srgrimes 2128216587Scharnier if (data < E1000_82580_RXPBS_TABLE_SIZE) 21291558Srgrimes ret_val = e1000_82580_rxpbs_table[data]; 21301558Srgrimes 21311558Srgrimes return ret_val; 21321558Srgrimes} 21331558Srgrimes 21341558Srgrimes/** 21351558Srgrimes * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 21369336Sdfr * checksum 21371558Srgrimes * @hw: pointer to the HW structure 21381558Srgrimes * @offset: offset in words of the checksum protected region 21391558Srgrimes * 21401558Srgrimes * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 21411558Srgrimes * and then verifies that the sum of the EEPROM is equal to 0xBABA. 21421558Srgrimes **/ 21431558Srgrimess32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2144216587Scharnier{ 21451558Srgrimes s32 ret_val = E1000_SUCCESS; 21461558Srgrimes u16 checksum = 0; 214737663Scharnier u16 i, nvm_data; 21481558Srgrimes 21491558Srgrimes DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 21501558Srgrimes 21511558Srgrimes for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2152158857Srodrigc ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 21531558Srgrimes if (ret_val) { 21541558Srgrimes DEBUGOUT("NVM Read Error\n"); 21551558Srgrimes goto out; 2156158857Srodrigc } 2157158857Srodrigc checksum += nvm_data; 21581558Srgrimes } 215975841Siedowse 216074462Salfred if (checksum != (u16) NVM_SUM) { 2161192934Srmacklem DEBUGOUT("NVM Checksum Invalid\n"); 2162158857Srodrigc ret_val = -E1000_ERR_NVM; 2163158857Srodrigc goto out; 21641558Srgrimes } 2165158857Srodrigc 2166158857Srodrigcout: 2167184588Sdfr return ret_val; 2168158857Srodrigc} 2169192934Srmacklem 21701558Srgrimes/** 2171192934Srmacklem * e1000_update_nvm_checksum_with_offset - Update EEPROM 2172192934Srmacklem * checksum 2173192934Srmacklem * @hw: pointer to the HW structure 2174192934Srmacklem * @offset: offset in words of the checksum protected region 2175192934Srmacklem * 2176158857Srodrigc * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2177158857Srodrigc * up to the checksum. Then calculates the EEPROM checksum and writes the 2178158857Srodrigc * value to the EEPROM. 2179158857Srodrigc **/ 2180158857Srodrigcs32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 218175801Siedowse{ 2182192934Srmacklem s32 ret_val; 2183158857Srodrigc u16 checksum = 0; 2184192934Srmacklem u16 i, nvm_data; 2185192934Srmacklem 2186192934Srmacklem DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 218775641Siedowse 218874462Salfred for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 218975641Siedowse ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 219075641Siedowse if (ret_val) { 2191192934Srmacklem DEBUGOUT("NVM Read Error while updating checksum.\n"); 2192192934Srmacklem goto out; 2193192934Srmacklem } 2194192934Srmacklem checksum += nvm_data; 2195192934Srmacklem } 2196192934Srmacklem checksum = (u16) NVM_SUM - checksum; 2197184588Sdfr ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 21981558Srgrimes &checksum); 2199158857Srodrigc if (ret_val) 2200192934Srmacklem DEBUGOUT("NVM Write Error while updating checksum.\n"); 2201192934Srmacklem 2202192934Srmacklemout: 2203192934Srmacklem return ret_val; 2204192934Srmacklem} 2205192934Srmacklem 2206192934Srmacklem/** 2207192934Srmacklem * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2208192934Srmacklem * @hw: pointer to the HW structure 2209158857Srodrigc * 22101558Srgrimes * Calculates the EEPROM section checksum by reading/adding each word of 22111558Srgrimes * the EEPROM and then verifies that the sum of the EEPROM is 22121558Srgrimes * equal to 0xBABA. 221375641Siedowse **/ 221474462Salfredstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2215192934Srmacklem{ 2216192934Srmacklem s32 ret_val = E1000_SUCCESS; 2217192934Srmacklem u16 eeprom_regions_count = 1; 22181558Srgrimes u16 j, nvm_data; 22191558Srgrimes u16 nvm_offset; 222075801Siedowse 222174462Salfred DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 222274462Salfred 2223192934Srmacklem ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 222475801Siedowse if (ret_val) { 2225192934Srmacklem DEBUGOUT("NVM Read Error\n"); 2226158857Srodrigc goto out; 2227192934Srmacklem } 222875801Siedowse 2229192934Srmacklem if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 22301558Srgrimes /* if chekcsums compatibility bit is set validate checksums 223175641Siedowse * for all 4 ports. */ 2232192934Srmacklem eeprom_regions_count = 4; 2233192934Srmacklem } 2234192934Srmacklem 2235192934Srmacklem for (j = 0; j < eeprom_regions_count; j++) { 223675641Siedowse nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 22377401Swpaul ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2238158857Srodrigc nvm_offset); 2239158857Srodrigc if (ret_val != E1000_SUCCESS) 22407401Swpaul goto out; 22411558Srgrimes } 224237663Scharnier 22431558Srgrimesout: 22441558Srgrimes return ret_val; 2245158857Srodrigc} 2246158857Srodrigc 22471558Srgrimes/** 22481558Srgrimes * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 22491558Srgrimes * @hw: pointer to the HW structure 2250192934Srmacklem * 22511558Srgrimes * Updates the EEPROM section checksums for all 4 ports by reading/adding 2252192934Srmacklem * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2253192934Srmacklem * checksum and writes the value to the EEPROM. 2254192934Srmacklem **/ 2255192934Srmacklemstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2256192934Srmacklem{ 2257192934Srmacklem s32 ret_val; 2258158857Srodrigc u16 j, nvm_data; 2259192934Srmacklem u16 nvm_offset; 2260192934Srmacklem 2261192934Srmacklem DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2262192934Srmacklem 2263192934Srmacklem ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2264192934Srmacklem if (ret_val) { 2265192934Srmacklem DEBUGOUT("NVM Read Error while updating checksum" 2266192934Srmacklem " compatibility bit.\n"); 2267192934Srmacklem goto out; 2268192934Srmacklem } 2269192934Srmacklem 2270192934Srmacklem if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2271192934Srmacklem /* set compatibility bit to validate checksums appropriately */ 2272192934Srmacklem nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2273192934Srmacklem ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2274192934Srmacklem &nvm_data); 2275192934Srmacklem if (ret_val) { 2276192934Srmacklem DEBUGOUT("NVM Write Error while updating checksum" 2277192934Srmacklem " compatibility bit.\n"); 2278192934Srmacklem goto out; 2279192934Srmacklem } 2280192934Srmacklem } 2281192934Srmacklem 2282192934Srmacklem for (j = 0; j < 4; j++) { 2283192934Srmacklem nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2284192934Srmacklem ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2285192934Srmacklem if (ret_val) { 2286192934Srmacklem goto out; 2287192934Srmacklem } 2288192934Srmacklem } 2289192934Srmacklem 229075635Siedowseout: 2291192934Srmacklem return ret_val; 2292192934Srmacklem} 2293192934Srmacklem 2294192934Srmacklem/** 2295192934Srmacklem * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2296192934Srmacklem * @hw: pointer to the HW structure 2297100336Sjoerg * 2298192934Srmacklem * Calculates the EEPROM section checksum by reading/adding each word of 2299192934Srmacklem * the EEPROM and then verifies that the sum of the EEPROM is 2300192934Srmacklem * equal to 0xBABA. 2301192934Srmacklem **/ 2302192934Srmacklemstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2303192934Srmacklem{ 2304192934Srmacklem s32 ret_val = E1000_SUCCESS; 2305192934Srmacklem u16 j; 2306192934Srmacklem u16 nvm_offset; 2307192934Srmacklem 2308192934Srmacklem DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2309192934Srmacklem 2310192934Srmacklem for (j = 0; j < 4; j++) { 2311192934Srmacklem nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2312192934Srmacklem ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2313192934Srmacklem nvm_offset); 2314192934Srmacklem if (ret_val != E1000_SUCCESS) 2315192934Srmacklem goto out; 2316192934Srmacklem } 2317192934Srmacklem 2318192934Srmacklemout: 2319192934Srmacklem return ret_val; 2320192934Srmacklem} 2321192934Srmacklem 2322192934Srmacklem/** 2323192934Srmacklem * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2324192934Srmacklem * @hw: pointer to the HW structure 2325192934Srmacklem * 2326192934Srmacklem * Updates the EEPROM section checksums for all 4 ports by reading/adding 2327192934Srmacklem * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2328192934Srmacklem * checksum and writes the value to the EEPROM. 2329100336Sjoerg **/ 2330192934Srmacklemstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2331192934Srmacklem{ 2332192934Srmacklem s32 ret_val = E1000_SUCCESS; 2333192934Srmacklem u16 j; 2334192934Srmacklem u16 nvm_offset; 23351558Srgrimes 23361558Srgrimes DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2337192934Srmacklem 2338192934Srmacklem for (j = 0; j < 4; j++) { 2339192934Srmacklem nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2340192934Srmacklem ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2341192934Srmacklem if (ret_val != E1000_SUCCESS) 2342192934Srmacklem goto out; 2343192934Srmacklem } 2344192934Srmacklem 2345192934Srmacklemout: 2346192934Srmacklem return ret_val; 2347192934Srmacklem} 2348192934Srmacklem 2349192934Srmacklem/** 2350192934Srmacklem * e1000_set_eee_i350 - Enable/disable EEE support 2351192934Srmacklem * @hw: pointer to the HW structure 2352192934Srmacklem * 2353192934Srmacklem * Enable/disable EEE based on setting in dev_spec structure. 2354192934Srmacklem * 2355192934Srmacklem **/ 2356192934Srmacklems32 e1000_set_eee_i350(struct e1000_hw *hw) 2357192934Srmacklem{ 2358192934Srmacklem s32 ret_val = E1000_SUCCESS; 2359192934Srmacklem u32 ipcnfg, eeer, ctrl_ext; 236074462Salfred 236175641Siedowse DEBUGFUNC("e1000_set_eee_i350"); 236274462Salfred 236375641Siedowse ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 23641558Srgrimes if ((hw->mac.type != e1000_i350) || 23651558Srgrimes (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK)) 23661558Srgrimes goto out; 23671558Srgrimes ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2368158857Srodrigc eeer = E1000_READ_REG(hw, E1000_EEER); 2369158857Srodrigc 2370158857Srodrigc /* enable or disable per user setting */ 2371158857Srodrigc if (!(hw->dev_spec._82575.eee_disable)) { 2372158857Srodrigc ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | 2373158857Srodrigc E1000_IPCNFG_EEE_100M_AN); 2374158857Srodrigc eeer |= (E1000_EEER_TX_LPI_EN | 2375158857Srodrigc E1000_EEER_RX_LPI_EN | 2376158857Srodrigc E1000_EEER_LPI_FC); 2377158857Srodrigc 2378158857Srodrigc } else { 2379158857Srodrigc ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2380158857Srodrigc E1000_IPCNFG_EEE_100M_AN); 2381158857Srodrigc eeer &= ~(E1000_EEER_TX_LPI_EN | 23821558Srgrimes E1000_EEER_RX_LPI_EN | 23831558Srgrimes E1000_EEER_LPI_FC); 23841558Srgrimes } 23851558Srgrimes E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 238675801Siedowse E1000_WRITE_REG(hw, E1000_EEER, eeer); 238775801Siedowse E1000_READ_REG(hw, E1000_IPCNFG); 23881558Srgrimes E1000_READ_REG(hw, E1000_EEER); 23891558Srgrimesout: 2390216587Scharnier 23911558Srgrimes return ret_val; 239275861Siedowse} 239374462Salfred