e1000_82575.c revision 213234
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 213234 2010-09-28 00:13:15Z jfv $*/ 34 35/* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82575GB Gigabit Network Connection 40 * 82576 Gigabit Network Connection 41 * 82576 Quad Port Gigabit Mezzanine Adapter 42 */ 43 44#include "e1000_api.h" 45 46static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 47static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 48static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 49static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 50static void e1000_release_phy_82575(struct e1000_hw *hw); 51static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 52static void e1000_release_nvm_82575(struct e1000_hw *hw); 53static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 54static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 56 u16 *duplex); 57static s32 e1000_init_hw_82575(struct e1000_hw *hw); 58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 60 u16 *data); 61static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 62static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 63static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 64 u32 offset, u16 *data); 65static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 66 u32 offset, u16 data); 67static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 68 bool active); 69static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 70static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 71static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 72static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 73 u32 offset, u16 data); 74static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 75static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 76static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 77 u16 *speed, u16 *duplex); 78static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 79static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 80static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 81static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 82static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 83static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 84static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 85static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 86static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 87static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 88static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 89 90static const u16 e1000_82580_rxpbs_table[] = 91 { 36, 72, 144, 1, 2, 4, 8, 16, 92 35, 70, 140 }; 93#define E1000_82580_RXPBS_TABLE_SIZE \ 94 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 95 96 97/** 98 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 99 * @hw: pointer to the HW structure 100 * 101 * Called to determine if the I2C pins are being used for I2C or as an 102 * external MDIO interface since the two options are mutually exclusive. 103 **/ 104static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 105{ 106 u32 reg = 0; 107 bool ext_mdio = FALSE; 108 109 DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 110 111 switch (hw->mac.type) { 112 case e1000_82575: 113 case e1000_82576: 114 reg = E1000_READ_REG(hw, E1000_MDIC); 115 ext_mdio = !!(reg & E1000_MDIC_DEST); 116 break; 117 case e1000_82580: 118 reg = E1000_READ_REG(hw, E1000_MDICNFG); 119 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 120 break; 121 default: 122 break; 123 } 124 return ext_mdio; 125} 126 127/** 128 * e1000_init_phy_params_82575 - Init PHY func ptrs. 129 * @hw: pointer to the HW structure 130 **/ 131static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 132{ 133 struct e1000_phy_info *phy = &hw->phy; 134 s32 ret_val = E1000_SUCCESS; 135 u32 ctrl_ext; 136 137 DEBUGFUNC("e1000_init_phy_params_82575"); 138 139 if (hw->phy.media_type != e1000_media_type_copper) { 140 phy->type = e1000_phy_none; 141 goto out; 142 } 143 144 phy->ops.power_up = e1000_power_up_phy_copper; 145 phy->ops.power_down = e1000_power_down_phy_copper_82575; 146 147 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 148 phy->reset_delay_us = 100; 149 150 phy->ops.acquire = e1000_acquire_phy_82575; 151 phy->ops.check_reset_block = e1000_check_reset_block_generic; 152 phy->ops.commit = e1000_phy_sw_reset_generic; 153 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 154 phy->ops.release = e1000_release_phy_82575; 155 156 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 157 158 if (e1000_sgmii_active_82575(hw)) { 159 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 160 ctrl_ext |= E1000_CTRL_I2C_ENA; 161 } else { 162 phy->ops.reset = e1000_phy_hw_reset_generic; 163 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 164 } 165 166 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 167 e1000_reset_mdicnfg_82580(hw); 168 169 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 170 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 171 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 172 } else if (hw->mac.type >= e1000_82580) { 173 phy->ops.read_reg = e1000_read_phy_reg_82580; 174 phy->ops.write_reg = e1000_write_phy_reg_82580; 175 } else { 176 phy->ops.read_reg = e1000_read_phy_reg_igp; 177 phy->ops.write_reg = e1000_write_phy_reg_igp; 178 } 179 180 /* Set phy->phy_addr and phy->id. */ 181 ret_val = e1000_get_phy_id_82575(hw); 182 183 /* Verify phy id and set remaining function pointers */ 184 switch (phy->id) { 185 case M88E1111_I_PHY_ID: 186 phy->type = e1000_phy_m88; 187 phy->ops.check_polarity = e1000_check_polarity_m88; 188 phy->ops.get_info = e1000_get_phy_info_m88; 189 phy->ops.get_cable_length = e1000_get_cable_length_m88; 190 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 191 break; 192 case IGP03E1000_E_PHY_ID: 193 case IGP04E1000_E_PHY_ID: 194 phy->type = e1000_phy_igp_3; 195 phy->ops.check_polarity = e1000_check_polarity_igp; 196 phy->ops.get_info = e1000_get_phy_info_igp; 197 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 198 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 199 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 200 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 201 break; 202 case I82580_I_PHY_ID: 203 phy->type = e1000_phy_82580; 204 phy->ops.check_polarity = e1000_check_polarity_82577; 205 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; 206 phy->ops.get_cable_length = e1000_get_cable_length_82577; 207 phy->ops.get_info = e1000_get_phy_info_82577; 208 break; 209 default: 210 ret_val = -E1000_ERR_PHY; 211 goto out; 212 } 213 214out: 215 return ret_val; 216} 217 218/** 219 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 220 * @hw: pointer to the HW structure 221 **/ 222static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 223{ 224 struct e1000_nvm_info *nvm = &hw->nvm; 225 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 226 u16 size; 227 228 DEBUGFUNC("e1000_init_nvm_params_82575"); 229 230 nvm->opcode_bits = 8; 231 nvm->delay_usec = 1; 232 switch (nvm->override) { 233 case e1000_nvm_override_spi_large: 234 nvm->page_size = 32; 235 nvm->address_bits = 16; 236 break; 237 case e1000_nvm_override_spi_small: 238 nvm->page_size = 8; 239 nvm->address_bits = 8; 240 break; 241 default: 242 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 243 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 244 break; 245 } 246 247 nvm->type = e1000_nvm_eeprom_spi; 248 249 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 250 E1000_EECD_SIZE_EX_SHIFT); 251 252 /* 253 * Added to a constant, "size" becomes the left-shift value 254 * for setting word_size. 255 */ 256 size += NVM_WORD_SIZE_BASE_SHIFT; 257 258 /* EEPROM access above 16k is unsupported */ 259 if (size > 14) 260 size = 14; 261 nvm->word_size = 1 << size; 262 263 /* Function Pointers */ 264 nvm->ops.acquire = e1000_acquire_nvm_82575; 265 nvm->ops.read = e1000_read_nvm_eerd; 266 nvm->ops.release = e1000_release_nvm_82575; 267 nvm->ops.update = e1000_update_nvm_checksum_generic; 268 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 269 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 270 nvm->ops.write = e1000_write_nvm_spi; 271 272 return E1000_SUCCESS; 273} 274 275/** 276 * e1000_init_mac_params_82575 - Init MAC func ptrs. 277 * @hw: pointer to the HW structure 278 **/ 279static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 280{ 281 struct e1000_mac_info *mac = &hw->mac; 282 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 283 u32 ctrl_ext = 0; 284 285 DEBUGFUNC("e1000_init_mac_params_82575"); 286 287 /* Set media type */ 288 /* 289 * The 82575 uses bits 22:23 for link mode. The mode can be changed 290 * based on the EEPROM. We cannot rely upon device ID. There 291 * is no distinguishable difference between fiber and internal 292 * SerDes mode on the 82575. There can be an external PHY attached 293 * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 294 */ 295 hw->phy.media_type = e1000_media_type_copper; 296 dev_spec->sgmii_active = FALSE; 297 298 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 299 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 300 case E1000_CTRL_EXT_LINK_MODE_SGMII: 301 dev_spec->sgmii_active = TRUE; 302 break; 303 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 304 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 305 hw->phy.media_type = e1000_media_type_internal_serdes; 306 break; 307 default: 308 break; 309 } 310 311 /* Set mta register count */ 312 mac->mta_reg_count = 128; 313 /* Set uta register count */ 314 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 315 /* Set rar entry count */ 316 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 317 if (mac->type == e1000_82576) 318 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 319 if (mac->type == e1000_82580) 320 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 321 /* Set if part includes ASF firmware */ 322 mac->asf_firmware_present = TRUE; 323 /* FWSM register */ 324 mac->has_fwsm = TRUE; 325 /* ARC supported; valid only if manageability features are enabled. */ 326 mac->arc_subsystem_valid = 327 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 328 ? TRUE : FALSE; 329 330 /* Function pointers */ 331 332 /* bus type/speed/width */ 333 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 334 /* reset */ 335 if (mac->type >= e1000_82580) 336 mac->ops.reset_hw = e1000_reset_hw_82580; 337 else 338 mac->ops.reset_hw = e1000_reset_hw_82575; 339 /* hw initialization */ 340 mac->ops.init_hw = e1000_init_hw_82575; 341 /* link setup */ 342 mac->ops.setup_link = e1000_setup_link_generic; 343 /* physical interface link setup */ 344 mac->ops.setup_physical_interface = 345 (hw->phy.media_type == e1000_media_type_copper) 346 ? e1000_setup_copper_link_82575 347 : e1000_setup_serdes_link_82575; 348 /* physical interface shutdown */ 349 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 350 /* physical interface power up */ 351 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 352 /* check for link */ 353 mac->ops.check_for_link = e1000_check_for_link_82575; 354 /* receive address register setting */ 355 mac->ops.rar_set = e1000_rar_set_generic; 356 /* read mac address */ 357 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 358 /* configure collision distance */ 359 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 360 /* multicast address update */ 361 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 362 /* writing VFTA */ 363 mac->ops.write_vfta = e1000_write_vfta_generic; 364 /* clearing VFTA */ 365 mac->ops.clear_vfta = e1000_clear_vfta_generic; 366 /* ID LED init */ 367 mac->ops.id_led_init = e1000_id_led_init_generic; 368 /* blink LED */ 369 mac->ops.blink_led = e1000_blink_led_generic; 370 /* setup LED */ 371 mac->ops.setup_led = e1000_setup_led_generic; 372 /* cleanup LED */ 373 mac->ops.cleanup_led = e1000_cleanup_led_generic; 374 /* turn on/off LED */ 375 mac->ops.led_on = e1000_led_on_generic; 376 mac->ops.led_off = e1000_led_off_generic; 377 /* clear hardware counters */ 378 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 379 /* link info */ 380 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 381 382 /* set lan id for port to determine which phy lock to use */ 383 hw->mac.ops.set_lan_id(hw); 384 385 return E1000_SUCCESS; 386} 387 388/** 389 * e1000_init_function_pointers_82575 - Init func ptrs. 390 * @hw: pointer to the HW structure 391 * 392 * Called to initialize all function pointers and parameters. 393 **/ 394void e1000_init_function_pointers_82575(struct e1000_hw *hw) 395{ 396 DEBUGFUNC("e1000_init_function_pointers_82575"); 397 398 hw->mac.ops.init_params = e1000_init_mac_params_82575; 399 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 400 hw->phy.ops.init_params = e1000_init_phy_params_82575; 401 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 402} 403 404/** 405 * e1000_acquire_phy_82575 - Acquire rights to access PHY 406 * @hw: pointer to the HW structure 407 * 408 * Acquire access rights to the correct PHY. 409 **/ 410static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 411{ 412 u16 mask = E1000_SWFW_PHY0_SM; 413 414 DEBUGFUNC("e1000_acquire_phy_82575"); 415 416 if (hw->bus.func == E1000_FUNC_1) 417 mask = E1000_SWFW_PHY1_SM; 418 else if (hw->bus.func == E1000_FUNC_2) 419 mask = E1000_SWFW_PHY2_SM; 420 else if (hw->bus.func == E1000_FUNC_3) 421 mask = E1000_SWFW_PHY3_SM; 422 423 return e1000_acquire_swfw_sync_82575(hw, mask); 424} 425 426/** 427 * e1000_release_phy_82575 - Release rights to access PHY 428 * @hw: pointer to the HW structure 429 * 430 * A wrapper to release access rights to the correct PHY. 431 **/ 432static void e1000_release_phy_82575(struct e1000_hw *hw) 433{ 434 u16 mask = E1000_SWFW_PHY0_SM; 435 436 DEBUGFUNC("e1000_release_phy_82575"); 437 438 if (hw->bus.func == E1000_FUNC_1) 439 mask = E1000_SWFW_PHY1_SM; 440 else if (hw->bus.func == E1000_FUNC_2) 441 mask = E1000_SWFW_PHY2_SM; 442 else if (hw->bus.func == E1000_FUNC_3) 443 mask = E1000_SWFW_PHY3_SM; 444 445 e1000_release_swfw_sync_82575(hw, mask); 446} 447 448/** 449 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 450 * @hw: pointer to the HW structure 451 * @offset: register offset to be read 452 * @data: pointer to the read data 453 * 454 * Reads the PHY register at offset using the serial gigabit media independent 455 * interface and stores the retrieved information in data. 456 **/ 457static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 458 u16 *data) 459{ 460 s32 ret_val = -E1000_ERR_PARAM; 461 462 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 463 464 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 465 DEBUGOUT1("PHY Address %u is out of range\n", offset); 466 goto out; 467 } 468 469 ret_val = hw->phy.ops.acquire(hw); 470 if (ret_val) 471 goto out; 472 473 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 474 475 hw->phy.ops.release(hw); 476 477out: 478 return ret_val; 479} 480 481/** 482 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 483 * @hw: pointer to the HW structure 484 * @offset: register offset to write to 485 * @data: data to write at register offset 486 * 487 * Writes the data to PHY register at the offset using the serial gigabit 488 * media independent interface. 489 **/ 490static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 491 u16 data) 492{ 493 s32 ret_val = -E1000_ERR_PARAM; 494 495 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 496 497 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 498 DEBUGOUT1("PHY Address %d is out of range\n", offset); 499 goto out; 500 } 501 502 ret_val = hw->phy.ops.acquire(hw); 503 if (ret_val) 504 goto out; 505 506 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 507 508 hw->phy.ops.release(hw); 509 510out: 511 return ret_val; 512} 513 514/** 515 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 516 * @hw: pointer to the HW structure 517 * 518 * Retrieves the PHY address and ID for both PHY's which do and do not use 519 * sgmi interface. 520 **/ 521static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 522{ 523 struct e1000_phy_info *phy = &hw->phy; 524 s32 ret_val = E1000_SUCCESS; 525 u16 phy_id; 526 u32 ctrl_ext; 527 u32 mdic; 528 529 DEBUGFUNC("e1000_get_phy_id_82575"); 530 531 /* 532 * For SGMII PHYs, we try the list of possible addresses until 533 * we find one that works. For non-SGMII PHYs 534 * (e.g. integrated copper PHYs), an address of 1 should 535 * work. The result of this function should mean phy->phy_addr 536 * and phy->id are set correctly. 537 */ 538 if (!e1000_sgmii_active_82575(hw)) { 539 phy->addr = 1; 540 ret_val = e1000_get_phy_id(hw); 541 goto out; 542 } 543 544 if (e1000_sgmii_uses_mdio_82575(hw)) { 545 switch (hw->mac.type) { 546 case e1000_82575: 547 case e1000_82576: 548 mdic = E1000_READ_REG(hw, E1000_MDIC); 549 mdic &= E1000_MDIC_PHY_MASK; 550 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 551 break; 552 case e1000_82580: 553 mdic = E1000_READ_REG(hw, E1000_MDICNFG); 554 mdic &= E1000_MDICNFG_PHY_MASK; 555 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 556 break; 557 default: 558 ret_val = -E1000_ERR_PHY; 559 goto out; 560 break; 561 } 562 ret_val = e1000_get_phy_id(hw); 563 goto out; 564 } 565 566 /* Power on sgmii phy if it is disabled */ 567 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 568 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 569 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 570 E1000_WRITE_FLUSH(hw); 571 msec_delay(300); 572 573 /* 574 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 575 * Therefore, we need to test 1-7 576 */ 577 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 578 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 579 if (ret_val == E1000_SUCCESS) { 580 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 581 phy_id, 582 phy->addr); 583 /* 584 * At the time of this writing, The M88 part is 585 * the only supported SGMII PHY product. 586 */ 587 if (phy_id == M88_VENDOR) 588 break; 589 } else { 590 DEBUGOUT1("PHY address %u was unreadable\n", 591 phy->addr); 592 } 593 } 594 595 /* A valid PHY type couldn't be found. */ 596 if (phy->addr == 8) { 597 phy->addr = 0; 598 ret_val = -E1000_ERR_PHY; 599 } else { 600 ret_val = e1000_get_phy_id(hw); 601 } 602 603 /* restore previous sfp cage power state */ 604 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 605 606out: 607 return ret_val; 608} 609 610/** 611 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 612 * @hw: pointer to the HW structure 613 * 614 * Resets the PHY using the serial gigabit media independent interface. 615 **/ 616static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 617{ 618 s32 ret_val = E1000_SUCCESS; 619 620 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 621 622 /* 623 * This isn't a TRUE "hard" reset, but is the only reset 624 * available to us at this time. 625 */ 626 627 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 628 629 if (!(hw->phy.ops.write_reg)) 630 goto out; 631 632 /* 633 * SFP documentation requires the following to configure the SPF module 634 * to work on SGMII. No further documentation is given. 635 */ 636 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 637 if (ret_val) 638 goto out; 639 640 ret_val = hw->phy.ops.commit(hw); 641 642out: 643 return ret_val; 644} 645 646/** 647 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 648 * @hw: pointer to the HW structure 649 * @active: TRUE to enable LPLU, FALSE to disable 650 * 651 * Sets the LPLU D0 state according to the active flag. When 652 * activating LPLU this function also disables smart speed 653 * and vice versa. LPLU will not be activated unless the 654 * device autonegotiation advertisement meets standards of 655 * either 10 or 10/100 or 10/100/1000 at all duplexes. 656 * This is a function pointer entry point only called by 657 * PHY setup routines. 658 **/ 659static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 660{ 661 struct e1000_phy_info *phy = &hw->phy; 662 s32 ret_val = E1000_SUCCESS; 663 u16 data; 664 665 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 666 667 if (!(hw->phy.ops.read_reg)) 668 goto out; 669 670 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 671 if (ret_val) 672 goto out; 673 674 if (active) { 675 data |= IGP02E1000_PM_D0_LPLU; 676 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 677 data); 678 if (ret_val) 679 goto out; 680 681 /* When LPLU is enabled, we should disable SmartSpeed */ 682 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 683 &data); 684 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 685 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 686 data); 687 if (ret_val) 688 goto out; 689 } else { 690 data &= ~IGP02E1000_PM_D0_LPLU; 691 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 692 data); 693 /* 694 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 695 * during Dx states where the power conservation is most 696 * important. During driver activity we should enable 697 * SmartSpeed, so performance is maintained. 698 */ 699 if (phy->smart_speed == e1000_smart_speed_on) { 700 ret_val = phy->ops.read_reg(hw, 701 IGP01E1000_PHY_PORT_CONFIG, 702 &data); 703 if (ret_val) 704 goto out; 705 706 data |= IGP01E1000_PSCFR_SMART_SPEED; 707 ret_val = phy->ops.write_reg(hw, 708 IGP01E1000_PHY_PORT_CONFIG, 709 data); 710 if (ret_val) 711 goto out; 712 } else if (phy->smart_speed == e1000_smart_speed_off) { 713 ret_val = phy->ops.read_reg(hw, 714 IGP01E1000_PHY_PORT_CONFIG, 715 &data); 716 if (ret_val) 717 goto out; 718 719 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 720 ret_val = phy->ops.write_reg(hw, 721 IGP01E1000_PHY_PORT_CONFIG, 722 data); 723 if (ret_val) 724 goto out; 725 } 726 } 727 728out: 729 return ret_val; 730} 731 732/** 733 * e1000_acquire_nvm_82575 - Request for access to EEPROM 734 * @hw: pointer to the HW structure 735 * 736 * Acquire the necessary semaphores for exclusive access to the EEPROM. 737 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 738 * Return successful if access grant bit set, else clear the request for 739 * EEPROM access and return -E1000_ERR_NVM (-1). 740 **/ 741static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 742{ 743 s32 ret_val; 744 745 DEBUGFUNC("e1000_acquire_nvm_82575"); 746 747 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 748 if (ret_val) 749 goto out; 750 751 ret_val = e1000_acquire_nvm_generic(hw); 752 753 if (ret_val) 754 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 755 756out: 757 return ret_val; 758} 759 760/** 761 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 762 * @hw: pointer to the HW structure 763 * 764 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 765 * then release the semaphores acquired. 766 **/ 767static void e1000_release_nvm_82575(struct e1000_hw *hw) 768{ 769 DEBUGFUNC("e1000_release_nvm_82575"); 770 771 e1000_release_nvm_generic(hw); 772 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 773} 774 775/** 776 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 777 * @hw: pointer to the HW structure 778 * @mask: specifies which semaphore to acquire 779 * 780 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 781 * will also specify which port we're acquiring the lock for. 782 **/ 783static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 784{ 785 u32 swfw_sync; 786 u32 swmask = mask; 787 u32 fwmask = mask << 16; 788 s32 ret_val = E1000_SUCCESS; 789 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 790 791 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 792 793 while (i < timeout) { 794 if (e1000_get_hw_semaphore_generic(hw)) { 795 ret_val = -E1000_ERR_SWFW_SYNC; 796 goto out; 797 } 798 799 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 800 if (!(swfw_sync & (fwmask | swmask))) 801 break; 802 803 /* 804 * Firmware currently using resource (fwmask) 805 * or other software thread using resource (swmask) 806 */ 807 e1000_put_hw_semaphore_generic(hw); 808 msec_delay_irq(5); 809 i++; 810 } 811 812 if (i == timeout) { 813 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 814 ret_val = -E1000_ERR_SWFW_SYNC; 815 goto out; 816 } 817 818 swfw_sync |= swmask; 819 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 820 821 e1000_put_hw_semaphore_generic(hw); 822 823out: 824 return ret_val; 825} 826 827/** 828 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 829 * @hw: pointer to the HW structure 830 * @mask: specifies which semaphore to acquire 831 * 832 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 833 * will also specify which port we're releasing the lock for. 834 **/ 835static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 836{ 837 u32 swfw_sync; 838 839 DEBUGFUNC("e1000_release_swfw_sync_82575"); 840 841 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 842 /* Empty */ 843 844 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 845 swfw_sync &= ~mask; 846 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 847 848 e1000_put_hw_semaphore_generic(hw); 849} 850 851/** 852 * e1000_get_cfg_done_82575 - Read config done bit 853 * @hw: pointer to the HW structure 854 * 855 * Read the management control register for the config done bit for 856 * completion status. NOTE: silicon which is EEPROM-less will fail trying 857 * to read the config done bit, so an error is *ONLY* logged and returns 858 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 859 * would not be able to be reset or change link. 860 **/ 861static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 862{ 863 s32 timeout = PHY_CFG_TIMEOUT; 864 s32 ret_val = E1000_SUCCESS; 865 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 866 867 DEBUGFUNC("e1000_get_cfg_done_82575"); 868 869 if (hw->bus.func == E1000_FUNC_1) 870 mask = E1000_NVM_CFG_DONE_PORT_1; 871 else if (hw->bus.func == E1000_FUNC_2) 872 mask = E1000_NVM_CFG_DONE_PORT_2; 873 else if (hw->bus.func == E1000_FUNC_3) 874 mask = E1000_NVM_CFG_DONE_PORT_3; 875 while (timeout) { 876 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 877 break; 878 msec_delay(1); 879 timeout--; 880 } 881 if (!timeout) 882 DEBUGOUT("MNG configuration cycle has not completed.\n"); 883 884 /* If EEPROM is not marked present, init the PHY manually */ 885 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 886 (hw->phy.type == e1000_phy_igp_3)) 887 e1000_phy_init_script_igp3(hw); 888 889 return ret_val; 890} 891 892/** 893 * e1000_get_link_up_info_82575 - Get link speed/duplex info 894 * @hw: pointer to the HW structure 895 * @speed: stores the current speed 896 * @duplex: stores the current duplex 897 * 898 * This is a wrapper function, if using the serial gigabit media independent 899 * interface, use PCS to retrieve the link speed and duplex information. 900 * Otherwise, use the generic function to get the link speed and duplex info. 901 **/ 902static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 903 u16 *duplex) 904{ 905 s32 ret_val; 906 907 DEBUGFUNC("e1000_get_link_up_info_82575"); 908 909 if (hw->phy.media_type != e1000_media_type_copper) 910 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 911 duplex); 912 else 913 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 914 duplex); 915 916 return ret_val; 917} 918 919/** 920 * e1000_check_for_link_82575 - Check for link 921 * @hw: pointer to the HW structure 922 * 923 * If sgmii is enabled, then use the pcs register to determine link, otherwise 924 * use the generic interface for determining link. 925 **/ 926static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 927{ 928 s32 ret_val; 929 u16 speed, duplex; 930 931 DEBUGFUNC("e1000_check_for_link_82575"); 932 933 if (hw->phy.media_type != e1000_media_type_copper) { 934 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 935 &duplex); 936 /* 937 * Use this flag to determine if link needs to be checked or 938 * not. If we have link clear the flag so that we do not 939 * continue to check for link. 940 */ 941 hw->mac.get_link_status = !hw->mac.serdes_has_link; 942 } else { 943 ret_val = e1000_check_for_copper_link_generic(hw); 944 } 945 946 return ret_val; 947} 948 949/** 950 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 951 * @hw: pointer to the HW structure 952 **/ 953static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 954{ 955 u32 reg; 956 957 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 958 959 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 960 !e1000_sgmii_active_82575(hw)) 961 return; 962 963 /* Enable PCS to turn on link */ 964 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 965 reg |= E1000_PCS_CFG_PCS_EN; 966 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 967 968 /* Power up the laser */ 969 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 970 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 971 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 972 973 /* flush the write to verify completion */ 974 E1000_WRITE_FLUSH(hw); 975 msec_delay(1); 976} 977 978/** 979 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 980 * @hw: pointer to the HW structure 981 * @speed: stores the current speed 982 * @duplex: stores the current duplex 983 * 984 * Using the physical coding sub-layer (PCS), retrieve the current speed and 985 * duplex, then store the values in the pointers provided. 986 **/ 987static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 988 u16 *speed, u16 *duplex) 989{ 990 struct e1000_mac_info *mac = &hw->mac; 991 u32 pcs; 992 993 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 994 995 /* Set up defaults for the return values of this function */ 996 mac->serdes_has_link = FALSE; 997 *speed = 0; 998 *duplex = 0; 999 1000 /* 1001 * Read the PCS Status register for link state. For non-copper mode, 1002 * the status register is not accurate. The PCS status register is 1003 * used instead. 1004 */ 1005 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1006 1007 /* 1008 * The link up bit determines when link is up on autoneg. The sync ok 1009 * gets set once both sides sync up and agree upon link. Stable link 1010 * can be determined by checking for both link up and link sync ok 1011 */ 1012 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1013 mac->serdes_has_link = TRUE; 1014 1015 /* Detect and store PCS speed */ 1016 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 1017 *speed = SPEED_1000; 1018 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 1019 *speed = SPEED_100; 1020 } else { 1021 *speed = SPEED_10; 1022 } 1023 1024 /* Detect and store PCS duplex */ 1025 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 1026 *duplex = FULL_DUPLEX; 1027 } else { 1028 *duplex = HALF_DUPLEX; 1029 } 1030 } 1031 1032 return E1000_SUCCESS; 1033} 1034 1035/** 1036 * e1000_shutdown_serdes_link_82575 - Remove link during power down 1037 * @hw: pointer to the HW structure 1038 * 1039 * In the case of serdes shut down sfp and PCS on driver unload 1040 * when management pass thru is not enabled. 1041 **/ 1042void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1043{ 1044 u32 reg; 1045 1046 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1047 1048 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1049 !e1000_sgmii_active_82575(hw)) 1050 return; 1051 1052 if (!e1000_enable_mng_pass_thru(hw)) { 1053 /* Disable PCS to turn off link */ 1054 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1055 reg &= ~E1000_PCS_CFG_PCS_EN; 1056 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1057 1058 /* shutdown the laser */ 1059 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1060 reg |= E1000_CTRL_EXT_SDP3_DATA; 1061 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1062 1063 /* flush the write to verify completion */ 1064 E1000_WRITE_FLUSH(hw); 1065 msec_delay(1); 1066 } 1067 1068 return; 1069} 1070 1071/** 1072 * e1000_reset_hw_82575 - Reset hardware 1073 * @hw: pointer to the HW structure 1074 * 1075 * This resets the hardware into a known state. 1076 **/ 1077static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1078{ 1079 u32 ctrl, icr; 1080 s32 ret_val; 1081 1082 DEBUGFUNC("e1000_reset_hw_82575"); 1083 1084 /* 1085 * Prevent the PCI-E bus from sticking if there is no TLP connection 1086 * on the last TLP read/write transaction when MAC is reset. 1087 */ 1088 ret_val = e1000_disable_pcie_master_generic(hw); 1089 if (ret_val) { 1090 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1091 } 1092 1093 /* set the completion timeout for interface */ 1094 ret_val = e1000_set_pcie_completion_timeout(hw); 1095 if (ret_val) { 1096 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1097 } 1098 1099 DEBUGOUT("Masking off all interrupts\n"); 1100 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1101 1102 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1103 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1104 E1000_WRITE_FLUSH(hw); 1105 1106 msec_delay(10); 1107 1108 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1109 1110 DEBUGOUT("Issuing a global reset to MAC\n"); 1111 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1112 1113 ret_val = e1000_get_auto_rd_done_generic(hw); 1114 if (ret_val) { 1115 /* 1116 * When auto config read does not complete, do not 1117 * return with an error. This can happen in situations 1118 * where there is no eeprom and prevents getting link. 1119 */ 1120 DEBUGOUT("Auto Read Done did not complete\n"); 1121 } 1122 1123 /* If EEPROM is not present, run manual init scripts */ 1124 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1125 e1000_reset_init_script_82575(hw); 1126 1127 /* Clear any pending interrupt events. */ 1128 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1129 icr = E1000_READ_REG(hw, E1000_ICR); 1130 1131 /* Install any alternate MAC address into RAR0 */ 1132 ret_val = e1000_check_alt_mac_addr_generic(hw); 1133 1134 return ret_val; 1135} 1136 1137/** 1138 * e1000_init_hw_82575 - Initialize hardware 1139 * @hw: pointer to the HW structure 1140 * 1141 * This inits the hardware readying it for operation. 1142 **/ 1143static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1144{ 1145 struct e1000_mac_info *mac = &hw->mac; 1146 s32 ret_val; 1147 u16 i, rar_count = mac->rar_entry_count; 1148 1149 DEBUGFUNC("e1000_init_hw_82575"); 1150 1151 /* Initialize identification LED */ 1152 ret_val = mac->ops.id_led_init(hw); 1153 if (ret_val) { 1154 DEBUGOUT("Error initializing identification LED\n"); 1155 /* This is not fatal and we should not stop init due to this */ 1156 } 1157 1158 /* Disabling VLAN filtering */ 1159 DEBUGOUT("Initializing the IEEE VLAN\n"); 1160 mac->ops.clear_vfta(hw); 1161 1162 /* Setup the receive address */ 1163 e1000_init_rx_addrs_generic(hw, rar_count); 1164 1165 /* Zero out the Multicast HASH table */ 1166 DEBUGOUT("Zeroing the MTA\n"); 1167 for (i = 0; i < mac->mta_reg_count; i++) 1168 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1169 1170 /* Zero out the Unicast HASH table */ 1171 DEBUGOUT("Zeroing the UTA\n"); 1172 for (i = 0; i < mac->uta_reg_count; i++) 1173 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1174 1175 /* Setup link and flow control */ 1176 ret_val = mac->ops.setup_link(hw); 1177 1178 /* 1179 * Clear all of the statistics registers (clear on read). It is 1180 * important that we do this after we have tried to establish link 1181 * because the symbol error count will increment wildly if there 1182 * is no link. 1183 */ 1184 e1000_clear_hw_cntrs_82575(hw); 1185 1186 return ret_val; 1187} 1188 1189/** 1190 * e1000_setup_copper_link_82575 - Configure copper link settings 1191 * @hw: pointer to the HW structure 1192 * 1193 * Configures the link for auto-neg or forced speed and duplex. Then we check 1194 * for link, once link is established calls to configure collision distance 1195 * and flow control are called. 1196 **/ 1197static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1198{ 1199 u32 ctrl; 1200 s32 ret_val; 1201 1202 DEBUGFUNC("e1000_setup_copper_link_82575"); 1203 1204 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1205 ctrl |= E1000_CTRL_SLU; 1206 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1207 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1208 1209 ret_val = e1000_setup_serdes_link_82575(hw); 1210 if (ret_val) 1211 goto out; 1212 1213 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1214 /* allow time for SFP cage time to power up phy */ 1215 msec_delay(300); 1216 1217 ret_val = hw->phy.ops.reset(hw); 1218 if (ret_val) { 1219 DEBUGOUT("Error resetting the PHY.\n"); 1220 goto out; 1221 } 1222 } 1223 switch (hw->phy.type) { 1224 case e1000_phy_m88: 1225 ret_val = e1000_copper_link_setup_m88(hw); 1226 break; 1227 case e1000_phy_igp_3: 1228 ret_val = e1000_copper_link_setup_igp(hw); 1229 break; 1230 case e1000_phy_82580: 1231 ret_val = e1000_copper_link_setup_82577(hw); 1232 break; 1233 default: 1234 ret_val = -E1000_ERR_PHY; 1235 break; 1236 } 1237 1238 if (ret_val) 1239 goto out; 1240 1241 ret_val = e1000_setup_copper_link_generic(hw); 1242out: 1243 return ret_val; 1244} 1245 1246/** 1247 * e1000_setup_serdes_link_82575 - Setup link for serdes 1248 * @hw: pointer to the HW structure 1249 * 1250 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1251 * used on copper connections where the serialized gigabit media independent 1252 * interface (sgmii), or serdes fiber is being used. Configures the link 1253 * for auto-negotiation or forces speed/duplex. 1254 **/ 1255static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1256{ 1257 u32 ctrl_ext, ctrl_reg, reg; 1258 bool pcs_autoneg; 1259 1260 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1261 1262 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1263 !e1000_sgmii_active_82575(hw)) 1264 return E1000_SUCCESS; 1265 1266 /* 1267 * On the 82575, SerDes loopback mode persists until it is 1268 * explicitly turned off or a power cycle is performed. A read to 1269 * the register does not indicate its status. Therefore, we ensure 1270 * loopback mode is disabled during initialization. 1271 */ 1272 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1273 1274 /* power on the sfp cage if present */ 1275 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1276 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1277 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1278 1279 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1280 ctrl_reg |= E1000_CTRL_SLU; 1281 1282 /* set both sw defined pins on 82575/82576*/ 1283 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1284 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1285 1286 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1287 1288 /* default pcs_autoneg to the same setting as mac autoneg */ 1289 pcs_autoneg = hw->mac.autoneg; 1290 1291 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1292 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1293 /* sgmii mode lets the phy handle forcing speed/duplex */ 1294 pcs_autoneg = TRUE; 1295 /* autoneg time out should be disabled for SGMII mode */ 1296 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1297 break; 1298 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1299 /* disable PCS autoneg and support parallel detect only */ 1300 pcs_autoneg = FALSE; 1301 /* fall through to default case */ 1302 default: 1303 /* 1304 * non-SGMII modes only supports a speed of 1000/Full for the 1305 * link so it is best to just force the MAC and let the pcs 1306 * link either autoneg or be forced to 1000/Full 1307 */ 1308 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1309 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1310 1311 /* set speed of 1000/Full if speed/duplex is forced */ 1312 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1313 break; 1314 } 1315 1316 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1317 1318 /* 1319 * New SerDes mode allows for forcing speed or autonegotiating speed 1320 * at 1gb. Autoneg should be default set by most drivers. This is the 1321 * mode that will be compatible with older link partners and switches. 1322 * However, both are supported by the hardware and some drivers/tools. 1323 */ 1324 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1325 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1326 1327 /* 1328 * We force flow control to prevent the CTRL register values from being 1329 * overwritten by the autonegotiated flow control values 1330 */ 1331 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1332 1333 if (pcs_autoneg) { 1334 /* Set PCS register for autoneg */ 1335 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1336 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1337 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1338 } else { 1339 /* Set PCS register for forced link */ 1340 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1341 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1342 } 1343 1344 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1345 1346 if (!e1000_sgmii_active_82575(hw)) 1347 e1000_force_mac_fc_generic(hw); 1348 1349 return E1000_SUCCESS; 1350} 1351 1352/** 1353 * e1000_valid_led_default_82575 - Verify a valid default LED config 1354 * @hw: pointer to the HW structure 1355 * @data: pointer to the NVM (EEPROM) 1356 * 1357 * Read the EEPROM for the current default LED configuration. If the 1358 * LED configuration is not valid, set to a valid LED configuration. 1359 **/ 1360static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1361{ 1362 s32 ret_val; 1363 1364 DEBUGFUNC("e1000_valid_led_default_82575"); 1365 1366 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1367 if (ret_val) { 1368 DEBUGOUT("NVM Read Error\n"); 1369 goto out; 1370 } 1371 1372 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1373 switch(hw->phy.media_type) { 1374 case e1000_media_type_internal_serdes: 1375 *data = ID_LED_DEFAULT_82575_SERDES; 1376 break; 1377 case e1000_media_type_copper: 1378 default: 1379 *data = ID_LED_DEFAULT; 1380 break; 1381 } 1382 } 1383out: 1384 return ret_val; 1385} 1386 1387/** 1388 * e1000_sgmii_active_82575 - Return sgmii state 1389 * @hw: pointer to the HW structure 1390 * 1391 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1392 * which can be enabled for use in the embedded applications. Simply 1393 * return the current state of the sgmii interface. 1394 **/ 1395static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1396{ 1397 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1398 return dev_spec->sgmii_active; 1399} 1400 1401/** 1402 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1403 * @hw: pointer to the HW structure 1404 * 1405 * Inits recommended HW defaults after a reset when there is no EEPROM 1406 * detected. This is only for the 82575. 1407 **/ 1408static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1409{ 1410 DEBUGFUNC("e1000_reset_init_script_82575"); 1411 1412 if (hw->mac.type == e1000_82575) { 1413 DEBUGOUT("Running reset init script for 82575\n"); 1414 /* SerDes configuration via SERDESCTRL */ 1415 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1416 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1417 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1418 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1419 1420 /* CCM configuration via CCMCTL register */ 1421 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1422 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1423 1424 /* PCIe lanes configuration */ 1425 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1426 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1427 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1428 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1429 1430 /* PCIe PLL Configuration */ 1431 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1432 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1433 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1434 } 1435 1436 return E1000_SUCCESS; 1437} 1438 1439/** 1440 * e1000_read_mac_addr_82575 - Read device MAC address 1441 * @hw: pointer to the HW structure 1442 **/ 1443static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1444{ 1445 s32 ret_val = E1000_SUCCESS; 1446 1447 DEBUGFUNC("e1000_read_mac_addr_82575"); 1448 1449 /* 1450 * If there's an alternate MAC address place it in RAR0 1451 * so that it will override the Si installed default perm 1452 * address. 1453 */ 1454 ret_val = e1000_check_alt_mac_addr_generic(hw); 1455 if (ret_val) 1456 goto out; 1457 1458 ret_val = e1000_read_mac_addr_generic(hw); 1459 1460out: 1461 return ret_val; 1462} 1463 1464/** 1465 * e1000_config_collision_dist_82575 - Configure collision distance 1466 * @hw: pointer to the HW structure 1467 * 1468 * Configures the collision distance to the default value and is used 1469 * during link setup. 1470 **/ 1471static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1472{ 1473 u32 tctl_ext; 1474 1475 DEBUGFUNC("e1000_config_collision_dist_82575"); 1476 1477 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1478 1479 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1480 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1481 1482 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1483 E1000_WRITE_FLUSH(hw); 1484} 1485 1486/** 1487 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1488 * @hw: pointer to the HW structure 1489 * 1490 * In the case of a PHY power down to save power, or to turn off link during a 1491 * driver unload, or wake on lan is not enabled, remove the link. 1492 **/ 1493static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1494{ 1495 struct e1000_phy_info *phy = &hw->phy; 1496 1497 if (!(phy->ops.check_reset_block)) 1498 return; 1499 1500 /* If the management interface is not enabled, then power down */ 1501 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 1502 e1000_power_down_phy_copper(hw); 1503 1504 return; 1505} 1506 1507/** 1508 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1509 * @hw: pointer to the HW structure 1510 * 1511 * Clears the hardware counters by reading the counter registers. 1512 **/ 1513static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1514{ 1515 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1516 1517 e1000_clear_hw_cntrs_base_generic(hw); 1518 1519 E1000_READ_REG(hw, E1000_PRC64); 1520 E1000_READ_REG(hw, E1000_PRC127); 1521 E1000_READ_REG(hw, E1000_PRC255); 1522 E1000_READ_REG(hw, E1000_PRC511); 1523 E1000_READ_REG(hw, E1000_PRC1023); 1524 E1000_READ_REG(hw, E1000_PRC1522); 1525 E1000_READ_REG(hw, E1000_PTC64); 1526 E1000_READ_REG(hw, E1000_PTC127); 1527 E1000_READ_REG(hw, E1000_PTC255); 1528 E1000_READ_REG(hw, E1000_PTC511); 1529 E1000_READ_REG(hw, E1000_PTC1023); 1530 E1000_READ_REG(hw, E1000_PTC1522); 1531 1532 E1000_READ_REG(hw, E1000_ALGNERRC); 1533 E1000_READ_REG(hw, E1000_RXERRC); 1534 E1000_READ_REG(hw, E1000_TNCRS); 1535 E1000_READ_REG(hw, E1000_CEXTERR); 1536 E1000_READ_REG(hw, E1000_TSCTC); 1537 E1000_READ_REG(hw, E1000_TSCTFC); 1538 1539 E1000_READ_REG(hw, E1000_MGTPRC); 1540 E1000_READ_REG(hw, E1000_MGTPDC); 1541 E1000_READ_REG(hw, E1000_MGTPTC); 1542 1543 E1000_READ_REG(hw, E1000_IAC); 1544 E1000_READ_REG(hw, E1000_ICRXOC); 1545 1546 E1000_READ_REG(hw, E1000_ICRXPTC); 1547 E1000_READ_REG(hw, E1000_ICRXATC); 1548 E1000_READ_REG(hw, E1000_ICTXPTC); 1549 E1000_READ_REG(hw, E1000_ICTXATC); 1550 E1000_READ_REG(hw, E1000_ICTXQEC); 1551 E1000_READ_REG(hw, E1000_ICTXQMTC); 1552 E1000_READ_REG(hw, E1000_ICRXDMTC); 1553 1554 E1000_READ_REG(hw, E1000_CBTMPC); 1555 E1000_READ_REG(hw, E1000_HTDPMC); 1556 E1000_READ_REG(hw, E1000_CBRMPC); 1557 E1000_READ_REG(hw, E1000_RPTHC); 1558 E1000_READ_REG(hw, E1000_HGPTC); 1559 E1000_READ_REG(hw, E1000_HTCBDPC); 1560 E1000_READ_REG(hw, E1000_HGORCL); 1561 E1000_READ_REG(hw, E1000_HGORCH); 1562 E1000_READ_REG(hw, E1000_HGOTCL); 1563 E1000_READ_REG(hw, E1000_HGOTCH); 1564 E1000_READ_REG(hw, E1000_LENERRS); 1565 1566 /* This register should not be read in copper configurations */ 1567 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1568 e1000_sgmii_active_82575(hw)) 1569 E1000_READ_REG(hw, E1000_SCVPC); 1570} 1571 1572/** 1573 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1574 * @hw: pointer to the HW structure 1575 * 1576 * After rx enable if managability is enabled then there is likely some 1577 * bad data at the start of the fifo and possibly in the DMA fifo. This 1578 * function clears the fifos and flushes any packets that came in as rx was 1579 * being enabled. 1580 **/ 1581void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1582{ 1583 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1584 int i, ms_wait; 1585 1586 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1587 if (hw->mac.type != e1000_82575 || 1588 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1589 return; 1590 1591 /* Disable all RX queues */ 1592 for (i = 0; i < 4; i++) { 1593 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1594 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1595 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1596 } 1597 /* Poll all queues to verify they have shut down */ 1598 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1599 msec_delay(1); 1600 rx_enabled = 0; 1601 for (i = 0; i < 4; i++) 1602 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1603 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1604 break; 1605 } 1606 1607 if (ms_wait == 10) 1608 DEBUGOUT("Queue disable timed out after 10ms\n"); 1609 1610 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1611 * incoming packets are rejected. Set enable and wait 2ms so that 1612 * any packet that was coming in as RCTL.EN was set is flushed 1613 */ 1614 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1615 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1616 1617 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1618 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1619 1620 rctl = E1000_READ_REG(hw, E1000_RCTL); 1621 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1622 temp_rctl |= E1000_RCTL_LPE; 1623 1624 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1625 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1626 E1000_WRITE_FLUSH(hw); 1627 msec_delay(2); 1628 1629 /* Enable RX queues that were previously enabled and restore our 1630 * previous state 1631 */ 1632 for (i = 0; i < 4; i++) 1633 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1634 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1635 E1000_WRITE_FLUSH(hw); 1636 1637 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1638 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1639 1640 /* Flush receive errors generated by workaround */ 1641 E1000_READ_REG(hw, E1000_ROC); 1642 E1000_READ_REG(hw, E1000_RNBC); 1643 E1000_READ_REG(hw, E1000_MPC); 1644} 1645 1646/** 1647 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1648 * @hw: pointer to the HW structure 1649 * 1650 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1651 * however the hardware default for these parts is 500us to 1ms which is less 1652 * than the 10ms recommended by the pci-e spec. To address this we need to 1653 * increase the value to either 10ms to 200ms for capability version 1 config, 1654 * or 16ms to 55ms for version 2. 1655 **/ 1656static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1657{ 1658 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1659 s32 ret_val = E1000_SUCCESS; 1660 u16 pcie_devctl2; 1661 1662 /* only take action if timeout value is defaulted to 0 */ 1663 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1664 goto out; 1665 1666 /* 1667 * if capababilities version is type 1 we can write the 1668 * timeout of 10ms to 200ms through the GCR register 1669 */ 1670 if (!(gcr & E1000_GCR_CAP_VER2)) { 1671 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1672 goto out; 1673 } 1674 1675 /* 1676 * for version 2 capabilities we need to write the config space 1677 * directly in order to set the completion timeout value for 1678 * 16ms to 55ms 1679 */ 1680 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1681 &pcie_devctl2); 1682 if (ret_val) 1683 goto out; 1684 1685 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1686 1687 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1688 &pcie_devctl2); 1689out: 1690 /* disable completion timeout resend */ 1691 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1692 1693 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1694 return ret_val; 1695} 1696 1697 1698/** 1699 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 1700 * @hw: pointer to the hardware struct 1701 * @enable: state to enter, either enabled or disabled 1702 * @pf: Physical Function pool - do not set anti-spoofing for the PF 1703 * 1704 * enables/disables L2 switch anti-spoofing functionality. 1705 **/ 1706void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 1707{ 1708 u32 dtxswc; 1709 1710 switch (hw->mac.type) { 1711 case e1000_82576: 1712 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1713 if (enable) { 1714 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 1715 E1000_DTXSWC_VLAN_SPOOF_MASK); 1716 /* The PF can spoof - it has to in order to 1717 * support emulation mode NICs */ 1718 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 1719 } else { 1720 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 1721 E1000_DTXSWC_VLAN_SPOOF_MASK); 1722 } 1723 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1724 break; 1725 default: 1726 break; 1727 } 1728} 1729 1730/** 1731 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 1732 * @hw: pointer to the hardware struct 1733 * @enable: state to enter, either enabled or disabled 1734 * 1735 * enables/disables L2 switch loopback functionality. 1736 **/ 1737void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1738{ 1739 u32 dtxswc; 1740 1741 switch (hw->mac.type) { 1742 case e1000_82576: 1743 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1744 if (enable) 1745 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1746 else 1747 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1748 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1749 break; 1750 default: 1751 /* Currently no other hardware supports loopback */ 1752 break; 1753 } 1754 1755 1756} 1757 1758/** 1759 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 1760 * @hw: pointer to the hardware struct 1761 * @enable: state to enter, either enabled or disabled 1762 * 1763 * enables/disables replication of packets across multiple pools. 1764 **/ 1765void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1766{ 1767 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 1768 1769 if (enable) 1770 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 1771 else 1772 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 1773 1774 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 1775} 1776 1777/** 1778 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 1779 * @hw: pointer to the HW structure 1780 * @offset: register offset to be read 1781 * @data: pointer to the read data 1782 * 1783 * Reads the MDI control register in the PHY at offset and stores the 1784 * information read to data. 1785 **/ 1786static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 1787{ 1788 s32 ret_val; 1789 1790 DEBUGFUNC("e1000_read_phy_reg_82580"); 1791 1792 ret_val = hw->phy.ops.acquire(hw); 1793 if (ret_val) 1794 goto out; 1795 1796 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 1797 1798 hw->phy.ops.release(hw); 1799 1800out: 1801 return ret_val; 1802} 1803 1804/** 1805 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 1806 * @hw: pointer to the HW structure 1807 * @offset: register offset to write to 1808 * @data: data to write to register at offset 1809 * 1810 * Writes data to MDI control register in the PHY at offset. 1811 **/ 1812static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 1813{ 1814 s32 ret_val; 1815 1816 DEBUGFUNC("e1000_write_phy_reg_82580"); 1817 1818 ret_val = hw->phy.ops.acquire(hw); 1819 if (ret_val) 1820 goto out; 1821 1822 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 1823 1824 hw->phy.ops.release(hw); 1825 1826out: 1827 return ret_val; 1828} 1829 1830/** 1831 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 1832 * @hw: pointer to the HW structure 1833 * 1834 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 1835 * the values found in the EEPROM. This addresses an issue in which these 1836 * bits are not restored from EEPROM after reset. 1837 **/ 1838static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 1839{ 1840 s32 ret_val = E1000_SUCCESS; 1841 u32 mdicnfg; 1842 u16 nvm_data; 1843 1844 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 1845 1846 if (hw->mac.type != e1000_82580) 1847 goto out; 1848 if (!e1000_sgmii_active_82575(hw)) 1849 goto out; 1850 1851 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 1852 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 1853 &nvm_data); 1854 if (ret_val) { 1855 DEBUGOUT("NVM Read Error\n"); 1856 goto out; 1857 } 1858 1859 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 1860 if (nvm_data & NVM_WORD24_EXT_MDIO) 1861 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1862 if (nvm_data & NVM_WORD24_COM_MDIO) 1863 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1864 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1865out: 1866 return ret_val; 1867} 1868 1869/** 1870 * e1000_reset_hw_82580 - Reset hardware 1871 * @hw: pointer to the HW structure 1872 * 1873 * This resets function or entire device (all ports, etc.) 1874 * to a known state. 1875 **/ 1876static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 1877{ 1878 s32 ret_val = E1000_SUCCESS; 1879 /* BH SW mailbox bit in SW_FW_SYNC */ 1880 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 1881 u32 ctrl, icr; 1882 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 1883 1884 DEBUGFUNC("e1000_reset_hw_82580"); 1885 1886 hw->dev_spec._82575.global_device_reset = FALSE; 1887 1888 /* Get current control state. */ 1889 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1890 1891 /* 1892 * Prevent the PCI-E bus from sticking if there is no TLP connection 1893 * on the last TLP read/write transaction when MAC is reset. 1894 */ 1895 ret_val = e1000_disable_pcie_master_generic(hw); 1896 if (ret_val) 1897 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1898 1899 DEBUGOUT("Masking off all interrupts\n"); 1900 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1901 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1902 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1903 E1000_WRITE_FLUSH(hw); 1904 1905 msec_delay(10); 1906 1907 /* Determine whether or not a global dev reset is requested */ 1908 if (global_device_reset && 1909 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask)) 1910 global_device_reset = FALSE; 1911 1912 if (global_device_reset && 1913 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 1914 ctrl |= E1000_CTRL_DEV_RST; 1915 else 1916 ctrl |= E1000_CTRL_RST; 1917 1918 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1919 1920 /* Add delay to insure DEV_RST has time to complete */ 1921 if (global_device_reset) 1922 msec_delay(5); 1923 1924 ret_val = e1000_get_auto_rd_done_generic(hw); 1925 if (ret_val) { 1926 /* 1927 * When auto config read does not complete, do not 1928 * return with an error. This can happen in situations 1929 * where there is no eeprom and prevents getting link. 1930 */ 1931 DEBUGOUT("Auto Read Done did not complete\n"); 1932 } 1933 1934 /* If EEPROM is not present, run manual init scripts */ 1935 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1936 e1000_reset_init_script_82575(hw); 1937 1938 /* clear global device reset status bit */ 1939 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 1940 1941 /* Clear any pending interrupt events. */ 1942 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1943 icr = E1000_READ_REG(hw, E1000_ICR); 1944 1945 ret_val = e1000_reset_mdicnfg_82580(hw); 1946 if (ret_val) 1947 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 1948 1949 /* Install any alternate MAC address into RAR0 */ 1950 ret_val = e1000_check_alt_mac_addr_generic(hw); 1951 1952 /* Release semaphore */ 1953 if (global_device_reset) 1954 e1000_release_swfw_sync_82575(hw, swmbsw_mask); 1955 1956 return ret_val; 1957} 1958 1959/** 1960 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 1961 * @data: data received by reading RXPBS register 1962 * 1963 * The 82580 uses a table based approach for packet buffer allocation sizes. 1964 * This function converts the retrieved value into the correct table value 1965 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 1966 * 0x0 36 72 144 1 2 4 8 16 1967 * 0x8 35 70 140 rsv rsv rsv rsv rsv 1968 */ 1969u16 e1000_rxpbs_adjust_82580(u32 data) 1970{ 1971 u16 ret_val = 0; 1972 1973 if (data < E1000_82580_RXPBS_TABLE_SIZE) 1974 ret_val = e1000_82580_rxpbs_table[data]; 1975 1976 return ret_val; 1977} 1978