e1000_82575.c revision 203049
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 203049 2010-01-26 22:32:22Z jfv $*/ 34 35/* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82575GB Gigabit Network Connection 40 * 82576 Gigabit Network Connection 41 * 82576 Quad Port Gigabit Mezzanine Adapter 42 */ 43 44#include "e1000_api.h" 45 46static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 47static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 48static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 49static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 50static void e1000_release_phy_82575(struct e1000_hw *hw); 51static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 52static void e1000_release_nvm_82575(struct e1000_hw *hw); 53static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 54static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 56 u16 *duplex); 57static s32 e1000_init_hw_82575(struct e1000_hw *hw); 58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 60 u16 *data); 61static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 62static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 63static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 64 u32 offset, u16 *data); 65static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 66 u32 offset, u16 data); 67static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 68 bool active); 69static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 70static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 71static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 72static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 73 u32 offset, u16 data); 74static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 75static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 76static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 77 u16 *speed, u16 *duplex); 78static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 79static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 80static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 81static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 82static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 83static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 84static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 85static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 86static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 87static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 88 89static const u16 e1000_82580_rxpbs_table[] = 90 { 36, 72, 144, 1, 2, 4, 8, 16, 91 35, 70, 140 }; 92#define E1000_82580_RXPBS_TABLE_SIZE \ 93 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 94 95/** 96 * e1000_init_phy_params_82575 - Init PHY func ptrs. 97 * @hw: pointer to the HW structure 98 **/ 99static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 100{ 101 struct e1000_phy_info *phy = &hw->phy; 102 s32 ret_val = E1000_SUCCESS; 103 104 DEBUGFUNC("e1000_init_phy_params_82575"); 105 106 if (hw->phy.media_type != e1000_media_type_copper) { 107 phy->type = e1000_phy_none; 108 goto out; 109 } 110 111 phy->ops.power_up = e1000_power_up_phy_copper; 112 phy->ops.power_down = e1000_power_down_phy_copper_82575; 113 114 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 115 phy->reset_delay_us = 100; 116 117 phy->ops.acquire = e1000_acquire_phy_82575; 118 phy->ops.check_reset_block = e1000_check_reset_block_generic; 119 phy->ops.commit = e1000_phy_sw_reset_generic; 120 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 121 phy->ops.release = e1000_release_phy_82575; 122 123 if (e1000_sgmii_active_82575(hw)) { 124 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 125 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 126 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 127 } else if (hw->mac.type >= e1000_82580) { 128 phy->ops.reset = e1000_phy_hw_reset_generic; 129 phy->ops.read_reg = e1000_read_phy_reg_82580; 130 phy->ops.write_reg = e1000_write_phy_reg_82580; 131 } else { 132 phy->ops.reset = e1000_phy_hw_reset_generic; 133 phy->ops.read_reg = e1000_read_phy_reg_igp; 134 phy->ops.write_reg = e1000_write_phy_reg_igp; 135 } 136 137 /* Set phy->phy_addr and phy->id. */ 138 ret_val = e1000_get_phy_id_82575(hw); 139 140 /* Verify phy id and set remaining function pointers */ 141 switch (phy->id) { 142 case M88E1111_I_PHY_ID: 143 phy->type = e1000_phy_m88; 144 phy->ops.check_polarity = e1000_check_polarity_m88; 145 phy->ops.get_info = e1000_get_phy_info_m88; 146 phy->ops.get_cable_length = e1000_get_cable_length_m88; 147 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 148 break; 149 case IGP03E1000_E_PHY_ID: 150 case IGP04E1000_E_PHY_ID: 151 phy->type = e1000_phy_igp_3; 152 phy->ops.check_polarity = e1000_check_polarity_igp; 153 phy->ops.get_info = e1000_get_phy_info_igp; 154 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 155 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 156 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 157 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 158 break; 159 case I82580_I_PHY_ID: 160 phy->type = e1000_phy_82580; 161 phy->ops.check_polarity = e1000_check_polarity_82577; 162 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; 163 phy->ops.get_cable_length = e1000_get_cable_length_82577; 164 phy->ops.get_info = e1000_get_phy_info_82577; 165 break; 166 default: 167 ret_val = -E1000_ERR_PHY; 168 goto out; 169 } 170 171out: 172 return ret_val; 173} 174 175/** 176 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 177 * @hw: pointer to the HW structure 178 **/ 179static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 180{ 181 struct e1000_nvm_info *nvm = &hw->nvm; 182 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 183 u16 size; 184 185 DEBUGFUNC("e1000_init_nvm_params_82575"); 186 187 nvm->opcode_bits = 8; 188 nvm->delay_usec = 1; 189 switch (nvm->override) { 190 case e1000_nvm_override_spi_large: 191 nvm->page_size = 32; 192 nvm->address_bits = 16; 193 break; 194 case e1000_nvm_override_spi_small: 195 nvm->page_size = 8; 196 nvm->address_bits = 8; 197 break; 198 default: 199 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 200 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 201 break; 202 } 203 204 nvm->type = e1000_nvm_eeprom_spi; 205 206 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 207 E1000_EECD_SIZE_EX_SHIFT); 208 209 /* 210 * Added to a constant, "size" becomes the left-shift value 211 * for setting word_size. 212 */ 213 size += NVM_WORD_SIZE_BASE_SHIFT; 214 215 /* EEPROM access above 16k is unsupported */ 216 if (size > 14) 217 size = 14; 218 nvm->word_size = 1 << size; 219 220 /* Function Pointers */ 221 nvm->ops.acquire = e1000_acquire_nvm_82575; 222 nvm->ops.read = e1000_read_nvm_eerd; 223 nvm->ops.release = e1000_release_nvm_82575; 224 nvm->ops.update = e1000_update_nvm_checksum_generic; 225 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 226 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 227 nvm->ops.write = e1000_write_nvm_spi; 228 229 return E1000_SUCCESS; 230} 231 232/** 233 * e1000_init_mac_params_82575 - Init MAC func ptrs. 234 * @hw: pointer to the HW structure 235 **/ 236static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 237{ 238 struct e1000_mac_info *mac = &hw->mac; 239 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 240 u32 ctrl_ext = 0; 241 242 DEBUGFUNC("e1000_init_mac_params_82575"); 243 244 /* Set media type */ 245 /* 246 * The 82575 uses bits 22:23 for link mode. The mode can be changed 247 * based on the EEPROM. We cannot rely upon device ID. There 248 * is no distinguishable difference between fiber and internal 249 * SerDes mode on the 82575. There can be an external PHY attached 250 * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 251 */ 252 hw->phy.media_type = e1000_media_type_copper; 253 dev_spec->sgmii_active = FALSE; 254 255 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 256 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 257 case E1000_CTRL_EXT_LINK_MODE_SGMII: 258 dev_spec->sgmii_active = TRUE; 259 ctrl_ext |= E1000_CTRL_I2C_ENA; 260 break; 261 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 262 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 263 hw->phy.media_type = e1000_media_type_internal_serdes; 264 ctrl_ext |= E1000_CTRL_I2C_ENA; 265 break; 266 default: 267 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 268 break; 269 } 270 271 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 272 273 /* 274 * if using i2c make certain the MDICNFG register is cleared to prevent 275 * communications from being misrouted to the mdic registers 276 */ 277 if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580)) 278 E1000_WRITE_REG(hw, E1000_MDICNFG, 0); 279 280 /* Set mta register count */ 281 mac->mta_reg_count = 128; 282 /* Set uta register count */ 283 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 284 /* Set rar entry count */ 285 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 286 if (mac->type == e1000_82576) 287 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 288 if (mac->type == e1000_82580) 289 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 290 /* Set if part includes ASF firmware */ 291 mac->asf_firmware_present = TRUE; 292 /* Set if manageability features are enabled. */ 293 mac->arc_subsystem_valid = 294 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 295 ? TRUE : FALSE; 296 297 /* Function pointers */ 298 299 /* bus type/speed/width */ 300 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 301 /* reset */ 302 if (mac->type >= e1000_82580) 303 mac->ops.reset_hw = e1000_reset_hw_82580; 304 else 305 mac->ops.reset_hw = e1000_reset_hw_82575; 306 /* hw initialization */ 307 mac->ops.init_hw = e1000_init_hw_82575; 308 /* link setup */ 309 mac->ops.setup_link = e1000_setup_link_generic; 310 /* physical interface link setup */ 311 mac->ops.setup_physical_interface = 312 (hw->phy.media_type == e1000_media_type_copper) 313 ? e1000_setup_copper_link_82575 314 : e1000_setup_serdes_link_82575; 315 /* physical interface shutdown */ 316 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 317 /* physical interface power up */ 318 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 319 /* check for link */ 320 mac->ops.check_for_link = e1000_check_for_link_82575; 321 /* receive address register setting */ 322 mac->ops.rar_set = e1000_rar_set_generic; 323 /* read mac address */ 324 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 325 /* configure collision distance */ 326 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 327 /* multicast address update */ 328 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 329 /* writing VFTA */ 330 mac->ops.write_vfta = e1000_write_vfta_generic; 331 /* clearing VFTA */ 332 mac->ops.clear_vfta = e1000_clear_vfta_generic; 333 /* ID LED init */ 334 mac->ops.id_led_init = e1000_id_led_init_generic; 335 /* blink LED */ 336 mac->ops.blink_led = e1000_blink_led_generic; 337 /* setup LED */ 338 mac->ops.setup_led = e1000_setup_led_generic; 339 /* cleanup LED */ 340 mac->ops.cleanup_led = e1000_cleanup_led_generic; 341 /* turn on/off LED */ 342 mac->ops.led_on = e1000_led_on_generic; 343 mac->ops.led_off = e1000_led_off_generic; 344 /* clear hardware counters */ 345 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 346 /* link info */ 347 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 348 349 /* set lan id for port to determine which phy lock to use */ 350 hw->mac.ops.set_lan_id(hw); 351 352 return E1000_SUCCESS; 353} 354 355/** 356 * e1000_init_function_pointers_82575 - Init func ptrs. 357 * @hw: pointer to the HW structure 358 * 359 * Called to initialize all function pointers and parameters. 360 **/ 361void e1000_init_function_pointers_82575(struct e1000_hw *hw) 362{ 363 DEBUGFUNC("e1000_init_function_pointers_82575"); 364 365 hw->mac.ops.init_params = e1000_init_mac_params_82575; 366 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 367 hw->phy.ops.init_params = e1000_init_phy_params_82575; 368} 369 370/** 371 * e1000_acquire_phy_82575 - Acquire rights to access PHY 372 * @hw: pointer to the HW structure 373 * 374 * Acquire access rights to the correct PHY. 375 **/ 376static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 377{ 378 u16 mask = E1000_SWFW_PHY0_SM; 379 380 DEBUGFUNC("e1000_acquire_phy_82575"); 381 382 if (hw->bus.func == E1000_FUNC_1) 383 mask = E1000_SWFW_PHY1_SM; 384 else if (hw->bus.func == E1000_FUNC_2) 385 mask = E1000_SWFW_PHY2_SM; 386 else if (hw->bus.func == E1000_FUNC_3) 387 mask = E1000_SWFW_PHY3_SM; 388 389 return e1000_acquire_swfw_sync_82575(hw, mask); 390} 391 392/** 393 * e1000_release_phy_82575 - Release rights to access PHY 394 * @hw: pointer to the HW structure 395 * 396 * A wrapper to release access rights to the correct PHY. 397 **/ 398static void e1000_release_phy_82575(struct e1000_hw *hw) 399{ 400 u16 mask = E1000_SWFW_PHY0_SM; 401 402 DEBUGFUNC("e1000_release_phy_82575"); 403 404 if (hw->bus.func == E1000_FUNC_1) 405 mask = E1000_SWFW_PHY1_SM; 406 else if (hw->bus.func == E1000_FUNC_2) 407 mask = E1000_SWFW_PHY2_SM; 408 else if (hw->bus.func == E1000_FUNC_3) 409 mask = E1000_SWFW_PHY3_SM; 410 411 e1000_release_swfw_sync_82575(hw, mask); 412} 413 414/** 415 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 416 * @hw: pointer to the HW structure 417 * @offset: register offset to be read 418 * @data: pointer to the read data 419 * 420 * Reads the PHY register at offset using the serial gigabit media independent 421 * interface and stores the retrieved information in data. 422 **/ 423static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 424 u16 *data) 425{ 426 s32 ret_val = -E1000_ERR_PARAM; 427 428 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 429 430 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 431 DEBUGOUT1("PHY Address %u is out of range\n", offset); 432 goto out; 433 } 434 435 ret_val = hw->phy.ops.acquire(hw); 436 if (ret_val) 437 goto out; 438 439 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 440 441 hw->phy.ops.release(hw); 442 443out: 444 return ret_val; 445} 446 447/** 448 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 449 * @hw: pointer to the HW structure 450 * @offset: register offset to write to 451 * @data: data to write at register offset 452 * 453 * Writes the data to PHY register at the offset using the serial gigabit 454 * media independent interface. 455 **/ 456static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 457 u16 data) 458{ 459 s32 ret_val = -E1000_ERR_PARAM; 460 461 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 462 463 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 464 DEBUGOUT1("PHY Address %d is out of range\n", offset); 465 goto out; 466 } 467 468 ret_val = hw->phy.ops.acquire(hw); 469 if (ret_val) 470 goto out; 471 472 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 473 474 hw->phy.ops.release(hw); 475 476out: 477 return ret_val; 478} 479 480/** 481 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 482 * @hw: pointer to the HW structure 483 * 484 * Retrieves the PHY address and ID for both PHY's which do and do not use 485 * sgmi interface. 486 **/ 487static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 488{ 489 struct e1000_phy_info *phy = &hw->phy; 490 s32 ret_val = E1000_SUCCESS; 491 u16 phy_id; 492 u32 ctrl_ext; 493 494 DEBUGFUNC("e1000_get_phy_id_82575"); 495 496 /* 497 * For SGMII PHYs, we try the list of possible addresses until 498 * we find one that works. For non-SGMII PHYs 499 * (e.g. integrated copper PHYs), an address of 1 should 500 * work. The result of this function should mean phy->phy_addr 501 * and phy->id are set correctly. 502 */ 503 if (!e1000_sgmii_active_82575(hw)) { 504 phy->addr = 1; 505 ret_val = e1000_get_phy_id(hw); 506 goto out; 507 } 508 509 /* Power on sgmii phy if it is disabled */ 510 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 511 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 512 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 513 E1000_WRITE_FLUSH(hw); 514 msec_delay(300); 515 516 /* 517 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 518 * Therefore, we need to test 1-7 519 */ 520 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 521 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 522 if (ret_val == E1000_SUCCESS) { 523 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 524 phy_id, 525 phy->addr); 526 /* 527 * At the time of this writing, The M88 part is 528 * the only supported SGMII PHY product. 529 */ 530 if (phy_id == M88_VENDOR) 531 break; 532 } else { 533 DEBUGOUT1("PHY address %u was unreadable\n", 534 phy->addr); 535 } 536 } 537 538 /* A valid PHY type couldn't be found. */ 539 if (phy->addr == 8) { 540 phy->addr = 0; 541 ret_val = -E1000_ERR_PHY; 542 } else { 543 ret_val = e1000_get_phy_id(hw); 544 } 545 546 /* restore previous sfp cage power state */ 547 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 548 549out: 550 return ret_val; 551} 552 553/** 554 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 555 * @hw: pointer to the HW structure 556 * 557 * Resets the PHY using the serial gigabit media independent interface. 558 **/ 559static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 560{ 561 s32 ret_val = E1000_SUCCESS; 562 563 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 564 565 /* 566 * This isn't a TRUE "hard" reset, but is the only reset 567 * available to us at this time. 568 */ 569 570 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 571 572 if (!(hw->phy.ops.write_reg)) 573 goto out; 574 575 /* 576 * SFP documentation requires the following to configure the SPF module 577 * to work on SGMII. No further documentation is given. 578 */ 579 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 580 if (ret_val) 581 goto out; 582 583 ret_val = hw->phy.ops.commit(hw); 584 585out: 586 return ret_val; 587} 588 589/** 590 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 591 * @hw: pointer to the HW structure 592 * @active: TRUE to enable LPLU, FALSE to disable 593 * 594 * Sets the LPLU D0 state according to the active flag. When 595 * activating LPLU this function also disables smart speed 596 * and vice versa. LPLU will not be activated unless the 597 * device autonegotiation advertisement meets standards of 598 * either 10 or 10/100 or 10/100/1000 at all duplexes. 599 * This is a function pointer entry point only called by 600 * PHY setup routines. 601 **/ 602static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 603{ 604 struct e1000_phy_info *phy = &hw->phy; 605 s32 ret_val = E1000_SUCCESS; 606 u16 data; 607 608 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 609 610 if (!(hw->phy.ops.read_reg)) 611 goto out; 612 613 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 614 if (ret_val) 615 goto out; 616 617 if (active) { 618 data |= IGP02E1000_PM_D0_LPLU; 619 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 620 data); 621 if (ret_val) 622 goto out; 623 624 /* When LPLU is enabled, we should disable SmartSpeed */ 625 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 626 &data); 627 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 628 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 629 data); 630 if (ret_val) 631 goto out; 632 } else { 633 data &= ~IGP02E1000_PM_D0_LPLU; 634 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 635 data); 636 /* 637 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 638 * during Dx states where the power conservation is most 639 * important. During driver activity we should enable 640 * SmartSpeed, so performance is maintained. 641 */ 642 if (phy->smart_speed == e1000_smart_speed_on) { 643 ret_val = phy->ops.read_reg(hw, 644 IGP01E1000_PHY_PORT_CONFIG, 645 &data); 646 if (ret_val) 647 goto out; 648 649 data |= IGP01E1000_PSCFR_SMART_SPEED; 650 ret_val = phy->ops.write_reg(hw, 651 IGP01E1000_PHY_PORT_CONFIG, 652 data); 653 if (ret_val) 654 goto out; 655 } else if (phy->smart_speed == e1000_smart_speed_off) { 656 ret_val = phy->ops.read_reg(hw, 657 IGP01E1000_PHY_PORT_CONFIG, 658 &data); 659 if (ret_val) 660 goto out; 661 662 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 663 ret_val = phy->ops.write_reg(hw, 664 IGP01E1000_PHY_PORT_CONFIG, 665 data); 666 if (ret_val) 667 goto out; 668 } 669 } 670 671out: 672 return ret_val; 673} 674 675/** 676 * e1000_acquire_nvm_82575 - Request for access to EEPROM 677 * @hw: pointer to the HW structure 678 * 679 * Acquire the necessary semaphores for exclusive access to the EEPROM. 680 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 681 * Return successful if access grant bit set, else clear the request for 682 * EEPROM access and return -E1000_ERR_NVM (-1). 683 **/ 684static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 685{ 686 s32 ret_val; 687 688 DEBUGFUNC("e1000_acquire_nvm_82575"); 689 690 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 691 if (ret_val) 692 goto out; 693 694 ret_val = e1000_acquire_nvm_generic(hw); 695 696 if (ret_val) 697 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 698 699out: 700 return ret_val; 701} 702 703/** 704 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 705 * @hw: pointer to the HW structure 706 * 707 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 708 * then release the semaphores acquired. 709 **/ 710static void e1000_release_nvm_82575(struct e1000_hw *hw) 711{ 712 DEBUGFUNC("e1000_release_nvm_82575"); 713 714 e1000_release_nvm_generic(hw); 715 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 716} 717 718/** 719 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 720 * @hw: pointer to the HW structure 721 * @mask: specifies which semaphore to acquire 722 * 723 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 724 * will also specify which port we're acquiring the lock for. 725 **/ 726static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 727{ 728 u32 swfw_sync; 729 u32 swmask = mask; 730 u32 fwmask = mask << 16; 731 s32 ret_val = E1000_SUCCESS; 732 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 733 734 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 735 736 while (i < timeout) { 737 if (e1000_get_hw_semaphore_generic(hw)) { 738 ret_val = -E1000_ERR_SWFW_SYNC; 739 goto out; 740 } 741 742 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 743 if (!(swfw_sync & (fwmask | swmask))) 744 break; 745 746 /* 747 * Firmware currently using resource (fwmask) 748 * or other software thread using resource (swmask) 749 */ 750 e1000_put_hw_semaphore_generic(hw); 751 msec_delay_irq(5); 752 i++; 753 } 754 755 if (i == timeout) { 756 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 757 ret_val = -E1000_ERR_SWFW_SYNC; 758 goto out; 759 } 760 761 swfw_sync |= swmask; 762 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 763 764 e1000_put_hw_semaphore_generic(hw); 765 766out: 767 return ret_val; 768} 769 770/** 771 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 772 * @hw: pointer to the HW structure 773 * @mask: specifies which semaphore to acquire 774 * 775 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 776 * will also specify which port we're releasing the lock for. 777 **/ 778static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 779{ 780 u32 swfw_sync; 781 782 DEBUGFUNC("e1000_release_swfw_sync_82575"); 783 784 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 785 /* Empty */ 786 787 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 788 swfw_sync &= ~mask; 789 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 790 791 e1000_put_hw_semaphore_generic(hw); 792} 793 794/** 795 * e1000_get_cfg_done_82575 - Read config done bit 796 * @hw: pointer to the HW structure 797 * 798 * Read the management control register for the config done bit for 799 * completion status. NOTE: silicon which is EEPROM-less will fail trying 800 * to read the config done bit, so an error is *ONLY* logged and returns 801 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 802 * would not be able to be reset or change link. 803 **/ 804static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 805{ 806 s32 timeout = PHY_CFG_TIMEOUT; 807 s32 ret_val = E1000_SUCCESS; 808 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 809 810 DEBUGFUNC("e1000_get_cfg_done_82575"); 811 812 if (hw->bus.func == E1000_FUNC_1) 813 mask = E1000_NVM_CFG_DONE_PORT_1; 814 else if (hw->bus.func == E1000_FUNC_2) 815 mask = E1000_NVM_CFG_DONE_PORT_2; 816 else if (hw->bus.func == E1000_FUNC_3) 817 mask = E1000_NVM_CFG_DONE_PORT_3; 818 while (timeout) { 819 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 820 break; 821 msec_delay(1); 822 timeout--; 823 } 824 if (!timeout) 825 DEBUGOUT("MNG configuration cycle has not completed.\n"); 826 827 /* If EEPROM is not marked present, init the PHY manually */ 828 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 829 (hw->phy.type == e1000_phy_igp_3)) 830 e1000_phy_init_script_igp3(hw); 831 832 return ret_val; 833} 834 835/** 836 * e1000_get_link_up_info_82575 - Get link speed/duplex info 837 * @hw: pointer to the HW structure 838 * @speed: stores the current speed 839 * @duplex: stores the current duplex 840 * 841 * This is a wrapper function, if using the serial gigabit media independent 842 * interface, use PCS to retrieve the link speed and duplex information. 843 * Otherwise, use the generic function to get the link speed and duplex info. 844 **/ 845static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 846 u16 *duplex) 847{ 848 s32 ret_val; 849 850 DEBUGFUNC("e1000_get_link_up_info_82575"); 851 852 if (hw->phy.media_type != e1000_media_type_copper) 853 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 854 duplex); 855 else 856 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 857 duplex); 858 859 return ret_val; 860} 861 862/** 863 * e1000_check_for_link_82575 - Check for link 864 * @hw: pointer to the HW structure 865 * 866 * If sgmii is enabled, then use the pcs register to determine link, otherwise 867 * use the generic interface for determining link. 868 **/ 869static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 870{ 871 s32 ret_val; 872 u16 speed, duplex; 873 874 DEBUGFUNC("e1000_check_for_link_82575"); 875 876 if (hw->phy.media_type != e1000_media_type_copper) { 877 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 878 &duplex); 879 /* 880 * Use this flag to determine if link needs to be checked or 881 * not. If we have link clear the flag so that we do not 882 * continue to check for link. 883 */ 884 hw->mac.get_link_status = !hw->mac.serdes_has_link; 885 } else { 886 ret_val = e1000_check_for_copper_link_generic(hw); 887 } 888 889 return ret_val; 890} 891 892/** 893 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 894 * @hw: pointer to the HW structure 895 **/ 896static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 897{ 898 u32 reg; 899 900 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 901 902 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 903 !e1000_sgmii_active_82575(hw)) 904 return; 905 906 /* Enable PCS to turn on link */ 907 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 908 reg |= E1000_PCS_CFG_PCS_EN; 909 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 910 911 /* Power up the laser */ 912 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 913 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 914 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 915 916 /* flush the write to verify completion */ 917 E1000_WRITE_FLUSH(hw); 918 msec_delay(1); 919} 920 921/** 922 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 923 * @hw: pointer to the HW structure 924 * @speed: stores the current speed 925 * @duplex: stores the current duplex 926 * 927 * Using the physical coding sub-layer (PCS), retrieve the current speed and 928 * duplex, then store the values in the pointers provided. 929 **/ 930static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 931 u16 *speed, u16 *duplex) 932{ 933 struct e1000_mac_info *mac = &hw->mac; 934 u32 pcs; 935 936 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 937 938 /* Set up defaults for the return values of this function */ 939 mac->serdes_has_link = FALSE; 940 *speed = 0; 941 *duplex = 0; 942 943 /* 944 * Read the PCS Status register for link state. For non-copper mode, 945 * the status register is not accurate. The PCS status register is 946 * used instead. 947 */ 948 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 949 950 /* 951 * The link up bit determines when link is up on autoneg. The sync ok 952 * gets set once both sides sync up and agree upon link. Stable link 953 * can be determined by checking for both link up and link sync ok 954 */ 955 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 956 mac->serdes_has_link = TRUE; 957 958 /* Detect and store PCS speed */ 959 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 960 *speed = SPEED_1000; 961 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 962 *speed = SPEED_100; 963 } else { 964 *speed = SPEED_10; 965 } 966 967 /* Detect and store PCS duplex */ 968 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 969 *duplex = FULL_DUPLEX; 970 } else { 971 *duplex = HALF_DUPLEX; 972 } 973 } 974 975 return E1000_SUCCESS; 976} 977 978/** 979 * e1000_shutdown_serdes_link_82575 - Remove link during power down 980 * @hw: pointer to the HW structure 981 * 982 * In the case of serdes shut down sfp and PCS on driver unload 983 * when management pass thru is not enabled. 984 **/ 985void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 986{ 987 u32 reg; 988 989 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 990 991 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 992 !e1000_sgmii_active_82575(hw)) 993 return; 994 995 if (!e1000_enable_mng_pass_thru(hw)) { 996 /* Disable PCS to turn off link */ 997 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 998 reg &= ~E1000_PCS_CFG_PCS_EN; 999 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1000 1001 /* shutdown the laser */ 1002 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1003 reg |= E1000_CTRL_EXT_SDP3_DATA; 1004 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1005 1006 /* flush the write to verify completion */ 1007 E1000_WRITE_FLUSH(hw); 1008 msec_delay(1); 1009 } 1010 1011 return; 1012} 1013 1014/** 1015 * e1000_reset_hw_82575 - Reset hardware 1016 * @hw: pointer to the HW structure 1017 * 1018 * This resets the hardware into a known state. 1019 **/ 1020static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1021{ 1022 u32 ctrl, icr; 1023 s32 ret_val; 1024 1025 DEBUGFUNC("e1000_reset_hw_82575"); 1026 1027 /* 1028 * Prevent the PCI-E bus from sticking if there is no TLP connection 1029 * on the last TLP read/write transaction when MAC is reset. 1030 */ 1031 ret_val = e1000_disable_pcie_master_generic(hw); 1032 if (ret_val) { 1033 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1034 } 1035 1036 /* set the completion timeout for interface */ 1037 ret_val = e1000_set_pcie_completion_timeout(hw); 1038 if (ret_val) { 1039 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1040 } 1041 1042 DEBUGOUT("Masking off all interrupts\n"); 1043 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1044 1045 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1046 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1047 E1000_WRITE_FLUSH(hw); 1048 1049 msec_delay(10); 1050 1051 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1052 1053 DEBUGOUT("Issuing a global reset to MAC\n"); 1054 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1055 1056 ret_val = e1000_get_auto_rd_done_generic(hw); 1057 if (ret_val) { 1058 /* 1059 * When auto config read does not complete, do not 1060 * return with an error. This can happen in situations 1061 * where there is no eeprom and prevents getting link. 1062 */ 1063 DEBUGOUT("Auto Read Done did not complete\n"); 1064 } 1065 1066 /* If EEPROM is not present, run manual init scripts */ 1067 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1068 e1000_reset_init_script_82575(hw); 1069 1070 /* Clear any pending interrupt events. */ 1071 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1072 icr = E1000_READ_REG(hw, E1000_ICR); 1073 1074 /* Install any alternate MAC address into RAR0 */ 1075 ret_val = e1000_check_alt_mac_addr_generic(hw); 1076 1077 return ret_val; 1078} 1079 1080/** 1081 * e1000_init_hw_82575 - Initialize hardware 1082 * @hw: pointer to the HW structure 1083 * 1084 * This inits the hardware readying it for operation. 1085 **/ 1086static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1087{ 1088 struct e1000_mac_info *mac = &hw->mac; 1089 s32 ret_val; 1090 u16 i, rar_count = mac->rar_entry_count; 1091 1092 DEBUGFUNC("e1000_init_hw_82575"); 1093 1094 /* Initialize identification LED */ 1095 ret_val = mac->ops.id_led_init(hw); 1096 if (ret_val) { 1097 DEBUGOUT("Error initializing identification LED\n"); 1098 /* This is not fatal and we should not stop init due to this */ 1099 } 1100 1101 /* Disabling VLAN filtering */ 1102 DEBUGOUT("Initializing the IEEE VLAN\n"); 1103 mac->ops.clear_vfta(hw); 1104 1105 /* Setup the receive address */ 1106 e1000_init_rx_addrs_generic(hw, rar_count); 1107 1108 /* Zero out the Multicast HASH table */ 1109 DEBUGOUT("Zeroing the MTA\n"); 1110 for (i = 0; i < mac->mta_reg_count; i++) 1111 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1112 1113 /* Zero out the Unicast HASH table */ 1114 DEBUGOUT("Zeroing the UTA\n"); 1115 for (i = 0; i < mac->uta_reg_count; i++) 1116 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1117 1118 /* Setup link and flow control */ 1119 ret_val = mac->ops.setup_link(hw); 1120 1121 /* 1122 * Clear all of the statistics registers (clear on read). It is 1123 * important that we do this after we have tried to establish link 1124 * because the symbol error count will increment wildly if there 1125 * is no link. 1126 */ 1127 e1000_clear_hw_cntrs_82575(hw); 1128 1129 return ret_val; 1130} 1131 1132/** 1133 * e1000_setup_copper_link_82575 - Configure copper link settings 1134 * @hw: pointer to the HW structure 1135 * 1136 * Configures the link for auto-neg or forced speed and duplex. Then we check 1137 * for link, once link is established calls to configure collision distance 1138 * and flow control are called. 1139 **/ 1140static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1141{ 1142 u32 ctrl; 1143 s32 ret_val; 1144 1145 DEBUGFUNC("e1000_setup_copper_link_82575"); 1146 1147 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1148 ctrl |= E1000_CTRL_SLU; 1149 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1150 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1151 1152 ret_val = e1000_setup_serdes_link_82575(hw); 1153 if (ret_val) 1154 goto out; 1155 1156 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1157 /* allow time for SFP cage time to power up phy */ 1158 msec_delay(300); 1159 1160 ret_val = hw->phy.ops.reset(hw); 1161 if (ret_val) { 1162 DEBUGOUT("Error resetting the PHY.\n"); 1163 goto out; 1164 } 1165 } 1166 switch (hw->phy.type) { 1167 case e1000_phy_m88: 1168 ret_val = e1000_copper_link_setup_m88(hw); 1169 break; 1170 case e1000_phy_igp_3: 1171 ret_val = e1000_copper_link_setup_igp(hw); 1172 break; 1173 case e1000_phy_82580: 1174 ret_val = e1000_copper_link_setup_82577(hw); 1175 break; 1176 default: 1177 ret_val = -E1000_ERR_PHY; 1178 break; 1179 } 1180 1181 if (ret_val) 1182 goto out; 1183 1184 ret_val = e1000_setup_copper_link_generic(hw); 1185out: 1186 return ret_val; 1187} 1188 1189/** 1190 * e1000_setup_serdes_link_82575 - Setup link for serdes 1191 * @hw: pointer to the HW structure 1192 * 1193 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1194 * used on copper connections where the serialized gigabit media independent 1195 * interface (sgmii), or serdes fiber is being used. Configures the link 1196 * for auto-negotiation or forces speed/duplex. 1197 **/ 1198static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1199{ 1200 u32 ctrl_ext, ctrl_reg, reg; 1201 bool pcs_autoneg; 1202 1203 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1204 1205 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1206 !e1000_sgmii_active_82575(hw)) 1207 return E1000_SUCCESS; 1208 1209 /* 1210 * On the 82575, SerDes loopback mode persists until it is 1211 * explicitly turned off or a power cycle is performed. A read to 1212 * the register does not indicate its status. Therefore, we ensure 1213 * loopback mode is disabled during initialization. 1214 */ 1215 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1216 1217 /* power on the sfp cage if present */ 1218 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1219 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1220 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1221 1222 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1223 ctrl_reg |= E1000_CTRL_SLU; 1224 1225 /* set both sw defined pins on 82575/82576*/ 1226 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1227 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1228 1229 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1230 1231 /* default pcs_autoneg to the same setting as mac autoneg */ 1232 pcs_autoneg = hw->mac.autoneg; 1233 1234 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1235 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1236 /* sgmii mode lets the phy handle forcing speed/duplex */ 1237 pcs_autoneg = TRUE; 1238 /* autoneg time out should be disabled for SGMII mode */ 1239 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1240 break; 1241 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1242 /* disable PCS autoneg and support parallel detect only */ 1243 pcs_autoneg = FALSE; 1244 default: 1245 /* 1246 * non-SGMII modes only supports a speed of 1000/Full for the 1247 * link so it is best to just force the MAC and let the pcs 1248 * link either autoneg or be forced to 1000/Full 1249 */ 1250 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1251 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1252 1253 /* set speed of 1000/Full if speed/duplex is forced */ 1254 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1255 break; 1256 } 1257 1258 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1259 1260 /* 1261 * New SerDes mode allows for forcing speed or autonegotiating speed 1262 * at 1gb. Autoneg should be default set by most drivers. This is the 1263 * mode that will be compatible with older link partners and switches. 1264 * However, both are supported by the hardware and some drivers/tools. 1265 */ 1266 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1267 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1268 1269 /* 1270 * We force flow control to prevent the CTRL register values from being 1271 * overwritten by the autonegotiated flow control values 1272 */ 1273 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1274 1275 if (pcs_autoneg) { 1276 /* Set PCS register for autoneg */ 1277 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1278 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1279 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1280 } else { 1281 /* Set PCS register for forced link */ 1282 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1283 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1284 } 1285 1286 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1287 1288 if (!e1000_sgmii_active_82575(hw)) 1289 e1000_force_mac_fc_generic(hw); 1290 1291 return E1000_SUCCESS; 1292} 1293 1294/** 1295 * e1000_valid_led_default_82575 - Verify a valid default LED config 1296 * @hw: pointer to the HW structure 1297 * @data: pointer to the NVM (EEPROM) 1298 * 1299 * Read the EEPROM for the current default LED configuration. If the 1300 * LED configuration is not valid, set to a valid LED configuration. 1301 **/ 1302static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1303{ 1304 s32 ret_val; 1305 1306 DEBUGFUNC("e1000_valid_led_default_82575"); 1307 1308 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1309 if (ret_val) { 1310 DEBUGOUT("NVM Read Error\n"); 1311 goto out; 1312 } 1313 1314 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1315 switch(hw->phy.media_type) { 1316 case e1000_media_type_internal_serdes: 1317 *data = ID_LED_DEFAULT_82575_SERDES; 1318 break; 1319 case e1000_media_type_copper: 1320 default: 1321 *data = ID_LED_DEFAULT; 1322 break; 1323 } 1324 } 1325out: 1326 return ret_val; 1327} 1328 1329/** 1330 * e1000_sgmii_active_82575 - Return sgmii state 1331 * @hw: pointer to the HW structure 1332 * 1333 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1334 * which can be enabled for use in the embedded applications. Simply 1335 * return the current state of the sgmii interface. 1336 **/ 1337static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1338{ 1339 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1340 return dev_spec->sgmii_active; 1341} 1342 1343/** 1344 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1345 * @hw: pointer to the HW structure 1346 * 1347 * Inits recommended HW defaults after a reset when there is no EEPROM 1348 * detected. This is only for the 82575. 1349 **/ 1350static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1351{ 1352 DEBUGFUNC("e1000_reset_init_script_82575"); 1353 1354 if (hw->mac.type == e1000_82575) { 1355 DEBUGOUT("Running reset init script for 82575\n"); 1356 /* SerDes configuration via SERDESCTRL */ 1357 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1358 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1359 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1360 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1361 1362 /* CCM configuration via CCMCTL register */ 1363 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1364 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1365 1366 /* PCIe lanes configuration */ 1367 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1368 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1369 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1370 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1371 1372 /* PCIe PLL Configuration */ 1373 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1374 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1375 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1376 } 1377 1378 return E1000_SUCCESS; 1379} 1380 1381/** 1382 * e1000_read_mac_addr_82575 - Read device MAC address 1383 * @hw: pointer to the HW structure 1384 **/ 1385static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1386{ 1387 s32 ret_val = E1000_SUCCESS; 1388 1389 DEBUGFUNC("e1000_read_mac_addr_82575"); 1390 1391 /* 1392 * If there's an alternate MAC address place it in RAR0 1393 * so that it will override the Si installed default perm 1394 * address. 1395 */ 1396 ret_val = e1000_check_alt_mac_addr_generic(hw); 1397 if (ret_val) 1398 goto out; 1399 1400 ret_val = e1000_read_mac_addr_generic(hw); 1401 1402out: 1403 return ret_val; 1404} 1405 1406/** 1407 * e1000_config_collision_dist_82575 - Configure collision distance 1408 * @hw: pointer to the HW structure 1409 * 1410 * Configures the collision distance to the default value and is used 1411 * during link setup. 1412 **/ 1413static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1414{ 1415 u32 tctl_ext; 1416 1417 DEBUGFUNC("e1000_config_collision_dist_82575"); 1418 1419 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1420 1421 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1422 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1423 1424 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1425 E1000_WRITE_FLUSH(hw); 1426} 1427 1428/** 1429 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1430 * @hw: pointer to the HW structure 1431 * 1432 * In the case of a PHY power down to save power, or to turn off link during a 1433 * driver unload, or wake on lan is not enabled, remove the link. 1434 **/ 1435static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1436{ 1437 struct e1000_phy_info *phy = &hw->phy; 1438 struct e1000_mac_info *mac = &hw->mac; 1439 1440 if (!(phy->ops.check_reset_block)) 1441 return; 1442 1443 /* If the management interface is not enabled, then power down */ 1444 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1445 e1000_power_down_phy_copper(hw); 1446 1447 return; 1448} 1449 1450/** 1451 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1452 * @hw: pointer to the HW structure 1453 * 1454 * Clears the hardware counters by reading the counter registers. 1455 **/ 1456static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1457{ 1458 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1459 1460 e1000_clear_hw_cntrs_base_generic(hw); 1461 1462 E1000_READ_REG(hw, E1000_PRC64); 1463 E1000_READ_REG(hw, E1000_PRC127); 1464 E1000_READ_REG(hw, E1000_PRC255); 1465 E1000_READ_REG(hw, E1000_PRC511); 1466 E1000_READ_REG(hw, E1000_PRC1023); 1467 E1000_READ_REG(hw, E1000_PRC1522); 1468 E1000_READ_REG(hw, E1000_PTC64); 1469 E1000_READ_REG(hw, E1000_PTC127); 1470 E1000_READ_REG(hw, E1000_PTC255); 1471 E1000_READ_REG(hw, E1000_PTC511); 1472 E1000_READ_REG(hw, E1000_PTC1023); 1473 E1000_READ_REG(hw, E1000_PTC1522); 1474 1475 E1000_READ_REG(hw, E1000_ALGNERRC); 1476 E1000_READ_REG(hw, E1000_RXERRC); 1477 E1000_READ_REG(hw, E1000_TNCRS); 1478 E1000_READ_REG(hw, E1000_CEXTERR); 1479 E1000_READ_REG(hw, E1000_TSCTC); 1480 E1000_READ_REG(hw, E1000_TSCTFC); 1481 1482 E1000_READ_REG(hw, E1000_MGTPRC); 1483 E1000_READ_REG(hw, E1000_MGTPDC); 1484 E1000_READ_REG(hw, E1000_MGTPTC); 1485 1486 E1000_READ_REG(hw, E1000_IAC); 1487 E1000_READ_REG(hw, E1000_ICRXOC); 1488 1489 E1000_READ_REG(hw, E1000_ICRXPTC); 1490 E1000_READ_REG(hw, E1000_ICRXATC); 1491 E1000_READ_REG(hw, E1000_ICTXPTC); 1492 E1000_READ_REG(hw, E1000_ICTXATC); 1493 E1000_READ_REG(hw, E1000_ICTXQEC); 1494 E1000_READ_REG(hw, E1000_ICTXQMTC); 1495 E1000_READ_REG(hw, E1000_ICRXDMTC); 1496 1497 E1000_READ_REG(hw, E1000_CBTMPC); 1498 E1000_READ_REG(hw, E1000_HTDPMC); 1499 E1000_READ_REG(hw, E1000_CBRMPC); 1500 E1000_READ_REG(hw, E1000_RPTHC); 1501 E1000_READ_REG(hw, E1000_HGPTC); 1502 E1000_READ_REG(hw, E1000_HTCBDPC); 1503 E1000_READ_REG(hw, E1000_HGORCL); 1504 E1000_READ_REG(hw, E1000_HGORCH); 1505 E1000_READ_REG(hw, E1000_HGOTCL); 1506 E1000_READ_REG(hw, E1000_HGOTCH); 1507 E1000_READ_REG(hw, E1000_LENERRS); 1508 1509 /* This register should not be read in copper configurations */ 1510 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1511 e1000_sgmii_active_82575(hw)) 1512 E1000_READ_REG(hw, E1000_SCVPC); 1513} 1514 1515/** 1516 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1517 * @hw: pointer to the HW structure 1518 * 1519 * After rx enable if managability is enabled then there is likely some 1520 * bad data at the start of the fifo and possibly in the DMA fifo. This 1521 * function clears the fifos and flushes any packets that came in as rx was 1522 * being enabled. 1523 **/ 1524void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1525{ 1526 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1527 int i, ms_wait; 1528 1529 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1530 if (hw->mac.type != e1000_82575 || 1531 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1532 return; 1533 1534 /* Disable all RX queues */ 1535 for (i = 0; i < 4; i++) { 1536 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1537 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1538 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1539 } 1540 /* Poll all queues to verify they have shut down */ 1541 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1542 msec_delay(1); 1543 rx_enabled = 0; 1544 for (i = 0; i < 4; i++) 1545 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1546 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1547 break; 1548 } 1549 1550 if (ms_wait == 10) 1551 DEBUGOUT("Queue disable timed out after 10ms\n"); 1552 1553 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1554 * incoming packets are rejected. Set enable and wait 2ms so that 1555 * any packet that was coming in as RCTL.EN was set is flushed 1556 */ 1557 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1558 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1559 1560 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1561 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1562 1563 rctl = E1000_READ_REG(hw, E1000_RCTL); 1564 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1565 temp_rctl |= E1000_RCTL_LPE; 1566 1567 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1568 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1569 E1000_WRITE_FLUSH(hw); 1570 msec_delay(2); 1571 1572 /* Enable RX queues that were previously enabled and restore our 1573 * previous state 1574 */ 1575 for (i = 0; i < 4; i++) 1576 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1577 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1578 E1000_WRITE_FLUSH(hw); 1579 1580 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1581 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1582 1583 /* Flush receive errors generated by workaround */ 1584 E1000_READ_REG(hw, E1000_ROC); 1585 E1000_READ_REG(hw, E1000_RNBC); 1586 E1000_READ_REG(hw, E1000_MPC); 1587} 1588 1589/** 1590 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1591 * @hw: pointer to the HW structure 1592 * 1593 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1594 * however the hardware default for these parts is 500us to 1ms which is less 1595 * than the 10ms recommended by the pci-e spec. To address this we need to 1596 * increase the value to either 10ms to 200ms for capability version 1 config, 1597 * or 16ms to 55ms for version 2. 1598 **/ 1599static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1600{ 1601 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1602 s32 ret_val = E1000_SUCCESS; 1603 u16 pcie_devctl2; 1604 1605 /* only take action if timeout value is defaulted to 0 */ 1606 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1607 goto out; 1608 1609 /* 1610 * if capababilities version is type 1 we can write the 1611 * timeout of 10ms to 200ms through the GCR register 1612 */ 1613 if (!(gcr & E1000_GCR_CAP_VER2)) { 1614 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1615 goto out; 1616 } 1617 1618 /* 1619 * for version 2 capabilities we need to write the config space 1620 * directly in order to set the completion timeout value for 1621 * 16ms to 55ms 1622 */ 1623 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1624 &pcie_devctl2); 1625 if (ret_val) 1626 goto out; 1627 1628 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1629 1630 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1631 &pcie_devctl2); 1632out: 1633 /* disable completion timeout resend */ 1634 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1635 1636 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1637 return ret_val; 1638} 1639 1640/** 1641 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 1642 * @hw: pointer to the hardware struct 1643 * @enable: state to enter, either enabled or disabled 1644 * 1645 * enables/disables L2 switch loopback functionality. 1646 **/ 1647void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1648{ 1649 u32 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1650 1651 if (enable) 1652 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1653 else 1654 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1655 1656 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1657} 1658 1659/** 1660 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 1661 * @hw: pointer to the hardware struct 1662 * @enable: state to enter, either enabled or disabled 1663 * 1664 * enables/disables replication of packets across multiple pools. 1665 **/ 1666void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1667{ 1668 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 1669 1670 if (enable) 1671 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 1672 else 1673 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 1674 1675 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 1676} 1677 1678/** 1679 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 1680 * @hw: pointer to the HW structure 1681 * @offset: register offset to be read 1682 * @data: pointer to the read data 1683 * 1684 * Reads the MDI control register in the PHY at offset and stores the 1685 * information read to data. 1686 **/ 1687static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 1688{ 1689 s32 ret_val; 1690 1691 DEBUGFUNC("e1000_read_phy_reg_82580"); 1692 1693 ret_val = hw->phy.ops.acquire(hw); 1694 if (ret_val) 1695 goto out; 1696 1697 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 1698 1699 hw->phy.ops.release(hw); 1700 1701out: 1702 return ret_val; 1703} 1704 1705/** 1706 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 1707 * @hw: pointer to the HW structure 1708 * @offset: register offset to write to 1709 * @data: data to write to register at offset 1710 * 1711 * Writes data to MDI control register in the PHY at offset. 1712 **/ 1713static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 1714{ 1715 s32 ret_val; 1716 1717 DEBUGFUNC("e1000_write_phy_reg_82580"); 1718 1719 ret_val = hw->phy.ops.acquire(hw); 1720 if (ret_val) 1721 goto out; 1722 1723 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 1724 1725 hw->phy.ops.release(hw); 1726 1727out: 1728 return ret_val; 1729} 1730 1731/** 1732 * e1000_reset_hw_82580 - Reset hardware 1733 * @hw: pointer to the HW structure 1734 * 1735 * This resets function or entire device (all ports, etc.) 1736 * to a known state. 1737 **/ 1738static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 1739{ 1740 s32 ret_val = E1000_SUCCESS; 1741 /* BH SW mailbox bit in SW_FW_SYNC */ 1742 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 1743 u32 ctrl, icr; 1744 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 1745 1746 DEBUGFUNC("e1000_reset_hw_82580"); 1747 1748 hw->dev_spec._82575.global_device_reset = FALSE; 1749 1750 /* Get current control state. */ 1751 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1752 1753 /* 1754 * Prevent the PCI-E bus from sticking if there is no TLP connection 1755 * on the last TLP read/write transaction when MAC is reset. 1756 */ 1757 ret_val = e1000_disable_pcie_master_generic(hw); 1758 if (ret_val) 1759 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1760 1761 DEBUGOUT("Masking off all interrupts\n"); 1762 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1763 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1764 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1765 E1000_WRITE_FLUSH(hw); 1766 1767 msec_delay(10); 1768 1769 /* Determine whether or not a global dev reset is requested */ 1770 if (global_device_reset && 1771 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask)) 1772 global_device_reset = FALSE; 1773 1774 if (global_device_reset && 1775 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 1776 ctrl |= E1000_CTRL_DEV_RST; 1777 else 1778 ctrl |= E1000_CTRL_RST; 1779 1780 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1781 1782 /* Add delay to insure DEV_RST has time to complete */ 1783 if (global_device_reset) 1784 msec_delay(5); 1785 1786 ret_val = e1000_get_auto_rd_done_generic(hw); 1787 if (ret_val) { 1788 /* 1789 * When auto config read does not complete, do not 1790 * return with an error. This can happen in situations 1791 * where there is no eeprom and prevents getting link. 1792 */ 1793 DEBUGOUT("Auto Read Done did not complete\n"); 1794 } 1795 1796 /* If EEPROM is not present, run manual init scripts */ 1797 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1798 e1000_reset_init_script_82575(hw); 1799 1800 /* clear global device reset status bit */ 1801 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 1802 1803 /* Clear any pending interrupt events. */ 1804 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1805 icr = E1000_READ_REG(hw, E1000_ICR); 1806 1807 /* Install any alternate MAC address into RAR0 */ 1808 ret_val = e1000_check_alt_mac_addr_generic(hw); 1809 1810 /* Release semaphore */ 1811 if (global_device_reset) 1812 e1000_release_swfw_sync_82575(hw, swmbsw_mask); 1813 1814 return ret_val; 1815} 1816 1817/** 1818 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 1819 * @data: data received by reading RXPBS register 1820 * 1821 * The 82580 uses a table based approach for packet buffer allocation sizes. 1822 * This function converts the retrieved value into the correct table value 1823 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 1824 * 0x0 36 72 144 1 2 4 8 16 1825 * 0x8 35 70 140 rsv rsv rsv rsv rsv 1826 */ 1827u16 e1000_rxpbs_adjust_82580(u32 data) 1828{ 1829 u16 ret_val = 0; 1830 1831 if (data < E1000_82580_RXPBS_TABLE_SIZE) 1832 ret_val = e1000_82580_rxpbs_table[data]; 1833 1834 return ret_val; 1835} 1836