e1000_82575.c revision 194865
1176667Sjfv/****************************************************************************** 2176667Sjfv 3190872Sjfv Copyright (c) 2001-2009, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 194865 2009-06-24 17:41:29Z jfv $*/ 34176667Sjfv 35185353Sjfv/* 36185353Sjfv * 82575EB Gigabit Network Connection 37185353Sjfv * 82575EB Gigabit Backplane Connection 38185353Sjfv * 82575GB Gigabit Network Connection 39190872Sjfv * 82575GB Gigabit Network Connection 40185353Sjfv * 82576 Gigabit Network Connection 41194865Sjfv * 82576 Quad Port Gigabit Mezzanine Adapter 42176667Sjfv */ 43176667Sjfv 44176667Sjfv#include "e1000_api.h" 45176667Sjfv 46176667Sjfvstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 47176667Sjfvstatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 48176667Sjfvstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 49176667Sjfvstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 50176667Sjfvstatic void e1000_release_phy_82575(struct e1000_hw *hw); 51176667Sjfvstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 52176667Sjfvstatic void e1000_release_nvm_82575(struct e1000_hw *hw); 53176667Sjfvstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw); 54176667Sjfvstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 55176667Sjfvstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 56176667Sjfv u16 *duplex); 57176667Sjfvstatic s32 e1000_init_hw_82575(struct e1000_hw *hw); 58176667Sjfvstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 59176667Sjfvstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 60176667Sjfv u16 *data); 61176667Sjfvstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw); 62176667Sjfvstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 63176667Sjfv bool active); 64176667Sjfvstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 65176667Sjfvstatic s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw); 66181027Sjfvstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 67176667Sjfvstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 68176667Sjfv u32 offset, u16 data); 69176667Sjfvstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 70176667Sjfvstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 71176667Sjfvstatic s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw); 72176667Sjfvstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 73176667Sjfv u16 *speed, u16 *duplex); 74176667Sjfvstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 75176667Sjfvstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 76176667Sjfvstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw); 77176667Sjfvstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 78176667Sjfvstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 79176667Sjfvstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 80181027Sjfvvoid e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); 81194865Sjfvstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 82176667Sjfv 83176667Sjfv/** 84176667Sjfv * e1000_init_phy_params_82575 - Init PHY func ptrs. 85176667Sjfv * @hw: pointer to the HW structure 86176667Sjfv **/ 87176667Sjfvstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 88176667Sjfv{ 89176667Sjfv struct e1000_phy_info *phy = &hw->phy; 90176667Sjfv s32 ret_val = E1000_SUCCESS; 91176667Sjfv 92176667Sjfv DEBUGFUNC("e1000_init_phy_params_82575"); 93176667Sjfv 94176667Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 95176667Sjfv phy->type = e1000_phy_none; 96176667Sjfv goto out; 97176667Sjfv } else { 98176667Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 99176667Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82575; 100176667Sjfv } 101176667Sjfv 102176667Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 103176667Sjfv phy->reset_delay_us = 100; 104176667Sjfv 105176667Sjfv phy->ops.acquire = e1000_acquire_phy_82575; 106176667Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 107176667Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 108176667Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 109176667Sjfv phy->ops.release = e1000_release_phy_82575; 110176667Sjfv 111176667Sjfv if (e1000_sgmii_active_82575(hw)) { 112176667Sjfv phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 113176667Sjfv phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 114176667Sjfv phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 115176667Sjfv } else { 116176667Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 117176667Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 118176667Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 119176667Sjfv } 120176667Sjfv 121176667Sjfv /* Set phy->phy_addr and phy->id. */ 122176667Sjfv ret_val = e1000_get_phy_id_82575(hw); 123176667Sjfv 124176667Sjfv /* Verify phy id and set remaining function pointers */ 125176667Sjfv switch (phy->id) { 126176667Sjfv case M88E1111_I_PHY_ID: 127176667Sjfv phy->type = e1000_phy_m88; 128176667Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 129176667Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 130176667Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 131176667Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 132176667Sjfv break; 133176667Sjfv case IGP03E1000_E_PHY_ID: 134181027Sjfv case IGP04E1000_E_PHY_ID: 135176667Sjfv phy->type = e1000_phy_igp_3; 136176667Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 137176667Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 138176667Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 139176667Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 140176667Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 141176667Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 142176667Sjfv break; 143176667Sjfv default: 144176667Sjfv ret_val = -E1000_ERR_PHY; 145176667Sjfv goto out; 146176667Sjfv } 147176667Sjfv 148176667Sjfvout: 149176667Sjfv return ret_val; 150176667Sjfv} 151176667Sjfv 152176667Sjfv/** 153176667Sjfv * e1000_init_nvm_params_82575 - Init NVM func ptrs. 154176667Sjfv * @hw: pointer to the HW structure 155176667Sjfv **/ 156176667Sjfvstatic s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 157176667Sjfv{ 158176667Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 159176667Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 160176667Sjfv u16 size; 161176667Sjfv 162176667Sjfv DEBUGFUNC("e1000_init_nvm_params_82575"); 163176667Sjfv 164176667Sjfv nvm->opcode_bits = 8; 165176667Sjfv nvm->delay_usec = 1; 166176667Sjfv switch (nvm->override) { 167176667Sjfv case e1000_nvm_override_spi_large: 168176667Sjfv nvm->page_size = 32; 169176667Sjfv nvm->address_bits = 16; 170176667Sjfv break; 171176667Sjfv case e1000_nvm_override_spi_small: 172176667Sjfv nvm->page_size = 8; 173176667Sjfv nvm->address_bits = 8; 174176667Sjfv break; 175176667Sjfv default: 176176667Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 177176667Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 178176667Sjfv break; 179176667Sjfv } 180176667Sjfv 181176667Sjfv nvm->type = e1000_nvm_eeprom_spi; 182176667Sjfv 183176667Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 184176667Sjfv E1000_EECD_SIZE_EX_SHIFT); 185176667Sjfv 186176667Sjfv /* 187176667Sjfv * Added to a constant, "size" becomes the left-shift value 188176667Sjfv * for setting word_size. 189176667Sjfv */ 190176667Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 191176667Sjfv 192176667Sjfv /* EEPROM access above 16k is unsupported */ 193176667Sjfv if (size > 14) 194176667Sjfv size = 14; 195176667Sjfv nvm->word_size = 1 << size; 196176667Sjfv 197176667Sjfv /* Function Pointers */ 198176667Sjfv nvm->ops.acquire = e1000_acquire_nvm_82575; 199176667Sjfv nvm->ops.read = e1000_read_nvm_eerd; 200176667Sjfv nvm->ops.release = e1000_release_nvm_82575; 201176667Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 202181027Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82575; 203176667Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 204176667Sjfv nvm->ops.write = e1000_write_nvm_spi; 205176667Sjfv 206176667Sjfv return E1000_SUCCESS; 207176667Sjfv} 208176667Sjfv 209176667Sjfv/** 210176667Sjfv * e1000_init_mac_params_82575 - Init MAC func ptrs. 211176667Sjfv * @hw: pointer to the HW structure 212176667Sjfv **/ 213176667Sjfvstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 214176667Sjfv{ 215176667Sjfv struct e1000_mac_info *mac = &hw->mac; 216185353Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 217176667Sjfv u32 ctrl_ext = 0; 218176667Sjfv 219176667Sjfv DEBUGFUNC("e1000_init_mac_params_82575"); 220176667Sjfv 221176667Sjfv /* Set media type */ 222176667Sjfv /* 223176667Sjfv * The 82575 uses bits 22:23 for link mode. The mode can be changed 224176667Sjfv * based on the EEPROM. We cannot rely upon device ID. There 225176667Sjfv * is no distinguishable difference between fiber and internal 226176667Sjfv * SerDes mode on the 82575. There can be an external PHY attached 227176667Sjfv * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 228176667Sjfv */ 229176667Sjfv hw->phy.media_type = e1000_media_type_copper; 230176667Sjfv dev_spec->sgmii_active = FALSE; 231176667Sjfv 232176667Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 233176667Sjfv if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 234176667Sjfv E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) { 235176667Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 236176667Sjfv ctrl_ext |= E1000_CTRL_I2C_ENA; 237176667Sjfv } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) { 238176667Sjfv dev_spec->sgmii_active = TRUE; 239176667Sjfv ctrl_ext |= E1000_CTRL_I2C_ENA; 240176667Sjfv } else { 241176667Sjfv ctrl_ext &= ~E1000_CTRL_I2C_ENA; 242176667Sjfv } 243176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 244176667Sjfv 245176667Sjfv /* Set mta register count */ 246176667Sjfv mac->mta_reg_count = 128; 247176667Sjfv /* Set rar entry count */ 248176667Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 249181027Sjfv if (mac->type == e1000_82576) 250181027Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 251176667Sjfv /* Set if part includes ASF firmware */ 252176667Sjfv mac->asf_firmware_present = TRUE; 253176667Sjfv /* Set if manageability features are enabled. */ 254176667Sjfv mac->arc_subsystem_valid = 255176667Sjfv (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 256176667Sjfv ? TRUE : FALSE; 257176667Sjfv 258176667Sjfv /* Function pointers */ 259176667Sjfv 260176667Sjfv /* bus type/speed/width */ 261176667Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 262176667Sjfv /* reset */ 263176667Sjfv mac->ops.reset_hw = e1000_reset_hw_82575; 264176667Sjfv /* hw initialization */ 265176667Sjfv mac->ops.init_hw = e1000_init_hw_82575; 266176667Sjfv /* link setup */ 267176667Sjfv mac->ops.setup_link = e1000_setup_link_generic; 268176667Sjfv /* physical interface link setup */ 269176667Sjfv mac->ops.setup_physical_interface = 270176667Sjfv (hw->phy.media_type == e1000_media_type_copper) 271176667Sjfv ? e1000_setup_copper_link_82575 272176667Sjfv : e1000_setup_fiber_serdes_link_82575; 273181027Sjfv /* physical interface shutdown */ 274181027Sjfv mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575; 275176667Sjfv /* check for link */ 276176667Sjfv mac->ops.check_for_link = e1000_check_for_link_82575; 277176667Sjfv /* receive address register setting */ 278176667Sjfv mac->ops.rar_set = e1000_rar_set_generic; 279176667Sjfv /* read mac address */ 280176667Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 281176667Sjfv /* multicast address update */ 282190872Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 283176667Sjfv /* writing VFTA */ 284176667Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 285176667Sjfv /* clearing VFTA */ 286176667Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 287176667Sjfv /* setting MTA */ 288176667Sjfv mac->ops.mta_set = e1000_mta_set_generic; 289190872Sjfv /* ID LED init */ 290190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 291176667Sjfv /* blink LED */ 292176667Sjfv mac->ops.blink_led = e1000_blink_led_generic; 293176667Sjfv /* setup LED */ 294176667Sjfv mac->ops.setup_led = e1000_setup_led_generic; 295176667Sjfv /* cleanup LED */ 296176667Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 297176667Sjfv /* turn on/off LED */ 298176667Sjfv mac->ops.led_on = e1000_led_on_generic; 299176667Sjfv mac->ops.led_off = e1000_led_off_generic; 300176667Sjfv /* clear hardware counters */ 301176667Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 302176667Sjfv /* link info */ 303176667Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 304176667Sjfv 305185353Sjfv return E1000_SUCCESS; 306176667Sjfv} 307176667Sjfv 308176667Sjfv/** 309176667Sjfv * e1000_init_function_pointers_82575 - Init func ptrs. 310176667Sjfv * @hw: pointer to the HW structure 311176667Sjfv * 312185353Sjfv * Called to initialize all function pointers and parameters. 313176667Sjfv **/ 314176667Sjfvvoid e1000_init_function_pointers_82575(struct e1000_hw *hw) 315176667Sjfv{ 316176667Sjfv DEBUGFUNC("e1000_init_function_pointers_82575"); 317176667Sjfv 318176667Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82575; 319176667Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 320176667Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82575; 321176667Sjfv} 322176667Sjfv 323176667Sjfv/** 324176667Sjfv * e1000_acquire_phy_82575 - Acquire rights to access PHY 325176667Sjfv * @hw: pointer to the HW structure 326176667Sjfv * 327185353Sjfv * Acquire access rights to the correct PHY. 328176667Sjfv **/ 329176667Sjfvstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 330176667Sjfv{ 331194865Sjfv u16 mask = E1000_SWFW_PHY0_SM; 332176667Sjfv 333176667Sjfv DEBUGFUNC("e1000_acquire_phy_82575"); 334176667Sjfv 335194865Sjfv if (hw->bus.func == E1000_FUNC_1) 336194865Sjfv mask = E1000_SWFW_PHY1_SM; 337176667Sjfv 338176667Sjfv return e1000_acquire_swfw_sync_82575(hw, mask); 339176667Sjfv} 340176667Sjfv 341176667Sjfv/** 342176667Sjfv * e1000_release_phy_82575 - Release rights to access PHY 343176667Sjfv * @hw: pointer to the HW structure 344176667Sjfv * 345185353Sjfv * A wrapper to release access rights to the correct PHY. 346176667Sjfv **/ 347176667Sjfvstatic void e1000_release_phy_82575(struct e1000_hw *hw) 348176667Sjfv{ 349194865Sjfv u16 mask = E1000_SWFW_PHY0_SM; 350176667Sjfv 351176667Sjfv DEBUGFUNC("e1000_release_phy_82575"); 352176667Sjfv 353194865Sjfv if (hw->bus.func == E1000_FUNC_1) 354194865Sjfv mask = E1000_SWFW_PHY1_SM; 355194865Sjfv 356176667Sjfv e1000_release_swfw_sync_82575(hw, mask); 357176667Sjfv} 358176667Sjfv 359176667Sjfv/** 360176667Sjfv * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 361176667Sjfv * @hw: pointer to the HW structure 362176667Sjfv * @offset: register offset to be read 363176667Sjfv * @data: pointer to the read data 364176667Sjfv * 365176667Sjfv * Reads the PHY register at offset using the serial gigabit media independent 366176667Sjfv * interface and stores the retrieved information in data. 367176667Sjfv **/ 368176667Sjfvstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 369176667Sjfv u16 *data) 370176667Sjfv{ 371176667Sjfv struct e1000_phy_info *phy = &hw->phy; 372176667Sjfv u32 i, i2ccmd = 0; 373176667Sjfv 374176667Sjfv DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 375176667Sjfv 376176667Sjfv if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 377176667Sjfv DEBUGOUT1("PHY Address %u is out of range\n", offset); 378176667Sjfv return -E1000_ERR_PARAM; 379176667Sjfv } 380176667Sjfv 381176667Sjfv /* 382176667Sjfv * Set up Op-code, Phy Address, and register address in the I2CCMD 383176667Sjfv * register. The MAC will take care of interfacing with the 384176667Sjfv * PHY to retrieve the desired data. 385176667Sjfv */ 386176667Sjfv i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 387176667Sjfv (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 388176667Sjfv (E1000_I2CCMD_OPCODE_READ)); 389176667Sjfv 390176667Sjfv E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 391176667Sjfv 392176667Sjfv /* Poll the ready bit to see if the I2C read completed */ 393176667Sjfv for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 394176667Sjfv usec_delay(50); 395176667Sjfv i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 396176667Sjfv if (i2ccmd & E1000_I2CCMD_READY) 397176667Sjfv break; 398176667Sjfv } 399176667Sjfv if (!(i2ccmd & E1000_I2CCMD_READY)) { 400176667Sjfv DEBUGOUT("I2CCMD Read did not complete\n"); 401176667Sjfv return -E1000_ERR_PHY; 402176667Sjfv } 403176667Sjfv if (i2ccmd & E1000_I2CCMD_ERROR) { 404176667Sjfv DEBUGOUT("I2CCMD Error bit set\n"); 405176667Sjfv return -E1000_ERR_PHY; 406176667Sjfv } 407176667Sjfv 408176667Sjfv /* Need to byte-swap the 16-bit value. */ 409176667Sjfv *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 410176667Sjfv 411176667Sjfv return E1000_SUCCESS; 412176667Sjfv} 413176667Sjfv 414176667Sjfv/** 415176667Sjfv * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 416176667Sjfv * @hw: pointer to the HW structure 417176667Sjfv * @offset: register offset to write to 418176667Sjfv * @data: data to write at register offset 419176667Sjfv * 420176667Sjfv * Writes the data to PHY register at the offset using the serial gigabit 421176667Sjfv * media independent interface. 422176667Sjfv **/ 423176667Sjfvstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 424176667Sjfv u16 data) 425176667Sjfv{ 426176667Sjfv struct e1000_phy_info *phy = &hw->phy; 427176667Sjfv u32 i, i2ccmd = 0; 428176667Sjfv u16 phy_data_swapped; 429176667Sjfv 430176667Sjfv DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 431176667Sjfv 432176667Sjfv if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 433176667Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 434176667Sjfv return -E1000_ERR_PARAM; 435176667Sjfv } 436176667Sjfv 437176667Sjfv /* Swap the data bytes for the I2C interface */ 438176667Sjfv phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 439176667Sjfv 440176667Sjfv /* 441176667Sjfv * Set up Op-code, Phy Address, and register address in the I2CCMD 442176667Sjfv * register. The MAC will take care of interfacing with the 443176667Sjfv * PHY to retrieve the desired data. 444176667Sjfv */ 445176667Sjfv i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 446176667Sjfv (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 447176667Sjfv E1000_I2CCMD_OPCODE_WRITE | 448176667Sjfv phy_data_swapped); 449176667Sjfv 450176667Sjfv E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 451176667Sjfv 452176667Sjfv /* Poll the ready bit to see if the I2C read completed */ 453176667Sjfv for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 454176667Sjfv usec_delay(50); 455176667Sjfv i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 456176667Sjfv if (i2ccmd & E1000_I2CCMD_READY) 457176667Sjfv break; 458176667Sjfv } 459176667Sjfv if (!(i2ccmd & E1000_I2CCMD_READY)) { 460176667Sjfv DEBUGOUT("I2CCMD Write did not complete\n"); 461176667Sjfv return -E1000_ERR_PHY; 462176667Sjfv } 463176667Sjfv if (i2ccmd & E1000_I2CCMD_ERROR) { 464176667Sjfv DEBUGOUT("I2CCMD Error bit set\n"); 465176667Sjfv return -E1000_ERR_PHY; 466176667Sjfv } 467176667Sjfv 468176667Sjfv return E1000_SUCCESS; 469176667Sjfv} 470176667Sjfv 471176667Sjfv/** 472176667Sjfv * e1000_get_phy_id_82575 - Retrieve PHY addr and id 473176667Sjfv * @hw: pointer to the HW structure 474176667Sjfv * 475176667Sjfv * Retrieves the PHY address and ID for both PHY's which do and do not use 476176667Sjfv * sgmi interface. 477176667Sjfv **/ 478176667Sjfvstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 479176667Sjfv{ 480176667Sjfv struct e1000_phy_info *phy = &hw->phy; 481176667Sjfv s32 ret_val = E1000_SUCCESS; 482176667Sjfv u16 phy_id; 483176667Sjfv 484176667Sjfv DEBUGFUNC("e1000_get_phy_id_82575"); 485176667Sjfv 486176667Sjfv /* 487176667Sjfv * For SGMII PHYs, we try the list of possible addresses until 488176667Sjfv * we find one that works. For non-SGMII PHYs 489176667Sjfv * (e.g. integrated copper PHYs), an address of 1 should 490176667Sjfv * work. The result of this function should mean phy->phy_addr 491176667Sjfv * and phy->id are set correctly. 492176667Sjfv */ 493176667Sjfv if (!(e1000_sgmii_active_82575(hw))) { 494176667Sjfv phy->addr = 1; 495176667Sjfv ret_val = e1000_get_phy_id(hw); 496176667Sjfv goto out; 497176667Sjfv } 498176667Sjfv 499176667Sjfv /* 500176667Sjfv * The address field in the I2CCMD register is 3 bits and 0 is invalid. 501176667Sjfv * Therefore, we need to test 1-7 502176667Sjfv */ 503176667Sjfv for (phy->addr = 1; phy->addr < 8; phy->addr++) { 504176667Sjfv ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 505176667Sjfv if (ret_val == E1000_SUCCESS) { 506176667Sjfv DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 507176667Sjfv phy_id, 508176667Sjfv phy->addr); 509176667Sjfv /* 510176667Sjfv * At the time of this writing, The M88 part is 511176667Sjfv * the only supported SGMII PHY product. 512176667Sjfv */ 513176667Sjfv if (phy_id == M88_VENDOR) 514176667Sjfv break; 515176667Sjfv } else { 516176667Sjfv DEBUGOUT1("PHY address %u was unreadable\n", 517176667Sjfv phy->addr); 518176667Sjfv } 519176667Sjfv } 520176667Sjfv 521176667Sjfv /* A valid PHY type couldn't be found. */ 522176667Sjfv if (phy->addr == 8) { 523176667Sjfv phy->addr = 0; 524176667Sjfv ret_val = -E1000_ERR_PHY; 525176667Sjfv goto out; 526176667Sjfv } 527176667Sjfv 528176667Sjfv ret_val = e1000_get_phy_id(hw); 529176667Sjfv 530176667Sjfvout: 531176667Sjfv return ret_val; 532176667Sjfv} 533176667Sjfv 534176667Sjfv/** 535176667Sjfv * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 536176667Sjfv * @hw: pointer to the HW structure 537176667Sjfv * 538176667Sjfv * Resets the PHY using the serial gigabit media independent interface. 539176667Sjfv **/ 540176667Sjfvstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 541176667Sjfv{ 542176667Sjfv s32 ret_val = E1000_SUCCESS; 543176667Sjfv 544176667Sjfv DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 545176667Sjfv 546176667Sjfv /* 547178523Sjfv * This isn't a TRUE "hard" reset, but is the only reset 548176667Sjfv * available to us at this time. 549176667Sjfv */ 550176667Sjfv 551176667Sjfv DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 552176667Sjfv 553176667Sjfv if (!(hw->phy.ops.write_reg)) 554176667Sjfv goto out; 555176667Sjfv 556176667Sjfv /* 557176667Sjfv * SFP documentation requires the following to configure the SPF module 558176667Sjfv * to work on SGMII. No further documentation is given. 559176667Sjfv */ 560176667Sjfv ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 561176667Sjfv if (ret_val) 562176667Sjfv goto out; 563176667Sjfv 564176667Sjfv ret_val = hw->phy.ops.commit(hw); 565176667Sjfv 566176667Sjfvout: 567176667Sjfv return ret_val; 568176667Sjfv} 569176667Sjfv 570176667Sjfv/** 571176667Sjfv * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 572176667Sjfv * @hw: pointer to the HW structure 573176667Sjfv * @active: TRUE to enable LPLU, FALSE to disable 574176667Sjfv * 575176667Sjfv * Sets the LPLU D0 state according to the active flag. When 576176667Sjfv * activating LPLU this function also disables smart speed 577176667Sjfv * and vice versa. LPLU will not be activated unless the 578176667Sjfv * device autonegotiation advertisement meets standards of 579176667Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 580176667Sjfv * This is a function pointer entry point only called by 581176667Sjfv * PHY setup routines. 582176667Sjfv **/ 583176667Sjfvstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 584176667Sjfv{ 585176667Sjfv struct e1000_phy_info *phy = &hw->phy; 586176667Sjfv s32 ret_val = E1000_SUCCESS; 587176667Sjfv u16 data; 588176667Sjfv 589176667Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 590176667Sjfv 591176667Sjfv if (!(hw->phy.ops.read_reg)) 592176667Sjfv goto out; 593176667Sjfv 594176667Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 595176667Sjfv if (ret_val) 596176667Sjfv goto out; 597176667Sjfv 598176667Sjfv if (active) { 599176667Sjfv data |= IGP02E1000_PM_D0_LPLU; 600176667Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 601176667Sjfv data); 602176667Sjfv if (ret_val) 603176667Sjfv goto out; 604176667Sjfv 605176667Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 606176667Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 607176667Sjfv &data); 608176667Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 609176667Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 610176667Sjfv data); 611176667Sjfv if (ret_val) 612176667Sjfv goto out; 613176667Sjfv } else { 614176667Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 615176667Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 616176667Sjfv data); 617176667Sjfv /* 618176667Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 619176667Sjfv * during Dx states where the power conservation is most 620176667Sjfv * important. During driver activity we should enable 621176667Sjfv * SmartSpeed, so performance is maintained. 622176667Sjfv */ 623176667Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 624176667Sjfv ret_val = phy->ops.read_reg(hw, 625176667Sjfv IGP01E1000_PHY_PORT_CONFIG, 626176667Sjfv &data); 627176667Sjfv if (ret_val) 628176667Sjfv goto out; 629176667Sjfv 630176667Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 631176667Sjfv ret_val = phy->ops.write_reg(hw, 632176667Sjfv IGP01E1000_PHY_PORT_CONFIG, 633176667Sjfv data); 634176667Sjfv if (ret_val) 635176667Sjfv goto out; 636176667Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 637176667Sjfv ret_val = phy->ops.read_reg(hw, 638176667Sjfv IGP01E1000_PHY_PORT_CONFIG, 639176667Sjfv &data); 640176667Sjfv if (ret_val) 641176667Sjfv goto out; 642176667Sjfv 643176667Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 644176667Sjfv ret_val = phy->ops.write_reg(hw, 645176667Sjfv IGP01E1000_PHY_PORT_CONFIG, 646176667Sjfv data); 647176667Sjfv if (ret_val) 648176667Sjfv goto out; 649176667Sjfv } 650176667Sjfv } 651176667Sjfv 652176667Sjfvout: 653176667Sjfv return ret_val; 654176667Sjfv} 655176667Sjfv 656176667Sjfv/** 657176667Sjfv * e1000_acquire_nvm_82575 - Request for access to EEPROM 658176667Sjfv * @hw: pointer to the HW structure 659176667Sjfv * 660176667Sjfv * Acquire the necessary semaphores for exclusive access to the EEPROM. 661176667Sjfv * Set the EEPROM access request bit and wait for EEPROM access grant bit. 662176667Sjfv * Return successful if access grant bit set, else clear the request for 663176667Sjfv * EEPROM access and return -E1000_ERR_NVM (-1). 664176667Sjfv **/ 665176667Sjfvstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 666176667Sjfv{ 667176667Sjfv s32 ret_val; 668176667Sjfv 669176667Sjfv DEBUGFUNC("e1000_acquire_nvm_82575"); 670176667Sjfv 671176667Sjfv ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 672176667Sjfv if (ret_val) 673176667Sjfv goto out; 674176667Sjfv 675176667Sjfv ret_val = e1000_acquire_nvm_generic(hw); 676176667Sjfv 677176667Sjfv if (ret_val) 678176667Sjfv e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 679176667Sjfv 680176667Sjfvout: 681176667Sjfv return ret_val; 682176667Sjfv} 683176667Sjfv 684176667Sjfv/** 685176667Sjfv * e1000_release_nvm_82575 - Release exclusive access to EEPROM 686176667Sjfv * @hw: pointer to the HW structure 687176667Sjfv * 688176667Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit, 689176667Sjfv * then release the semaphores acquired. 690176667Sjfv **/ 691176667Sjfvstatic void e1000_release_nvm_82575(struct e1000_hw *hw) 692176667Sjfv{ 693176667Sjfv DEBUGFUNC("e1000_release_nvm_82575"); 694176667Sjfv 695176667Sjfv e1000_release_nvm_generic(hw); 696176667Sjfv e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 697176667Sjfv} 698176667Sjfv 699176667Sjfv/** 700176667Sjfv * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 701176667Sjfv * @hw: pointer to the HW structure 702176667Sjfv * @mask: specifies which semaphore to acquire 703176667Sjfv * 704176667Sjfv * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 705176667Sjfv * will also specify which port we're acquiring the lock for. 706176667Sjfv **/ 707176667Sjfvstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 708176667Sjfv{ 709176667Sjfv u32 swfw_sync; 710176667Sjfv u32 swmask = mask; 711176667Sjfv u32 fwmask = mask << 16; 712176667Sjfv s32 ret_val = E1000_SUCCESS; 713176667Sjfv s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 714176667Sjfv 715176667Sjfv DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 716176667Sjfv 717176667Sjfv while (i < timeout) { 718176667Sjfv if (e1000_get_hw_semaphore_generic(hw)) { 719176667Sjfv ret_val = -E1000_ERR_SWFW_SYNC; 720176667Sjfv goto out; 721176667Sjfv } 722176667Sjfv 723176667Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 724176667Sjfv if (!(swfw_sync & (fwmask | swmask))) 725176667Sjfv break; 726176667Sjfv 727176667Sjfv /* 728176667Sjfv * Firmware currently using resource (fwmask) 729176667Sjfv * or other software thread using resource (swmask) 730176667Sjfv */ 731176667Sjfv e1000_put_hw_semaphore_generic(hw); 732176667Sjfv msec_delay_irq(5); 733176667Sjfv i++; 734176667Sjfv } 735176667Sjfv 736176667Sjfv if (i == timeout) { 737176667Sjfv DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 738176667Sjfv ret_val = -E1000_ERR_SWFW_SYNC; 739176667Sjfv goto out; 740176667Sjfv } 741176667Sjfv 742176667Sjfv swfw_sync |= swmask; 743176667Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 744176667Sjfv 745176667Sjfv e1000_put_hw_semaphore_generic(hw); 746176667Sjfv 747176667Sjfvout: 748176667Sjfv return ret_val; 749176667Sjfv} 750176667Sjfv 751176667Sjfv/** 752176667Sjfv * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 753176667Sjfv * @hw: pointer to the HW structure 754176667Sjfv * @mask: specifies which semaphore to acquire 755176667Sjfv * 756176667Sjfv * Release the SW/FW semaphore used to access the PHY or NVM. The mask 757176667Sjfv * will also specify which port we're releasing the lock for. 758176667Sjfv **/ 759176667Sjfvstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 760176667Sjfv{ 761176667Sjfv u32 swfw_sync; 762176667Sjfv 763176667Sjfv DEBUGFUNC("e1000_release_swfw_sync_82575"); 764176667Sjfv 765176667Sjfv while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 766176667Sjfv /* Empty */ 767176667Sjfv 768176667Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 769176667Sjfv swfw_sync &= ~mask; 770176667Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 771176667Sjfv 772176667Sjfv e1000_put_hw_semaphore_generic(hw); 773176667Sjfv} 774176667Sjfv 775176667Sjfv/** 776176667Sjfv * e1000_get_cfg_done_82575 - Read config done bit 777176667Sjfv * @hw: pointer to the HW structure 778176667Sjfv * 779176667Sjfv * Read the management control register for the config done bit for 780176667Sjfv * completion status. NOTE: silicon which is EEPROM-less will fail trying 781176667Sjfv * to read the config done bit, so an error is *ONLY* logged and returns 782176667Sjfv * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 783176667Sjfv * would not be able to be reset or change link. 784176667Sjfv **/ 785176667Sjfvstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 786176667Sjfv{ 787176667Sjfv s32 timeout = PHY_CFG_TIMEOUT; 788176667Sjfv s32 ret_val = E1000_SUCCESS; 789176667Sjfv u32 mask = E1000_NVM_CFG_DONE_PORT_0; 790176667Sjfv 791176667Sjfv DEBUGFUNC("e1000_get_cfg_done_82575"); 792176667Sjfv 793194865Sjfv if (hw->bus.func == E1000_FUNC_1) 794176667Sjfv mask = E1000_NVM_CFG_DONE_PORT_1; 795176667Sjfv while (timeout) { 796176667Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 797176667Sjfv break; 798176667Sjfv msec_delay(1); 799176667Sjfv timeout--; 800176667Sjfv } 801176667Sjfv if (!timeout) { 802176667Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 803176667Sjfv } 804176667Sjfv 805176667Sjfv /* If EEPROM is not marked present, init the PHY manually */ 806176667Sjfv if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 807176667Sjfv (hw->phy.type == e1000_phy_igp_3)) { 808176667Sjfv e1000_phy_init_script_igp3(hw); 809176667Sjfv } 810176667Sjfv 811176667Sjfv return ret_val; 812176667Sjfv} 813176667Sjfv 814176667Sjfv/** 815176667Sjfv * e1000_get_link_up_info_82575 - Get link speed/duplex info 816176667Sjfv * @hw: pointer to the HW structure 817176667Sjfv * @speed: stores the current speed 818176667Sjfv * @duplex: stores the current duplex 819176667Sjfv * 820176667Sjfv * This is a wrapper function, if using the serial gigabit media independent 821176667Sjfv * interface, use PCS to retrieve the link speed and duplex information. 822176667Sjfv * Otherwise, use the generic function to get the link speed and duplex info. 823176667Sjfv **/ 824176667Sjfvstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 825176667Sjfv u16 *duplex) 826176667Sjfv{ 827176667Sjfv s32 ret_val; 828176667Sjfv 829176667Sjfv DEBUGFUNC("e1000_get_link_up_info_82575"); 830176667Sjfv 831176667Sjfv if (hw->phy.media_type != e1000_media_type_copper || 832176667Sjfv e1000_sgmii_active_82575(hw)) { 833176667Sjfv ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 834176667Sjfv duplex); 835176667Sjfv } else { 836176667Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 837176667Sjfv duplex); 838176667Sjfv } 839176667Sjfv 840176667Sjfv return ret_val; 841176667Sjfv} 842176667Sjfv 843176667Sjfv/** 844176667Sjfv * e1000_check_for_link_82575 - Check for link 845176667Sjfv * @hw: pointer to the HW structure 846176667Sjfv * 847176667Sjfv * If sgmii is enabled, then use the pcs register to determine link, otherwise 848176667Sjfv * use the generic interface for determining link. 849176667Sjfv **/ 850176667Sjfvstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw) 851176667Sjfv{ 852176667Sjfv s32 ret_val; 853176667Sjfv u16 speed, duplex; 854176667Sjfv 855176667Sjfv DEBUGFUNC("e1000_check_for_link_82575"); 856176667Sjfv 857176667Sjfv /* SGMII link check is done through the PCS register. */ 858176667Sjfv if ((hw->phy.media_type != e1000_media_type_copper) || 859190872Sjfv (e1000_sgmii_active_82575(hw))) { 860176667Sjfv ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 861176667Sjfv &duplex); 862190872Sjfv /* 863190872Sjfv * Use this flag to determine if link needs to be checked or 864190872Sjfv * not. If we have link clear the flag so that we do not 865190872Sjfv * continue to check for link. 866190872Sjfv */ 867190872Sjfv hw->mac.get_link_status = !hw->mac.serdes_has_link; 868190872Sjfv } else { 869176667Sjfv ret_val = e1000_check_for_copper_link_generic(hw); 870190872Sjfv } 871176667Sjfv 872176667Sjfv return ret_val; 873176667Sjfv} 874176667Sjfv 875176667Sjfv/** 876176667Sjfv * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 877176667Sjfv * @hw: pointer to the HW structure 878176667Sjfv * @speed: stores the current speed 879176667Sjfv * @duplex: stores the current duplex 880176667Sjfv * 881176667Sjfv * Using the physical coding sub-layer (PCS), retrieve the current speed and 882176667Sjfv * duplex, then store the values in the pointers provided. 883176667Sjfv **/ 884176667Sjfvstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 885176667Sjfv u16 *speed, u16 *duplex) 886176667Sjfv{ 887176667Sjfv struct e1000_mac_info *mac = &hw->mac; 888176667Sjfv u32 pcs; 889176667Sjfv 890176667Sjfv DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 891176667Sjfv 892176667Sjfv /* Set up defaults for the return values of this function */ 893176667Sjfv mac->serdes_has_link = FALSE; 894176667Sjfv *speed = 0; 895176667Sjfv *duplex = 0; 896176667Sjfv 897176667Sjfv /* 898176667Sjfv * Read the PCS Status register for link state. For non-copper mode, 899176667Sjfv * the status register is not accurate. The PCS status register is 900176667Sjfv * used instead. 901176667Sjfv */ 902176667Sjfv pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 903176667Sjfv 904176667Sjfv /* 905176667Sjfv * The link up bit determines when link is up on autoneg. The sync ok 906176667Sjfv * gets set once both sides sync up and agree upon link. Stable link 907176667Sjfv * can be determined by checking for both link up and link sync ok 908176667Sjfv */ 909176667Sjfv if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 910176667Sjfv mac->serdes_has_link = TRUE; 911176667Sjfv 912176667Sjfv /* Detect and store PCS speed */ 913176667Sjfv if (pcs & E1000_PCS_LSTS_SPEED_1000) { 914176667Sjfv *speed = SPEED_1000; 915176667Sjfv } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 916176667Sjfv *speed = SPEED_100; 917176667Sjfv } else { 918176667Sjfv *speed = SPEED_10; 919176667Sjfv } 920176667Sjfv 921176667Sjfv /* Detect and store PCS duplex */ 922176667Sjfv if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 923176667Sjfv *duplex = FULL_DUPLEX; 924176667Sjfv } else { 925176667Sjfv *duplex = HALF_DUPLEX; 926176667Sjfv } 927176667Sjfv } 928176667Sjfv 929176667Sjfv return E1000_SUCCESS; 930176667Sjfv} 931176667Sjfv 932176667Sjfv/** 933181027Sjfv * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down 934181027Sjfv * @hw: pointer to the HW structure 935181027Sjfv * 936181027Sjfv * In the case of fiber serdes shut down optics and PCS on driver unload 937181027Sjfv * when management pass thru is not enabled. 938181027Sjfv **/ 939181027Sjfvvoid e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) 940181027Sjfv{ 941181027Sjfv u32 reg; 942185353Sjfv u16 eeprom_data = 0; 943181027Sjfv 944194865Sjfv if (hw->phy.media_type != e1000_media_type_internal_serdes) 945181027Sjfv return; 946181027Sjfv 947194865Sjfv if (hw->bus.func == E1000_FUNC_0) 948185353Sjfv hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 949194865Sjfv else if (hw->bus.func == E1000_FUNC_1) 950194865Sjfv hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 951185353Sjfv 952185353Sjfv /* 953185353Sjfv * If APM is not enabled in the EEPROM and management interface is 954185353Sjfv * not enabled, then power down. 955185353Sjfv */ 956185353Sjfv if (!(eeprom_data & E1000_NVM_APME_82575) && 957185353Sjfv !e1000_enable_mng_pass_thru(hw)) { 958181027Sjfv /* Disable PCS to turn off link */ 959181027Sjfv reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 960181027Sjfv reg &= ~E1000_PCS_CFG_PCS_EN; 961181027Sjfv E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 962181027Sjfv 963181027Sjfv /* shutdown the laser */ 964181027Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 965181027Sjfv reg |= E1000_CTRL_EXT_SDP7_DATA; 966181027Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 967181027Sjfv 968181027Sjfv /* flush the write to verfiy completion */ 969181027Sjfv E1000_WRITE_FLUSH(hw); 970181027Sjfv msec_delay(1); 971181027Sjfv } 972181027Sjfv 973181027Sjfv return; 974181027Sjfv} 975181027Sjfv 976181027Sjfv/** 977194865Sjfv * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 978190872Sjfv * @hw: pointer to the HW structure 979194865Sjfv * @enable: state to enter, either enabled or disabled 980194865Sjfv * 981194865Sjfv * enables/disables L2 switch loopback functionality 982190872Sjfv **/ 983194865Sjfvvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 984190872Sjfv{ 985190872Sjfv u32 reg; 986190872Sjfv 987190872Sjfv reg = E1000_READ_REG(hw, E1000_DTXSWC); 988194865Sjfv if (enable) 989194865Sjfv reg |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 990194865Sjfv else 991194865Sjfv reg &= ~(E1000_DTXSWC_VMDQ_LOOPBACK_EN); 992190872Sjfv E1000_WRITE_REG(hw, E1000_DTXSWC, reg); 993190872Sjfv} 994190872Sjfv 995190872Sjfv/** 996194865Sjfv * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 997190872Sjfv * @hw: pointer to the HW structure 998194865Sjfv * @enable: state to enter, either enabled or disabled 999190872Sjfv * 1000194865Sjfv * enables/disables replication of packets across multiple pools 1001190872Sjfv **/ 1002194865Sjfvvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1003190872Sjfv{ 1004190872Sjfv u32 reg; 1005190872Sjfv 1006190872Sjfv reg = E1000_READ_REG(hw, E1000_VT_CTL); 1007194865Sjfv if (enable) 1008194865Sjfv reg |= E1000_VT_CTL_VM_REPL_EN; 1009194865Sjfv else 1010194865Sjfv reg &= ~(E1000_VT_CTL_VM_REPL_EN); 1011190872Sjfv 1012190872Sjfv E1000_WRITE_REG(hw, E1000_VT_CTL, reg); 1013190872Sjfv} 1014190872Sjfv 1015190872Sjfv/** 1016176667Sjfv * e1000_reset_hw_82575 - Reset hardware 1017176667Sjfv * @hw: pointer to the HW structure 1018176667Sjfv * 1019185353Sjfv * This resets the hardware into a known state. 1020176667Sjfv **/ 1021176667Sjfvstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1022176667Sjfv{ 1023176667Sjfv u32 ctrl, icr; 1024176667Sjfv s32 ret_val; 1025176667Sjfv 1026176667Sjfv DEBUGFUNC("e1000_reset_hw_82575"); 1027176667Sjfv 1028176667Sjfv /* 1029176667Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 1030176667Sjfv * on the last TLP read/write transaction when MAC is reset. 1031176667Sjfv */ 1032176667Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 1033176667Sjfv if (ret_val) { 1034176667Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1035176667Sjfv } 1036176667Sjfv 1037194865Sjfv /* set the completion timeout for interface */ 1038194865Sjfv ret_val = e1000_set_pcie_completion_timeout(hw); 1039194865Sjfv if (ret_val) { 1040194865Sjfv DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1041194865Sjfv } 1042194865Sjfv 1043176667Sjfv DEBUGOUT("Masking off all interrupts\n"); 1044176667Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1045176667Sjfv 1046176667Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 1047176667Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1048176667Sjfv E1000_WRITE_FLUSH(hw); 1049176667Sjfv 1050176667Sjfv msec_delay(10); 1051176667Sjfv 1052176667Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1053176667Sjfv 1054176667Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 1055176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1056176667Sjfv 1057176667Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 1058176667Sjfv if (ret_val) { 1059176667Sjfv /* 1060176667Sjfv * When auto config read does not complete, do not 1061176667Sjfv * return with an error. This can happen in situations 1062176667Sjfv * where there is no eeprom and prevents getting link. 1063176667Sjfv */ 1064176667Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 1065176667Sjfv } 1066176667Sjfv 1067176667Sjfv /* If EEPROM is not present, run manual init scripts */ 1068176667Sjfv if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1069176667Sjfv e1000_reset_init_script_82575(hw); 1070176667Sjfv 1071176667Sjfv /* Clear any pending interrupt events. */ 1072176667Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1073176667Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 1074176667Sjfv 1075190872Sjfv /* Install any alternate MAC address into RAR0 */ 1076190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1077176667Sjfv 1078176667Sjfv return ret_val; 1079176667Sjfv} 1080176667Sjfv 1081176667Sjfv/** 1082176667Sjfv * e1000_init_hw_82575 - Initialize hardware 1083176667Sjfv * @hw: pointer to the HW structure 1084176667Sjfv * 1085176667Sjfv * This inits the hardware readying it for operation. 1086176667Sjfv **/ 1087176667Sjfvstatic s32 e1000_init_hw_82575(struct e1000_hw *hw) 1088176667Sjfv{ 1089176667Sjfv struct e1000_mac_info *mac = &hw->mac; 1090176667Sjfv s32 ret_val; 1091176667Sjfv u16 i, rar_count = mac->rar_entry_count; 1092176667Sjfv 1093176667Sjfv DEBUGFUNC("e1000_init_hw_82575"); 1094176667Sjfv 1095176667Sjfv /* Initialize identification LED */ 1096190872Sjfv ret_val = mac->ops.id_led_init(hw); 1097176667Sjfv if (ret_val) { 1098176667Sjfv DEBUGOUT("Error initializing identification LED\n"); 1099176667Sjfv /* This is not fatal and we should not stop init due to this */ 1100176667Sjfv } 1101176667Sjfv 1102176667Sjfv /* Disabling VLAN filtering */ 1103176667Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 1104176667Sjfv mac->ops.clear_vfta(hw); 1105176667Sjfv 1106176667Sjfv /* Setup the receive address */ 1107190872Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 1108190872Sjfv 1109176667Sjfv /* Zero out the Multicast HASH table */ 1110176667Sjfv DEBUGOUT("Zeroing the MTA\n"); 1111176667Sjfv for (i = 0; i < mac->mta_reg_count; i++) 1112176667Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1113176667Sjfv 1114176667Sjfv /* Setup link and flow control */ 1115176667Sjfv ret_val = mac->ops.setup_link(hw); 1116176667Sjfv 1117176667Sjfv /* 1118176667Sjfv * Clear all of the statistics registers (clear on read). It is 1119176667Sjfv * important that we do this after we have tried to establish link 1120176667Sjfv * because the symbol error count will increment wildly if there 1121176667Sjfv * is no link. 1122176667Sjfv */ 1123176667Sjfv e1000_clear_hw_cntrs_82575(hw); 1124176667Sjfv 1125176667Sjfv return ret_val; 1126176667Sjfv} 1127176667Sjfv 1128176667Sjfv/** 1129176667Sjfv * e1000_setup_copper_link_82575 - Configure copper link settings 1130176667Sjfv * @hw: pointer to the HW structure 1131176667Sjfv * 1132176667Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1133176667Sjfv * for link, once link is established calls to configure collision distance 1134176667Sjfv * and flow control are called. 1135176667Sjfv **/ 1136176667Sjfvstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1137176667Sjfv{ 1138194865Sjfv u32 ctrl; 1139176667Sjfv s32 ret_val; 1140176667Sjfv bool link; 1141176667Sjfv 1142176667Sjfv DEBUGFUNC("e1000_setup_copper_link_82575"); 1143176667Sjfv 1144176667Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1145176667Sjfv ctrl |= E1000_CTRL_SLU; 1146176667Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1147176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1148176667Sjfv 1149176667Sjfv switch (hw->phy.type) { 1150176667Sjfv case e1000_phy_m88: 1151176667Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1152176667Sjfv break; 1153176667Sjfv case e1000_phy_igp_3: 1154176667Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1155176667Sjfv break; 1156176667Sjfv default: 1157176667Sjfv ret_val = -E1000_ERR_PHY; 1158176667Sjfv break; 1159176667Sjfv } 1160176667Sjfv 1161176667Sjfv if (ret_val) 1162176667Sjfv goto out; 1163176667Sjfv 1164176667Sjfv if (hw->mac.autoneg) { 1165176667Sjfv /* 1166176667Sjfv * Setup autoneg and flow control advertisement 1167176667Sjfv * and perform autonegotiation. 1168176667Sjfv */ 1169176667Sjfv ret_val = e1000_copper_link_autoneg(hw); 1170176667Sjfv if (ret_val) 1171176667Sjfv goto out; 1172176667Sjfv } else { 1173176667Sjfv /* 1174176667Sjfv * PHY will be set to 10H, 10F, 100H or 100F 1175176667Sjfv * depending on user settings. 1176176667Sjfv */ 1177176667Sjfv DEBUGOUT("Forcing Speed and Duplex\n"); 1178176667Sjfv ret_val = hw->phy.ops.force_speed_duplex(hw); 1179176667Sjfv if (ret_val) { 1180176667Sjfv DEBUGOUT("Error Forcing Speed and Duplex\n"); 1181176667Sjfv goto out; 1182176667Sjfv } 1183176667Sjfv } 1184176667Sjfv 1185176667Sjfv ret_val = e1000_configure_pcs_link_82575(hw); 1186176667Sjfv if (ret_val) 1187176667Sjfv goto out; 1188176667Sjfv 1189176667Sjfv /* 1190176667Sjfv * Check link status. Wait up to 100 microseconds for link to become 1191176667Sjfv * valid. 1192176667Sjfv */ 1193176667Sjfv ret_val = e1000_phy_has_link_generic(hw, 1194176667Sjfv COPPER_LINK_UP_LIMIT, 1195176667Sjfv 10, 1196176667Sjfv &link); 1197176667Sjfv if (ret_val) 1198176667Sjfv goto out; 1199176667Sjfv 1200176667Sjfv if (link) { 1201176667Sjfv DEBUGOUT("Valid link established!!!\n"); 1202176667Sjfv /* Config the MAC and PHY after link is up */ 1203176667Sjfv e1000_config_collision_dist_generic(hw); 1204176667Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1205176667Sjfv } else { 1206176667Sjfv DEBUGOUT("Unable to establish link!!!\n"); 1207176667Sjfv } 1208176667Sjfv 1209176667Sjfvout: 1210176667Sjfv return ret_val; 1211176667Sjfv} 1212176667Sjfv 1213176667Sjfv/** 1214176667Sjfv * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes 1215176667Sjfv * @hw: pointer to the HW structure 1216176667Sjfv * 1217176667Sjfv * Configures speed and duplex for fiber and serdes links. 1218176667Sjfv **/ 1219176667Sjfvstatic s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw) 1220176667Sjfv{ 1221176667Sjfv u32 reg; 1222176667Sjfv 1223176667Sjfv DEBUGFUNC("e1000_setup_fiber_serdes_link_82575"); 1224176667Sjfv 1225176667Sjfv /* 1226176667Sjfv * On the 82575, SerDes loopback mode persists until it is 1227176667Sjfv * explicitly turned off or a power cycle is performed. A read to 1228176667Sjfv * the register does not indicate its status. Therefore, we ensure 1229176667Sjfv * loopback mode is disabled during initialization. 1230176667Sjfv */ 1231176667Sjfv E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1232176667Sjfv 1233194865Sjfv /* Force link up, set 1gb */ 1234176667Sjfv reg = E1000_READ_REG(hw, E1000_CTRL); 1235194865Sjfv reg |= E1000_CTRL_SLU | E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD; 1236194865Sjfv if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1237194865Sjfv /* set both sw defined pins */ 1238194865Sjfv reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1239194865Sjfv } 1240176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL, reg); 1241181027Sjfv /* Power on phy for 82576 fiber adapters */ 1242181027Sjfv if (hw->mac.type == e1000_82576) { 1243181027Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1244181027Sjfv reg &= ~E1000_CTRL_EXT_SDP7_DATA; 1245181027Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1246181027Sjfv } 1247181027Sjfv 1248176667Sjfv /* Set switch control to serdes energy detect */ 1249176667Sjfv reg = E1000_READ_REG(hw, E1000_CONNSW); 1250176667Sjfv reg |= E1000_CONNSW_ENRGSRC; 1251176667Sjfv E1000_WRITE_REG(hw, E1000_CONNSW, reg); 1252176667Sjfv 1253176667Sjfv /* 1254176667Sjfv * New SerDes mode allows for forcing speed or autonegotiating speed 1255176667Sjfv * at 1gb. Autoneg should be default set by most drivers. This is the 1256176667Sjfv * mode that will be compatible with older link partners and switches. 1257176667Sjfv * However, both are supported by the hardware and some drivers/tools. 1258176667Sjfv */ 1259176667Sjfv reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1260176667Sjfv 1261176667Sjfv reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1262176667Sjfv E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1263176667Sjfv 1264176667Sjfv if (hw->mac.autoneg) { 1265176667Sjfv /* Set PCS register for autoneg */ 1266176667Sjfv reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1267176667Sjfv E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1268176667Sjfv E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1269176667Sjfv E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1270176667Sjfv DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); 1271176667Sjfv } else { 1272176667Sjfv /* Set PCS register for forced speed */ 1273176667Sjfv reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1274176667Sjfv E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1275176667Sjfv E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1276176667Sjfv E1000_PCS_LCTL_FSD | /* Force Speed */ 1277176667Sjfv E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1278176667Sjfv DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg); 1279176667Sjfv } 1280181027Sjfv 1281181027Sjfv if (hw->mac.type == e1000_82576) { 1282181027Sjfv reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1283181027Sjfv e1000_force_mac_fc_generic(hw); 1284181027Sjfv } 1285181027Sjfv 1286176667Sjfv E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1287176667Sjfv 1288176667Sjfv return E1000_SUCCESS; 1289176667Sjfv} 1290176667Sjfv 1291176667Sjfv/** 1292181027Sjfv * e1000_valid_led_default_82575 - Verify a valid default LED config 1293181027Sjfv * @hw: pointer to the HW structure 1294181027Sjfv * @data: pointer to the NVM (EEPROM) 1295181027Sjfv * 1296181027Sjfv * Read the EEPROM for the current default LED configuration. If the 1297181027Sjfv * LED configuration is not valid, set to a valid LED configuration. 1298181027Sjfv **/ 1299181027Sjfvstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1300181027Sjfv{ 1301181027Sjfv s32 ret_val; 1302181027Sjfv 1303181027Sjfv DEBUGFUNC("e1000_valid_led_default_82575"); 1304181027Sjfv 1305181027Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1306181027Sjfv if (ret_val) { 1307181027Sjfv DEBUGOUT("NVM Read Error\n"); 1308181027Sjfv goto out; 1309181027Sjfv } 1310181027Sjfv 1311181027Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1312181027Sjfv switch(hw->phy.media_type) { 1313181027Sjfv case e1000_media_type_internal_serdes: 1314181027Sjfv *data = ID_LED_DEFAULT_82575_SERDES; 1315181027Sjfv break; 1316181027Sjfv case e1000_media_type_copper: 1317181027Sjfv default: 1318181027Sjfv *data = ID_LED_DEFAULT; 1319181027Sjfv break; 1320181027Sjfv } 1321181027Sjfv } 1322181027Sjfvout: 1323181027Sjfv return ret_val; 1324181027Sjfv} 1325181027Sjfv 1326181027Sjfv/** 1327176667Sjfv * e1000_configure_pcs_link_82575 - Configure PCS link 1328176667Sjfv * @hw: pointer to the HW structure 1329176667Sjfv * 1330176667Sjfv * Configure the physical coding sub-layer (PCS) link. The PCS link is 1331176667Sjfv * only used on copper connections where the serialized gigabit media 1332176667Sjfv * independent interface (sgmii) is being used. Configures the link 1333176667Sjfv * for auto-negotiation or forces speed/duplex. 1334176667Sjfv **/ 1335176667Sjfvstatic s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw) 1336176667Sjfv{ 1337176667Sjfv struct e1000_mac_info *mac = &hw->mac; 1338176667Sjfv u32 reg = 0; 1339176667Sjfv 1340176667Sjfv DEBUGFUNC("e1000_configure_pcs_link_82575"); 1341176667Sjfv 1342176667Sjfv if (hw->phy.media_type != e1000_media_type_copper || 1343176667Sjfv !(e1000_sgmii_active_82575(hw))) 1344176667Sjfv goto out; 1345176667Sjfv 1346176667Sjfv /* For SGMII, we need to issue a PCS autoneg restart */ 1347176667Sjfv reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1348176667Sjfv 1349176667Sjfv /* AN time out should be disabled for SGMII mode */ 1350176667Sjfv reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1351176667Sjfv 1352176667Sjfv if (mac->autoneg) { 1353176667Sjfv /* Make sure forced speed and force link are not set */ 1354176667Sjfv reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1355176667Sjfv 1356176667Sjfv /* 1357176667Sjfv * The PHY should be setup prior to calling this function. 1358176667Sjfv * All we need to do is restart autoneg and enable autoneg. 1359176667Sjfv */ 1360176667Sjfv reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE; 1361176667Sjfv } else { 1362176667Sjfv /* Set PCS register for forced speed */ 1363176667Sjfv 1364176667Sjfv /* Turn off bits for full duplex, speed, and autoneg */ 1365176667Sjfv reg &= ~(E1000_PCS_LCTL_FSV_1000 | 1366176667Sjfv E1000_PCS_LCTL_FSV_100 | 1367176667Sjfv E1000_PCS_LCTL_FDV_FULL | 1368176667Sjfv E1000_PCS_LCTL_AN_ENABLE); 1369176667Sjfv 1370176667Sjfv /* Check for duplex first */ 1371176667Sjfv if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 1372176667Sjfv reg |= E1000_PCS_LCTL_FDV_FULL; 1373176667Sjfv 1374176667Sjfv /* Now set speed */ 1375176667Sjfv if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) 1376176667Sjfv reg |= E1000_PCS_LCTL_FSV_100; 1377176667Sjfv 1378176667Sjfv /* Force speed and force link */ 1379176667Sjfv reg |= E1000_PCS_LCTL_FSD | 1380176667Sjfv E1000_PCS_LCTL_FORCE_LINK | 1381176667Sjfv E1000_PCS_LCTL_FLV_LINK_UP; 1382176667Sjfv 1383176667Sjfv DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n", 1384176667Sjfv reg); 1385176667Sjfv } 1386176667Sjfv E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1387176667Sjfv 1388176667Sjfvout: 1389176667Sjfv return E1000_SUCCESS; 1390176667Sjfv} 1391176667Sjfv 1392176667Sjfv/** 1393176667Sjfv * e1000_sgmii_active_82575 - Return sgmii state 1394176667Sjfv * @hw: pointer to the HW structure 1395176667Sjfv * 1396176667Sjfv * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1397176667Sjfv * which can be enabled for use in the embedded applications. Simply 1398176667Sjfv * return the current state of the sgmii interface. 1399176667Sjfv **/ 1400176667Sjfvstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1401176667Sjfv{ 1402185353Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1403185353Sjfv return dev_spec->sgmii_active; 1404176667Sjfv} 1405176667Sjfv 1406176667Sjfv/** 1407176667Sjfv * e1000_reset_init_script_82575 - Inits HW defaults after reset 1408176667Sjfv * @hw: pointer to the HW structure 1409176667Sjfv * 1410176667Sjfv * Inits recommended HW defaults after a reset when there is no EEPROM 1411176667Sjfv * detected. This is only for the 82575. 1412176667Sjfv **/ 1413176667Sjfvstatic s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1414176667Sjfv{ 1415176667Sjfv DEBUGFUNC("e1000_reset_init_script_82575"); 1416176667Sjfv 1417176667Sjfv if (hw->mac.type == e1000_82575) { 1418176667Sjfv DEBUGOUT("Running reset init script for 82575\n"); 1419176667Sjfv /* SerDes configuration via SERDESCTRL */ 1420178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1421178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1422178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1423178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1424176667Sjfv 1425176667Sjfv /* CCM configuration via CCMCTL register */ 1426178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1427178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1428176667Sjfv 1429176667Sjfv /* PCIe lanes configuration */ 1430178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1431178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1432178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1433178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1434176667Sjfv 1435176667Sjfv /* PCIe PLL Configuration */ 1436178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1437178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1438178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1439176667Sjfv } 1440176667Sjfv 1441176667Sjfv return E1000_SUCCESS; 1442176667Sjfv} 1443176667Sjfv 1444176667Sjfv/** 1445176667Sjfv * e1000_read_mac_addr_82575 - Read device MAC address 1446176667Sjfv * @hw: pointer to the HW structure 1447176667Sjfv **/ 1448176667Sjfvstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1449176667Sjfv{ 1450176667Sjfv s32 ret_val = E1000_SUCCESS; 1451176667Sjfv 1452176667Sjfv DEBUGFUNC("e1000_read_mac_addr_82575"); 1453176667Sjfv 1454190872Sjfv /* 1455190872Sjfv * If there's an alternate MAC address place it in RAR0 1456190872Sjfv * so that it will override the Si installed default perm 1457190872Sjfv * address. 1458190872Sjfv */ 1459190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1460190872Sjfv if (ret_val) 1461190872Sjfv goto out; 1462190872Sjfv 1463190872Sjfv ret_val = e1000_read_mac_addr_generic(hw); 1464190872Sjfv 1465190872Sjfvout: 1466176667Sjfv return ret_val; 1467176667Sjfv} 1468176667Sjfv 1469176667Sjfv/** 1470176667Sjfv * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1471176667Sjfv * @hw: pointer to the HW structure 1472176667Sjfv * 1473176667Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1474176667Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1475176667Sjfv **/ 1476176667Sjfvstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1477176667Sjfv{ 1478176667Sjfv struct e1000_phy_info *phy = &hw->phy; 1479176667Sjfv struct e1000_mac_info *mac = &hw->mac; 1480176667Sjfv 1481176667Sjfv if (!(phy->ops.check_reset_block)) 1482176667Sjfv return; 1483176667Sjfv 1484176667Sjfv /* If the management interface is not enabled, then power down */ 1485176667Sjfv if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1486176667Sjfv e1000_power_down_phy_copper(hw); 1487176667Sjfv 1488176667Sjfv return; 1489176667Sjfv} 1490176667Sjfv 1491176667Sjfv/** 1492176667Sjfv * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1493176667Sjfv * @hw: pointer to the HW structure 1494176667Sjfv * 1495176667Sjfv * Clears the hardware counters by reading the counter registers. 1496176667Sjfv **/ 1497176667Sjfvstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1498176667Sjfv{ 1499176667Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1500176667Sjfv 1501176667Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1502176667Sjfv 1503185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 1504185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 1505185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 1506185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 1507185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 1508185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 1509185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 1510185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 1511185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 1512185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 1513185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 1514185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 1515176667Sjfv 1516185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 1517185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 1518185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 1519185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 1520185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 1521185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 1522176667Sjfv 1523185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 1524185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 1525185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 1526176667Sjfv 1527185353Sjfv E1000_READ_REG(hw, E1000_IAC); 1528185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 1529176667Sjfv 1530185353Sjfv E1000_READ_REG(hw, E1000_ICRXPTC); 1531185353Sjfv E1000_READ_REG(hw, E1000_ICRXATC); 1532185353Sjfv E1000_READ_REG(hw, E1000_ICTXPTC); 1533185353Sjfv E1000_READ_REG(hw, E1000_ICTXATC); 1534185353Sjfv E1000_READ_REG(hw, E1000_ICTXQEC); 1535185353Sjfv E1000_READ_REG(hw, E1000_ICTXQMTC); 1536185353Sjfv E1000_READ_REG(hw, E1000_ICRXDMTC); 1537176667Sjfv 1538185353Sjfv E1000_READ_REG(hw, E1000_CBTMPC); 1539185353Sjfv E1000_READ_REG(hw, E1000_HTDPMC); 1540185353Sjfv E1000_READ_REG(hw, E1000_CBRMPC); 1541185353Sjfv E1000_READ_REG(hw, E1000_RPTHC); 1542185353Sjfv E1000_READ_REG(hw, E1000_HGPTC); 1543185353Sjfv E1000_READ_REG(hw, E1000_HTCBDPC); 1544185353Sjfv E1000_READ_REG(hw, E1000_HGORCL); 1545185353Sjfv E1000_READ_REG(hw, E1000_HGORCH); 1546185353Sjfv E1000_READ_REG(hw, E1000_HGOTCL); 1547185353Sjfv E1000_READ_REG(hw, E1000_HGOTCH); 1548185353Sjfv E1000_READ_REG(hw, E1000_LENERRS); 1549176667Sjfv 1550176667Sjfv /* This register should not be read in copper configurations */ 1551176667Sjfv if (hw->phy.media_type == e1000_media_type_internal_serdes) 1552185353Sjfv E1000_READ_REG(hw, E1000_SCVPC); 1553176667Sjfv} 1554194865Sjfv 1555181027Sjfv/** 1556181027Sjfv * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1557181027Sjfv * @hw: pointer to the HW structure 1558181027Sjfv * 1559181027Sjfv * After rx enable if managability is enabled then there is likely some 1560181027Sjfv * bad data at the start of the fifo and possibly in the DMA fifo. This 1561181027Sjfv * function clears the fifos and flushes any packets that came in as rx was 1562181027Sjfv * being enabled. 1563181027Sjfv **/ 1564181027Sjfvvoid e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1565181027Sjfv{ 1566181027Sjfv u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1567181027Sjfv int i, ms_wait; 1568181027Sjfv 1569181027Sjfv DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1570181027Sjfv if (hw->mac.type != e1000_82575 || 1571181027Sjfv !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1572181027Sjfv return; 1573181027Sjfv 1574181027Sjfv /* Disable all RX queues */ 1575181027Sjfv for (i = 0; i < 4; i++) { 1576181027Sjfv rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1577181027Sjfv E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1578181027Sjfv rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1579181027Sjfv } 1580181027Sjfv /* Poll all queues to verify they have shut down */ 1581181027Sjfv for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1582181027Sjfv msec_delay(1); 1583181027Sjfv rx_enabled = 0; 1584181027Sjfv for (i = 0; i < 4; i++) 1585181027Sjfv rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1586181027Sjfv if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1587181027Sjfv break; 1588181027Sjfv } 1589181027Sjfv 1590181027Sjfv if (ms_wait == 10) 1591181027Sjfv DEBUGOUT("Queue disable timed out after 10ms\n"); 1592181027Sjfv 1593181027Sjfv /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1594181027Sjfv * incoming packets are rejected. Set enable and wait 2ms so that 1595181027Sjfv * any packet that was coming in as RCTL.EN was set is flushed 1596181027Sjfv */ 1597181027Sjfv rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1598181027Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1599181027Sjfv 1600181027Sjfv rlpml = E1000_READ_REG(hw, E1000_RLPML); 1601181027Sjfv E1000_WRITE_REG(hw, E1000_RLPML, 0); 1602181027Sjfv 1603181027Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 1604181027Sjfv temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1605181027Sjfv temp_rctl |= E1000_RCTL_LPE; 1606181027Sjfv 1607181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1608181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1609181027Sjfv E1000_WRITE_FLUSH(hw); 1610181027Sjfv msec_delay(2); 1611181027Sjfv 1612181027Sjfv /* Enable RX queues that were previously enabled and restore our 1613181027Sjfv * previous state 1614181027Sjfv */ 1615181027Sjfv for (i = 0; i < 4; i++) 1616181027Sjfv E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1617181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1618181027Sjfv E1000_WRITE_FLUSH(hw); 1619181027Sjfv 1620181027Sjfv E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1621181027Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1622181027Sjfv 1623181027Sjfv /* Flush receive errors generated by workaround */ 1624181027Sjfv E1000_READ_REG(hw, E1000_ROC); 1625181027Sjfv E1000_READ_REG(hw, E1000_RNBC); 1626181027Sjfv E1000_READ_REG(hw, E1000_MPC); 1627181027Sjfv} 1628185353Sjfv 1629194865Sjfv/** 1630194865Sjfv * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1631194865Sjfv * @hw: pointer to the HW structure 1632194865Sjfv * 1633194865Sjfv * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1634194865Sjfv * however the hardware default for these parts is 500us to 1ms which is less 1635194865Sjfv * than the 10ms recommended by the pci-e spec. To address this we need to 1636194865Sjfv * increase the value to either 10ms to 200ms for capability version 1 config, 1637194865Sjfv * or 16ms to 55ms for version 2. 1638194865Sjfv **/ 1639194865Sjfvstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1640194865Sjfv{ 1641194865Sjfv u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1642194865Sjfv s32 ret_val = E1000_SUCCESS; 1643194865Sjfv u16 pcie_devctl2; 1644194865Sjfv 1645194865Sjfv /* only take action if timeout value is defaulted to 0 */ 1646194865Sjfv if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1647194865Sjfv goto out; 1648194865Sjfv 1649194865Sjfv /* 1650194865Sjfv * if capababilities version is type 1 we can write the 1651194865Sjfv * timeout of 10ms to 200ms through the GCR register 1652194865Sjfv */ 1653194865Sjfv if (!(gcr & E1000_GCR_CAP_VER2)) { 1654194865Sjfv gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1655194865Sjfv goto out; 1656194865Sjfv } 1657194865Sjfv 1658194865Sjfv /* 1659194865Sjfv * for version 2 capabilities we need to write the config space 1660194865Sjfv * directly in order to set the completion timeout value for 1661194865Sjfv * 16ms to 55ms 1662194865Sjfv */ 1663194865Sjfv ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1664194865Sjfv &pcie_devctl2); 1665194865Sjfv if (ret_val) 1666194865Sjfv goto out; 1667194865Sjfv 1668194865Sjfv pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1669194865Sjfv 1670194865Sjfv ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1671194865Sjfv &pcie_devctl2); 1672194865Sjfvout: 1673194865Sjfv /* disable completion timeout resend */ 1674194865Sjfv gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1675194865Sjfv 1676194865Sjfv E1000_WRITE_REG(hw, E1000_GCR, gcr); 1677194865Sjfv return ret_val; 1678194865Sjfv} 1679194865Sjfv 1680