e1000_82542.c revision 185353
1177867Sjfv/****************************************************************************** 2169240Sjfv 3176667Sjfv Copyright (c) 2001-2008, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: head/sys/dev/e1000/e1000_82542.c 185353 2008-11-26 23:57:23Z jfv $*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82542 Gigabit Ethernet Controller 37169240Sjfv */ 38169240Sjfv 39169240Sjfv#include "e1000_api.h" 40169240Sjfv 41177867Sjfvstatic s32 e1000_init_phy_params_82542(struct e1000_hw *hw); 42177867Sjfvstatic s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); 43177867Sjfvstatic s32 e1000_init_mac_params_82542(struct e1000_hw *hw); 44177867Sjfvstatic s32 e1000_get_bus_info_82542(struct e1000_hw *hw); 45177867Sjfvstatic s32 e1000_reset_hw_82542(struct e1000_hw *hw); 46177867Sjfvstatic s32 e1000_init_hw_82542(struct e1000_hw *hw); 47177867Sjfvstatic s32 e1000_setup_link_82542(struct e1000_hw *hw); 48177867Sjfvstatic s32 e1000_led_on_82542(struct e1000_hw *hw); 49177867Sjfvstatic s32 e1000_led_off_82542(struct e1000_hw *hw); 50177867Sjfvstatic void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); 51177867Sjfvstatic void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); 52169240Sjfv 53169240Sjfv/** 54169240Sjfv * e1000_init_phy_params_82542 - Init PHY func ptrs. 55169589Sjfv * @hw: pointer to the HW structure 56169240Sjfv **/ 57177867Sjfvstatic s32 e1000_init_phy_params_82542(struct e1000_hw *hw) 58169240Sjfv{ 59169240Sjfv struct e1000_phy_info *phy = &hw->phy; 60169240Sjfv s32 ret_val = E1000_SUCCESS; 61169240Sjfv 62169240Sjfv DEBUGFUNC("e1000_init_phy_params_82542"); 63169240Sjfv 64169240Sjfv phy->type = e1000_phy_none; 65169240Sjfv 66169240Sjfv return ret_val; 67169240Sjfv} 68169240Sjfv 69169240Sjfv/** 70169240Sjfv * e1000_init_nvm_params_82542 - Init NVM func ptrs. 71169589Sjfv * @hw: pointer to the HW structure 72169240Sjfv **/ 73177867Sjfvstatic s32 e1000_init_nvm_params_82542(struct e1000_hw *hw) 74169240Sjfv{ 75169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 76169240Sjfv 77169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82542"); 78169240Sjfv 79169240Sjfv nvm->address_bits = 6; 80169240Sjfv nvm->delay_usec = 50; 81169240Sjfv nvm->opcode_bits = 3; 82169240Sjfv nvm->type = e1000_nvm_eeprom_microwire; 83169240Sjfv nvm->word_size = 64; 84169240Sjfv 85169240Sjfv /* Function Pointers */ 86177867Sjfv nvm->ops.read = e1000_read_nvm_microwire; 87177867Sjfv nvm->ops.release = e1000_stop_nvm; 88177867Sjfv nvm->ops.write = e1000_write_nvm_microwire; 89177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 90177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 91169240Sjfv 92169240Sjfv return E1000_SUCCESS; 93169240Sjfv} 94169240Sjfv 95169240Sjfv/** 96169240Sjfv * e1000_init_mac_params_82542 - Init MAC func ptrs. 97169589Sjfv * @hw: pointer to the HW structure 98169240Sjfv **/ 99177867Sjfvstatic s32 e1000_init_mac_params_82542(struct e1000_hw *hw) 100169240Sjfv{ 101169240Sjfv struct e1000_mac_info *mac = &hw->mac; 102169240Sjfv 103169240Sjfv DEBUGFUNC("e1000_init_mac_params_82542"); 104169240Sjfv 105169240Sjfv /* Set media type */ 106173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 107169240Sjfv 108169240Sjfv /* Set mta register count */ 109169240Sjfv mac->mta_reg_count = 128; 110169240Sjfv /* Set rar entry count */ 111169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 112169240Sjfv 113169240Sjfv /* Function pointers */ 114169240Sjfv 115169240Sjfv /* bus type/speed/width */ 116177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_82542; 117185353Sjfv /* function id */ 118185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 119169240Sjfv /* reset */ 120177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82542; 121169240Sjfv /* hw initialization */ 122177867Sjfv mac->ops.init_hw = e1000_init_hw_82542; 123169240Sjfv /* link setup */ 124177867Sjfv mac->ops.setup_link = e1000_setup_link_82542; 125169240Sjfv /* phy/fiber/serdes setup */ 126177867Sjfv mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic; 127169240Sjfv /* check for link */ 128177867Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 129169240Sjfv /* multicast address update */ 130177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 131169240Sjfv /* writing VFTA */ 132177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 133169240Sjfv /* clearing VFTA */ 134177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 135169240Sjfv /* setting MTA */ 136177867Sjfv mac->ops.mta_set = e1000_mta_set_generic; 137177867Sjfv /* set RAR */ 138177867Sjfv mac->ops.rar_set = e1000_rar_set_82542; 139169240Sjfv /* turn on/off LED */ 140177867Sjfv mac->ops.led_on = e1000_led_on_82542; 141177867Sjfv mac->ops.led_off = e1000_led_off_82542; 142169240Sjfv /* clear hardware counters */ 143177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; 144169240Sjfv /* link info */ 145177867Sjfv mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic; 146169240Sjfv 147185353Sjfv return E1000_SUCCESS; 148169240Sjfv} 149169240Sjfv 150169240Sjfv/** 151169240Sjfv * e1000_init_function_pointers_82542 - Init func ptrs. 152169589Sjfv * @hw: pointer to the HW structure 153169240Sjfv * 154185353Sjfv * Called to initialize all function pointers and parameters. 155169240Sjfv **/ 156173788Sjfvvoid e1000_init_function_pointers_82542(struct e1000_hw *hw) 157169240Sjfv{ 158169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82542"); 159169240Sjfv 160177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82542; 161177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82542; 162177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82542; 163169240Sjfv} 164169240Sjfv 165169240Sjfv/** 166169240Sjfv * e1000_get_bus_info_82542 - Obtain bus information for adapter 167169589Sjfv * @hw: pointer to the HW structure 168169240Sjfv * 169169240Sjfv * This will obtain information about the HW bus for which the 170185353Sjfv * adapter is attached and stores it in the hw structure. 171169240Sjfv **/ 172177867Sjfvstatic s32 e1000_get_bus_info_82542(struct e1000_hw *hw) 173169240Sjfv{ 174169240Sjfv DEBUGFUNC("e1000_get_bus_info_82542"); 175169240Sjfv 176169240Sjfv hw->bus.type = e1000_bus_type_pci; 177169240Sjfv hw->bus.speed = e1000_bus_speed_unknown; 178169240Sjfv hw->bus.width = e1000_bus_width_unknown; 179169240Sjfv 180169240Sjfv return E1000_SUCCESS; 181169240Sjfv} 182169240Sjfv 183169240Sjfv/** 184169240Sjfv * e1000_reset_hw_82542 - Reset hardware 185169589Sjfv * @hw: pointer to the HW structure 186169240Sjfv * 187185353Sjfv * This resets the hardware into a known state. 188169240Sjfv **/ 189177867Sjfvstatic s32 e1000_reset_hw_82542(struct e1000_hw *hw) 190169240Sjfv{ 191169240Sjfv struct e1000_bus_info *bus = &hw->bus; 192169240Sjfv s32 ret_val = E1000_SUCCESS; 193169240Sjfv u32 ctrl, icr; 194169240Sjfv 195169240Sjfv DEBUGFUNC("e1000_reset_hw_82542"); 196169240Sjfv 197169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 198169240Sjfv DEBUGOUT("Disabling MWI on 82542 rev 2\n"); 199169240Sjfv e1000_pci_clear_mwi(hw); 200169240Sjfv } 201169240Sjfv 202169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 203169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 204169240Sjfv 205169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 206169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 207169240Sjfv E1000_WRITE_FLUSH(hw); 208169240Sjfv 209173788Sjfv /* 210173788Sjfv * Delay to allow any outstanding PCI transactions to complete before 211169240Sjfv * resetting the device 212169240Sjfv */ 213169240Sjfv msec_delay(10); 214169240Sjfv 215169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 216169240Sjfv 217169240Sjfv DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); 218169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 219169240Sjfv 220177867Sjfv hw->nvm.ops.reload(hw); 221169240Sjfv msec_delay(2); 222169240Sjfv 223169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 224169240Sjfv icr = E1000_READ_REG(hw, E1000_ICR); 225169240Sjfv 226169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 227169240Sjfv if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 228169240Sjfv e1000_pci_set_mwi(hw); 229169240Sjfv } 230169240Sjfv 231169240Sjfv return ret_val; 232169240Sjfv} 233169240Sjfv 234169240Sjfv/** 235169240Sjfv * e1000_init_hw_82542 - Initialize hardware 236169589Sjfv * @hw: pointer to the HW structure 237169240Sjfv * 238185353Sjfv * This inits the hardware readying it for operation. 239169240Sjfv **/ 240177867Sjfvstatic s32 e1000_init_hw_82542(struct e1000_hw *hw) 241169240Sjfv{ 242169240Sjfv struct e1000_mac_info *mac = &hw->mac; 243185353Sjfv struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542; 244169240Sjfv s32 ret_val = E1000_SUCCESS; 245169240Sjfv u32 ctrl; 246169240Sjfv u16 i; 247169240Sjfv 248169240Sjfv DEBUGFUNC("e1000_init_hw_82542"); 249169240Sjfv 250169240Sjfv /* Disabling VLAN filtering */ 251169240Sjfv E1000_WRITE_REG(hw, E1000_VET, 0); 252177867Sjfv mac->ops.clear_vfta(hw); 253169240Sjfv 254169240Sjfv /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 255169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 256169240Sjfv DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 257169240Sjfv e1000_pci_clear_mwi(hw); 258169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 259169240Sjfv E1000_WRITE_FLUSH(hw); 260169240Sjfv msec_delay(5); 261169240Sjfv } 262169240Sjfv 263169240Sjfv /* Setup the receive address. */ 264169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 265169240Sjfv 266169240Sjfv /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 267169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 268169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 269169240Sjfv E1000_WRITE_FLUSH(hw); 270169240Sjfv msec_delay(1); 271169240Sjfv if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 272169240Sjfv e1000_pci_set_mwi(hw); 273169240Sjfv } 274169240Sjfv 275169240Sjfv /* Zero out the Multicast HASH table */ 276169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 277169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 278169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 279169240Sjfv 280173788Sjfv /* 281173788Sjfv * Set the PCI priority bit correctly in the CTRL register. This 282169240Sjfv * determines if the adapter gives priority to receives, or if it 283169240Sjfv * gives equal priority to transmits and receives. 284169240Sjfv */ 285169240Sjfv if (dev_spec->dma_fairness) { 286169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 287169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 288169240Sjfv } 289169240Sjfv 290169240Sjfv /* Setup link and flow control */ 291169240Sjfv ret_val = e1000_setup_link_82542(hw); 292169240Sjfv 293173788Sjfv /* 294173788Sjfv * Clear all of the statistics registers (clear on read). It is 295169240Sjfv * important that we do this after we have tried to establish link 296169240Sjfv * because the symbol error count will increment wildly if there 297169240Sjfv * is no link. 298169240Sjfv */ 299169240Sjfv e1000_clear_hw_cntrs_82542(hw); 300169240Sjfv 301169240Sjfv return ret_val; 302169240Sjfv} 303169240Sjfv 304169240Sjfv/** 305169240Sjfv * e1000_setup_link_82542 - Setup flow control and link settings 306169589Sjfv * @hw: pointer to the HW structure 307169240Sjfv * 308169240Sjfv * Determines which flow control settings to use, then configures flow 309169240Sjfv * control. Calls the appropriate media-specific link configuration 310169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 311169240Sjfv * should be established. Assumes the hardware has previously been reset 312185353Sjfv * and the transmitter and receiver are not enabled. 313169240Sjfv **/ 314177867Sjfvstatic s32 e1000_setup_link_82542(struct e1000_hw *hw) 315169240Sjfv{ 316169240Sjfv struct e1000_mac_info *mac = &hw->mac; 317169240Sjfv s32 ret_val = E1000_SUCCESS; 318169240Sjfv 319169240Sjfv DEBUGFUNC("e1000_setup_link_82542"); 320169240Sjfv 321169240Sjfv ret_val = e1000_set_default_fc_generic(hw); 322169240Sjfv if (ret_val) 323169240Sjfv goto out; 324169240Sjfv 325185353Sjfv hw->fc.requested_mode &= ~e1000_fc_tx_pause; 326169240Sjfv 327169240Sjfv if (mac->report_tx_early == 1) 328185353Sjfv hw->fc.requested_mode &= ~e1000_fc_rx_pause; 329169240Sjfv 330173788Sjfv /* 331185353Sjfv * Save off the requested flow control mode for use later. Depending 332185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 333169240Sjfv */ 334185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 335169240Sjfv 336185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 337185353Sjfv hw->fc.current_mode); 338169240Sjfv 339169240Sjfv /* Call the necessary subroutine to configure the link. */ 340177867Sjfv ret_val = mac->ops.setup_physical_interface(hw); 341169240Sjfv if (ret_val) 342169240Sjfv goto out; 343169240Sjfv 344173788Sjfv /* 345173788Sjfv * Initialize the flow control address, type, and PAUSE timer 346169240Sjfv * registers to their default values. This is done even if flow 347169240Sjfv * control is disabled, because it does not hurt anything to 348169240Sjfv * initialize these registers. 349169240Sjfv */ 350169240Sjfv DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 351169240Sjfv 352169240Sjfv E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 353169240Sjfv E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 354169240Sjfv E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 355169240Sjfv 356173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 357169240Sjfv 358169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 359169240Sjfv 360169240Sjfvout: 361169240Sjfv return ret_val; 362169240Sjfv} 363169240Sjfv 364169240Sjfv/** 365169240Sjfv * e1000_led_on_82542 - Turn on SW controllable LED 366169589Sjfv * @hw: pointer to the HW structure 367169240Sjfv * 368185353Sjfv * Turns the SW defined LED on. 369169240Sjfv **/ 370177867Sjfvstatic s32 e1000_led_on_82542(struct e1000_hw *hw) 371169240Sjfv{ 372169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 373169240Sjfv 374169240Sjfv DEBUGFUNC("e1000_led_on_82542"); 375169240Sjfv 376169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 377169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 378169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 379169240Sjfv 380169240Sjfv return E1000_SUCCESS; 381169240Sjfv} 382169240Sjfv 383169240Sjfv/** 384169240Sjfv * e1000_led_off_82542 - Turn off SW controllable LED 385169589Sjfv * @hw: pointer to the HW structure 386169240Sjfv * 387185353Sjfv * Turns the SW defined LED off. 388169240Sjfv **/ 389177867Sjfvstatic s32 e1000_led_off_82542(struct e1000_hw *hw) 390169240Sjfv{ 391169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 392169240Sjfv 393169240Sjfv DEBUGFUNC("e1000_led_off_82542"); 394169240Sjfv 395169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 396169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 397169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 398169240Sjfv 399169240Sjfv return E1000_SUCCESS; 400169240Sjfv} 401169240Sjfv 402169240Sjfv/** 403177867Sjfv * e1000_rar_set_82542 - Set receive address register 404177867Sjfv * @hw: pointer to the HW structure 405177867Sjfv * @addr: pointer to the receive address 406177867Sjfv * @index: receive address array register 407177867Sjfv * 408177867Sjfv * Sets the receive address array register at index to the address passed 409177867Sjfv * in by addr. 410177867Sjfv **/ 411177867Sjfvstatic void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) 412177867Sjfv{ 413177867Sjfv u32 rar_low, rar_high; 414177867Sjfv 415177867Sjfv DEBUGFUNC("e1000_rar_set_82542"); 416177867Sjfv 417177867Sjfv /* 418177867Sjfv * HW expects these in little endian so we reverse the byte order 419177867Sjfv * from network order (big endian) to little endian 420177867Sjfv */ 421177867Sjfv rar_low = ((u32) addr[0] | 422177867Sjfv ((u32) addr[1] << 8) | 423177867Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 424177867Sjfv 425177867Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 426177867Sjfv 427177867Sjfv /* If MAC address zero, no need to set the AV bit */ 428185353Sjfv if (rar_low || rar_high) 429185353Sjfv rar_high |= E1000_RAH_AV; 430177867Sjfv 431177867Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 432177867Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 433177867Sjfv} 434177867Sjfv 435177867Sjfv/** 436176667Sjfv * e1000_translate_register_82542 - Translate the proper register offset 437169589Sjfv * @reg: e1000 register to be read 438169240Sjfv * 439169240Sjfv * Registers in 82542 are located in different offsets than other adapters 440169240Sjfv * even though they function in the same manner. This function takes in 441169240Sjfv * the name of the register to read and returns the correct offset for 442169240Sjfv * 82542 silicon. 443169240Sjfv **/ 444173788Sjfvu32 e1000_translate_register_82542(u32 reg) 445169240Sjfv{ 446173788Sjfv /* 447173788Sjfv * Some of the 82542 registers are located at different 448169240Sjfv * offsets than they are in newer adapters. 449169240Sjfv * Despite the difference in location, the registers 450169240Sjfv * function in the same manner. 451169240Sjfv */ 452169240Sjfv switch (reg) { 453169240Sjfv case E1000_RA: 454169240Sjfv reg = 0x00040; 455169240Sjfv break; 456169240Sjfv case E1000_RDTR: 457169240Sjfv reg = 0x00108; 458169240Sjfv break; 459173788Sjfv case E1000_RDBAL(0): 460169240Sjfv reg = 0x00110; 461169240Sjfv break; 462173788Sjfv case E1000_RDBAH(0): 463169240Sjfv reg = 0x00114; 464169240Sjfv break; 465173788Sjfv case E1000_RDLEN(0): 466169240Sjfv reg = 0x00118; 467169240Sjfv break; 468173788Sjfv case E1000_RDH(0): 469169240Sjfv reg = 0x00120; 470169240Sjfv break; 471173788Sjfv case E1000_RDT(0): 472169240Sjfv reg = 0x00128; 473169240Sjfv break; 474173788Sjfv case E1000_RDBAL(1): 475169240Sjfv reg = 0x00138; 476169240Sjfv break; 477173788Sjfv case E1000_RDBAH(1): 478169240Sjfv reg = 0x0013C; 479169240Sjfv break; 480173788Sjfv case E1000_RDLEN(1): 481169240Sjfv reg = 0x00140; 482169240Sjfv break; 483173788Sjfv case E1000_RDH(1): 484169240Sjfv reg = 0x00148; 485169240Sjfv break; 486173788Sjfv case E1000_RDT(1): 487169240Sjfv reg = 0x00150; 488169240Sjfv break; 489169240Sjfv case E1000_FCRTH: 490169240Sjfv reg = 0x00160; 491169240Sjfv break; 492169240Sjfv case E1000_FCRTL: 493169240Sjfv reg = 0x00168; 494169240Sjfv break; 495169240Sjfv case E1000_MTA: 496169240Sjfv reg = 0x00200; 497169240Sjfv break; 498173788Sjfv case E1000_TDBAL(0): 499169240Sjfv reg = 0x00420; 500169240Sjfv break; 501173788Sjfv case E1000_TDBAH(0): 502169240Sjfv reg = 0x00424; 503169240Sjfv break; 504173788Sjfv case E1000_TDLEN(0): 505169240Sjfv reg = 0x00428; 506169240Sjfv break; 507173788Sjfv case E1000_TDH(0): 508169240Sjfv reg = 0x00430; 509169240Sjfv break; 510173788Sjfv case E1000_TDT(0): 511169240Sjfv reg = 0x00438; 512169240Sjfv break; 513169240Sjfv case E1000_TIDV: 514169240Sjfv reg = 0x00440; 515169240Sjfv break; 516169240Sjfv case E1000_VFTA: 517169240Sjfv reg = 0x00600; 518169240Sjfv break; 519169240Sjfv case E1000_TDFH: 520169240Sjfv reg = 0x08010; 521169240Sjfv break; 522169240Sjfv case E1000_TDFT: 523169240Sjfv reg = 0x08018; 524169240Sjfv break; 525169240Sjfv default: 526169240Sjfv break; 527169240Sjfv } 528169240Sjfv 529169240Sjfv return reg; 530169240Sjfv} 531169240Sjfv 532169240Sjfv/** 533169240Sjfv * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters 534169589Sjfv * @hw: pointer to the HW structure 535169240Sjfv * 536169240Sjfv * Clears the hardware counters by reading the counter registers. 537169240Sjfv **/ 538177867Sjfvstatic void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) 539169240Sjfv{ 540169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82542"); 541169240Sjfv 542169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 543169240Sjfv 544185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 545185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 546185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 547185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 548185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 549185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 550185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 551185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 552185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 553185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 554185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 555185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 556169240Sjfv} 557