1177867Sjfv/****************************************************************************** 2169240Sjfv 3286833Ssbruno Copyright (c) 2001-2015, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82542 Gigabit Ethernet Controller 37169240Sjfv */ 38169240Sjfv 39169240Sjfv#include "e1000_api.h" 40169240Sjfv 41177867Sjfvstatic s32 e1000_init_phy_params_82542(struct e1000_hw *hw); 42177867Sjfvstatic s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); 43177867Sjfvstatic s32 e1000_init_mac_params_82542(struct e1000_hw *hw); 44177867Sjfvstatic s32 e1000_get_bus_info_82542(struct e1000_hw *hw); 45177867Sjfvstatic s32 e1000_reset_hw_82542(struct e1000_hw *hw); 46177867Sjfvstatic s32 e1000_init_hw_82542(struct e1000_hw *hw); 47177867Sjfvstatic s32 e1000_setup_link_82542(struct e1000_hw *hw); 48177867Sjfvstatic s32 e1000_led_on_82542(struct e1000_hw *hw); 49177867Sjfvstatic s32 e1000_led_off_82542(struct e1000_hw *hw); 50267935Sjfvstatic int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); 51177867Sjfvstatic void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); 52195409Sjfvstatic s32 e1000_read_mac_addr_82542(struct e1000_hw *hw); 53169240Sjfv 54169240Sjfv/** 55169240Sjfv * e1000_init_phy_params_82542 - Init PHY func ptrs. 56169589Sjfv * @hw: pointer to the HW structure 57169240Sjfv **/ 58177867Sjfvstatic s32 e1000_init_phy_params_82542(struct e1000_hw *hw) 59169240Sjfv{ 60169240Sjfv struct e1000_phy_info *phy = &hw->phy; 61169240Sjfv s32 ret_val = E1000_SUCCESS; 62169240Sjfv 63169240Sjfv DEBUGFUNC("e1000_init_phy_params_82542"); 64169240Sjfv 65287112Ssbruno phy->type = e1000_phy_none; 66169240Sjfv 67169240Sjfv return ret_val; 68169240Sjfv} 69169240Sjfv 70169240Sjfv/** 71169240Sjfv * e1000_init_nvm_params_82542 - Init NVM func ptrs. 72169589Sjfv * @hw: pointer to the HW structure 73169240Sjfv **/ 74177867Sjfvstatic s32 e1000_init_nvm_params_82542(struct e1000_hw *hw) 75169240Sjfv{ 76169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 77169240Sjfv 78169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82542"); 79169240Sjfv 80287112Ssbruno nvm->address_bits = 6; 81287112Ssbruno nvm->delay_usec = 50; 82287112Ssbruno nvm->opcode_bits = 3; 83287112Ssbruno nvm->type = e1000_nvm_eeprom_microwire; 84287112Ssbruno nvm->word_size = 64; 85169240Sjfv 86169240Sjfv /* Function Pointers */ 87287112Ssbruno nvm->ops.read = e1000_read_nvm_microwire; 88287112Ssbruno nvm->ops.release = e1000_stop_nvm; 89287112Ssbruno nvm->ops.write = e1000_write_nvm_microwire; 90287112Ssbruno nvm->ops.update = e1000_update_nvm_checksum_generic; 91287112Ssbruno nvm->ops.validate = e1000_validate_nvm_checksum_generic; 92169240Sjfv 93169240Sjfv return E1000_SUCCESS; 94169240Sjfv} 95169240Sjfv 96169240Sjfv/** 97169240Sjfv * e1000_init_mac_params_82542 - Init MAC func ptrs. 98169589Sjfv * @hw: pointer to the HW structure 99169240Sjfv **/ 100177867Sjfvstatic s32 e1000_init_mac_params_82542(struct e1000_hw *hw) 101169240Sjfv{ 102169240Sjfv struct e1000_mac_info *mac = &hw->mac; 103169240Sjfv 104169240Sjfv DEBUGFUNC("e1000_init_mac_params_82542"); 105169240Sjfv 106169240Sjfv /* Set media type */ 107173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 108169240Sjfv 109169240Sjfv /* Set mta register count */ 110169240Sjfv mac->mta_reg_count = 128; 111169240Sjfv /* Set rar entry count */ 112169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 113169240Sjfv 114169240Sjfv /* Function pointers */ 115169240Sjfv 116169240Sjfv /* bus type/speed/width */ 117177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_82542; 118185353Sjfv /* function id */ 119185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 120169240Sjfv /* reset */ 121177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82542; 122169240Sjfv /* hw initialization */ 123177867Sjfv mac->ops.init_hw = e1000_init_hw_82542; 124169240Sjfv /* link setup */ 125177867Sjfv mac->ops.setup_link = e1000_setup_link_82542; 126169240Sjfv /* phy/fiber/serdes setup */ 127287112Ssbruno mac->ops.setup_physical_interface = 128287112Ssbruno e1000_setup_fiber_serdes_link_generic; 129169240Sjfv /* check for link */ 130177867Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 131169240Sjfv /* multicast address update */ 132177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 133169240Sjfv /* writing VFTA */ 134177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 135169240Sjfv /* clearing VFTA */ 136177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 137195409Sjfv /* read mac address */ 138195409Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82542; 139177867Sjfv /* set RAR */ 140177867Sjfv mac->ops.rar_set = e1000_rar_set_82542; 141169240Sjfv /* turn on/off LED */ 142177867Sjfv mac->ops.led_on = e1000_led_on_82542; 143177867Sjfv mac->ops.led_off = e1000_led_off_82542; 144169240Sjfv /* clear hardware counters */ 145177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; 146169240Sjfv /* link info */ 147287112Ssbruno mac->ops.get_link_up_info = 148287112Ssbruno e1000_get_speed_and_duplex_fiber_serdes_generic; 149169240Sjfv 150185353Sjfv return E1000_SUCCESS; 151169240Sjfv} 152169240Sjfv 153169240Sjfv/** 154169240Sjfv * e1000_init_function_pointers_82542 - Init func ptrs. 155169589Sjfv * @hw: pointer to the HW structure 156169240Sjfv * 157185353Sjfv * Called to initialize all function pointers and parameters. 158169240Sjfv **/ 159173788Sjfvvoid e1000_init_function_pointers_82542(struct e1000_hw *hw) 160169240Sjfv{ 161169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82542"); 162169240Sjfv 163177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82542; 164177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82542; 165177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82542; 166169240Sjfv} 167169240Sjfv 168169240Sjfv/** 169169240Sjfv * e1000_get_bus_info_82542 - Obtain bus information for adapter 170169589Sjfv * @hw: pointer to the HW structure 171169240Sjfv * 172169240Sjfv * This will obtain information about the HW bus for which the 173185353Sjfv * adapter is attached and stores it in the hw structure. 174169240Sjfv **/ 175177867Sjfvstatic s32 e1000_get_bus_info_82542(struct e1000_hw *hw) 176169240Sjfv{ 177169240Sjfv DEBUGFUNC("e1000_get_bus_info_82542"); 178169240Sjfv 179169240Sjfv hw->bus.type = e1000_bus_type_pci; 180169240Sjfv hw->bus.speed = e1000_bus_speed_unknown; 181169240Sjfv hw->bus.width = e1000_bus_width_unknown; 182169240Sjfv 183169240Sjfv return E1000_SUCCESS; 184169240Sjfv} 185169240Sjfv 186169240Sjfv/** 187169240Sjfv * e1000_reset_hw_82542 - Reset hardware 188169589Sjfv * @hw: pointer to the HW structure 189169240Sjfv * 190185353Sjfv * This resets the hardware into a known state. 191169240Sjfv **/ 192177867Sjfvstatic s32 e1000_reset_hw_82542(struct e1000_hw *hw) 193169240Sjfv{ 194169240Sjfv struct e1000_bus_info *bus = &hw->bus; 195169240Sjfv s32 ret_val = E1000_SUCCESS; 196218581Sjfv u32 ctrl; 197169240Sjfv 198169240Sjfv DEBUGFUNC("e1000_reset_hw_82542"); 199169240Sjfv 200169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 201169240Sjfv DEBUGOUT("Disabling MWI on 82542 rev 2\n"); 202169240Sjfv e1000_pci_clear_mwi(hw); 203169240Sjfv } 204169240Sjfv 205169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 206169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 207169240Sjfv 208169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 209169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 210169240Sjfv E1000_WRITE_FLUSH(hw); 211169240Sjfv 212173788Sjfv /* 213173788Sjfv * Delay to allow any outstanding PCI transactions to complete before 214169240Sjfv * resetting the device 215169240Sjfv */ 216169240Sjfv msec_delay(10); 217169240Sjfv 218169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 219169240Sjfv 220169240Sjfv DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); 221169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 222169240Sjfv 223177867Sjfv hw->nvm.ops.reload(hw); 224169240Sjfv msec_delay(2); 225169240Sjfv 226169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 227218581Sjfv E1000_READ_REG(hw, E1000_ICR); 228169240Sjfv 229169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 230169240Sjfv if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 231169240Sjfv e1000_pci_set_mwi(hw); 232169240Sjfv } 233169240Sjfv 234169240Sjfv return ret_val; 235169240Sjfv} 236169240Sjfv 237169240Sjfv/** 238169240Sjfv * e1000_init_hw_82542 - Initialize hardware 239169589Sjfv * @hw: pointer to the HW structure 240169240Sjfv * 241185353Sjfv * This inits the hardware readying it for operation. 242169240Sjfv **/ 243177867Sjfvstatic s32 e1000_init_hw_82542(struct e1000_hw *hw) 244169240Sjfv{ 245169240Sjfv struct e1000_mac_info *mac = &hw->mac; 246185353Sjfv struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542; 247169240Sjfv s32 ret_val = E1000_SUCCESS; 248169240Sjfv u32 ctrl; 249169240Sjfv u16 i; 250169240Sjfv 251169240Sjfv DEBUGFUNC("e1000_init_hw_82542"); 252169240Sjfv 253169240Sjfv /* Disabling VLAN filtering */ 254169240Sjfv E1000_WRITE_REG(hw, E1000_VET, 0); 255177867Sjfv mac->ops.clear_vfta(hw); 256169240Sjfv 257169240Sjfv /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 258169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 259169240Sjfv DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 260169240Sjfv e1000_pci_clear_mwi(hw); 261169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 262169240Sjfv E1000_WRITE_FLUSH(hw); 263169240Sjfv msec_delay(5); 264169240Sjfv } 265169240Sjfv 266169240Sjfv /* Setup the receive address. */ 267169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 268169240Sjfv 269169240Sjfv /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 270169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 271169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 272169240Sjfv E1000_WRITE_FLUSH(hw); 273169240Sjfv msec_delay(1); 274169240Sjfv if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 275169240Sjfv e1000_pci_set_mwi(hw); 276169240Sjfv } 277169240Sjfv 278169240Sjfv /* Zero out the Multicast HASH table */ 279169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 280169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 281169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 282169240Sjfv 283173788Sjfv /* 284173788Sjfv * Set the PCI priority bit correctly in the CTRL register. This 285169240Sjfv * determines if the adapter gives priority to receives, or if it 286169240Sjfv * gives equal priority to transmits and receives. 287169240Sjfv */ 288169240Sjfv if (dev_spec->dma_fairness) { 289169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 290169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 291169240Sjfv } 292169240Sjfv 293169240Sjfv /* Setup link and flow control */ 294169240Sjfv ret_val = e1000_setup_link_82542(hw); 295169240Sjfv 296173788Sjfv /* 297173788Sjfv * Clear all of the statistics registers (clear on read). It is 298169240Sjfv * important that we do this after we have tried to establish link 299169240Sjfv * because the symbol error count will increment wildly if there 300169240Sjfv * is no link. 301169240Sjfv */ 302169240Sjfv e1000_clear_hw_cntrs_82542(hw); 303169240Sjfv 304169240Sjfv return ret_val; 305169240Sjfv} 306169240Sjfv 307169240Sjfv/** 308169240Sjfv * e1000_setup_link_82542 - Setup flow control and link settings 309169589Sjfv * @hw: pointer to the HW structure 310169240Sjfv * 311169240Sjfv * Determines which flow control settings to use, then configures flow 312169240Sjfv * control. Calls the appropriate media-specific link configuration 313169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 314169240Sjfv * should be established. Assumes the hardware has previously been reset 315185353Sjfv * and the transmitter and receiver are not enabled. 316169240Sjfv **/ 317177867Sjfvstatic s32 e1000_setup_link_82542(struct e1000_hw *hw) 318169240Sjfv{ 319169240Sjfv struct e1000_mac_info *mac = &hw->mac; 320295323Serj s32 ret_val; 321169240Sjfv 322169240Sjfv DEBUGFUNC("e1000_setup_link_82542"); 323169240Sjfv 324169240Sjfv ret_val = e1000_set_default_fc_generic(hw); 325169240Sjfv if (ret_val) 326169240Sjfv goto out; 327169240Sjfv 328185353Sjfv hw->fc.requested_mode &= ~e1000_fc_tx_pause; 329169240Sjfv 330287112Ssbruno if (mac->report_tx_early) 331185353Sjfv hw->fc.requested_mode &= ~e1000_fc_rx_pause; 332169240Sjfv 333173788Sjfv /* 334185353Sjfv * Save off the requested flow control mode for use later. Depending 335185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 336169240Sjfv */ 337185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 338169240Sjfv 339185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 340287112Ssbruno hw->fc.current_mode); 341169240Sjfv 342169240Sjfv /* Call the necessary subroutine to configure the link. */ 343177867Sjfv ret_val = mac->ops.setup_physical_interface(hw); 344169240Sjfv if (ret_val) 345169240Sjfv goto out; 346169240Sjfv 347173788Sjfv /* 348173788Sjfv * Initialize the flow control address, type, and PAUSE timer 349169240Sjfv * registers to their default values. This is done even if flow 350169240Sjfv * control is disabled, because it does not hurt anything to 351169240Sjfv * initialize these registers. 352169240Sjfv */ 353169240Sjfv DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 354169240Sjfv 355169240Sjfv E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 356169240Sjfv E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 357169240Sjfv E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 358169240Sjfv 359173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 360169240Sjfv 361169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 362169240Sjfv 363169240Sjfvout: 364169240Sjfv return ret_val; 365169240Sjfv} 366169240Sjfv 367169240Sjfv/** 368169240Sjfv * e1000_led_on_82542 - Turn on SW controllable LED 369169589Sjfv * @hw: pointer to the HW structure 370169240Sjfv * 371185353Sjfv * Turns the SW defined LED on. 372169240Sjfv **/ 373177867Sjfvstatic s32 e1000_led_on_82542(struct e1000_hw *hw) 374169240Sjfv{ 375169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 376169240Sjfv 377169240Sjfv DEBUGFUNC("e1000_led_on_82542"); 378169240Sjfv 379169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 380169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 381169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 382169240Sjfv 383169240Sjfv return E1000_SUCCESS; 384169240Sjfv} 385169240Sjfv 386169240Sjfv/** 387169240Sjfv * e1000_led_off_82542 - Turn off SW controllable LED 388169589Sjfv * @hw: pointer to the HW structure 389169240Sjfv * 390185353Sjfv * Turns the SW defined LED off. 391169240Sjfv **/ 392177867Sjfvstatic s32 e1000_led_off_82542(struct e1000_hw *hw) 393169240Sjfv{ 394169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 395169240Sjfv 396169240Sjfv DEBUGFUNC("e1000_led_off_82542"); 397169240Sjfv 398169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 399169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 400169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 401169240Sjfv 402169240Sjfv return E1000_SUCCESS; 403169240Sjfv} 404169240Sjfv 405169240Sjfv/** 406177867Sjfv * e1000_rar_set_82542 - Set receive address register 407177867Sjfv * @hw: pointer to the HW structure 408177867Sjfv * @addr: pointer to the receive address 409177867Sjfv * @index: receive address array register 410177867Sjfv * 411177867Sjfv * Sets the receive address array register at index to the address passed 412177867Sjfv * in by addr. 413177867Sjfv **/ 414267935Sjfvstatic int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) 415177867Sjfv{ 416177867Sjfv u32 rar_low, rar_high; 417177867Sjfv 418177867Sjfv DEBUGFUNC("e1000_rar_set_82542"); 419177867Sjfv 420177867Sjfv /* 421177867Sjfv * HW expects these in little endian so we reverse the byte order 422177867Sjfv * from network order (big endian) to little endian 423177867Sjfv */ 424287112Ssbruno rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 425287112Ssbruno ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 426177867Sjfv 427177867Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 428177867Sjfv 429177867Sjfv /* If MAC address zero, no need to set the AV bit */ 430185353Sjfv if (rar_low || rar_high) 431185353Sjfv rar_high |= E1000_RAH_AV; 432177867Sjfv 433177867Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 434177867Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 435287112Ssbruno 436267935Sjfv return E1000_SUCCESS; 437177867Sjfv} 438177867Sjfv 439177867Sjfv/** 440176667Sjfv * e1000_translate_register_82542 - Translate the proper register offset 441169589Sjfv * @reg: e1000 register to be read 442169240Sjfv * 443169240Sjfv * Registers in 82542 are located in different offsets than other adapters 444169240Sjfv * even though they function in the same manner. This function takes in 445169240Sjfv * the name of the register to read and returns the correct offset for 446169240Sjfv * 82542 silicon. 447169240Sjfv **/ 448173788Sjfvu32 e1000_translate_register_82542(u32 reg) 449169240Sjfv{ 450173788Sjfv /* 451173788Sjfv * Some of the 82542 registers are located at different 452169240Sjfv * offsets than they are in newer adapters. 453169240Sjfv * Despite the difference in location, the registers 454169240Sjfv * function in the same manner. 455169240Sjfv */ 456169240Sjfv switch (reg) { 457169240Sjfv case E1000_RA: 458169240Sjfv reg = 0x00040; 459169240Sjfv break; 460169240Sjfv case E1000_RDTR: 461169240Sjfv reg = 0x00108; 462169240Sjfv break; 463173788Sjfv case E1000_RDBAL(0): 464169240Sjfv reg = 0x00110; 465169240Sjfv break; 466173788Sjfv case E1000_RDBAH(0): 467169240Sjfv reg = 0x00114; 468169240Sjfv break; 469173788Sjfv case E1000_RDLEN(0): 470169240Sjfv reg = 0x00118; 471169240Sjfv break; 472173788Sjfv case E1000_RDH(0): 473169240Sjfv reg = 0x00120; 474169240Sjfv break; 475173788Sjfv case E1000_RDT(0): 476169240Sjfv reg = 0x00128; 477169240Sjfv break; 478173788Sjfv case E1000_RDBAL(1): 479169240Sjfv reg = 0x00138; 480169240Sjfv break; 481173788Sjfv case E1000_RDBAH(1): 482169240Sjfv reg = 0x0013C; 483169240Sjfv break; 484173788Sjfv case E1000_RDLEN(1): 485169240Sjfv reg = 0x00140; 486169240Sjfv break; 487173788Sjfv case E1000_RDH(1): 488169240Sjfv reg = 0x00148; 489169240Sjfv break; 490173788Sjfv case E1000_RDT(1): 491169240Sjfv reg = 0x00150; 492169240Sjfv break; 493169240Sjfv case E1000_FCRTH: 494169240Sjfv reg = 0x00160; 495169240Sjfv break; 496169240Sjfv case E1000_FCRTL: 497169240Sjfv reg = 0x00168; 498169240Sjfv break; 499169240Sjfv case E1000_MTA: 500169240Sjfv reg = 0x00200; 501169240Sjfv break; 502173788Sjfv case E1000_TDBAL(0): 503169240Sjfv reg = 0x00420; 504169240Sjfv break; 505173788Sjfv case E1000_TDBAH(0): 506169240Sjfv reg = 0x00424; 507169240Sjfv break; 508173788Sjfv case E1000_TDLEN(0): 509169240Sjfv reg = 0x00428; 510169240Sjfv break; 511173788Sjfv case E1000_TDH(0): 512169240Sjfv reg = 0x00430; 513169240Sjfv break; 514173788Sjfv case E1000_TDT(0): 515169240Sjfv reg = 0x00438; 516169240Sjfv break; 517169240Sjfv case E1000_TIDV: 518169240Sjfv reg = 0x00440; 519169240Sjfv break; 520169240Sjfv case E1000_VFTA: 521169240Sjfv reg = 0x00600; 522169240Sjfv break; 523169240Sjfv case E1000_TDFH: 524169240Sjfv reg = 0x08010; 525169240Sjfv break; 526169240Sjfv case E1000_TDFT: 527169240Sjfv reg = 0x08018; 528169240Sjfv break; 529169240Sjfv default: 530169240Sjfv break; 531169240Sjfv } 532169240Sjfv 533169240Sjfv return reg; 534169240Sjfv} 535169240Sjfv 536169240Sjfv/** 537169240Sjfv * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters 538169589Sjfv * @hw: pointer to the HW structure 539169240Sjfv * 540169240Sjfv * Clears the hardware counters by reading the counter registers. 541169240Sjfv **/ 542177867Sjfvstatic void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) 543169240Sjfv{ 544169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82542"); 545169240Sjfv 546169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 547169240Sjfv 548185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 549185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 550185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 551185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 552185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 553185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 554185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 555185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 556185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 557185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 558185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 559185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 560169240Sjfv} 561195409Sjfv 562195409Sjfv/** 563195409Sjfv * e1000_read_mac_addr_82542 - Read device MAC address 564195409Sjfv * @hw: pointer to the HW structure 565195409Sjfv * 566195409Sjfv * Reads the device MAC address from the EEPROM and stores the value. 567195409Sjfv **/ 568295323Serjs32 e1000_read_mac_addr_82542(struct e1000_hw *hw) 569195409Sjfv{ 570195409Sjfv s32 ret_val = E1000_SUCCESS; 571195409Sjfv u16 offset, nvm_data, i; 572195409Sjfv 573195409Sjfv DEBUGFUNC("e1000_read_mac_addr"); 574195409Sjfv 575195409Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 576195409Sjfv offset = i >> 1; 577195409Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 578195409Sjfv if (ret_val) { 579195409Sjfv DEBUGOUT("NVM Read Error\n"); 580195409Sjfv goto out; 581195409Sjfv } 582195409Sjfv hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 583195409Sjfv hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 584195409Sjfv } 585195409Sjfv 586195409Sjfv for (i = 0; i < ETH_ADDR_LEN; i++) 587195409Sjfv hw->mac.addr[i] = hw->mac.perm_addr[i]; 588195409Sjfv 589195409Sjfvout: 590195409Sjfv return ret_val; 591195409Sjfv} 592