e1000_80003es2lan.c revision 181027
195771Sjeff/****************************************************************************** 2103623Sjeff 395771Sjeff Copyright (c) 2001-2008, Intel Corporation 495771Sjeff All rights reserved. 595771Sjeff 695771Sjeff Redistribution and use in source and binary forms, with or without 795771Sjeff modification, are permitted provided that the following conditions are met: 895771Sjeff 995771Sjeff 1. Redistributions of source code must retain the above copyright notice, 1095771Sjeff this list of conditions and the following disclaimer. 1195771Sjeff 1295771Sjeff 2. Redistributions in binary form must reproduce the above copyright 1395771Sjeff notice, this list of conditions and the following disclaimer in the 1495771Sjeff documentation and/or other materials provided with the distribution. 1595771Sjeff 1695771Sjeff 3. Neither the name of the Intel Corporation nor the names of its 1795771Sjeff contributors may be used to endorse or promote products derived from 1895771Sjeff this software without specific prior written permission. 1995771Sjeff 2095771Sjeff THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2195771Sjeff AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2295771Sjeff IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2395771Sjeff ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2495771Sjeff LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2595771Sjeff CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2695771Sjeff SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2795771Sjeff INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2895771Sjeff CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2995771Sjeff ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3095771Sjeff POSSIBILITY OF SUCH DAMAGE. 3195771Sjeff 32116226Sobrien******************************************************************************/ 33116226Sobrien/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 181027 2008-07-30 21:56:53Z jfv $*/ 3495771Sjeff 3595771Sjeff/* e1000_80003es2lan 3695771Sjeff */ 3795771Sjeff 3895771Sjeff#include "e1000_api.h" 3995771Sjeff 4095771Sjeffstatic s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 4195771Sjeffstatic s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 4295931Sjeffstatic s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 4395771Sjeffstatic s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 44103531Sjeffstatic void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 45103531Sjeffstatic s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 46103531Sjeffstatic void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 4795771Sjeffstatic s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 4895771Sjeff u32 offset, 4995771Sjeff u16 *data); 5095771Sjeffstatic s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 5195771Sjeff u32 offset, 5295771Sjeff u16 data); 5395771Sjeffstatic s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 54132987Sgreen u16 words, u16 *data); 55132987Sgreenstatic s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 5695771Sjeffstatic s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 5795771Sjeffstatic s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 5895771Sjeffstatic s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 5995771Sjeff u16 *duplex); 60132987Sgreenstatic s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 61132987Sgreenstatic s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 6295771Sjeffstatic s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 6395771Sjeffstatic void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 6495771Sjeffstatic s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 6595771Sjeffstatic s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 6695771Sjeffstatic s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 6795771Sjeffstatic s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 6895771Sjeffstatic void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 6995771Sjeffstatic void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 70120526Sphkstatic s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 71120526Sphkstatic void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 72132987Sgreen 7395771Sjeff/* 7495771Sjeff * A table for the GG82563 cable length where the range is defined 7595771Sjeff * with a lower bound at "index" and the upper bound at 7695771Sjeff * "index + 5". 7795771Sjeff */ 7895771Sjeffstatic const u16 e1000_gg82563_cable_length_table[] = 7995771Sjeff { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 8095771Sjeff#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 8195771Sjeff (sizeof(e1000_gg82563_cable_length_table) / \ 8295771Sjeff sizeof(e1000_gg82563_cable_length_table[0])) 8395771Sjeff 8495771Sjeff/** 8595771Sjeff * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 8695771Sjeff * @hw: pointer to the HW structure 8795771Sjeff * 8895771Sjeff * This is a function pointer entry point called by the api module. 8995771Sjeff **/ 9095771Sjeffstatic s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 9195771Sjeff{ 9295771Sjeff struct e1000_phy_info *phy = &hw->phy; 9395771Sjeff s32 ret_val = E1000_SUCCESS; 9495771Sjeff 9595771Sjeff DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 9695771Sjeff 9795771Sjeff if (hw->phy.media_type != e1000_media_type_copper) { 9895771Sjeff phy->type = e1000_phy_none; 99132987Sgreen goto out; 100132987Sgreen } else { 10195771Sjeff phy->ops.power_up = e1000_power_up_phy_copper; 10295771Sjeff phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 103132987Sgreen } 10495771Sjeff 10595771Sjeff phy->addr = 1; 10695771Sjeff phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 10795771Sjeff phy->reset_delay_us = 100; 10895771Sjeff phy->type = e1000_phy_gg82563; 10995771Sjeff 11095771Sjeff phy->ops.acquire = e1000_acquire_phy_80003es2lan; 11195771Sjeff phy->ops.check_polarity = e1000_check_polarity_m88; 11295771Sjeff phy->ops.check_reset_block = e1000_check_reset_block_generic; 11395771Sjeff phy->ops.commit = e1000_phy_sw_reset_generic; 11495771Sjeff phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 115132987Sgreen phy->ops.get_info = e1000_get_phy_info_m88; 11695771Sjeff phy->ops.release = e1000_release_phy_80003es2lan; 11795899Sjeff phy->ops.reset = e1000_phy_hw_reset_generic; 118132987Sgreen phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 119132987Sgreen 12095931Sjeff phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 12195931Sjeff phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 12295931Sjeff phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 12395931Sjeff phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 12495931Sjeff 12595931Sjeff /* This can only be done after all function pointers are setup. */ 12695931Sjeff ret_val = e1000_get_phy_id(hw); 12795931Sjeff 12895931Sjeff /* Verify phy id */ 12995931Sjeff if (phy->id != GG82563_E_PHY_ID) { 13095931Sjeff ret_val = -E1000_ERR_PHY; 13195931Sjeff goto out; 132120526Sphk } 133120526Sphk 13495931Sjeffout: 13595931Sjeff return ret_val; 13695931Sjeff} 137132987Sgreen 13895931Sjeff/** 13995931Sjeff * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 14095931Sjeff * @hw: pointer to the HW structure 14195931Sjeff * 14295931Sjeff * This is a function pointer entry point called by the api module. 14395931Sjeff **/ 14495931Sjeffstatic s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 14595931Sjeff{ 14695931Sjeff struct e1000_nvm_info *nvm = &hw->nvm; 14795931Sjeff u32 eecd = E1000_READ_REG(hw, E1000_EECD); 14895931Sjeff u16 size; 14995931Sjeff 15095931Sjeff DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 15195931Sjeff 15295931Sjeff nvm->opcode_bits = 8; 15395931Sjeff nvm->delay_usec = 1; 15495931Sjeff switch (nvm->override) { 15595931Sjeff case e1000_nvm_override_spi_large: 15695931Sjeff nvm->page_size = 32; 15795931Sjeff nvm->address_bits = 16; 15895931Sjeff break; 15995931Sjeff case e1000_nvm_override_spi_small: 16095931Sjeff nvm->page_size = 8; 16195931Sjeff nvm->address_bits = 8; 16295931Sjeff break; 16395931Sjeff default: 16495931Sjeff nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 165132987Sgreen nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 166132987Sgreen break; 16795931Sjeff } 16895931Sjeff 16995931Sjeff nvm->type = e1000_nvm_eeprom_spi; 17095931Sjeff 17195931Sjeff size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 17295931Sjeff E1000_EECD_SIZE_EX_SHIFT); 17395931Sjeff 17495931Sjeff /* 175132987Sgreen * Added to a constant, "size" becomes the left-shift value 17695931Sjeff * for setting word_size. 17795931Sjeff */ 17895931Sjeff size += NVM_WORD_SIZE_BASE_SHIFT; 179132987Sgreen 180132987Sgreen /* EEPROM access above 16k is unsupported */ 18195931Sjeff if (size > 14) 18295931Sjeff size = 14; 18395931Sjeff nvm->word_size = 1 << size; 18495931Sjeff 18595931Sjeff /* Function Pointers */ 18695931Sjeff nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 18795931Sjeff nvm->ops.read = e1000_read_nvm_eerd; 188132987Sgreen nvm->ops.release = e1000_release_nvm_80003es2lan; 18995931Sjeff nvm->ops.update = e1000_update_nvm_checksum_generic; 19095931Sjeff nvm->ops.valid_led_default = e1000_valid_led_default_generic; 19195899Sjeff nvm->ops.validate = e1000_validate_nvm_checksum_generic; 19295899Sjeff nvm->ops.write = e1000_write_nvm_80003es2lan; 19395899Sjeff 19495899Sjeff return E1000_SUCCESS; 195129906Sbmilekic} 19695899Sjeff 19795899Sjeff/** 198129906Sbmilekic * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 19995899Sjeff * @hw: pointer to the HW structure 200129906Sbmilekic * 201103531Sjeff * This is a function pointer entry point called by the api module. 202129906Sbmilekic **/ 203129906Sbmilekicstatic s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 20495899Sjeff{ 205129906Sbmilekic struct e1000_mac_info *mac = &hw->mac; 20695899Sjeff s32 ret_val = E1000_SUCCESS; 20795899Sjeff 20895899Sjeff DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 20995899Sjeff 21095899Sjeff /* Set media type */ 21195899Sjeff switch (hw->device_id) { 21295899Sjeff case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 21395899Sjeff hw->phy.media_type = e1000_media_type_internal_serdes; 21495899Sjeff break; 21595899Sjeff default: 21695899Sjeff hw->phy.media_type = e1000_media_type_copper; 21795899Sjeff break; 21895899Sjeff } 21995899Sjeff 220129906Sbmilekic /* Set mta register count */ 22195899Sjeff mac->mta_reg_count = 128; 22295899Sjeff /* Set rar entry count */ 223129906Sbmilekic mac->rar_entry_count = E1000_RAR_ENTRIES; 22495899Sjeff /* Set if part includes ASF firmware */ 22595899Sjeff mac->asf_firmware_present = TRUE; 22695899Sjeff /* Set if manageability features are enabled. */ 22795899Sjeff mac->arc_subsystem_valid = 22895899Sjeff (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 22995899Sjeff ? TRUE : FALSE; 23095899Sjeff 23195899Sjeff /* Function pointers */ 232129906Sbmilekic 23395899Sjeff /* bus type/speed/width */ 234129906Sbmilekic mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 23595899Sjeff /* reset */ 23695899Sjeff mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 23795899Sjeff /* hw initialization */ 23895899Sjeff mac->ops.init_hw = e1000_init_hw_80003es2lan; 23995899Sjeff /* link setup */ 24095899Sjeff mac->ops.setup_link = e1000_setup_link_generic; 24195899Sjeff /* physical interface link setup */ 24295899Sjeff mac->ops.setup_physical_interface = 24395899Sjeff (hw->phy.media_type == e1000_media_type_copper) 24495899Sjeff ? e1000_setup_copper_link_80003es2lan 24595899Sjeff : e1000_setup_fiber_serdes_link_generic; 24695899Sjeff /* check for link */ 24795899Sjeff switch (hw->phy.media_type) { 248129906Sbmilekic case e1000_media_type_copper: 24995899Sjeff mac->ops.check_for_link = e1000_check_for_copper_link_generic; 25095899Sjeff break; 251129906Sbmilekic case e1000_media_type_fiber: 25295899Sjeff mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 25395899Sjeff break; 25495899Sjeff case e1000_media_type_internal_serdes: 25595899Sjeff mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 25695899Sjeff break; 25795899Sjeff default: 25895899Sjeff ret_val = -E1000_ERR_CONFIG; 25995899Sjeff goto out; 260129906Sbmilekic break; 26195899Sjeff } 262129906Sbmilekic /* check management mode */ 26397453Speter mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 264129906Sbmilekic /* multicast address update */ 26595899Sjeff mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 266129906Sbmilekic /* writing VFTA */ 26795899Sjeff mac->ops.write_vfta = e1000_write_vfta_generic; 26895899Sjeff /* clearing VFTA */ 26995899Sjeff mac->ops.clear_vfta = e1000_clear_vfta_generic; 270129906Sbmilekic /* setting MTA */ 27195899Sjeff mac->ops.mta_set = e1000_mta_set_generic; 27295899Sjeff /* read mac address */ 273129906Sbmilekic mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 27495899Sjeff /* blink LED */ 275129906Sbmilekic mac->ops.blink_led = e1000_blink_led_generic; 27695899Sjeff /* setup LED */ 27795899Sjeff mac->ops.setup_led = e1000_setup_led_generic; 27895899Sjeff /* cleanup LED */ 27995899Sjeff mac->ops.cleanup_led = e1000_cleanup_led_generic; 28095899Sjeff /* turn on/off LED */ 28195899Sjeff mac->ops.led_on = e1000_led_on_generic; 28295899Sjeff mac->ops.led_off = e1000_led_off_generic; 28395899Sjeff /* remove device */ 28495899Sjeff mac->ops.remove_device = e1000_remove_device_generic; 285129906Sbmilekic /* clear hardware counters */ 28695899Sjeff mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 287 /* link info */ 288 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 289 290out: 291 return ret_val; 292} 293 294/** 295 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 296 * @hw: pointer to the HW structure 297 * 298 * The only function explicitly called by the api module to initialize 299 * all function pointers and parameters. 300 **/ 301void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 302{ 303 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 304 305 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 306 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 307 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 308} 309 310/** 311 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 312 * @hw: pointer to the HW structure 313 * 314 * A wrapper to acquire access rights to the correct PHY. This is a 315 * function pointer entry point called by the api module. 316 **/ 317static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 318{ 319 u16 mask; 320 321 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 322 323 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 324 mask |= E1000_SWFW_CSR_SM; 325 326 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 327} 328 329/** 330 * e1000_release_phy_80003es2lan - Release rights to access PHY 331 * @hw: pointer to the HW structure 332 * 333 * A wrapper to release access rights to the correct PHY. This is a 334 * function pointer entry point called by the api module. 335 **/ 336static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 337{ 338 u16 mask; 339 340 DEBUGFUNC("e1000_release_phy_80003es2lan"); 341 342 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 343 mask |= E1000_SWFW_CSR_SM; 344 345 e1000_release_swfw_sync_80003es2lan(hw, mask); 346} 347 348/** 349 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 350 * @hw: pointer to the HW structure 351 * 352 * Acquire the semaphore to access the EEPROM. This is a function 353 * pointer entry point called by the api module. 354 **/ 355static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 356{ 357 s32 ret_val; 358 359 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 360 361 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 362 if (ret_val) 363 goto out; 364 365 ret_val = e1000_acquire_nvm_generic(hw); 366 367 if (ret_val) 368 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 369 370out: 371 return ret_val; 372} 373 374/** 375 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 376 * @hw: pointer to the HW structure 377 * 378 * Release the semaphore used to access the EEPROM. This is a 379 * function pointer entry point called by the api module. 380 **/ 381static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 382{ 383 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 384 385 e1000_release_nvm_generic(hw); 386 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 387} 388 389/** 390 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 391 * @hw: pointer to the HW structure 392 * @mask: specifies which semaphore to acquire 393 * 394 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 395 * will also specify which port we're acquiring the lock for. 396 **/ 397static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 398{ 399 u32 swfw_sync; 400 u32 swmask = mask; 401 u32 fwmask = mask << 16; 402 s32 ret_val = E1000_SUCCESS; 403 s32 i = 0, timeout = 200; 404 405 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 406 407 while (i < timeout) { 408 if (e1000_get_hw_semaphore_generic(hw)) { 409 ret_val = -E1000_ERR_SWFW_SYNC; 410 goto out; 411 } 412 413 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 414 if (!(swfw_sync & (fwmask | swmask))) 415 break; 416 417 /* 418 * Firmware currently using resource (fwmask) 419 * or other software thread using resource (swmask) 420 */ 421 e1000_put_hw_semaphore_generic(hw); 422 msec_delay_irq(5); 423 i++; 424 } 425 426 if (i == timeout) { 427 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 428 ret_val = -E1000_ERR_SWFW_SYNC; 429 goto out; 430 } 431 432 swfw_sync |= swmask; 433 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 434 435 e1000_put_hw_semaphore_generic(hw); 436 437out: 438 return ret_val; 439} 440 441/** 442 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 443 * @hw: pointer to the HW structure 444 * @mask: specifies which semaphore to acquire 445 * 446 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 447 * will also specify which port we're releasing the lock for. 448 **/ 449static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 450{ 451 u32 swfw_sync; 452 453 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 454 455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 456 /* Empty */ 457 458 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 459 swfw_sync &= ~mask; 460 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 461 462 e1000_put_hw_semaphore_generic(hw); 463} 464 465/** 466 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 467 * @hw: pointer to the HW structure 468 * @offset: offset of the register to read 469 * @data: pointer to the data returned from the operation 470 * 471 * Read the GG82563 PHY register. This is a function pointer entry 472 * point called by the api module. 473 **/ 474static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 475 u32 offset, u16 *data) 476{ 477 s32 ret_val; 478 u32 page_select; 479 u16 temp; 480 481 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 482 483 ret_val = e1000_acquire_phy_80003es2lan(hw); 484 if (ret_val) 485 goto out; 486 487 /* Select Configuration Page */ 488 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 489 page_select = GG82563_PHY_PAGE_SELECT; 490 } else { 491 /* 492 * Use Alternative Page Select register to access 493 * registers 30 and 31 494 */ 495 page_select = GG82563_PHY_PAGE_SELECT_ALT; 496 } 497 498 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 499 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 500 if (ret_val) { 501 e1000_release_phy_80003es2lan(hw); 502 goto out; 503 } 504 505 /* 506 * The "ready" bit in the MDIC register may be incorrectly set 507 * before the device has completed the "Page Select" MDI 508 * transaction. So we wait 200us after each MDI command... 509 */ 510 usec_delay(200); 511 512 /* ...and verify the command was successful. */ 513 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 514 515 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 516 ret_val = -E1000_ERR_PHY; 517 e1000_release_phy_80003es2lan(hw); 518 goto out; 519 } 520 521 usec_delay(200); 522 523 ret_val = e1000_read_phy_reg_mdic(hw, 524 MAX_PHY_REG_ADDRESS & offset, 525 data); 526 527 usec_delay(200); 528 e1000_release_phy_80003es2lan(hw); 529 530out: 531 return ret_val; 532} 533 534/** 535 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 536 * @hw: pointer to the HW structure 537 * @offset: offset of the register to read 538 * @data: value to write to the register 539 * 540 * Write to the GG82563 PHY register. This is a function pointer entry 541 * point called by the api module. 542 **/ 543static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 544 u32 offset, u16 data) 545{ 546 s32 ret_val; 547 u32 page_select; 548 u16 temp; 549 550 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 551 552 ret_val = e1000_acquire_phy_80003es2lan(hw); 553 if (ret_val) 554 goto out; 555 556 /* Select Configuration Page */ 557 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 558 page_select = GG82563_PHY_PAGE_SELECT; 559 } else { 560 /* 561 * Use Alternative Page Select register to access 562 * registers 30 and 31 563 */ 564 page_select = GG82563_PHY_PAGE_SELECT_ALT; 565 } 566 567 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 568 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 569 if (ret_val) { 570 e1000_release_phy_80003es2lan(hw); 571 goto out; 572 } 573 574 575 /* 576 * The "ready" bit in the MDIC register may be incorrectly set 577 * before the device has completed the "Page Select" MDI 578 * transaction. So we wait 200us after each MDI command... 579 */ 580 usec_delay(200); 581 582 /* ...and verify the command was successful. */ 583 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 584 585 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 586 ret_val = -E1000_ERR_PHY; 587 e1000_release_phy_80003es2lan(hw); 588 goto out; 589 } 590 591 usec_delay(200); 592 593 ret_val = e1000_write_phy_reg_mdic(hw, 594 MAX_PHY_REG_ADDRESS & offset, 595 data); 596 597 usec_delay(200); 598 e1000_release_phy_80003es2lan(hw); 599 600out: 601 return ret_val; 602} 603 604/** 605 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 606 * @hw: pointer to the HW structure 607 * @offset: offset of the register to read 608 * @words: number of words to write 609 * @data: buffer of data to write to the NVM 610 * 611 * Write "words" of data to the ESB2 NVM. This is a function 612 * pointer entry point called by the api module. 613 **/ 614static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 615 u16 words, u16 *data) 616{ 617 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 618 619 return e1000_write_nvm_spi(hw, offset, words, data); 620} 621 622/** 623 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 624 * @hw: pointer to the HW structure 625 * 626 * Wait a specific amount of time for manageability processes to complete. 627 * This is a function pointer entry point called by the phy module. 628 **/ 629static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 630{ 631 s32 timeout = PHY_CFG_TIMEOUT; 632 s32 ret_val = E1000_SUCCESS; 633 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 634 635 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 636 637 if (hw->bus.func == 1) 638 mask = E1000_NVM_CFG_DONE_PORT_1; 639 640 while (timeout) { 641 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 642 break; 643 msec_delay(1); 644 timeout--; 645 } 646 if (!timeout) { 647 DEBUGOUT("MNG configuration cycle has not completed.\n"); 648 ret_val = -E1000_ERR_RESET; 649 goto out; 650 } 651 652out: 653 return ret_val; 654} 655 656/** 657 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 658 * @hw: pointer to the HW structure 659 * 660 * Force the speed and duplex settings onto the PHY. This is a 661 * function pointer entry point called by the phy module. 662 **/ 663static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 664{ 665 s32 ret_val = E1000_SUCCESS; 666 u16 phy_data; 667 bool link; 668 669 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 670 671 if (!(hw->phy.ops.read_reg)) 672 goto out; 673 674 /* 675 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 676 * forced whenever speed and duplex are forced. 677 */ 678 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 679 if (ret_val) 680 goto out; 681 682 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 683 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 684 if (ret_val) 685 goto out; 686 687 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 688 689 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 690 if (ret_val) 691 goto out; 692 693 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 694 695 /* Reset the phy to commit changes. */ 696 phy_data |= MII_CR_RESET; 697 698 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 699 if (ret_val) 700 goto out; 701 702 usec_delay(1); 703 704 if (hw->phy.autoneg_wait_to_complete) { 705 DEBUGOUT("Waiting for forced speed/duplex link " 706 "on GG82563 phy.\n"); 707 708 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 709 100000, &link); 710 if (ret_val) 711 goto out; 712 713 if (!link) { 714 /* 715 * We didn't get link. 716 * Reset the DSP and cross our fingers. 717 */ 718 ret_val = e1000_phy_reset_dsp_generic(hw); 719 if (ret_val) 720 goto out; 721 } 722 723 /* Try once more */ 724 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 725 100000, &link); 726 if (ret_val) 727 goto out; 728 } 729 730 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 731 if (ret_val) 732 goto out; 733 734 /* 735 * Resetting the phy means we need to verify the TX_CLK corresponds 736 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 737 */ 738 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 739 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 740 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 741 else 742 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 743 744 /* 745 * In addition, we must re-enable CRS on Tx for both half and full 746 * duplex. 747 */ 748 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 749 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 750 751out: 752 return ret_val; 753} 754 755/** 756 * e1000_get_cable_length_80003es2lan - Set approximate cable length 757 * @hw: pointer to the HW structure 758 * 759 * Find the approximate cable length as measured by the GG82563 PHY. 760 * This is a function pointer entry point called by the phy module. 761 **/ 762static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 763{ 764 struct e1000_phy_info *phy = &hw->phy; 765 s32 ret_val = E1000_SUCCESS; 766 u16 phy_data, index; 767 768 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 769 770 if (!(hw->phy.ops.read_reg)) 771 goto out; 772 773 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 774 if (ret_val) 775 goto out; 776 777 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 778 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 779 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; 780 781 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 782 783out: 784 return ret_val; 785} 786 787/** 788 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 789 * @hw: pointer to the HW structure 790 * @speed: pointer to speed buffer 791 * @duplex: pointer to duplex buffer 792 * 793 * Retrieve the current speed and duplex configuration. 794 * This is a function pointer entry point called by the api module. 795 **/ 796static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 797 u16 *duplex) 798{ 799 s32 ret_val; 800 801 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 802 803 if (hw->phy.media_type == e1000_media_type_copper) { 804 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 805 speed, 806 duplex); 807 if (ret_val) 808 goto out; 809 if (*speed == SPEED_1000) 810 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 811 else 812 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, 813 *duplex); 814 } else { 815 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 816 speed, 817 duplex); 818 } 819 820out: 821 return ret_val; 822} 823 824/** 825 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 826 * @hw: pointer to the HW structure 827 * 828 * Perform a global reset to the ESB2 controller. 829 * This is a function pointer entry point called by the api module. 830 **/ 831static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 832{ 833 u32 ctrl, icr; 834 s32 ret_val; 835 836 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 837 838 /* 839 * Prevent the PCI-E bus from sticking if there is no TLP connection 840 * on the last TLP read/write transaction when MAC is reset. 841 */ 842 ret_val = e1000_disable_pcie_master_generic(hw); 843 if (ret_val) { 844 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 845 } 846 847 DEBUGOUT("Masking off all interrupts\n"); 848 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 849 850 E1000_WRITE_REG(hw, E1000_RCTL, 0); 851 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 852 E1000_WRITE_FLUSH(hw); 853 854 msec_delay(10); 855 856 ctrl = E1000_READ_REG(hw, E1000_CTRL); 857 858 DEBUGOUT("Issuing a global reset to MAC\n"); 859 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 860 861 ret_val = e1000_get_auto_rd_done_generic(hw); 862 if (ret_val) 863 /* We don't want to continue accessing MAC registers. */ 864 goto out; 865 866 /* Clear any pending interrupt events. */ 867 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 868 icr = E1000_READ_REG(hw, E1000_ICR); 869 870 e1000_check_alt_mac_addr_generic(hw); 871 872out: 873 return ret_val; 874} 875 876/** 877 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 878 * @hw: pointer to the HW structure 879 * 880 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 881 * This is a function pointer entry point called by the api module. 882 **/ 883static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 884{ 885 struct e1000_mac_info *mac = &hw->mac; 886 u32 reg_data; 887 s32 ret_val; 888 u16 i; 889 890 DEBUGFUNC("e1000_init_hw_80003es2lan"); 891 892 e1000_initialize_hw_bits_80003es2lan(hw); 893 894 /* Initialize identification LED */ 895 ret_val = e1000_id_led_init_generic(hw); 896 if (ret_val) { 897 DEBUGOUT("Error initializing identification LED\n"); 898 /* This is not fatal and we should not stop init due to this */ 899 } 900 901 /* Disabling VLAN filtering */ 902 DEBUGOUT("Initializing the IEEE VLAN\n"); 903 mac->ops.clear_vfta(hw); 904 905 /* Setup the receive address. */ 906 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 907 908 /* Zero out the Multicast HASH table */ 909 DEBUGOUT("Zeroing the MTA\n"); 910 for (i = 0; i < mac->mta_reg_count; i++) 911 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 912 913 /* Setup link and flow control */ 914 ret_val = mac->ops.setup_link(hw); 915 916 /* Set the transmit descriptor write-back policy */ 917 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 918 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 919 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 920 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 921 922 /* ...for both queues. */ 923 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 924 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 925 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 926 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 927 928 /* Enable retransmit on late collisions */ 929 reg_data = E1000_READ_REG(hw, E1000_TCTL); 930 reg_data |= E1000_TCTL_RTLC; 931 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 932 933 /* Configure Gigabit Carry Extend Padding */ 934 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 935 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 936 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 937 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 938 939 /* Configure Transmit Inter-Packet Gap */ 940 reg_data = E1000_READ_REG(hw, E1000_TIPG); 941 reg_data &= ~E1000_TIPG_IPGT_MASK; 942 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 943 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 944 945 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 946 reg_data &= ~0x00100000; 947 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 948 949 /* 950 * Clear all of the statistics registers (clear on read). It is 951 * important that we do this after we have tried to establish link 952 * because the symbol error count will increment wildly if there 953 * is no link. 954 */ 955 e1000_clear_hw_cntrs_80003es2lan(hw); 956 957 return ret_val; 958} 959 960/** 961 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 962 * @hw: pointer to the HW structure 963 * 964 * Initializes required hardware-dependent bits needed for normal operation. 965 **/ 966static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 967{ 968 u32 reg; 969 970 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 971 972 if (hw->mac.disable_hw_init_bits) 973 goto out; 974 975 /* Transmit Descriptor Control 0 */ 976 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 977 reg |= (1 << 22); 978 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 979 980 /* Transmit Descriptor Control 1 */ 981 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 982 reg |= (1 << 22); 983 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 984 985 /* Transmit Arbitration Control 0 */ 986 reg = E1000_READ_REG(hw, E1000_TARC(0)); 987 reg &= ~(0xF << 27); /* 30:27 */ 988 if (hw->phy.media_type != e1000_media_type_copper) 989 reg &= ~(1 << 20); 990 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 991 992 /* Transmit Arbitration Control 1 */ 993 reg = E1000_READ_REG(hw, E1000_TARC(1)); 994 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 995 reg &= ~(1 << 28); 996 else 997 reg |= (1 << 28); 998 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 999 1000out: 1001 return; 1002} 1003 1004/** 1005 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1006 * @hw: pointer to the HW structure 1007 * 1008 * Setup some GG82563 PHY registers for obtaining link 1009 **/ 1010static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1011{ 1012 struct e1000_phy_info *phy = &hw->phy; 1013 s32 ret_val; 1014 u32 ctrl_ext; 1015 u32 i = 0; 1016 u16 data, data2; 1017 1018 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1019 1020 if (!phy->reset_disable) { 1021 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1022 &data); 1023 if (ret_val) 1024 goto out; 1025 1026 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1027 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1028 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1029 1030 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1031 data); 1032 if (ret_val) 1033 goto out; 1034 1035 /* 1036 * Options: 1037 * MDI/MDI-X = 0 (default) 1038 * 0 - Auto for all speeds 1039 * 1 - MDI mode 1040 * 2 - MDI-X mode 1041 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1042 */ 1043 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1044 if (ret_val) 1045 goto out; 1046 1047 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1048 1049 switch (phy->mdix) { 1050 case 1: 1051 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1052 break; 1053 case 2: 1054 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1055 break; 1056 case 0: 1057 default: 1058 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1059 break; 1060 } 1061 1062 /* 1063 * Options: 1064 * disable_polarity_correction = 0 (default) 1065 * Automatic Correction for Reversed Cable Polarity 1066 * 0 - Disabled 1067 * 1 - Enabled 1068 */ 1069 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1070 if (phy->disable_polarity_correction) 1071 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1072 1073 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1074 if (ret_val) 1075 goto out; 1076 1077 /* SW Reset the PHY so all changes take effect */ 1078 ret_val = hw->phy.ops.commit(hw); 1079 if (ret_val) { 1080 DEBUGOUT("Error Resetting the PHY\n"); 1081 goto out; 1082 } 1083 1084 } 1085 1086 /* Bypass Rx and Tx FIFO's */ 1087 ret_val = e1000_write_kmrn_reg_generic(hw, 1088 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1089 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1090 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1091 if (ret_val) 1092 goto out; 1093 1094 ret_val = e1000_read_kmrn_reg_generic(hw, 1095 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1096 &data); 1097 if (ret_val) 1098 goto out; 1099 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1100 ret_val = e1000_write_kmrn_reg_generic(hw, 1101 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1102 data); 1103 if (ret_val) 1104 goto out; 1105 1106 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1107 if (ret_val) 1108 goto out; 1109 1110 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1111 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1112 if (ret_val) 1113 goto out; 1114 1115 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1116 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1117 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1118 1119 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1120 if (ret_val) 1121 goto out; 1122 1123 /* 1124 * Do not init these registers when the HW is in IAMT mode, since the 1125 * firmware will have already initialized them. We only initialize 1126 * them if the HW is not in IAMT mode. 1127 */ 1128 if (!(hw->mac.ops.check_mng_mode(hw))) { 1129 /* Enable Electrical Idle on the PHY */ 1130 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1131 ret_val = hw->phy.ops.write_reg(hw, 1132 GG82563_PHY_PWR_MGMT_CTRL, 1133 data); 1134 if (ret_val) 1135 goto out; 1136 1137 do { 1138 ret_val = hw->phy.ops.read_reg(hw, 1139 GG82563_PHY_KMRN_MODE_CTRL, 1140 &data); 1141 if (ret_val) 1142 goto out; 1143 1144 ret_val = hw->phy.ops.read_reg(hw, 1145 GG82563_PHY_KMRN_MODE_CTRL, 1146 &data2); 1147 if (ret_val) 1148 goto out; 1149 i++; 1150 } while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY)); 1151 1152 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1153 ret_val = hw->phy.ops.write_reg(hw, 1154 GG82563_PHY_KMRN_MODE_CTRL, 1155 data); 1156 1157 if (ret_val) 1158 goto out; 1159 } 1160 1161 /* 1162 * Workaround: Disable padding in Kumeran interface in the MAC 1163 * and in the PHY to avoid CRC errors. 1164 */ 1165 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1166 if (ret_val) 1167 goto out; 1168 1169 data |= GG82563_ICR_DIS_PADDING; 1170 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1171 if (ret_val) 1172 goto out; 1173 1174out: 1175 return ret_val; 1176} 1177 1178/** 1179 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1180 * @hw: pointer to the HW structure 1181 * 1182 * Essentially a wrapper for setting up all things "copper" related. 1183 * This is a function pointer entry point called by the mac module. 1184 **/ 1185static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1186{ 1187 u32 ctrl; 1188 s32 ret_val; 1189 u16 reg_data; 1190 1191 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1192 1193 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1194 ctrl |= E1000_CTRL_SLU; 1195 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1196 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1197 1198 /* 1199 * Set the mac to wait the maximum time between each 1200 * iteration and increase the max iterations when 1201 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1202 */ 1203 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4), 1204 0xFFFF); 1205 if (ret_val) 1206 goto out; 1207 ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 1208 ®_data); 1209 if (ret_val) 1210 goto out; 1211 reg_data |= 0x3F; 1212 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9), 1213 reg_data); 1214 if (ret_val) 1215 goto out; 1216 ret_val = e1000_read_kmrn_reg_generic(hw, 1217 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1218 ®_data); 1219 if (ret_val) 1220 goto out; 1221 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1222 ret_val = e1000_write_kmrn_reg_generic(hw, 1223 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1224 reg_data); 1225 if (ret_val) 1226 goto out; 1227 1228 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1229 if (ret_val) 1230 goto out; 1231 1232 ret_val = e1000_setup_copper_link_generic(hw); 1233 1234out: 1235 return ret_val; 1236} 1237 1238/** 1239 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1240 * @hw: pointer to the HW structure 1241 * @duplex: current duplex setting 1242 * 1243 * Configure the KMRN interface by applying last minute quirks for 1244 * 10/100 operation. 1245 **/ 1246static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1247{ 1248 s32 ret_val = E1000_SUCCESS; 1249 u32 tipg; 1250 u32 i = 0; 1251 u16 reg_data, reg_data2; 1252 1253 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1254 1255 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1256 ret_val = e1000_write_kmrn_reg_generic(hw, 1257 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1258 reg_data); 1259 if (ret_val) 1260 goto out; 1261 1262 /* Configure Transmit Inter-Packet Gap */ 1263 tipg = E1000_READ_REG(hw, E1000_TIPG); 1264 tipg &= ~E1000_TIPG_IPGT_MASK; 1265 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1266 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1267 1268 1269 do { 1270 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1271 ®_data); 1272 if (ret_val) 1273 goto out; 1274 1275 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1276 ®_data2); 1277 if (ret_val) 1278 goto out; 1279 i++; 1280 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1281 1282 if (duplex == HALF_DUPLEX) 1283 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1284 else 1285 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1286 1287 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1288 1289out: 1290 return ret_val; 1291} 1292 1293/** 1294 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1295 * @hw: pointer to the HW structure 1296 * 1297 * Configure the KMRN interface by applying last minute quirks for 1298 * gigabit operation. 1299 **/ 1300static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1301{ 1302 s32 ret_val = E1000_SUCCESS; 1303 u16 reg_data, reg_data2; 1304 u32 tipg; 1305 u32 i = 0; 1306 1307 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1308 1309 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1310 ret_val = e1000_write_kmrn_reg_generic(hw, 1311 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1312 reg_data); 1313 if (ret_val) 1314 goto out; 1315 1316 /* Configure Transmit Inter-Packet Gap */ 1317 tipg = E1000_READ_REG(hw, E1000_TIPG); 1318 tipg &= ~E1000_TIPG_IPGT_MASK; 1319 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1320 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1321 1322 1323 do { 1324 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1325 ®_data); 1326 if (ret_val) 1327 goto out; 1328 1329 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1330 ®_data2); 1331 if (ret_val) 1332 goto out; 1333 i++; 1334 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1335 1336 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1337 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1338 1339out: 1340 return ret_val; 1341} 1342 1343/** 1344 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1345 * @hw: pointer to the HW structure 1346 **/ 1347static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1348{ 1349 s32 ret_val = E1000_SUCCESS; 1350 1351 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1352 if (e1000_check_alt_mac_addr_generic(hw)) 1353 ret_val = e1000_read_mac_addr_generic(hw); 1354 1355 return ret_val; 1356} 1357 1358/** 1359 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1360 * @hw: pointer to the HW structure 1361 * 1362 * In the case of a PHY power down to save power, or to turn off link during a 1363 * driver unload, or wake on lan is not enabled, remove the link. 1364 **/ 1365static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1366{ 1367 /* If the management interface is not enabled, then power down */ 1368 if (!(hw->mac.ops.check_mng_mode(hw) || 1369 hw->phy.ops.check_reset_block(hw))) 1370 e1000_power_down_phy_copper(hw); 1371 1372 return; 1373} 1374 1375/** 1376 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1377 * @hw: pointer to the HW structure 1378 * 1379 * Clears the hardware counters by reading the counter registers. 1380 **/ 1381static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1382{ 1383 volatile u32 temp; 1384 1385 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1386 1387 e1000_clear_hw_cntrs_base_generic(hw); 1388 1389 temp = E1000_READ_REG(hw, E1000_PRC64); 1390 temp = E1000_READ_REG(hw, E1000_PRC127); 1391 temp = E1000_READ_REG(hw, E1000_PRC255); 1392 temp = E1000_READ_REG(hw, E1000_PRC511); 1393 temp = E1000_READ_REG(hw, E1000_PRC1023); 1394 temp = E1000_READ_REG(hw, E1000_PRC1522); 1395 temp = E1000_READ_REG(hw, E1000_PTC64); 1396 temp = E1000_READ_REG(hw, E1000_PTC127); 1397 temp = E1000_READ_REG(hw, E1000_PTC255); 1398 temp = E1000_READ_REG(hw, E1000_PTC511); 1399 temp = E1000_READ_REG(hw, E1000_PTC1023); 1400 temp = E1000_READ_REG(hw, E1000_PTC1522); 1401 1402 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1403 temp = E1000_READ_REG(hw, E1000_RXERRC); 1404 temp = E1000_READ_REG(hw, E1000_TNCRS); 1405 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1406 temp = E1000_READ_REG(hw, E1000_TSCTC); 1407 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1408 1409 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1410 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1411 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1412 1413 temp = E1000_READ_REG(hw, E1000_IAC); 1414 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1415 1416 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1417 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1418 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1419 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1420 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1421 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1422 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1423} 1424