e1000_80003es2lan.c revision 286833
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 286833 2015-08-16 20:13:58Z sbruno $*/ 34 35/* 80003ES2LAN Gigabit Ethernet Controller (Copper) 36 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 37 */ 38 39#include "e1000_api.h" 40 41static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 42static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 43static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 44static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 45static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 46 u32 offset, 47 u16 *data); 48static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 49 u32 offset, 50 u16 data); 51static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 52 u16 words, u16 *data); 53static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 54static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 55static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 56static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 57 u16 *duplex); 58static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 59static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 60static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 61static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 62static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 63static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 64static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 65static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 66static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 67 u16 *data); 68static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 69 u16 data); 70static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 71static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 72static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 73static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 74 75/* A table for the GG82563 cable length where the range is defined 76 * with a lower bound at "index" and the upper bound at 77 * "index + 5". 78 */ 79static const u16 e1000_gg82563_cable_length_table[] = { 80 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 81#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 82 (sizeof(e1000_gg82563_cable_length_table) / \ 83 sizeof(e1000_gg82563_cable_length_table[0])) 84 85/** 86 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 87 * @hw: pointer to the HW structure 88 **/ 89static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 90{ 91 struct e1000_phy_info *phy = &hw->phy; 92 s32 ret_val; 93 94 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 95 96 if (hw->phy.media_type != e1000_media_type_copper) { 97 phy->type = e1000_phy_none; 98 return E1000_SUCCESS; 99 } else { 100 phy->ops.power_up = e1000_power_up_phy_copper; 101 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 102 } 103 104 phy->addr = 1; 105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106 phy->reset_delay_us = 100; 107 phy->type = e1000_phy_gg82563; 108 109 phy->ops.acquire = e1000_acquire_phy_80003es2lan; 110 phy->ops.check_polarity = e1000_check_polarity_m88; 111 phy->ops.check_reset_block = e1000_check_reset_block_generic; 112 phy->ops.commit = e1000_phy_sw_reset_generic; 113 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 114 phy->ops.get_info = e1000_get_phy_info_m88; 115 phy->ops.release = e1000_release_phy_80003es2lan; 116 phy->ops.reset = e1000_phy_hw_reset_generic; 117 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 118 119 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 120 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 121 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 122 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 123 124 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 125 126 /* This can only be done after all function pointers are setup. */ 127 ret_val = e1000_get_phy_id(hw); 128 129 /* Verify phy id */ 130 if (phy->id != GG82563_E_PHY_ID) 131 return -E1000_ERR_PHY; 132 133 return ret_val; 134} 135 136/** 137 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 138 * @hw: pointer to the HW structure 139 **/ 140static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 141{ 142 struct e1000_nvm_info *nvm = &hw->nvm; 143 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 144 u16 size; 145 146 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 147 148 nvm->opcode_bits = 8; 149 nvm->delay_usec = 1; 150 switch (nvm->override) { 151 case e1000_nvm_override_spi_large: 152 nvm->page_size = 32; 153 nvm->address_bits = 16; 154 break; 155 case e1000_nvm_override_spi_small: 156 nvm->page_size = 8; 157 nvm->address_bits = 8; 158 break; 159 default: 160 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 161 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 162 break; 163 } 164 165 nvm->type = e1000_nvm_eeprom_spi; 166 167 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 168 E1000_EECD_SIZE_EX_SHIFT); 169 170 /* Added to a constant, "size" becomes the left-shift value 171 * for setting word_size. 172 */ 173 size += NVM_WORD_SIZE_BASE_SHIFT; 174 175 /* EEPROM access above 16k is unsupported */ 176 if (size > 14) 177 size = 14; 178 nvm->word_size = 1 << size; 179 180 /* Function Pointers */ 181 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 182 nvm->ops.read = e1000_read_nvm_eerd; 183 nvm->ops.release = e1000_release_nvm_80003es2lan; 184 nvm->ops.update = e1000_update_nvm_checksum_generic; 185 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 186 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 187 nvm->ops.write = e1000_write_nvm_80003es2lan; 188 189 return E1000_SUCCESS; 190} 191 192/** 193 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 194 * @hw: pointer to the HW structure 195 **/ 196static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 197{ 198 struct e1000_mac_info *mac = &hw->mac; 199 200 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 201 202 /* Set media type and media-dependent function pointers */ 203 switch (hw->device_id) { 204 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 205 hw->phy.media_type = e1000_media_type_internal_serdes; 206 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 207 mac->ops.setup_physical_interface = 208 e1000_setup_fiber_serdes_link_generic; 209 break; 210 default: 211 hw->phy.media_type = e1000_media_type_copper; 212 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 213 mac->ops.setup_physical_interface = 214 e1000_setup_copper_link_80003es2lan; 215 break; 216 } 217 218 /* Set mta register count */ 219 mac->mta_reg_count = 128; 220 /* Set rar entry count */ 221 mac->rar_entry_count = E1000_RAR_ENTRIES; 222 /* Set if part includes ASF firmware */ 223 mac->asf_firmware_present = TRUE; 224 /* FWSM register */ 225 mac->has_fwsm = TRUE; 226 /* ARC supported; valid only if manageability features are enabled. */ 227 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 228 E1000_FWSM_MODE_MASK); 229 /* Adaptive IFS not supported */ 230 mac->adaptive_ifs = FALSE; 231 232 /* Function pointers */ 233 234 /* bus type/speed/width */ 235 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 236 /* reset */ 237 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 238 /* hw initialization */ 239 mac->ops.init_hw = e1000_init_hw_80003es2lan; 240 /* link setup */ 241 mac->ops.setup_link = e1000_setup_link_generic; 242 /* check management mode */ 243 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 244 /* multicast address update */ 245 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 246 /* writing VFTA */ 247 mac->ops.write_vfta = e1000_write_vfta_generic; 248 /* clearing VFTA */ 249 mac->ops.clear_vfta = e1000_clear_vfta_generic; 250 /* read mac address */ 251 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 252 /* ID LED init */ 253 mac->ops.id_led_init = e1000_id_led_init_generic; 254 /* blink LED */ 255 mac->ops.blink_led = e1000_blink_led_generic; 256 /* setup LED */ 257 mac->ops.setup_led = e1000_setup_led_generic; 258 /* cleanup LED */ 259 mac->ops.cleanup_led = e1000_cleanup_led_generic; 260 /* turn on/off LED */ 261 mac->ops.led_on = e1000_led_on_generic; 262 mac->ops.led_off = e1000_led_off_generic; 263 /* clear hardware counters */ 264 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 265 /* link info */ 266 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 267 268 /* set lan id for port to determine which phy lock to use */ 269 hw->mac.ops.set_lan_id(hw); 270 271 return E1000_SUCCESS; 272} 273 274/** 275 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 276 * @hw: pointer to the HW structure 277 * 278 * Called to initialize all function pointers and parameters. 279 **/ 280void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 281{ 282 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 283 284 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 285 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 286 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 287} 288 289/** 290 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 291 * @hw: pointer to the HW structure 292 * 293 * A wrapper to acquire access rights to the correct PHY. 294 **/ 295static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 296{ 297 u16 mask; 298 299 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 300 301 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 302 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 303} 304 305/** 306 * e1000_release_phy_80003es2lan - Release rights to access PHY 307 * @hw: pointer to the HW structure 308 * 309 * A wrapper to release access rights to the correct PHY. 310 **/ 311static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 312{ 313 u16 mask; 314 315 DEBUGFUNC("e1000_release_phy_80003es2lan"); 316 317 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 318 e1000_release_swfw_sync_80003es2lan(hw, mask); 319} 320 321/** 322 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 323 * @hw: pointer to the HW structure 324 * 325 * Acquire the semaphore to access the Kumeran interface. 326 * 327 **/ 328static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 329{ 330 u16 mask; 331 332 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 333 334 mask = E1000_SWFW_CSR_SM; 335 336 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 337} 338 339/** 340 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 341 * @hw: pointer to the HW structure 342 * 343 * Release the semaphore used to access the Kumeran interface 344 **/ 345static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 346{ 347 u16 mask; 348 349 DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 350 351 mask = E1000_SWFW_CSR_SM; 352 353 e1000_release_swfw_sync_80003es2lan(hw, mask); 354} 355 356/** 357 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 358 * @hw: pointer to the HW structure 359 * 360 * Acquire the semaphore to access the EEPROM. 361 **/ 362static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 363{ 364 s32 ret_val; 365 366 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 367 368 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 369 if (ret_val) 370 return ret_val; 371 372 ret_val = e1000_acquire_nvm_generic(hw); 373 374 if (ret_val) 375 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 376 377 return ret_val; 378} 379 380/** 381 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 382 * @hw: pointer to the HW structure 383 * 384 * Release the semaphore used to access the EEPROM. 385 **/ 386static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 387{ 388 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 389 390 e1000_release_nvm_generic(hw); 391 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 392} 393 394/** 395 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 396 * @hw: pointer to the HW structure 397 * @mask: specifies which semaphore to acquire 398 * 399 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 400 * will also specify which port we're acquiring the lock for. 401 **/ 402static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 403{ 404 u32 swfw_sync; 405 u32 swmask = mask; 406 u32 fwmask = mask << 16; 407 s32 i = 0; 408 s32 timeout = 50; 409 410 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 411 412 while (i < timeout) { 413 if (e1000_get_hw_semaphore_generic(hw)) 414 return -E1000_ERR_SWFW_SYNC; 415 416 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 417 if (!(swfw_sync & (fwmask | swmask))) 418 break; 419 420 /* Firmware currently using resource (fwmask) 421 * or other software thread using resource (swmask) 422 */ 423 e1000_put_hw_semaphore_generic(hw); 424 msec_delay_irq(5); 425 i++; 426 } 427 428 if (i == timeout) { 429 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 430 return -E1000_ERR_SWFW_SYNC; 431 } 432 433 swfw_sync |= swmask; 434 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 435 436 e1000_put_hw_semaphore_generic(hw); 437 438 return E1000_SUCCESS; 439} 440 441/** 442 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 443 * @hw: pointer to the HW structure 444 * @mask: specifies which semaphore to acquire 445 * 446 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 447 * will also specify which port we're releasing the lock for. 448 **/ 449static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 450{ 451 u32 swfw_sync; 452 453 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 454 455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 456 ; /* Empty */ 457 458 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 459 swfw_sync &= ~mask; 460 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 461 462 e1000_put_hw_semaphore_generic(hw); 463} 464 465/** 466 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 467 * @hw: pointer to the HW structure 468 * @offset: offset of the register to read 469 * @data: pointer to the data returned from the operation 470 * 471 * Read the GG82563 PHY register. 472 **/ 473static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 474 u32 offset, u16 *data) 475{ 476 s32 ret_val; 477 u32 page_select; 478 u16 temp; 479 480 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 481 482 ret_val = e1000_acquire_phy_80003es2lan(hw); 483 if (ret_val) 484 return ret_val; 485 486 /* Select Configuration Page */ 487 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 488 page_select = GG82563_PHY_PAGE_SELECT; 489 } else { 490 /* Use Alternative Page Select register to access 491 * registers 30 and 31 492 */ 493 page_select = GG82563_PHY_PAGE_SELECT_ALT; 494 } 495 496 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 497 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 498 if (ret_val) { 499 e1000_release_phy_80003es2lan(hw); 500 return ret_val; 501 } 502 503 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 504 /* The "ready" bit in the MDIC register may be incorrectly set 505 * before the device has completed the "Page Select" MDI 506 * transaction. So we wait 200us after each MDI command... 507 */ 508 usec_delay(200); 509 510 /* ...and verify the command was successful. */ 511 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 512 513 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 514 e1000_release_phy_80003es2lan(hw); 515 return -E1000_ERR_PHY; 516 } 517 518 usec_delay(200); 519 520 ret_val = e1000_read_phy_reg_mdic(hw, 521 MAX_PHY_REG_ADDRESS & offset, 522 data); 523 524 usec_delay(200); 525 } else { 526 ret_val = e1000_read_phy_reg_mdic(hw, 527 MAX_PHY_REG_ADDRESS & offset, 528 data); 529 } 530 531 e1000_release_phy_80003es2lan(hw); 532 533 return ret_val; 534} 535 536/** 537 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 538 * @hw: pointer to the HW structure 539 * @offset: offset of the register to read 540 * @data: value to write to the register 541 * 542 * Write to the GG82563 PHY register. 543 **/ 544static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 545 u32 offset, u16 data) 546{ 547 s32 ret_val; 548 u32 page_select; 549 u16 temp; 550 551 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 552 553 ret_val = e1000_acquire_phy_80003es2lan(hw); 554 if (ret_val) 555 return ret_val; 556 557 /* Select Configuration Page */ 558 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 559 page_select = GG82563_PHY_PAGE_SELECT; 560 } else { 561 /* Use Alternative Page Select register to access 562 * registers 30 and 31 563 */ 564 page_select = GG82563_PHY_PAGE_SELECT_ALT; 565 } 566 567 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 568 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 569 if (ret_val) { 570 e1000_release_phy_80003es2lan(hw); 571 return ret_val; 572 } 573 574 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 575 /* The "ready" bit in the MDIC register may be incorrectly set 576 * before the device has completed the "Page Select" MDI 577 * transaction. So we wait 200us after each MDI command... 578 */ 579 usec_delay(200); 580 581 /* ...and verify the command was successful. */ 582 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 583 584 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 585 e1000_release_phy_80003es2lan(hw); 586 return -E1000_ERR_PHY; 587 } 588 589 usec_delay(200); 590 591 ret_val = e1000_write_phy_reg_mdic(hw, 592 MAX_PHY_REG_ADDRESS & offset, 593 data); 594 595 usec_delay(200); 596 } else { 597 ret_val = e1000_write_phy_reg_mdic(hw, 598 MAX_PHY_REG_ADDRESS & offset, 599 data); 600 } 601 602 e1000_release_phy_80003es2lan(hw); 603 604 return ret_val; 605} 606 607/** 608 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 609 * @hw: pointer to the HW structure 610 * @offset: offset of the register to read 611 * @words: number of words to write 612 * @data: buffer of data to write to the NVM 613 * 614 * Write "words" of data to the ESB2 NVM. 615 **/ 616static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 617 u16 words, u16 *data) 618{ 619 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 620 621 return e1000_write_nvm_spi(hw, offset, words, data); 622} 623 624/** 625 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 626 * @hw: pointer to the HW structure 627 * 628 * Wait a specific amount of time for manageability processes to complete. 629 * This is a function pointer entry point called by the phy module. 630 **/ 631static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 632{ 633 s32 timeout = PHY_CFG_TIMEOUT; 634 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 635 636 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 637 638 if (hw->bus.func == 1) 639 mask = E1000_NVM_CFG_DONE_PORT_1; 640 641 while (timeout) { 642 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 643 break; 644 msec_delay(1); 645 timeout--; 646 } 647 if (!timeout) { 648 DEBUGOUT("MNG configuration cycle has not completed.\n"); 649 return -E1000_ERR_RESET; 650 } 651 652 return E1000_SUCCESS; 653} 654 655/** 656 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 657 * @hw: pointer to the HW structure 658 * 659 * Force the speed and duplex settings onto the PHY. This is a 660 * function pointer entry point called by the phy module. 661 **/ 662static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 663{ 664 s32 ret_val; 665 u16 phy_data; 666 bool link; 667 668 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 669 670 if (!(hw->phy.ops.read_reg)) 671 return E1000_SUCCESS; 672 673 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 674 * forced whenever speed and duplex are forced. 675 */ 676 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 677 if (ret_val) 678 return ret_val; 679 680 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 682 if (ret_val) 683 return ret_val; 684 685 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 686 687 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 688 if (ret_val) 689 return ret_val; 690 691 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 692 693 /* Reset the phy to commit changes. */ 694 phy_data |= MII_CR_RESET; 695 696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 697 if (ret_val) 698 return ret_val; 699 700 usec_delay(1); 701 702 if (hw->phy.autoneg_wait_to_complete) { 703 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); 704 705 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 706 100000, &link); 707 if (ret_val) 708 return ret_val; 709 710 if (!link) { 711 /* We didn't get link. 712 * Reset the DSP and cross our fingers. 713 */ 714 ret_val = e1000_phy_reset_dsp_generic(hw); 715 if (ret_val) 716 return ret_val; 717 } 718 719 /* Try once more */ 720 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 721 100000, &link); 722 if (ret_val) 723 return ret_val; 724 } 725 726 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 727 &phy_data); 728 if (ret_val) 729 return ret_val; 730 731 /* Resetting the phy means we need to verify the TX_CLK corresponds 732 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 733 */ 734 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 735 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 736 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 737 else 738 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 739 740 /* In addition, we must re-enable CRS on Tx for both half and full 741 * duplex. 742 */ 743 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 745 phy_data); 746 747 return ret_val; 748} 749 750/** 751 * e1000_get_cable_length_80003es2lan - Set approximate cable length 752 * @hw: pointer to the HW structure 753 * 754 * Find the approximate cable length as measured by the GG82563 PHY. 755 * This is a function pointer entry point called by the phy module. 756 **/ 757static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 758{ 759 struct e1000_phy_info *phy = &hw->phy; 760 s32 ret_val; 761 u16 phy_data, index; 762 763 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 764 765 if (!(hw->phy.ops.read_reg)) 766 return E1000_SUCCESS; 767 768 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 769 if (ret_val) 770 return ret_val; 771 772 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 773 774 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 775 return -E1000_ERR_PHY; 776 777 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 778 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 779 780 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 781 782 return E1000_SUCCESS; 783} 784 785/** 786 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 787 * @hw: pointer to the HW structure 788 * @speed: pointer to speed buffer 789 * @duplex: pointer to duplex buffer 790 * 791 * Retrieve the current speed and duplex configuration. 792 **/ 793static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 794 u16 *duplex) 795{ 796 s32 ret_val; 797 798 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 799 800 if (hw->phy.media_type == e1000_media_type_copper) { 801 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 802 duplex); 803 hw->phy.ops.cfg_on_link_up(hw); 804 } else { 805 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 806 speed, 807 duplex); 808 } 809 810 return ret_val; 811} 812 813/** 814 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 815 * @hw: pointer to the HW structure 816 * 817 * Perform a global reset to the ESB2 controller. 818 **/ 819static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 820{ 821 u32 ctrl; 822 s32 ret_val; 823 u16 kum_reg_data; 824 825 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 826 827 /* Prevent the PCI-E bus from sticking if there is no TLP connection 828 * on the last TLP read/write transaction when MAC is reset. 829 */ 830 ret_val = e1000_disable_pcie_master_generic(hw); 831 if (ret_val) 832 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 833 834 DEBUGOUT("Masking off all interrupts\n"); 835 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 836 837 E1000_WRITE_REG(hw, E1000_RCTL, 0); 838 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 839 E1000_WRITE_FLUSH(hw); 840 841 msec_delay(10); 842 843 ctrl = E1000_READ_REG(hw, E1000_CTRL); 844 845 ret_val = e1000_acquire_phy_80003es2lan(hw); 846 if (ret_val) 847 return ret_val; 848 849 DEBUGOUT("Issuing a global reset to MAC\n"); 850 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 851 e1000_release_phy_80003es2lan(hw); 852 853 /* Disable IBIST slave mode (far-end loopback) */ 854 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 855 &kum_reg_data); 856 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 857 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 858 kum_reg_data); 859 860 ret_val = e1000_get_auto_rd_done_generic(hw); 861 if (ret_val) 862 /* We don't want to continue accessing MAC registers. */ 863 return ret_val; 864 865 /* Clear any pending interrupt events. */ 866 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 867 E1000_READ_REG(hw, E1000_ICR); 868 869 return e1000_check_alt_mac_addr_generic(hw); 870} 871 872/** 873 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 874 * @hw: pointer to the HW structure 875 * 876 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 877 **/ 878static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 879{ 880 struct e1000_mac_info *mac = &hw->mac; 881 u32 reg_data; 882 s32 ret_val; 883 u16 kum_reg_data; 884 u16 i; 885 886 DEBUGFUNC("e1000_init_hw_80003es2lan"); 887 888 e1000_initialize_hw_bits_80003es2lan(hw); 889 890 /* Initialize identification LED */ 891 ret_val = mac->ops.id_led_init(hw); 892 /* An error is not fatal and we should not stop init due to this */ 893 if (ret_val) 894 DEBUGOUT("Error initializing identification LED\n"); 895 896 /* Disabling VLAN filtering */ 897 DEBUGOUT("Initializing the IEEE VLAN\n"); 898 mac->ops.clear_vfta(hw); 899 900 /* Setup the receive address. */ 901 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 902 903 /* Zero out the Multicast HASH table */ 904 DEBUGOUT("Zeroing the MTA\n"); 905 for (i = 0; i < mac->mta_reg_count; i++) 906 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 907 908 /* Setup link and flow control */ 909 ret_val = mac->ops.setup_link(hw); 910 if (ret_val) 911 return ret_val; 912 913 /* Disable IBIST slave mode (far-end loopback) */ 914 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 915 &kum_reg_data); 916 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 917 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 918 kum_reg_data); 919 920 /* Set the transmit descriptor write-back policy */ 921 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 922 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 923 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 924 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 925 926 /* ...for both queues. */ 927 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 928 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 929 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 930 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 931 932 /* Enable retransmit on late collisions */ 933 reg_data = E1000_READ_REG(hw, E1000_TCTL); 934 reg_data |= E1000_TCTL_RTLC; 935 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 936 937 /* Configure Gigabit Carry Extend Padding */ 938 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 939 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 940 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 941 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 942 943 /* Configure Transmit Inter-Packet Gap */ 944 reg_data = E1000_READ_REG(hw, E1000_TIPG); 945 reg_data &= ~E1000_TIPG_IPGT_MASK; 946 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 947 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 948 949 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 950 reg_data &= ~0x00100000; 951 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 952 953 /* default to TRUE to enable the MDIC W/A */ 954 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; 955 956 ret_val = 957 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> 958 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); 959 if (!ret_val) { 960 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 961 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 962 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE; 963 } 964 965 /* Clear all of the statistics registers (clear on read). It is 966 * important that we do this after we have tried to establish link 967 * because the symbol error count will increment wildly if there 968 * is no link. 969 */ 970 e1000_clear_hw_cntrs_80003es2lan(hw); 971 972 return ret_val; 973} 974 975/** 976 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 977 * @hw: pointer to the HW structure 978 * 979 * Initializes required hardware-dependent bits needed for normal operation. 980 **/ 981static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 982{ 983 u32 reg; 984 985 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 986 987 /* Transmit Descriptor Control 0 */ 988 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 989 reg |= (1 << 22); 990 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 991 992 /* Transmit Descriptor Control 1 */ 993 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 994 reg |= (1 << 22); 995 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 996 997 /* Transmit Arbitration Control 0 */ 998 reg = E1000_READ_REG(hw, E1000_TARC(0)); 999 reg &= ~(0xF << 27); /* 30:27 */ 1000 if (hw->phy.media_type != e1000_media_type_copper) 1001 reg &= ~(1 << 20); 1002 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1003 1004 /* Transmit Arbitration Control 1 */ 1005 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1006 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1007 reg &= ~(1 << 28); 1008 else 1009 reg |= (1 << 28); 1010 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1011 1012 /* Disable IPv6 extension header parsing because some malformed 1013 * IPv6 headers can hang the Rx. 1014 */ 1015 reg = E1000_READ_REG(hw, E1000_RFCTL); 1016 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1017 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1018 1019 return; 1020} 1021 1022/** 1023 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1024 * @hw: pointer to the HW structure 1025 * 1026 * Setup some GG82563 PHY registers for obtaining link 1027 **/ 1028static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1029{ 1030 struct e1000_phy_info *phy = &hw->phy; 1031 s32 ret_val; 1032 u32 reg; 1033 u16 data; 1034 1035 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1036 1037 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 1038 if (ret_val) 1039 return ret_val; 1040 1041 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1042 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1043 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1044 1045 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 1046 if (ret_val) 1047 return ret_val; 1048 1049 /* Options: 1050 * MDI/MDI-X = 0 (default) 1051 * 0 - Auto for all speeds 1052 * 1 - MDI mode 1053 * 2 - MDI-X mode 1054 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1055 */ 1056 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1057 if (ret_val) 1058 return ret_val; 1059 1060 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1061 1062 switch (phy->mdix) { 1063 case 1: 1064 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1065 break; 1066 case 2: 1067 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1068 break; 1069 case 0: 1070 default: 1071 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1072 break; 1073 } 1074 1075 /* Options: 1076 * disable_polarity_correction = 0 (default) 1077 * Automatic Correction for Reversed Cable Polarity 1078 * 0 - Disabled 1079 * 1 - Enabled 1080 */ 1081 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1082 if (phy->disable_polarity_correction) 1083 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1084 1085 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1086 if (ret_val) 1087 return ret_val; 1088 1089 /* SW Reset the PHY so all changes take effect */ 1090 ret_val = hw->phy.ops.commit(hw); 1091 if (ret_val) { 1092 DEBUGOUT("Error Resetting the PHY\n"); 1093 return ret_val; 1094 } 1095 1096 /* Bypass Rx and Tx FIFO's */ 1097 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; 1098 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1099 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1100 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1101 if (ret_val) 1102 return ret_val; 1103 1104 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; 1105 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); 1106 if (ret_val) 1107 return ret_val; 1108 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1109 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1110 if (ret_val) 1111 return ret_val; 1112 1113 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1114 if (ret_val) 1115 return ret_val; 1116 1117 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1118 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1119 if (ret_val) 1120 return ret_val; 1121 1122 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1123 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1124 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1125 1126 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1127 if (ret_val) 1128 return ret_val; 1129 1130 /* Do not init these registers when the HW is in IAMT mode, since the 1131 * firmware will have already initialized them. We only initialize 1132 * them if the HW is not in IAMT mode. 1133 */ 1134 if (!hw->mac.ops.check_mng_mode(hw)) { 1135 /* Enable Electrical Idle on the PHY */ 1136 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1137 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1138 data); 1139 if (ret_val) 1140 return ret_val; 1141 1142 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1143 &data); 1144 if (ret_val) 1145 return ret_val; 1146 1147 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1148 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1149 data); 1150 if (ret_val) 1151 return ret_val; 1152 } 1153 1154 /* Workaround: Disable padding in Kumeran interface in the MAC 1155 * and in the PHY to avoid CRC errors. 1156 */ 1157 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1158 if (ret_val) 1159 return ret_val; 1160 1161 data |= GG82563_ICR_DIS_PADDING; 1162 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1163 if (ret_val) 1164 return ret_val; 1165 1166 return E1000_SUCCESS; 1167} 1168 1169/** 1170 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1171 * @hw: pointer to the HW structure 1172 * 1173 * Essentially a wrapper for setting up all things "copper" related. 1174 * This is a function pointer entry point called by the mac module. 1175 **/ 1176static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1177{ 1178 u32 ctrl; 1179 s32 ret_val; 1180 u16 reg_data; 1181 1182 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1183 1184 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1185 ctrl |= E1000_CTRL_SLU; 1186 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1187 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1188 1189 /* Set the mac to wait the maximum time between each 1190 * iteration and increase the max iterations when 1191 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1192 */ 1193 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1194 0xFFFF); 1195 if (ret_val) 1196 return ret_val; 1197 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1198 ®_data); 1199 if (ret_val) 1200 return ret_val; 1201 reg_data |= 0x3F; 1202 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1203 reg_data); 1204 if (ret_val) 1205 return ret_val; 1206 ret_val = 1207 e1000_read_kmrn_reg_80003es2lan(hw, 1208 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1209 ®_data); 1210 if (ret_val) 1211 return ret_val; 1212 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1213 ret_val = 1214 e1000_write_kmrn_reg_80003es2lan(hw, 1215 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1216 reg_data); 1217 if (ret_val) 1218 return ret_val; 1219 1220 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1221 if (ret_val) 1222 return ret_val; 1223 1224 return e1000_setup_copper_link_generic(hw); 1225} 1226 1227/** 1228 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1229 * @hw: pointer to the HW structure 1230 * @duplex: current duplex setting 1231 * 1232 * Configure the KMRN interface by applying last minute quirks for 1233 * 10/100 operation. 1234 **/ 1235static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1236{ 1237 s32 ret_val = E1000_SUCCESS; 1238 u16 speed; 1239 u16 duplex; 1240 1241 DEBUGFUNC("e1000_configure_on_link_up"); 1242 1243 if (hw->phy.media_type == e1000_media_type_copper) { 1244 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, 1245 &duplex); 1246 if (ret_val) 1247 return ret_val; 1248 1249 if (speed == SPEED_1000) 1250 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1251 else 1252 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1253 } 1254 1255 return ret_val; 1256} 1257 1258/** 1259 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1260 * @hw: pointer to the HW structure 1261 * @duplex: current duplex setting 1262 * 1263 * Configure the KMRN interface by applying last minute quirks for 1264 * 10/100 operation. 1265 **/ 1266static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1267{ 1268 s32 ret_val; 1269 u32 tipg; 1270 u32 i = 0; 1271 u16 reg_data, reg_data2; 1272 1273 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1274 1275 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1276 ret_val = 1277 e1000_write_kmrn_reg_80003es2lan(hw, 1278 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1279 reg_data); 1280 if (ret_val) 1281 return ret_val; 1282 1283 /* Configure Transmit Inter-Packet Gap */ 1284 tipg = E1000_READ_REG(hw, E1000_TIPG); 1285 tipg &= ~E1000_TIPG_IPGT_MASK; 1286 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1287 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1288 1289 do { 1290 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1291 ®_data); 1292 if (ret_val) 1293 return ret_val; 1294 1295 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1296 ®_data2); 1297 if (ret_val) 1298 return ret_val; 1299 i++; 1300 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1301 1302 if (duplex == HALF_DUPLEX) 1303 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1304 else 1305 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1306 1307 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1308} 1309 1310/** 1311 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1312 * @hw: pointer to the HW structure 1313 * 1314 * Configure the KMRN interface by applying last minute quirks for 1315 * gigabit operation. 1316 **/ 1317static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1318{ 1319 s32 ret_val; 1320 u16 reg_data, reg_data2; 1321 u32 tipg; 1322 u32 i = 0; 1323 1324 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1325 1326 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1327 ret_val = 1328 e1000_write_kmrn_reg_80003es2lan(hw, 1329 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1330 reg_data); 1331 if (ret_val) 1332 return ret_val; 1333 1334 /* Configure Transmit Inter-Packet Gap */ 1335 tipg = E1000_READ_REG(hw, E1000_TIPG); 1336 tipg &= ~E1000_TIPG_IPGT_MASK; 1337 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1338 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1339 1340 do { 1341 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1342 ®_data); 1343 if (ret_val) 1344 return ret_val; 1345 1346 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1347 ®_data2); 1348 if (ret_val) 1349 return ret_val; 1350 i++; 1351 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1352 1353 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1354 1355 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1356} 1357 1358/** 1359 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1360 * @hw: pointer to the HW structure 1361 * @offset: register offset to be read 1362 * @data: pointer to the read data 1363 * 1364 * Acquire semaphore, then read the PHY register at offset 1365 * using the kumeran interface. The information retrieved is stored in data. 1366 * Release the semaphore before exiting. 1367 **/ 1368static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1369 u16 *data) 1370{ 1371 u32 kmrnctrlsta; 1372 s32 ret_val; 1373 1374 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1375 1376 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1377 if (ret_val) 1378 return ret_val; 1379 1380 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1381 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1382 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1383 E1000_WRITE_FLUSH(hw); 1384 1385 usec_delay(2); 1386 1387 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1388 *data = (u16)kmrnctrlsta; 1389 1390 e1000_release_mac_csr_80003es2lan(hw); 1391 1392 return ret_val; 1393} 1394 1395/** 1396 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1397 * @hw: pointer to the HW structure 1398 * @offset: register offset to write to 1399 * @data: data to write at register offset 1400 * 1401 * Acquire semaphore, then write the data to PHY register 1402 * at the offset using the kumeran interface. Release semaphore 1403 * before exiting. 1404 **/ 1405static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1406 u16 data) 1407{ 1408 u32 kmrnctrlsta; 1409 s32 ret_val; 1410 1411 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1412 1413 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1414 if (ret_val) 1415 return ret_val; 1416 1417 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1418 E1000_KMRNCTRLSTA_OFFSET) | data; 1419 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1420 E1000_WRITE_FLUSH(hw); 1421 1422 usec_delay(2); 1423 1424 e1000_release_mac_csr_80003es2lan(hw); 1425 1426 return ret_val; 1427} 1428 1429/** 1430 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1431 * @hw: pointer to the HW structure 1432 **/ 1433static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1434{ 1435 s32 ret_val; 1436 1437 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1438 1439 /* If there's an alternate MAC address place it in RAR0 1440 * so that it will override the Si installed default perm 1441 * address. 1442 */ 1443 ret_val = e1000_check_alt_mac_addr_generic(hw); 1444 if (ret_val) 1445 return ret_val; 1446 1447 return e1000_read_mac_addr_generic(hw); 1448} 1449 1450/** 1451 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1452 * @hw: pointer to the HW structure 1453 * 1454 * In the case of a PHY power down to save power, or to turn off link during a 1455 * driver unload, or wake on lan is not enabled, remove the link. 1456 **/ 1457static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1458{ 1459 /* If the management interface is not enabled, then power down */ 1460 if (!(hw->mac.ops.check_mng_mode(hw) || 1461 hw->phy.ops.check_reset_block(hw))) 1462 e1000_power_down_phy_copper(hw); 1463 1464 return; 1465} 1466 1467/** 1468 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1469 * @hw: pointer to the HW structure 1470 * 1471 * Clears the hardware counters by reading the counter registers. 1472 **/ 1473static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1474{ 1475 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1476 1477 e1000_clear_hw_cntrs_base_generic(hw); 1478 1479 E1000_READ_REG(hw, E1000_PRC64); 1480 E1000_READ_REG(hw, E1000_PRC127); 1481 E1000_READ_REG(hw, E1000_PRC255); 1482 E1000_READ_REG(hw, E1000_PRC511); 1483 E1000_READ_REG(hw, E1000_PRC1023); 1484 E1000_READ_REG(hw, E1000_PRC1522); 1485 E1000_READ_REG(hw, E1000_PTC64); 1486 E1000_READ_REG(hw, E1000_PTC127); 1487 E1000_READ_REG(hw, E1000_PTC255); 1488 E1000_READ_REG(hw, E1000_PTC511); 1489 E1000_READ_REG(hw, E1000_PTC1023); 1490 E1000_READ_REG(hw, E1000_PTC1522); 1491 1492 E1000_READ_REG(hw, E1000_ALGNERRC); 1493 E1000_READ_REG(hw, E1000_RXERRC); 1494 E1000_READ_REG(hw, E1000_TNCRS); 1495 E1000_READ_REG(hw, E1000_CEXTERR); 1496 E1000_READ_REG(hw, E1000_TSCTC); 1497 E1000_READ_REG(hw, E1000_TSCTFC); 1498 1499 E1000_READ_REG(hw, E1000_MGTPRC); 1500 E1000_READ_REG(hw, E1000_MGTPDC); 1501 E1000_READ_REG(hw, E1000_MGTPTC); 1502 1503 E1000_READ_REG(hw, E1000_IAC); 1504 E1000_READ_REG(hw, E1000_ICRXOC); 1505 1506 E1000_READ_REG(hw, E1000_ICRXPTC); 1507 E1000_READ_REG(hw, E1000_ICRXATC); 1508 E1000_READ_REG(hw, E1000_ICTXPTC); 1509 E1000_READ_REG(hw, E1000_ICTXATC); 1510 E1000_READ_REG(hw, E1000_ICTXQEC); 1511 E1000_READ_REG(hw, E1000_ICTXQMTC); 1512 E1000_READ_REG(hw, E1000_ICRXDMTC); 1513} 1514