e1000_80003es2lan.c revision 228386
1/****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 228386 2011-12-10 06:55:02Z jfv $*/ 34 35/* 36 * 80003ES2LAN Gigabit Ethernet Controller (Copper) 37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 38 */ 39 40#include "e1000_api.h" 41 42static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 43static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 44static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 45static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 46static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 47static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 48static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 49static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 50 u32 offset, 51 u16 *data); 52static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 53 u32 offset, 54 u16 data); 55static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 56 u16 words, u16 *data); 57static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 58static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 59static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 60static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 61 u16 *duplex); 62static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 63static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 64static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 65static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 66static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 67static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 68static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 69static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 70static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 71 u16 *data); 72static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 73 u16 data); 74static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 75static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 76static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 77static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 78static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 79 80/* 81 * A table for the GG82563 cable length where the range is defined 82 * with a lower bound at "index" and the upper bound at 83 * "index + 5". 84 */ 85static const u16 e1000_gg82563_cable_length_table[] = { 86 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 87#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 88 (sizeof(e1000_gg82563_cable_length_table) / \ 89 sizeof(e1000_gg82563_cable_length_table[0])) 90 91/** 92 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 93 * @hw: pointer to the HW structure 94 **/ 95static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 96{ 97 struct e1000_phy_info *phy = &hw->phy; 98 s32 ret_val = E1000_SUCCESS; 99 100 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 101 102 if (hw->phy.media_type != e1000_media_type_copper) { 103 phy->type = e1000_phy_none; 104 goto out; 105 } else { 106 phy->ops.power_up = e1000_power_up_phy_copper; 107 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 108 } 109 110 phy->addr = 1; 111 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 112 phy->reset_delay_us = 100; 113 phy->type = e1000_phy_gg82563; 114 115 phy->ops.acquire = e1000_acquire_phy_80003es2lan; 116 phy->ops.check_polarity = e1000_check_polarity_m88; 117 phy->ops.check_reset_block = e1000_check_reset_block_generic; 118 phy->ops.commit = e1000_phy_sw_reset_generic; 119 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 120 phy->ops.get_info = e1000_get_phy_info_m88; 121 phy->ops.release = e1000_release_phy_80003es2lan; 122 phy->ops.reset = e1000_phy_hw_reset_generic; 123 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 124 125 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 126 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 127 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 128 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 129 130 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 131 132 /* This can only be done after all function pointers are setup. */ 133 ret_val = e1000_get_phy_id(hw); 134 135 /* Verify phy id */ 136 if (phy->id != GG82563_E_PHY_ID) { 137 ret_val = -E1000_ERR_PHY; 138 goto out; 139 } 140 141out: 142 return ret_val; 143} 144 145/** 146 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 147 * @hw: pointer to the HW structure 148 **/ 149static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 150{ 151 struct e1000_nvm_info *nvm = &hw->nvm; 152 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 153 u16 size; 154 155 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 156 157 nvm->opcode_bits = 8; 158 nvm->delay_usec = 1; 159 switch (nvm->override) { 160 case e1000_nvm_override_spi_large: 161 nvm->page_size = 32; 162 nvm->address_bits = 16; 163 break; 164 case e1000_nvm_override_spi_small: 165 nvm->page_size = 8; 166 nvm->address_bits = 8; 167 break; 168 default: 169 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 170 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 171 break; 172 } 173 174 nvm->type = e1000_nvm_eeprom_spi; 175 176 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 177 E1000_EECD_SIZE_EX_SHIFT); 178 179 /* 180 * Added to a constant, "size" becomes the left-shift value 181 * for setting word_size. 182 */ 183 size += NVM_WORD_SIZE_BASE_SHIFT; 184 185 /* EEPROM access above 16k is unsupported */ 186 if (size > 14) 187 size = 14; 188 nvm->word_size = 1 << size; 189 190 /* Function Pointers */ 191 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 192 nvm->ops.read = e1000_read_nvm_eerd; 193 nvm->ops.release = e1000_release_nvm_80003es2lan; 194 nvm->ops.update = e1000_update_nvm_checksum_generic; 195 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 196 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 197 nvm->ops.write = e1000_write_nvm_80003es2lan; 198 199 return E1000_SUCCESS; 200} 201 202/** 203 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 204 * @hw: pointer to the HW structure 205 **/ 206static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 207{ 208 struct e1000_mac_info *mac = &hw->mac; 209 210 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 211 212 /* Set media type and media-dependent function pointers */ 213 switch (hw->device_id) { 214 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 215 hw->phy.media_type = e1000_media_type_internal_serdes; 216 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 217 mac->ops.setup_physical_interface = 218 e1000_setup_fiber_serdes_link_generic; 219 break; 220 default: 221 hw->phy.media_type = e1000_media_type_copper; 222 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 223 mac->ops.setup_physical_interface = 224 e1000_setup_copper_link_80003es2lan; 225 break; 226 } 227 228 /* Set mta register count */ 229 mac->mta_reg_count = 128; 230 /* Set rar entry count */ 231 mac->rar_entry_count = E1000_RAR_ENTRIES; 232 /* Set if part includes ASF firmware */ 233 mac->asf_firmware_present = TRUE; 234 /* FWSM register */ 235 mac->has_fwsm = TRUE; 236 /* ARC supported; valid only if manageability features are enabled. */ 237 mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) & 238 E1000_FWSM_MODE_MASK) ? TRUE : FALSE; 239 /* Adaptive IFS not supported */ 240 mac->adaptive_ifs = FALSE; 241 242 /* Function pointers */ 243 244 /* bus type/speed/width */ 245 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 246 /* reset */ 247 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 248 /* hw initialization */ 249 mac->ops.init_hw = e1000_init_hw_80003es2lan; 250 /* link setup */ 251 mac->ops.setup_link = e1000_setup_link_generic; 252 /* check management mode */ 253 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 254 /* multicast address update */ 255 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 256 /* writing VFTA */ 257 mac->ops.write_vfta = e1000_write_vfta_generic; 258 /* clearing VFTA */ 259 mac->ops.clear_vfta = e1000_clear_vfta_generic; 260 /* read mac address */ 261 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 262 /* ID LED init */ 263 mac->ops.id_led_init = e1000_id_led_init_generic; 264 /* blink LED */ 265 mac->ops.blink_led = e1000_blink_led_generic; 266 /* setup LED */ 267 mac->ops.setup_led = e1000_setup_led_generic; 268 /* cleanup LED */ 269 mac->ops.cleanup_led = e1000_cleanup_led_generic; 270 /* turn on/off LED */ 271 mac->ops.led_on = e1000_led_on_generic; 272 mac->ops.led_off = e1000_led_off_generic; 273 /* clear hardware counters */ 274 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 275 /* link info */ 276 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 277 278 /* set lan id for port to determine which phy lock to use */ 279 hw->mac.ops.set_lan_id(hw); 280 281 return E1000_SUCCESS; 282} 283 284/** 285 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 286 * @hw: pointer to the HW structure 287 * 288 * Called to initialize all function pointers and parameters. 289 **/ 290void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 291{ 292 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 293 294 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 295 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 296 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 297} 298 299/** 300 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 301 * @hw: pointer to the HW structure 302 * 303 * A wrapper to acquire access rights to the correct PHY. 304 **/ 305static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 306{ 307 u16 mask; 308 309 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 310 311 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 312 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 313} 314 315/** 316 * e1000_release_phy_80003es2lan - Release rights to access PHY 317 * @hw: pointer to the HW structure 318 * 319 * A wrapper to release access rights to the correct PHY. 320 **/ 321static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 322{ 323 u16 mask; 324 325 DEBUGFUNC("e1000_release_phy_80003es2lan"); 326 327 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 328 e1000_release_swfw_sync_80003es2lan(hw, mask); 329} 330 331/** 332 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 333 * @hw: pointer to the HW structure 334 * 335 * Acquire the semaphore to access the Kumeran interface. 336 * 337 **/ 338static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 339{ 340 u16 mask; 341 342 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 343 344 mask = E1000_SWFW_CSR_SM; 345 346 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 347} 348 349/** 350 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 351 * @hw: pointer to the HW structure 352 * 353 * Release the semaphore used to access the Kumeran interface 354 **/ 355static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 356{ 357 u16 mask; 358 359 DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 360 361 mask = E1000_SWFW_CSR_SM; 362 363 e1000_release_swfw_sync_80003es2lan(hw, mask); 364} 365 366/** 367 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 368 * @hw: pointer to the HW structure 369 * 370 * Acquire the semaphore to access the EEPROM. 371 **/ 372static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 373{ 374 s32 ret_val; 375 376 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 377 378 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 379 if (ret_val) 380 goto out; 381 382 ret_val = e1000_acquire_nvm_generic(hw); 383 384 if (ret_val) 385 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 386 387out: 388 return ret_val; 389} 390 391/** 392 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 393 * @hw: pointer to the HW structure 394 * 395 * Release the semaphore used to access the EEPROM. 396 **/ 397static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 398{ 399 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 400 401 e1000_release_nvm_generic(hw); 402 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 403} 404 405/** 406 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 407 * @hw: pointer to the HW structure 408 * @mask: specifies which semaphore to acquire 409 * 410 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 411 * will also specify which port we're acquiring the lock for. 412 **/ 413static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 414{ 415 u32 swfw_sync; 416 u32 swmask = mask; 417 u32 fwmask = mask << 16; 418 s32 ret_val = E1000_SUCCESS; 419 s32 i = 0, timeout = 50; 420 421 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 422 423 while (i < timeout) { 424 if (e1000_get_hw_semaphore_generic(hw)) { 425 ret_val = -E1000_ERR_SWFW_SYNC; 426 goto out; 427 } 428 429 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 430 if (!(swfw_sync & (fwmask | swmask))) 431 break; 432 433 /* 434 * Firmware currently using resource (fwmask) 435 * or other software thread using resource (swmask) 436 */ 437 e1000_put_hw_semaphore_generic(hw); 438 msec_delay_irq(5); 439 i++; 440 } 441 442 if (i == timeout) { 443 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 444 ret_val = -E1000_ERR_SWFW_SYNC; 445 goto out; 446 } 447 448 swfw_sync |= swmask; 449 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 450 451 e1000_put_hw_semaphore_generic(hw); 452 453out: 454 return ret_val; 455} 456 457/** 458 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 459 * @hw: pointer to the HW structure 460 * @mask: specifies which semaphore to acquire 461 * 462 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 463 * will also specify which port we're releasing the lock for. 464 **/ 465static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 466{ 467 u32 swfw_sync; 468 469 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 470 471 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 472 ; /* Empty */ 473 474 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 475 swfw_sync &= ~mask; 476 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 477 478 e1000_put_hw_semaphore_generic(hw); 479} 480 481/** 482 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 483 * @hw: pointer to the HW structure 484 * @offset: offset of the register to read 485 * @data: pointer to the data returned from the operation 486 * 487 * Read the GG82563 PHY register. 488 **/ 489static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 490 u32 offset, u16 *data) 491{ 492 s32 ret_val; 493 u32 page_select; 494 u16 temp; 495 496 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 497 498 ret_val = e1000_acquire_phy_80003es2lan(hw); 499 if (ret_val) 500 goto out; 501 502 /* Select Configuration Page */ 503 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 504 page_select = GG82563_PHY_PAGE_SELECT; 505 } else { 506 /* 507 * Use Alternative Page Select register to access 508 * registers 30 and 31 509 */ 510 page_select = GG82563_PHY_PAGE_SELECT_ALT; 511 } 512 513 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 514 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 515 if (ret_val) { 516 e1000_release_phy_80003es2lan(hw); 517 goto out; 518 } 519 520 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) { 521 /* 522 * The "ready" bit in the MDIC register may be incorrectly set 523 * before the device has completed the "Page Select" MDI 524 * transaction. So we wait 200us after each MDI command... 525 */ 526 usec_delay(200); 527 528 /* ...and verify the command was successful. */ 529 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 530 531 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 532 ret_val = -E1000_ERR_PHY; 533 e1000_release_phy_80003es2lan(hw); 534 goto out; 535 } 536 537 usec_delay(200); 538 539 ret_val = e1000_read_phy_reg_mdic(hw, 540 MAX_PHY_REG_ADDRESS & offset, 541 data); 542 543 usec_delay(200); 544 } else { 545 ret_val = e1000_read_phy_reg_mdic(hw, 546 MAX_PHY_REG_ADDRESS & offset, 547 data); 548 } 549 550 e1000_release_phy_80003es2lan(hw); 551 552out: 553 return ret_val; 554} 555 556/** 557 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 558 * @hw: pointer to the HW structure 559 * @offset: offset of the register to read 560 * @data: value to write to the register 561 * 562 * Write to the GG82563 PHY register. 563 **/ 564static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 565 u32 offset, u16 data) 566{ 567 s32 ret_val; 568 u32 page_select; 569 u16 temp; 570 571 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 572 573 ret_val = e1000_acquire_phy_80003es2lan(hw); 574 if (ret_val) 575 goto out; 576 577 /* Select Configuration Page */ 578 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 579 page_select = GG82563_PHY_PAGE_SELECT; 580 } else { 581 /* 582 * Use Alternative Page Select register to access 583 * registers 30 and 31 584 */ 585 page_select = GG82563_PHY_PAGE_SELECT_ALT; 586 } 587 588 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 589 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 590 if (ret_val) { 591 e1000_release_phy_80003es2lan(hw); 592 goto out; 593 } 594 595 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) { 596 /* 597 * The "ready" bit in the MDIC register may be incorrectly set 598 * before the device has completed the "Page Select" MDI 599 * transaction. So we wait 200us after each MDI command... 600 */ 601 usec_delay(200); 602 603 /* ...and verify the command was successful. */ 604 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 605 606 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 607 ret_val = -E1000_ERR_PHY; 608 e1000_release_phy_80003es2lan(hw); 609 goto out; 610 } 611 612 usec_delay(200); 613 614 ret_val = e1000_write_phy_reg_mdic(hw, 615 MAX_PHY_REG_ADDRESS & offset, 616 data); 617 618 usec_delay(200); 619 } else { 620 ret_val = e1000_write_phy_reg_mdic(hw, 621 MAX_PHY_REG_ADDRESS & offset, 622 data); 623 } 624 625 e1000_release_phy_80003es2lan(hw); 626 627out: 628 return ret_val; 629} 630 631/** 632 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 633 * @hw: pointer to the HW structure 634 * @offset: offset of the register to read 635 * @words: number of words to write 636 * @data: buffer of data to write to the NVM 637 * 638 * Write "words" of data to the ESB2 NVM. 639 **/ 640static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 641 u16 words, u16 *data) 642{ 643 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 644 645 return e1000_write_nvm_spi(hw, offset, words, data); 646} 647 648/** 649 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 650 * @hw: pointer to the HW structure 651 * 652 * Wait a specific amount of time for manageability processes to complete. 653 * This is a function pointer entry point called by the phy module. 654 **/ 655static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 656{ 657 s32 timeout = PHY_CFG_TIMEOUT; 658 s32 ret_val = E1000_SUCCESS; 659 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 660 661 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 662 663 if (hw->bus.func == 1) 664 mask = E1000_NVM_CFG_DONE_PORT_1; 665 666 while (timeout) { 667 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 668 break; 669 msec_delay(1); 670 timeout--; 671 } 672 if (!timeout) { 673 DEBUGOUT("MNG configuration cycle has not completed.\n"); 674 ret_val = -E1000_ERR_RESET; 675 goto out; 676 } 677 678out: 679 return ret_val; 680} 681 682/** 683 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 684 * @hw: pointer to the HW structure 685 * 686 * Force the speed and duplex settings onto the PHY. This is a 687 * function pointer entry point called by the phy module. 688 **/ 689static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 690{ 691 s32 ret_val = E1000_SUCCESS; 692 u16 phy_data; 693 bool link; 694 695 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 696 697 if (!(hw->phy.ops.read_reg)) 698 goto out; 699 700 /* 701 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 702 * forced whenever speed and duplex are forced. 703 */ 704 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 705 if (ret_val) 706 goto out; 707 708 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 709 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 710 if (ret_val) 711 goto out; 712 713 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 714 715 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 716 if (ret_val) 717 goto out; 718 719 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 720 721 /* Reset the phy to commit changes. */ 722 phy_data |= MII_CR_RESET; 723 724 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 725 if (ret_val) 726 goto out; 727 728 usec_delay(1); 729 730 if (hw->phy.autoneg_wait_to_complete) { 731 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); 732 733 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 734 100000, &link); 735 if (ret_val) 736 goto out; 737 738 if (!link) { 739 /* 740 * We didn't get link. 741 * Reset the DSP and cross our fingers. 742 */ 743 ret_val = e1000_phy_reset_dsp_generic(hw); 744 if (ret_val) 745 goto out; 746 } 747 748 /* Try once more */ 749 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 750 100000, &link); 751 if (ret_val) 752 goto out; 753 } 754 755 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 756 &phy_data); 757 if (ret_val) 758 goto out; 759 760 /* 761 * Resetting the phy means we need to verify the TX_CLK corresponds 762 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 763 */ 764 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 765 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 766 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 767 else 768 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 769 770 /* 771 * In addition, we must re-enable CRS on Tx for both half and full 772 * duplex. 773 */ 774 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 775 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 776 phy_data); 777 778out: 779 return ret_val; 780} 781 782/** 783 * e1000_get_cable_length_80003es2lan - Set approximate cable length 784 * @hw: pointer to the HW structure 785 * 786 * Find the approximate cable length as measured by the GG82563 PHY. 787 * This is a function pointer entry point called by the phy module. 788 **/ 789static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 790{ 791 struct e1000_phy_info *phy = &hw->phy; 792 s32 ret_val = E1000_SUCCESS; 793 u16 phy_data, index; 794 795 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 796 797 if (!(hw->phy.ops.read_reg)) 798 goto out; 799 800 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 801 if (ret_val) 802 goto out; 803 804 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 805 806 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) { 807 ret_val = -E1000_ERR_PHY; 808 goto out; 809 } 810 811 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 812 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 813 814 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 815 816out: 817 return ret_val; 818} 819 820/** 821 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 822 * @hw: pointer to the HW structure 823 * @speed: pointer to speed buffer 824 * @duplex: pointer to duplex buffer 825 * 826 * Retrieve the current speed and duplex configuration. 827 **/ 828static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 829 u16 *duplex) 830{ 831 s32 ret_val; 832 833 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 834 835 if (hw->phy.media_type == e1000_media_type_copper) { 836 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 837 duplex); 838 hw->phy.ops.cfg_on_link_up(hw); 839 } else { 840 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 841 speed, 842 duplex); 843 } 844 845 return ret_val; 846} 847 848/** 849 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 850 * @hw: pointer to the HW structure 851 * 852 * Perform a global reset to the ESB2 controller. 853 **/ 854static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 855{ 856 u32 ctrl; 857 s32 ret_val; 858 859 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 860 861 /* 862 * Prevent the PCI-E bus from sticking if there is no TLP connection 863 * on the last TLP read/write transaction when MAC is reset. 864 */ 865 ret_val = e1000_disable_pcie_master_generic(hw); 866 if (ret_val) 867 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 868 869 DEBUGOUT("Masking off all interrupts\n"); 870 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 871 872 E1000_WRITE_REG(hw, E1000_RCTL, 0); 873 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 874 E1000_WRITE_FLUSH(hw); 875 876 msec_delay(10); 877 878 ctrl = E1000_READ_REG(hw, E1000_CTRL); 879 880 ret_val = e1000_acquire_phy_80003es2lan(hw); 881 DEBUGOUT("Issuing a global reset to MAC\n"); 882 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 883 e1000_release_phy_80003es2lan(hw); 884 885 ret_val = e1000_get_auto_rd_done_generic(hw); 886 if (ret_val) 887 /* We don't want to continue accessing MAC registers. */ 888 goto out; 889 890 /* Clear any pending interrupt events. */ 891 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 892 E1000_READ_REG(hw, E1000_ICR); 893 894 ret_val = e1000_check_alt_mac_addr_generic(hw); 895 896out: 897 return ret_val; 898} 899 900/** 901 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 902 * @hw: pointer to the HW structure 903 * 904 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 905 **/ 906static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 907{ 908 struct e1000_mac_info *mac = &hw->mac; 909 u32 reg_data; 910 s32 ret_val; 911 u16 kum_reg_data; 912 u16 i; 913 914 DEBUGFUNC("e1000_init_hw_80003es2lan"); 915 916 e1000_initialize_hw_bits_80003es2lan(hw); 917 918 /* Initialize identification LED */ 919 ret_val = mac->ops.id_led_init(hw); 920 if (ret_val) 921 DEBUGOUT("Error initializing identification LED\n"); 922 /* This is not fatal and we should not stop init due to this */ 923 924 /* Disabling VLAN filtering */ 925 DEBUGOUT("Initializing the IEEE VLAN\n"); 926 mac->ops.clear_vfta(hw); 927 928 /* Setup the receive address. */ 929 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 930 931 /* Zero out the Multicast HASH table */ 932 DEBUGOUT("Zeroing the MTA\n"); 933 for (i = 0; i < mac->mta_reg_count; i++) 934 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 935 936 /* Setup link and flow control */ 937 ret_val = mac->ops.setup_link(hw); 938 939 /* Disable IBIST slave mode (far-end loopback) */ 940 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 941 &kum_reg_data); 942 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 943 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 944 kum_reg_data); 945 946 /* Set the transmit descriptor write-back policy */ 947 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 948 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 949 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 950 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 951 952 /* ...for both queues. */ 953 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 954 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 955 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 956 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 957 958 /* Enable retransmit on late collisions */ 959 reg_data = E1000_READ_REG(hw, E1000_TCTL); 960 reg_data |= E1000_TCTL_RTLC; 961 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 962 963 /* Configure Gigabit Carry Extend Padding */ 964 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 965 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 966 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 967 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 968 969 /* Configure Transmit Inter-Packet Gap */ 970 reg_data = E1000_READ_REG(hw, E1000_TIPG); 971 reg_data &= ~E1000_TIPG_IPGT_MASK; 972 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 973 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 974 975 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 976 reg_data &= ~0x00100000; 977 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 978 979 /* default to TRUE to enable the MDIC W/A */ 980 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; 981 982 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 983 E1000_KMRNCTRLSTA_OFFSET >> 984 E1000_KMRNCTRLSTA_OFFSET_SHIFT, 985 &i); 986 if (!ret_val) { 987 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 988 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 989 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE; 990 } 991 992 /* 993 * Clear all of the statistics registers (clear on read). It is 994 * important that we do this after we have tried to establish link 995 * because the symbol error count will increment wildly if there 996 * is no link. 997 */ 998 e1000_clear_hw_cntrs_80003es2lan(hw); 999 1000 return ret_val; 1001} 1002 1003/** 1004 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 1005 * @hw: pointer to the HW structure 1006 * 1007 * Initializes required hardware-dependent bits needed for normal operation. 1008 **/ 1009static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 1010{ 1011 u32 reg; 1012 1013 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 1014 1015 /* Transmit Descriptor Control 0 */ 1016 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1017 reg |= (1 << 22); 1018 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1019 1020 /* Transmit Descriptor Control 1 */ 1021 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1022 reg |= (1 << 22); 1023 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1024 1025 /* Transmit Arbitration Control 0 */ 1026 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1027 reg &= ~(0xF << 27); /* 30:27 */ 1028 if (hw->phy.media_type != e1000_media_type_copper) 1029 reg &= ~(1 << 20); 1030 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1031 1032 /* Transmit Arbitration Control 1 */ 1033 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1034 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1035 reg &= ~(1 << 28); 1036 else 1037 reg |= (1 << 28); 1038 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1039 1040 return; 1041} 1042 1043/** 1044 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1045 * @hw: pointer to the HW structure 1046 * 1047 * Setup some GG82563 PHY registers for obtaining link 1048 **/ 1049static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1050{ 1051 struct e1000_phy_info *phy = &hw->phy; 1052 s32 ret_val; 1053 u32 ctrl_ext; 1054 u16 data; 1055 1056 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1057 1058 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 1059 if (ret_val) 1060 goto out; 1061 1062 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1063 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1064 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1065 1066 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 1067 if (ret_val) 1068 goto out; 1069 1070 /* 1071 * Options: 1072 * MDI/MDI-X = 0 (default) 1073 * 0 - Auto for all speeds 1074 * 1 - MDI mode 1075 * 2 - MDI-X mode 1076 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1077 */ 1078 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1079 if (ret_val) 1080 goto out; 1081 1082 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1083 1084 switch (phy->mdix) { 1085 case 1: 1086 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1087 break; 1088 case 2: 1089 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1090 break; 1091 case 0: 1092 default: 1093 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1094 break; 1095 } 1096 1097 /* 1098 * Options: 1099 * disable_polarity_correction = 0 (default) 1100 * Automatic Correction for Reversed Cable Polarity 1101 * 0 - Disabled 1102 * 1 - Enabled 1103 */ 1104 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1105 if (phy->disable_polarity_correction) 1106 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1107 1108 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1109 if (ret_val) 1110 goto out; 1111 1112 /* SW Reset the PHY so all changes take effect */ 1113 ret_val = hw->phy.ops.commit(hw); 1114 if (ret_val) { 1115 DEBUGOUT("Error Resetting the PHY\n"); 1116 goto out; 1117 } 1118 1119 /* Bypass Rx and Tx FIFO's */ 1120 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1121 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1122 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1123 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1124 if (ret_val) 1125 goto out; 1126 1127 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1128 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data); 1129 if (ret_val) 1130 goto out; 1131 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1132 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1133 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data); 1134 if (ret_val) 1135 goto out; 1136 1137 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1138 if (ret_val) 1139 goto out; 1140 1141 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1142 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1143 if (ret_val) 1144 goto out; 1145 1146 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1147 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1148 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1149 1150 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1151 if (ret_val) 1152 goto out; 1153 1154 /* 1155 * Do not init these registers when the HW is in IAMT mode, since the 1156 * firmware will have already initialized them. We only initialize 1157 * them if the HW is not in IAMT mode. 1158 */ 1159 if (!(hw->mac.ops.check_mng_mode(hw))) { 1160 /* Enable Electrical Idle on the PHY */ 1161 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1162 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1163 data); 1164 if (ret_val) 1165 goto out; 1166 1167 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1168 &data); 1169 if (ret_val) 1170 goto out; 1171 1172 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1173 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1174 data); 1175 if (ret_val) 1176 goto out; 1177 } 1178 1179 /* 1180 * Workaround: Disable padding in Kumeran interface in the MAC 1181 * and in the PHY to avoid CRC errors. 1182 */ 1183 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1184 if (ret_val) 1185 goto out; 1186 1187 data |= GG82563_ICR_DIS_PADDING; 1188 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1189 if (ret_val) 1190 goto out; 1191 1192out: 1193 return ret_val; 1194} 1195 1196/** 1197 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1198 * @hw: pointer to the HW structure 1199 * 1200 * Essentially a wrapper for setting up all things "copper" related. 1201 * This is a function pointer entry point called by the mac module. 1202 **/ 1203static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1204{ 1205 u32 ctrl; 1206 s32 ret_val; 1207 u16 reg_data; 1208 1209 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1210 1211 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1212 ctrl |= E1000_CTRL_SLU; 1213 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1214 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1215 1216 /* 1217 * Set the mac to wait the maximum time between each 1218 * iteration and increase the max iterations when 1219 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1220 */ 1221 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1222 0xFFFF); 1223 if (ret_val) 1224 goto out; 1225 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1226 ®_data); 1227 if (ret_val) 1228 goto out; 1229 reg_data |= 0x3F; 1230 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1231 reg_data); 1232 if (ret_val) 1233 goto out; 1234 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1235 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ®_data); 1236 if (ret_val) 1237 goto out; 1238 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1239 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1240 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data); 1241 if (ret_val) 1242 goto out; 1243 1244 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1245 if (ret_val) 1246 goto out; 1247 1248 ret_val = e1000_setup_copper_link_generic(hw); 1249 1250out: 1251 return ret_val; 1252} 1253 1254/** 1255 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1256 * @hw: pointer to the HW structure 1257 * @duplex: current duplex setting 1258 * 1259 * Configure the KMRN interface by applying last minute quirks for 1260 * 10/100 operation. 1261 **/ 1262static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1263{ 1264 s32 ret_val = E1000_SUCCESS; 1265 u16 speed; 1266 u16 duplex; 1267 1268 DEBUGFUNC("e1000_configure_on_link_up"); 1269 1270 if (hw->phy.media_type == e1000_media_type_copper) { 1271 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, 1272 &duplex); 1273 if (ret_val) 1274 goto out; 1275 1276 if (speed == SPEED_1000) 1277 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1278 else 1279 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1280 } 1281 1282out: 1283 return ret_val; 1284} 1285 1286/** 1287 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1288 * @hw: pointer to the HW structure 1289 * @duplex: current duplex setting 1290 * 1291 * Configure the KMRN interface by applying last minute quirks for 1292 * 10/100 operation. 1293 **/ 1294static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1295{ 1296 s32 ret_val = E1000_SUCCESS; 1297 u32 tipg; 1298 u32 i = 0; 1299 u16 reg_data, reg_data2; 1300 1301 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1302 1303 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1304 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1305 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1306 reg_data); 1307 if (ret_val) 1308 goto out; 1309 1310 /* Configure Transmit Inter-Packet Gap */ 1311 tipg = E1000_READ_REG(hw, E1000_TIPG); 1312 tipg &= ~E1000_TIPG_IPGT_MASK; 1313 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1314 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1315 1316 do { 1317 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1318 ®_data); 1319 if (ret_val) 1320 goto out; 1321 1322 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1323 ®_data2); 1324 if (ret_val) 1325 goto out; 1326 i++; 1327 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1328 1329 if (duplex == HALF_DUPLEX) 1330 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1331 else 1332 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1333 1334 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1335 reg_data); 1336 1337out: 1338 return ret_val; 1339} 1340 1341/** 1342 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1343 * @hw: pointer to the HW structure 1344 * 1345 * Configure the KMRN interface by applying last minute quirks for 1346 * gigabit operation. 1347 **/ 1348static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1349{ 1350 s32 ret_val = E1000_SUCCESS; 1351 u16 reg_data, reg_data2; 1352 u32 tipg; 1353 u32 i = 0; 1354 1355 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1356 1357 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1358 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1359 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data); 1360 if (ret_val) 1361 goto out; 1362 1363 /* Configure Transmit Inter-Packet Gap */ 1364 tipg = E1000_READ_REG(hw, E1000_TIPG); 1365 tipg &= ~E1000_TIPG_IPGT_MASK; 1366 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1367 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1368 1369 do { 1370 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1371 ®_data); 1372 if (ret_val) 1373 goto out; 1374 1375 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1376 ®_data2); 1377 if (ret_val) 1378 goto out; 1379 i++; 1380 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1381 1382 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1383 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1384 reg_data); 1385 1386out: 1387 return ret_val; 1388} 1389 1390/** 1391 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1392 * @hw: pointer to the HW structure 1393 * @offset: register offset to be read 1394 * @data: pointer to the read data 1395 * 1396 * Acquire semaphore, then read the PHY register at offset 1397 * using the kumeran interface. The information retrieved is stored in data. 1398 * Release the semaphore before exiting. 1399 **/ 1400static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1401 u16 *data) 1402{ 1403 u32 kmrnctrlsta; 1404 s32 ret_val = E1000_SUCCESS; 1405 1406 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1407 1408 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1409 if (ret_val) 1410 goto out; 1411 1412 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1413 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1414 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1415 E1000_WRITE_FLUSH(hw); 1416 1417 usec_delay(2); 1418 1419 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1420 *data = (u16)kmrnctrlsta; 1421 1422 e1000_release_mac_csr_80003es2lan(hw); 1423 1424out: 1425 return ret_val; 1426} 1427 1428/** 1429 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1430 * @hw: pointer to the HW structure 1431 * @offset: register offset to write to 1432 * @data: data to write at register offset 1433 * 1434 * Acquire semaphore, then write the data to PHY register 1435 * at the offset using the kumeran interface. Release semaphore 1436 * before exiting. 1437 **/ 1438static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1439 u16 data) 1440{ 1441 u32 kmrnctrlsta; 1442 s32 ret_val = E1000_SUCCESS; 1443 1444 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1445 1446 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1447 if (ret_val) 1448 goto out; 1449 1450 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1451 E1000_KMRNCTRLSTA_OFFSET) | data; 1452 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1453 E1000_WRITE_FLUSH(hw); 1454 1455 usec_delay(2); 1456 1457 e1000_release_mac_csr_80003es2lan(hw); 1458 1459out: 1460 return ret_val; 1461} 1462 1463/** 1464 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1465 * @hw: pointer to the HW structure 1466 **/ 1467static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1468{ 1469 s32 ret_val = E1000_SUCCESS; 1470 1471 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1472 1473 /* 1474 * If there's an alternate MAC address place it in RAR0 1475 * so that it will override the Si installed default perm 1476 * address. 1477 */ 1478 ret_val = e1000_check_alt_mac_addr_generic(hw); 1479 if (ret_val) 1480 goto out; 1481 1482 ret_val = e1000_read_mac_addr_generic(hw); 1483 1484out: 1485 return ret_val; 1486} 1487 1488/** 1489 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1490 * @hw: pointer to the HW structure 1491 * 1492 * In the case of a PHY power down to save power, or to turn off link during a 1493 * driver unload, or wake on lan is not enabled, remove the link. 1494 **/ 1495static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1496{ 1497 /* If the management interface is not enabled, then power down */ 1498 if (!(hw->mac.ops.check_mng_mode(hw) || 1499 hw->phy.ops.check_reset_block(hw))) 1500 e1000_power_down_phy_copper(hw); 1501 1502 return; 1503} 1504 1505/** 1506 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1507 * @hw: pointer to the HW structure 1508 * 1509 * Clears the hardware counters by reading the counter registers. 1510 **/ 1511static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1512{ 1513 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1514 1515 e1000_clear_hw_cntrs_base_generic(hw); 1516 1517 E1000_READ_REG(hw, E1000_PRC64); 1518 E1000_READ_REG(hw, E1000_PRC127); 1519 E1000_READ_REG(hw, E1000_PRC255); 1520 E1000_READ_REG(hw, E1000_PRC511); 1521 E1000_READ_REG(hw, E1000_PRC1023); 1522 E1000_READ_REG(hw, E1000_PRC1522); 1523 E1000_READ_REG(hw, E1000_PTC64); 1524 E1000_READ_REG(hw, E1000_PTC127); 1525 E1000_READ_REG(hw, E1000_PTC255); 1526 E1000_READ_REG(hw, E1000_PTC511); 1527 E1000_READ_REG(hw, E1000_PTC1023); 1528 E1000_READ_REG(hw, E1000_PTC1522); 1529 1530 E1000_READ_REG(hw, E1000_ALGNERRC); 1531 E1000_READ_REG(hw, E1000_RXERRC); 1532 E1000_READ_REG(hw, E1000_TNCRS); 1533 E1000_READ_REG(hw, E1000_CEXTERR); 1534 E1000_READ_REG(hw, E1000_TSCTC); 1535 E1000_READ_REG(hw, E1000_TSCTFC); 1536 1537 E1000_READ_REG(hw, E1000_MGTPRC); 1538 E1000_READ_REG(hw, E1000_MGTPDC); 1539 E1000_READ_REG(hw, E1000_MGTPTC); 1540 1541 E1000_READ_REG(hw, E1000_IAC); 1542 E1000_READ_REG(hw, E1000_ICRXOC); 1543 1544 E1000_READ_REG(hw, E1000_ICRXPTC); 1545 E1000_READ_REG(hw, E1000_ICRXATC); 1546 E1000_READ_REG(hw, E1000_ICTXPTC); 1547 E1000_READ_REG(hw, E1000_ICTXATC); 1548 E1000_READ_REG(hw, E1000_ICTXQEC); 1549 E1000_READ_REG(hw, E1000_ICTXQMTC); 1550 E1000_READ_REG(hw, E1000_ICRXDMTC); 1551} 1552