e1000_80003es2lan.c revision 169240
1/******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33$FreeBSD: head/sys/dev/em/e1000_80003es2lan.c 169240 2007-05-04 00:00:12Z jfv $ 34 35/* e1000_80003es2lan 36 */ 37 38#include "e1000_80003es2lan.h" 39 40void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw); 41 42STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 43STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 44STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 45STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 46STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 47STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 48STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 49STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 50 u32 offset, 51 u16 *data); 52STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 53 u32 offset, 54 u16 data); 55STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 56 u16 words, u16 *data); 57STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 58STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 59STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 60STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 61 u16 *duplex); 62STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 63STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 64STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 65STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 66static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 67static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 68static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 69static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 70static s32 e1000_get_hw_semaphore_80003es2lan(struct e1000_hw *hw); 71static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 72static void e1000_put_hw_semaphore_80003es2lan(struct e1000_hw *hw); 73static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 74 75/* A table for the GG82563 cable length where the range is defined 76 * with a lower bound at "index" and the upper bound at 77 * "index + 5". 78 */ 79static const 80u16 e1000_gg82563_cable_length_table[] = 81 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 82#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 83 (sizeof(e1000_gg82563_cable_length_table) / \ 84 sizeof(e1000_gg82563_cable_length_table[0])) 85 86/** 87 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 88 * @hw - pointer to the HW structure 89 * 90 * This is a function pointer entry point called by the api module. 91 **/ 92STATIC s32 93e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 94{ 95 struct e1000_phy_info *phy = &hw->phy; 96 struct e1000_functions *func = &hw->func; 97 s32 ret_val = E1000_SUCCESS; 98 99 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 100 101 if (hw->media_type != e1000_media_type_copper) { 102 phy->type = e1000_phy_none; 103 goto out; 104 } 105 106 phy->addr = 1; 107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 108 phy->reset_delay_us = 100; 109 phy->type = e1000_phy_gg82563; 110 111 func->acquire_phy = e1000_acquire_phy_80003es2lan; 112 func->check_polarity = e1000_check_polarity_m88; 113 func->check_reset_block = e1000_check_reset_block_generic; 114 func->commit_phy = e1000_phy_sw_reset_generic; 115 func->get_cfg_done = e1000_get_cfg_done_80003es2lan; 116 func->get_phy_info = e1000_get_phy_info_m88; 117 func->release_phy = e1000_release_phy_80003es2lan; 118 func->reset_phy = e1000_phy_hw_reset_generic; 119 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 120 121 func->force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 122 func->get_cable_length = e1000_get_cable_length_80003es2lan; 123 func->read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan; 124 func->write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan; 125 126 /* This can only be done after all function pointers are setup. */ 127 ret_val = e1000_get_phy_id(hw); 128 129 /* Verify phy id */ 130 if (phy->id != GG82563_E_PHY_ID) { 131 ret_val = -E1000_ERR_PHY; 132 goto out; 133 } 134 135out: 136 return ret_val; 137} 138 139/** 140 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 141 * @hw - pointer to the HW structure 142 * 143 * This is a function pointer entry point called by the api module. 144 **/ 145STATIC s32 146e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 147{ 148 struct e1000_nvm_info *nvm = &hw->nvm; 149 struct e1000_functions *func = &hw->func; 150 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 151 u16 size; 152 153 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 154 155 nvm->opcode_bits = 8; 156 nvm->delay_usec = 1; 157 switch (nvm->override) { 158 case e1000_nvm_override_spi_large: 159 nvm->page_size = 32; 160 nvm->address_bits = 16; 161 break; 162 case e1000_nvm_override_spi_small: 163 nvm->page_size = 8; 164 nvm->address_bits = 8; 165 break; 166 default: 167 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 168 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 169 break; 170 } 171 172 nvm->type = e1000_nvm_eeprom_spi; 173 174 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 175 E1000_EECD_SIZE_EX_SHIFT); 176 177 /* Added to a constant, "size" becomes the left-shift value 178 * for setting word_size. 179 */ 180 size += NVM_WORD_SIZE_BASE_SHIFT; 181 nvm->word_size = 1 << size; 182 183 /* Function Pointers */ 184 func->acquire_nvm = e1000_acquire_nvm_80003es2lan; 185 func->read_nvm = e1000_read_nvm_eerd; 186 func->release_nvm = e1000_release_nvm_80003es2lan; 187 func->update_nvm = e1000_update_nvm_checksum_generic; 188 func->valid_led_default = e1000_valid_led_default_generic; 189 func->validate_nvm = e1000_validate_nvm_checksum_generic; 190 func->write_nvm = e1000_write_nvm_80003es2lan; 191 192 return E1000_SUCCESS; 193} 194 195/** 196 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 197 * @hw - pointer to the HW structure 198 * 199 * This is a function pointer entry point called by the api module. 200 **/ 201STATIC s32 202e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 203{ 204 struct e1000_mac_info *mac = &hw->mac; 205 struct e1000_functions *func = &hw->func; 206 s32 ret_val = E1000_SUCCESS; 207 208 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 209 210 /* Set media type */ 211 switch (hw->device_id) { 212 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 213 hw->media_type = e1000_media_type_internal_serdes; 214 break; 215 default: 216 hw->media_type = e1000_media_type_copper; 217 break; 218 } 219 220 /* Set mta register count */ 221 mac->mta_reg_count = 128; 222 /* Set rar entry count */ 223 mac->rar_entry_count = E1000_RAR_ENTRIES; 224 /* Set if part includes ASF firmware */ 225 mac->asf_firmware_present = TRUE; 226 /* Set if manageability features are enabled. */ 227 mac->arc_subsystem_valid = 228 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 229 ? TRUE : FALSE; 230 231 /* Function pointers */ 232 233 /* bus type/speed/width */ 234 func->get_bus_info = e1000_get_bus_info_pcie_generic; 235 /* reset */ 236 func->reset_hw = e1000_reset_hw_80003es2lan; 237 /* hw initialization */ 238 func->init_hw = e1000_init_hw_80003es2lan; 239 /* link setup */ 240 func->setup_link = e1000_setup_link_generic; 241 /* physical interface link setup */ 242 func->setup_physical_interface = 243 (hw->media_type == e1000_media_type_copper) 244 ? e1000_setup_copper_link_80003es2lan 245 : e1000_setup_fiber_serdes_link_generic; 246 /* check for link */ 247 switch (hw->media_type) { 248 case e1000_media_type_copper: 249 func->check_for_link = e1000_check_for_copper_link_generic; 250 break; 251 case e1000_media_type_fiber: 252 func->check_for_link = e1000_check_for_fiber_link_generic; 253 break; 254 case e1000_media_type_internal_serdes: 255 func->check_for_link = e1000_check_for_serdes_link_generic; 256 break; 257 default: 258 ret_val = -E1000_ERR_CONFIG; 259 goto out; 260 break; 261 } 262 /* check management mode */ 263 func->check_mng_mode = e1000_check_mng_mode_generic; 264 /* multicast address update */ 265 func->mc_addr_list_update = e1000_mc_addr_list_update_generic; 266 /* writing VFTA */ 267 func->write_vfta = e1000_write_vfta_generic; 268 /* clearing VFTA */ 269 func->clear_vfta = e1000_clear_vfta_generic; 270 /* setting MTA */ 271 func->mta_set = e1000_mta_set_generic; 272 /* blink LED */ 273 func->blink_led = e1000_blink_led_generic; 274 /* setup LED */ 275 func->setup_led = e1000_setup_led_generic; 276 /* cleanup LED */ 277 func->cleanup_led = e1000_cleanup_led_generic; 278 /* turn on/off LED */ 279 func->led_on = e1000_led_on_generic; 280 func->led_off = e1000_led_off_generic; 281 /* remove device */ 282 func->remove_device = e1000_remove_device_generic; 283 /* clear hardware counters */ 284 func->clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 285 /* link info */ 286 func->get_link_up_info = e1000_get_link_up_info_80003es2lan; 287 288out: 289 return ret_val; 290} 291 292/** 293 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 294 * @hw - pointer to the HW structure 295 * 296 * The only function explicitly called by the api module to initialize 297 * all function pointers and parameters. 298 **/ 299void 300e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 301{ 302 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 303 304 hw->func.init_mac_params = e1000_init_mac_params_80003es2lan; 305 hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan; 306 hw->func.init_phy_params = e1000_init_phy_params_80003es2lan; 307} 308 309/** 310 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 311 * @hw - pointer to the HW structure 312 * 313 * A wrapper to acquire access rights to the correct PHY. This is a 314 * function pointer entry point called by the api module. 315 **/ 316STATIC s32 317e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 318{ 319 u16 mask; 320 321 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 322 323 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 324 325 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 326} 327 328/** 329 * e1000_release_phy_80003es2lan - Release rights to access PHY 330 * @hw - pointer to the HW structure 331 * 332 * A wrapper to release access rights to the correct PHY. This is a 333 * function pointer entry point called by the api module. 334 **/ 335STATIC void 336e1000_release_phy_80003es2lan(struct e1000_hw *hw) 337{ 338 u16 mask; 339 340 DEBUGFUNC("e1000_release_phy_80003es2lan"); 341 342 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 343 e1000_release_swfw_sync_80003es2lan(hw, mask); 344} 345 346/** 347 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 348 * @hw - pointer to the HW structure 349 * 350 * Acquire the semaphore to access the EEPROM. This is a function 351 * pointer entry point called by the api module. 352 **/ 353STATIC s32 354e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 355{ 356 s32 ret_val; 357 358 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 359 360 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 361 if (ret_val) 362 goto out; 363 364 ret_val = e1000_acquire_nvm_generic(hw); 365 366 if (ret_val) 367 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 368 369out: 370 return ret_val; 371} 372 373/** 374 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 375 * @hw - pointer to the HW structure 376 * 377 * Release the semaphore used to access the EEPROM. This is a 378 * function pointer entry point called by the api module. 379 **/ 380STATIC void 381e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 382{ 383 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 384 385 e1000_release_nvm_generic(hw); 386 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 387} 388 389/** 390 * e1000_get_hw_semaphore_80003es2lan - Acquire HW semaphore for PHY/NVM access 391 * @hw - pointer to the HW structure 392 * 393 * Acquire the HW semaphore to access the PHY or NVM 394 **/ 395static s32 396e1000_get_hw_semaphore_80003es2lan(struct e1000_hw *hw) 397{ 398 u32 swsm; 399 s32 ret_val = E1000_SUCCESS; 400 s32 timeout = hw->nvm.word_size + 1; 401 s32 i = 0; 402 403 DEBUGFUNC("e1000_get_hw_semaphore_80003es2lan"); 404 405 /* Get the SW semaphore. */ 406 while (i < timeout) { 407 swsm = E1000_READ_REG(hw, E1000_SWSM); 408 if (!(swsm & E1000_SWSM_SMBI)) 409 break; 410 411 msec_delay_irq(1); 412 i++; 413 } 414 415 if (i == timeout) { 416 DEBUGOUT("Driver can't access device " 417 "- SMBI bit is set.\n"); 418 ret_val = -E1000_ERR_NVM; 419 goto out; 420 } 421 422 /* Get the FW semaphore. */ 423 ret_val = e1000_get_hw_semaphore_generic(hw); 424 if (ret_val) { 425 /* Release 80003es2lan semaphores */ 426 e1000_put_hw_semaphore_80003es2lan(hw); 427 goto out; 428 } 429 430out: 431 return ret_val; 432} 433 434/** 435 * e1000_put_hw_semaphore_80003es2lan - Release HW semaphore for PHY/NVM access 436 * @hw - pointer to the HW structure 437 * 438 * Release the HW semaphore used to access the PHY or NVM 439 **/ 440static void 441e1000_put_hw_semaphore_80003es2lan(struct e1000_hw *hw) 442{ 443 u32 swsm; 444 445 DEBUGFUNC("e1000_put_hw_semaphore_80003es2lan"); 446 447 swsm = E1000_READ_REG(hw, E1000_SWSM); 448 449 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 450 451 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 452} 453 454/** 455 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 456 * @hw - pointer to the HW structure 457 * @mask - specifies which semaphore to acquire 458 * 459 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 460 * will also specify which port we're acquiring the lock for. 461 **/ 462static s32 463e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 464{ 465 u32 swfw_sync; 466 u32 swmask = mask; 467 u32 fwmask = mask << 16; 468 s32 ret_val = E1000_SUCCESS; 469 s32 i = 0, timeout = 200; 470 471 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 472 473 while (i < timeout) { 474 if (e1000_get_hw_semaphore_80003es2lan(hw)) { 475 ret_val = -E1000_ERR_SWFW_SYNC; 476 goto out; 477 } 478 479 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 480 if (!(swfw_sync & (fwmask | swmask))) 481 break; 482 483 /* Firmware currently using resource (fwmask) 484 * or other software thread using resource (swmask) */ 485 e1000_put_hw_semaphore_80003es2lan(hw); 486 msec_delay_irq(5); 487 i++; 488 } 489 490 if (i == timeout) { 491 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 492 ret_val = -E1000_ERR_SWFW_SYNC; 493 goto out; 494 } 495 496 swfw_sync |= swmask; 497 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 498 499 e1000_put_hw_semaphore_80003es2lan(hw); 500 501out: 502 return ret_val; 503} 504 505/** 506 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 507 * @hw - pointer to the HW structure 508 * @mask - specifies which semaphore to acquire 509 * 510 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 511 * will also specify which port we're releasing the lock for. 512 **/ 513static void 514e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 515{ 516 u32 swfw_sync; 517 518 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 519 520 while (e1000_get_hw_semaphore_80003es2lan(hw) != E1000_SUCCESS); 521 /* Empty */ 522 523 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 524 swfw_sync &= ~mask; 525 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 526 527 e1000_put_hw_semaphore_80003es2lan(hw); 528} 529 530/** 531 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 532 * @hw - pointer to the HW structure 533 * @offset - offset of the register to read 534 * @data - pointer to the data returned from the operation 535 * 536 * Read the GG82563 PHY register. This is a function pointer entry 537 * point called by the api module. 538 **/ 539STATIC s32 540e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset, 541 u16 *data) 542{ 543 s32 ret_val; 544 u32 page_select; 545 u16 temp; 546 547 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 548 549 /* Select Configuration Page */ 550 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) 551 page_select = GG82563_PHY_PAGE_SELECT; 552 else { 553 /* Use Alternative Page Select register to access 554 * registers 30 and 31 555 */ 556 page_select = GG82563_PHY_PAGE_SELECT_ALT; 557 } 558 559 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 560 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 561 if (ret_val) 562 goto out; 563 564 /* The "ready" bit in the MDIC register may be incorrectly set 565 * before the device has completed the "Page Select" MDI 566 * transaction. So we wait 200us after each MDI command... 567 */ 568 usec_delay(200); 569 570 /* ...and verify the command was successful. */ 571 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 572 573 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 574 ret_val = -E1000_ERR_PHY; 575 goto out; 576 } 577 578 usec_delay(200); 579 580 ret_val = e1000_read_phy_reg_m88(hw, 581 MAX_PHY_REG_ADDRESS & offset, 582 data); 583 584 usec_delay(200); 585 586out: 587 return ret_val; 588} 589 590/** 591 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 592 * @hw - pointer to the HW structure 593 * @offset - offset of the register to read 594 * @data - value to write to the register 595 * 596 * Write to the GG82563 PHY register. This is a function pointer entry 597 * point called by the api module. 598 **/ 599STATIC s32 600e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset, 601 u16 data) 602{ 603 s32 ret_val; 604 u32 page_select; 605 u16 temp; 606 607 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 608 609 /* Select Configuration Page */ 610 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) 611 page_select = GG82563_PHY_PAGE_SELECT; 612 else { 613 /* Use Alternative Page Select register to access 614 * registers 30 and 31 615 */ 616 page_select = GG82563_PHY_PAGE_SELECT_ALT; 617 } 618 619 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 620 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 621 if (ret_val) 622 goto out; 623 624 625 /* The "ready" bit in the MDIC register may be incorrectly set 626 * before the device has completed the "Page Select" MDI 627 * transaction. So we wait 200us after each MDI command... 628 */ 629 usec_delay(200); 630 631 /* ...and verify the command was successful. */ 632 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 633 634 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 635 ret_val = -E1000_ERR_PHY; 636 goto out; 637 } 638 639 usec_delay(200); 640 641 ret_val = e1000_write_phy_reg_m88(hw, 642 MAX_PHY_REG_ADDRESS & offset, 643 data); 644 645 usec_delay(200); 646 647out: 648 return ret_val; 649} 650 651/** 652 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 653 * @hw - pointer to the HW structure 654 * @offset - offset of the register to read 655 * @words - number of words to write 656 * @data - buffer of data to write to the NVM 657 * 658 * Write "words" of data to the ESB2 NVM. This is a function 659 * pointer entry point called by the api module. 660 **/ 661STATIC s32 662e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 663 u16 words, u16 *data) 664{ 665 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 666 667 return e1000_write_nvm_spi(hw, offset, words, data); 668} 669 670/** 671 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 672 * @hw - pointer to the HW structure 673 * 674 * Wait a specific amount of time for manageability processes to complete. 675 * This is a function pointer entry point called by the phy module. 676 **/ 677STATIC s32 678e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 679{ 680 s32 timeout = PHY_CFG_TIMEOUT; 681 s32 ret_val = E1000_SUCCESS; 682 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 683 684 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 685 686 if (hw->bus.func == 1) 687 mask = E1000_NVM_CFG_DONE_PORT_1; 688 689 while (timeout) { 690 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 691 break; 692 msec_delay(1); 693 timeout--; 694 } 695 if (!timeout) { 696 DEBUGOUT("MNG configuration cycle has not completed.\n"); 697 ret_val = -E1000_ERR_RESET; 698 goto out; 699 } 700 701out: 702 return ret_val; 703} 704 705/** 706 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 707 * @hw - pointer to the HW structure 708 * 709 * Force the speed and duplex settings onto the PHY. This is a 710 * function pointer entry point called by the phy module. 711 **/ 712STATIC s32 713e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 714{ 715 s32 ret_val; 716 u16 phy_data; 717 boolean_t link; 718 719 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 720 721 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 722 * forced whenever speed and duplex are forced. 723 */ 724 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 725 if (ret_val) 726 goto out; 727 728 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 729 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 730 if (ret_val) 731 goto out; 732 733 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 734 735 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 736 if (ret_val) 737 goto out; 738 739 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 740 741 /* Reset the phy to commit changes. */ 742 phy_data |= MII_CR_RESET; 743 744 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 745 if (ret_val) 746 goto out; 747 748 usec_delay(1); 749 750 if (hw->phy.wait_for_link) { 751 DEBUGOUT("Waiting for forced speed/duplex link " 752 "on GG82563 phy.\n"); 753 754 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 755 100000, &link); 756 if (ret_val) 757 goto out; 758 759 if (!link) { 760 /* We didn't get link. 761 * Reset the DSP and cross our fingers. 762 */ 763 ret_val = e1000_phy_reset_dsp_generic(hw); 764 if (ret_val) 765 goto out; 766 } 767 768 /* Try once more */ 769 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 770 100000, &link); 771 if (ret_val) 772 goto out; 773 } 774 775 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 776 if (ret_val) 777 goto out; 778 779 /* Resetting the phy means we need to verify the TX_CLK corresponds 780 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 781 */ 782 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 783 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 784 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 785 else 786 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 787 788 /* In addition, we must re-enable CRS on Tx for both half and full 789 * duplex. 790 */ 791 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 792 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 793 794out: 795 return ret_val; 796} 797 798/** 799 * e1000_get_cable_length_80003es2lan - Set approximate cable length 800 * @hw - pointer to the HW structure 801 * 802 * Find the approximate cable length as measured by the GG82563 PHY. 803 * This is a function pointer entry point called by the phy module. 804 **/ 805STATIC s32 806e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 807{ 808 struct e1000_phy_info *phy = &hw->phy; 809 s32 ret_val; 810 u16 phy_data, index; 811 812 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 813 814 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 815 if (ret_val) 816 goto out; 817 818 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 819 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 820 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; 821 822 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 823 824out: 825 return ret_val; 826} 827 828/** 829 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 830 * @hw - pointer to the HW structure 831 * @speed - pointer to speed buffer 832 * @duplex - pointer to duplex buffer 833 * 834 * Retrieve the current speed and duplex configuration. 835 * This is a function pointer entry point called by the api module. 836 **/ 837STATIC s32 838e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, u16 *duplex) 839{ 840 s32 ret_val; 841 842 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 843 844 if (hw->media_type == e1000_media_type_copper) { 845 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 846 speed, 847 duplex); 848 if (ret_val) 849 goto out; 850 if (*speed == SPEED_1000) 851 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 852 else 853 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, 854 *duplex); 855 } else 856 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 857 speed, 858 duplex); 859 860out: 861 return ret_val; 862} 863 864/** 865 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 866 * @hw - pointer to the HW structure 867 * 868 * Perform a global reset to the ESB2 controller. 869 * This is a function pointer entry point called by the api module. 870 **/ 871STATIC s32 872e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 873{ 874 u32 ctrl, icr; 875 s32 ret_val; 876 877 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 878 879 /* Prevent the PCI-E bus from sticking if there is no TLP connection 880 * on the last TLP read/write transaction when MAC is reset. 881 */ 882 ret_val = e1000_disable_pcie_master_generic(hw); 883 if (ret_val) { 884 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 885 } 886 887 DEBUGOUT("Masking off all interrupts\n"); 888 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 889 890 E1000_WRITE_REG(hw, E1000_RCTL, 0); 891 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 892 E1000_WRITE_FLUSH(hw); 893 894 msec_delay(10); 895 896 ctrl = E1000_READ_REG(hw, E1000_CTRL); 897 898 DEBUGOUT("Issuing a global reset to MAC\n"); 899 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 900 901 ret_val = e1000_get_auto_rd_done_generic(hw); 902 if (ret_val) 903 /* We don't want to continue accessing MAC registers. */ 904 goto out; 905 906 /* Clear any pending interrupt events. */ 907 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 908 icr = E1000_READ_REG(hw, E1000_ICR); 909 910out: 911 return ret_val; 912} 913 914/** 915 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 916 * @hw - pointer to the HW structure 917 * 918 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 919 * This is a function pointer entry point called by the api module. 920 **/ 921STATIC s32 922e1000_init_hw_80003es2lan(struct e1000_hw *hw) 923{ 924 struct e1000_mac_info *mac = &hw->mac; 925 u32 reg_data; 926 s32 ret_val; 927 u16 i; 928 929 DEBUGFUNC("e1000_init_hw_80003es2lan"); 930 931 e1000_initialize_hw_bits_80003es2lan(hw); 932 933 /* Initialize identification LED */ 934 ret_val = e1000_id_led_init_generic(hw); 935 if (ret_val) { 936 DEBUGOUT("Error initializing identification LED\n"); 937 goto out; 938 } 939 940 /* Disabling VLAN filtering */ 941 DEBUGOUT("Initializing the IEEE VLAN\n"); 942 e1000_clear_vfta(hw); 943 944 /* Setup the receive address. */ 945 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 946 947 /* Zero out the Multicast HASH table */ 948 DEBUGOUT("Zeroing the MTA\n"); 949 for (i = 0; i < mac->mta_reg_count; i++) 950 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 951 952 /* Setup link and flow control */ 953 ret_val = e1000_setup_link(hw); 954 955 /* Set the transmit descriptor write-back policy */ 956 reg_data = E1000_READ_REG(hw, E1000_TXDCTL); 957 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 958 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 959 E1000_WRITE_REG(hw, E1000_TXDCTL, reg_data); 960 961 /* ...for both queues. */ 962 reg_data = E1000_READ_REG(hw, E1000_TXDCTL1); 963 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 964 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 965 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg_data); 966 967 /* Enable retransmit on late collisions */ 968 reg_data = E1000_READ_REG(hw, E1000_TCTL); 969 reg_data |= E1000_TCTL_RTLC; 970 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 971 972 /* Configure Gigabit Carry Extend Padding */ 973 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 974 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 975 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 976 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 977 978 /* Configure Transmit Inter-Packet Gap */ 979 reg_data = E1000_READ_REG(hw, E1000_TIPG); 980 reg_data &= ~E1000_TIPG_IPGT_MASK; 981 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 982 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 983 984 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 985 reg_data &= ~0x00100000; 986 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 987 988 /* Clear all of the statistics registers (clear on read). It is 989 * important that we do this after we have tried to establish link 990 * because the symbol error count will increment wildly if there 991 * is no link. 992 */ 993 e1000_clear_hw_cntrs_80003es2lan(hw); 994 995out: 996 return ret_val; 997} 998 999/** 1000 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 1001 * @hw - pointer to the HW structure 1002 * 1003 * Initializes required hardware-dependent bits needed for normal operation. 1004 **/ 1005static void 1006e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 1007{ 1008 u32 reg; 1009 1010 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 1011 1012 if (hw->mac.disable_hw_init_bits) 1013 goto out; 1014 1015 /* Transmit Descriptor Control 0 */ 1016 reg = E1000_READ_REG(hw, E1000_TXDCTL); 1017 reg |= (1 << 22); 1018 E1000_WRITE_REG(hw, E1000_TXDCTL, reg); 1019 1020 /* Transmit Descriptor Control 1 */ 1021 reg = E1000_READ_REG(hw, E1000_TXDCTL1); 1022 reg |= (1 << 22); 1023 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg); 1024 1025 /* Transmit Arbitration Control 0 */ 1026 reg = E1000_READ_REG(hw, E1000_TARC0); 1027 reg &= ~(0xF << 27); /* 30:27 */ 1028 if (hw->media_type != e1000_media_type_copper) 1029 reg &= ~(1 << 20); 1030 E1000_WRITE_REG(hw, E1000_TARC0, reg); 1031 1032 /* Transmit Arbitration Control 1 */ 1033 reg = E1000_READ_REG(hw, E1000_TARC1); 1034 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1035 reg &= ~(1 << 28); 1036 else 1037 reg |= (1 << 28); 1038 E1000_WRITE_REG(hw, E1000_TARC1, reg); 1039 1040out: 1041 return; 1042} 1043 1044/** 1045 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1046 * @hw - pointer to the HW structure 1047 * 1048 * Setup some GG82563 PHY registers for obtaining link 1049 **/ 1050static s32 1051e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1052{ 1053 struct e1000_phy_info *phy = &hw->phy; 1054 s32 ret_val; 1055 u32 ctrl_ext; 1056 u16 data; 1057 1058 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1059 1060 if (!phy->reset_disable) { 1061 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1062 &data); 1063 if (ret_val) 1064 goto out; 1065 1066 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1067 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1068 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1069 1070 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1071 data); 1072 if (ret_val) 1073 goto out; 1074 1075 /* Options: 1076 * MDI/MDI-X = 0 (default) 1077 * 0 - Auto for all speeds 1078 * 1 - MDI mode 1079 * 2 - MDI-X mode 1080 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1081 */ 1082 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1083 if (ret_val) 1084 goto out; 1085 1086 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1087 1088 switch (phy->mdix) { 1089 case 1: 1090 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1091 break; 1092 case 2: 1093 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1094 break; 1095 case 0: 1096 default: 1097 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1098 break; 1099 } 1100 1101 /* Options: 1102 * disable_polarity_correction = 0 (default) 1103 * Automatic Correction for Reversed Cable Polarity 1104 * 0 - Disabled 1105 * 1 - Enabled 1106 */ 1107 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1108 if (phy->disable_polarity_correction == TRUE) 1109 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1110 1111 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1112 if (ret_val) 1113 goto out; 1114 1115 /* SW Reset the PHY so all changes take effect */ 1116 ret_val = e1000_phy_commit(hw); 1117 if (ret_val) { 1118 DEBUGOUT("Error Resetting the PHY\n"); 1119 goto out; 1120 } 1121 1122 } 1123 1124 /* Bypass RX and TX FIFO's */ 1125 ret_val = e1000_write_kmrn_reg(hw, 1126 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1127 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1128 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1129 if (ret_val) 1130 goto out; 1131 1132 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1133 if (ret_val) 1134 goto out; 1135 1136 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1137 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1138 if (ret_val) 1139 goto out; 1140 1141 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1142 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1143 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1144 1145 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1146 if (ret_val) 1147 goto out; 1148 1149 /* Do not init these registers when the HW is in IAMT mode, since the 1150 * firmware will have already initialized them. We only initialize 1151 * them if the HW is not in IAMT mode. 1152 */ 1153 if (e1000_check_mng_mode(hw) == FALSE) { 1154 /* Enable Electrical Idle on the PHY */ 1155 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1156 ret_val = e1000_write_phy_reg(hw, 1157 GG82563_PHY_PWR_MGMT_CTRL, 1158 data); 1159 if (ret_val) 1160 goto out; 1161 1162 ret_val = e1000_read_phy_reg(hw, 1163 GG82563_PHY_KMRN_MODE_CTRL, 1164 &data); 1165 if (ret_val) 1166 goto out; 1167 1168 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1169 ret_val = e1000_write_phy_reg(hw, 1170 GG82563_PHY_KMRN_MODE_CTRL, 1171 data); 1172 1173 if (ret_val) 1174 goto out; 1175 } 1176 1177 /* Workaround: Disable padding in Kumeran interface in the MAC 1178 * and in the PHY to avoid CRC errors. 1179 */ 1180 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1181 if (ret_val) 1182 goto out; 1183 1184 data |= GG82563_ICR_DIS_PADDING; 1185 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1186 if (ret_val) 1187 goto out; 1188 1189out: 1190 return ret_val; 1191} 1192 1193/** 1194 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1195 * @hw - pointer to the HW structure 1196 * 1197 * Essentially a wrapper for setting up all things "copper" related. 1198 * This is a function pointer entry point called by the mac module. 1199 **/ 1200STATIC s32 1201e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1202{ 1203 u32 ctrl; 1204 s32 ret_val; 1205 u16 reg_data; 1206 1207 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1208 1209 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1210 ctrl |= E1000_CTRL_SLU; 1211 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1212 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1213 1214 /* Set the mac to wait the maximum time between each 1215 * iteration and increase the max iterations when 1216 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 1217 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1218 if (ret_val) 1219 goto out; 1220 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 1221 if (ret_val) 1222 goto out; 1223 reg_data |= 0x3F; 1224 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 1225 if (ret_val) 1226 goto out; 1227 ret_val = e1000_read_kmrn_reg(hw, 1228 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1229 ®_data); 1230 if (ret_val) 1231 goto out; 1232 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1233 ret_val = e1000_write_kmrn_reg(hw, 1234 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1235 reg_data); 1236 if (ret_val) 1237 goto out; 1238 1239 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1240 if (ret_val) 1241 goto out; 1242 1243 ret_val = e1000_setup_copper_link_generic(hw); 1244 1245out: 1246 return ret_val; 1247} 1248 1249/** 1250 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1251 * @hw - pointer to the HW structure 1252 * @duplex - current duplex setting 1253 * 1254 * Configure the KMRN interface by applying last minute quirks for 1255 * 10/100 operation. 1256 **/ 1257static s32 1258e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1259{ 1260 s32 ret_val = E1000_SUCCESS; 1261 u32 tipg; 1262 u16 reg_data; 1263 1264 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1265 1266 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1267 ret_val = e1000_write_kmrn_reg(hw, 1268 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1269 reg_data); 1270 if (ret_val) 1271 goto out; 1272 1273 /* Configure Transmit Inter-Packet Gap */ 1274 tipg = E1000_READ_REG(hw, E1000_TIPG); 1275 tipg &= ~E1000_TIPG_IPGT_MASK; 1276 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1277 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1278 1279 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 1280 if (ret_val) 1281 goto out; 1282 1283 if (duplex == HALF_DUPLEX) 1284 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1285 else 1286 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1287 1288 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1289 1290out: 1291 return ret_val; 1292} 1293 1294/** 1295 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1296 * @hw - pointer to the HW structure 1297 * 1298 * Configure the KMRN interface by applying last minute quirks for 1299 * gigabit operation. 1300 **/ 1301static s32 1302e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1303{ 1304 s32 ret_val = E1000_SUCCESS; 1305 u16 reg_data; 1306 u32 tipg; 1307 1308 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1309 1310 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1311 ret_val = e1000_write_kmrn_reg(hw, 1312 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1313 reg_data); 1314 if (ret_val) 1315 goto out; 1316 1317 /* Configure Transmit Inter-Packet Gap */ 1318 tipg = E1000_READ_REG(hw, E1000_TIPG); 1319 tipg &= ~E1000_TIPG_IPGT_MASK; 1320 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1321 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1322 1323 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 1324 if (ret_val) 1325 goto out; 1326 1327 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1328 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1329 1330out: 1331 return ret_val; 1332} 1333 1334/** 1335 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1336 * @hw - pointer to the HW structure 1337 * 1338 * Clears the hardware counters by reading the counter registers. 1339 **/ 1340STATIC void 1341e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1342{ 1343 volatile u32 temp; 1344 1345 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1346 1347 e1000_clear_hw_cntrs_base_generic(hw); 1348 1349 temp = E1000_READ_REG(hw, E1000_PRC64); 1350 temp = E1000_READ_REG(hw, E1000_PRC127); 1351 temp = E1000_READ_REG(hw, E1000_PRC255); 1352 temp = E1000_READ_REG(hw, E1000_PRC511); 1353 temp = E1000_READ_REG(hw, E1000_PRC1023); 1354 temp = E1000_READ_REG(hw, E1000_PRC1522); 1355 temp = E1000_READ_REG(hw, E1000_PTC64); 1356 temp = E1000_READ_REG(hw, E1000_PTC127); 1357 temp = E1000_READ_REG(hw, E1000_PTC255); 1358 temp = E1000_READ_REG(hw, E1000_PTC511); 1359 temp = E1000_READ_REG(hw, E1000_PTC1023); 1360 temp = E1000_READ_REG(hw, E1000_PTC1522); 1361 1362 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1363 temp = E1000_READ_REG(hw, E1000_RXERRC); 1364 temp = E1000_READ_REG(hw, E1000_TNCRS); 1365 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1366 temp = E1000_READ_REG(hw, E1000_TSCTC); 1367 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1368 1369 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1370 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1371 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1372 1373 temp = E1000_READ_REG(hw, E1000_IAC); 1374 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1375 1376 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1377 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1378 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1379 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1380 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1381 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1382 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1383} 1384