1177867Sjfv/****************************************************************************** 2169240Sjfv 3286833Ssbruno Copyright (c) 2001-2015, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35256200Sjfv/* 80003ES2LAN Gigabit Ethernet Controller (Copper) 36185353Sjfv * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 37169240Sjfv */ 38169240Sjfv 39169589Sjfv#include "e1000_api.h" 40169240Sjfv 41177867Sjfvstatic s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 42177867Sjfvstatic void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 43177867Sjfvstatic s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 44177867Sjfvstatic void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 45177867Sjfvstatic s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 46228386Sjfv u32 offset, 47228386Sjfv u16 *data); 48177867Sjfvstatic s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 49228386Sjfv u32 offset, 50228386Sjfv u16 data); 51177867Sjfvstatic s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 52228386Sjfv u16 words, u16 *data); 53177867Sjfvstatic s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 54177867Sjfvstatic s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 55177867Sjfvstatic s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 56177867Sjfvstatic s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 57228386Sjfv u16 *duplex); 58177867Sjfvstatic s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 59177867Sjfvstatic s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 60177867Sjfvstatic s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 61177867Sjfvstatic void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 62169240Sjfvstatic s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 63169240Sjfvstatic s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 64169240Sjfvstatic s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 65185353Sjfvstatic s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 66185353Sjfvstatic s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 67228386Sjfv u16 *data); 68185353Sjfvstatic s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 69228386Sjfv u16 data); 70169240Sjfvstatic void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 71169240Sjfvstatic void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 72177867Sjfvstatic s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 73177867Sjfvstatic void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 74169240Sjfv 75256200Sjfv/* A table for the GG82563 cable length where the range is defined 76169240Sjfv * with a lower bound at "index" and the upper bound at 77169240Sjfv * "index + 5". 78169240Sjfv */ 79218588Sjfvstatic const u16 e1000_gg82563_cable_length_table[] = { 80218588Sjfv 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 81169240Sjfv#define GG82563_CABLE_LENGTH_TABLE_SIZE \ 82228386Sjfv (sizeof(e1000_gg82563_cable_length_table) / \ 83228386Sjfv sizeof(e1000_gg82563_cable_length_table[0])) 84169240Sjfv 85169240Sjfv/** 86169240Sjfv * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 87169589Sjfv * @hw: pointer to the HW structure 88169240Sjfv **/ 89177867Sjfvstatic s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 90169240Sjfv{ 91169240Sjfv struct e1000_phy_info *phy = &hw->phy; 92256200Sjfv s32 ret_val; 93169240Sjfv 94169240Sjfv DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 95169240Sjfv 96173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 97228386Sjfv phy->type = e1000_phy_none; 98256200Sjfv return E1000_SUCCESS; 99173788Sjfv } else { 100177867Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 101177867Sjfv phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 102169240Sjfv } 103169240Sjfv 104228386Sjfv phy->addr = 1; 105228386Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106228386Sjfv phy->reset_delay_us = 100; 107228386Sjfv phy->type = e1000_phy_gg82563; 108169240Sjfv 109228386Sjfv phy->ops.acquire = e1000_acquire_phy_80003es2lan; 110228386Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 111228386Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 112228386Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 113228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 114228386Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 115228386Sjfv phy->ops.release = e1000_release_phy_80003es2lan; 116228386Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 117228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 118169240Sjfv 119177867Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 120228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 121228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 122228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 123169240Sjfv 124228386Sjfv phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 125185353Sjfv 126169240Sjfv /* This can only be done after all function pointers are setup. */ 127169240Sjfv ret_val = e1000_get_phy_id(hw); 128169240Sjfv 129169240Sjfv /* Verify phy id */ 130256200Sjfv if (phy->id != GG82563_E_PHY_ID) 131256200Sjfv return -E1000_ERR_PHY; 132169240Sjfv 133169240Sjfv return ret_val; 134169240Sjfv} 135169240Sjfv 136169240Sjfv/** 137169240Sjfv * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 138169589Sjfv * @hw: pointer to the HW structure 139169240Sjfv **/ 140177867Sjfvstatic s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 141169240Sjfv{ 142169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 143169240Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 144169240Sjfv u16 size; 145169240Sjfv 146169240Sjfv DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 147169240Sjfv 148228386Sjfv nvm->opcode_bits = 8; 149228386Sjfv nvm->delay_usec = 1; 150169240Sjfv switch (nvm->override) { 151169240Sjfv case e1000_nvm_override_spi_large: 152228386Sjfv nvm->page_size = 32; 153169240Sjfv nvm->address_bits = 16; 154169240Sjfv break; 155169240Sjfv case e1000_nvm_override_spi_small: 156228386Sjfv nvm->page_size = 8; 157169240Sjfv nvm->address_bits = 8; 158169240Sjfv break; 159169240Sjfv default: 160228386Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 161169240Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 162169240Sjfv break; 163169240Sjfv } 164169240Sjfv 165200243Sjfv nvm->type = e1000_nvm_eeprom_spi; 166169240Sjfv 167169240Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 168228386Sjfv E1000_EECD_SIZE_EX_SHIFT); 169169240Sjfv 170256200Sjfv /* Added to a constant, "size" becomes the left-shift value 171169240Sjfv * for setting word_size. 172169240Sjfv */ 173169240Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 174173788Sjfv 175173788Sjfv /* EEPROM access above 16k is unsupported */ 176173788Sjfv if (size > 14) 177173788Sjfv size = 14; 178228386Sjfv nvm->word_size = 1 << size; 179169240Sjfv 180169240Sjfv /* Function Pointers */ 181228386Sjfv nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 182228386Sjfv nvm->ops.read = e1000_read_nvm_eerd; 183228386Sjfv nvm->ops.release = e1000_release_nvm_80003es2lan; 184228386Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 185177867Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_generic; 186228386Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 187228386Sjfv nvm->ops.write = e1000_write_nvm_80003es2lan; 188169240Sjfv 189169240Sjfv return E1000_SUCCESS; 190169240Sjfv} 191169240Sjfv 192169240Sjfv/** 193169240Sjfv * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 194169589Sjfv * @hw: pointer to the HW structure 195169240Sjfv **/ 196177867Sjfvstatic s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 197169240Sjfv{ 198169240Sjfv struct e1000_mac_info *mac = &hw->mac; 199169240Sjfv 200169240Sjfv DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 201169240Sjfv 202200243Sjfv /* Set media type and media-dependent function pointers */ 203169240Sjfv switch (hw->device_id) { 204169240Sjfv case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 205173788Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 206200243Sjfv mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 207200243Sjfv mac->ops.setup_physical_interface = 208228386Sjfv e1000_setup_fiber_serdes_link_generic; 209169240Sjfv break; 210169240Sjfv default: 211173788Sjfv hw->phy.media_type = e1000_media_type_copper; 212200243Sjfv mac->ops.check_for_link = e1000_check_for_copper_link_generic; 213200243Sjfv mac->ops.setup_physical_interface = 214228386Sjfv e1000_setup_copper_link_80003es2lan; 215169240Sjfv break; 216169240Sjfv } 217169240Sjfv 218169240Sjfv /* Set mta register count */ 219169240Sjfv mac->mta_reg_count = 128; 220169240Sjfv /* Set rar entry count */ 221169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 222169240Sjfv /* Set if part includes ASF firmware */ 223169240Sjfv mac->asf_firmware_present = TRUE; 224205869Sjfv /* FWSM register */ 225205869Sjfv mac->has_fwsm = TRUE; 226205869Sjfv /* ARC supported; valid only if manageability features are enabled. */ 227256200Sjfv mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 228256200Sjfv E1000_FWSM_MODE_MASK); 229200243Sjfv /* Adaptive IFS not supported */ 230200243Sjfv mac->adaptive_ifs = FALSE; 231169240Sjfv 232169240Sjfv /* Function pointers */ 233169240Sjfv 234169240Sjfv /* bus type/speed/width */ 235177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 236169240Sjfv /* reset */ 237177867Sjfv mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 238169240Sjfv /* hw initialization */ 239177867Sjfv mac->ops.init_hw = e1000_init_hw_80003es2lan; 240169240Sjfv /* link setup */ 241177867Sjfv mac->ops.setup_link = e1000_setup_link_generic; 242169240Sjfv /* check management mode */ 243177867Sjfv mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 244169240Sjfv /* multicast address update */ 245177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 246169240Sjfv /* writing VFTA */ 247177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 248169240Sjfv /* clearing VFTA */ 249177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 250176667Sjfv /* read mac address */ 251177867Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 252190872Sjfv /* ID LED init */ 253190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 254169240Sjfv /* blink LED */ 255177867Sjfv mac->ops.blink_led = e1000_blink_led_generic; 256169240Sjfv /* setup LED */ 257177867Sjfv mac->ops.setup_led = e1000_setup_led_generic; 258169240Sjfv /* cleanup LED */ 259177867Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 260169240Sjfv /* turn on/off LED */ 261177867Sjfv mac->ops.led_on = e1000_led_on_generic; 262177867Sjfv mac->ops.led_off = e1000_led_off_generic; 263169240Sjfv /* clear hardware counters */ 264177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 265169240Sjfv /* link info */ 266177867Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 267169240Sjfv 268200243Sjfv /* set lan id for port to determine which phy lock to use */ 269200243Sjfv hw->mac.ops.set_lan_id(hw); 270200243Sjfv 271200243Sjfv return E1000_SUCCESS; 272169240Sjfv} 273169240Sjfv 274169240Sjfv/** 275169240Sjfv * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 276169589Sjfv * @hw: pointer to the HW structure 277169240Sjfv * 278185353Sjfv * Called to initialize all function pointers and parameters. 279169240Sjfv **/ 280173788Sjfvvoid e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 281169240Sjfv{ 282169240Sjfv DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 283169240Sjfv 284177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 285177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 286177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 287169240Sjfv} 288169240Sjfv 289169240Sjfv/** 290169240Sjfv * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 291169589Sjfv * @hw: pointer to the HW structure 292169240Sjfv * 293185353Sjfv * A wrapper to acquire access rights to the correct PHY. 294169240Sjfv **/ 295177867Sjfvstatic s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 296169240Sjfv{ 297169240Sjfv u16 mask; 298169240Sjfv 299169240Sjfv DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 300169240Sjfv 301169240Sjfv mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 302169240Sjfv return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 303169240Sjfv} 304169240Sjfv 305169240Sjfv/** 306169240Sjfv * e1000_release_phy_80003es2lan - Release rights to access PHY 307169589Sjfv * @hw: pointer to the HW structure 308169240Sjfv * 309185353Sjfv * A wrapper to release access rights to the correct PHY. 310169240Sjfv **/ 311177867Sjfvstatic void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 312169240Sjfv{ 313169240Sjfv u16 mask; 314169240Sjfv 315169240Sjfv DEBUGFUNC("e1000_release_phy_80003es2lan"); 316169240Sjfv 317169240Sjfv mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 318185353Sjfv e1000_release_swfw_sync_80003es2lan(hw, mask); 319185353Sjfv} 320176667Sjfv 321185353Sjfv/** 322228386Sjfv * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 323185353Sjfv * @hw: pointer to the HW structure 324185353Sjfv * 325185353Sjfv * Acquire the semaphore to access the Kumeran interface. 326185353Sjfv * 327185353Sjfv **/ 328185353Sjfvstatic s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 329185353Sjfv{ 330185353Sjfv u16 mask; 331185353Sjfv 332185353Sjfv DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 333185353Sjfv 334185353Sjfv mask = E1000_SWFW_CSR_SM; 335185353Sjfv 336185353Sjfv return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 337185353Sjfv} 338185353Sjfv 339185353Sjfv/** 340228386Sjfv * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 341185353Sjfv * @hw: pointer to the HW structure 342185353Sjfv * 343185353Sjfv * Release the semaphore used to access the Kumeran interface 344185353Sjfv **/ 345185353Sjfvstatic void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 346185353Sjfv{ 347185353Sjfv u16 mask; 348185353Sjfv 349185353Sjfv DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 350185353Sjfv 351185353Sjfv mask = E1000_SWFW_CSR_SM; 352185353Sjfv 353169240Sjfv e1000_release_swfw_sync_80003es2lan(hw, mask); 354169240Sjfv} 355169240Sjfv 356169240Sjfv/** 357169240Sjfv * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 358169589Sjfv * @hw: pointer to the HW structure 359169240Sjfv * 360185353Sjfv * Acquire the semaphore to access the EEPROM. 361169240Sjfv **/ 362177867Sjfvstatic s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 363169240Sjfv{ 364169240Sjfv s32 ret_val; 365169240Sjfv 366169240Sjfv DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 367169240Sjfv 368169240Sjfv ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 369169240Sjfv if (ret_val) 370256200Sjfv return ret_val; 371169240Sjfv 372169240Sjfv ret_val = e1000_acquire_nvm_generic(hw); 373169240Sjfv 374169240Sjfv if (ret_val) 375169240Sjfv e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 376169240Sjfv 377169240Sjfv return ret_val; 378169240Sjfv} 379169240Sjfv 380169240Sjfv/** 381169240Sjfv * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 382169589Sjfv * @hw: pointer to the HW structure 383169240Sjfv * 384185353Sjfv * Release the semaphore used to access the EEPROM. 385169240Sjfv **/ 386177867Sjfvstatic void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 387169240Sjfv{ 388169240Sjfv DEBUGFUNC("e1000_release_nvm_80003es2lan"); 389169240Sjfv 390169240Sjfv e1000_release_nvm_generic(hw); 391169240Sjfv e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 392169240Sjfv} 393169240Sjfv 394169240Sjfv/** 395169240Sjfv * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 396169589Sjfv * @hw: pointer to the HW structure 397169589Sjfv * @mask: specifies which semaphore to acquire 398169240Sjfv * 399169240Sjfv * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 400169240Sjfv * will also specify which port we're acquiring the lock for. 401169240Sjfv **/ 402173788Sjfvstatic s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 403169240Sjfv{ 404169240Sjfv u32 swfw_sync; 405169240Sjfv u32 swmask = mask; 406169240Sjfv u32 fwmask = mask << 16; 407256200Sjfv s32 i = 0; 408256200Sjfv s32 timeout = 50; 409169240Sjfv 410169240Sjfv DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 411169240Sjfv 412169240Sjfv while (i < timeout) { 413256200Sjfv if (e1000_get_hw_semaphore_generic(hw)) 414256200Sjfv return -E1000_ERR_SWFW_SYNC; 415169240Sjfv 416169240Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 417169240Sjfv if (!(swfw_sync & (fwmask | swmask))) 418169240Sjfv break; 419169240Sjfv 420256200Sjfv /* Firmware currently using resource (fwmask) 421173788Sjfv * or other software thread using resource (swmask) 422173788Sjfv */ 423169589Sjfv e1000_put_hw_semaphore_generic(hw); 424169240Sjfv msec_delay_irq(5); 425169240Sjfv i++; 426169240Sjfv } 427169240Sjfv 428169240Sjfv if (i == timeout) { 429169240Sjfv DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 430256200Sjfv return -E1000_ERR_SWFW_SYNC; 431169240Sjfv } 432169240Sjfv 433169240Sjfv swfw_sync |= swmask; 434169240Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 435169240Sjfv 436169589Sjfv e1000_put_hw_semaphore_generic(hw); 437169240Sjfv 438256200Sjfv return E1000_SUCCESS; 439169240Sjfv} 440169240Sjfv 441169240Sjfv/** 442169240Sjfv * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 443169589Sjfv * @hw: pointer to the HW structure 444169589Sjfv * @mask: specifies which semaphore to acquire 445169240Sjfv * 446169240Sjfv * Release the SW/FW semaphore used to access the PHY or NVM. The mask 447169240Sjfv * will also specify which port we're releasing the lock for. 448169240Sjfv **/ 449173788Sjfvstatic void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 450169240Sjfv{ 451169240Sjfv u32 swfw_sync; 452169240Sjfv 453169240Sjfv DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 454169240Sjfv 455185353Sjfv while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 456185353Sjfv ; /* Empty */ 457169240Sjfv 458169240Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 459169240Sjfv swfw_sync &= ~mask; 460169240Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 461169240Sjfv 462169589Sjfv e1000_put_hw_semaphore_generic(hw); 463169240Sjfv} 464169240Sjfv 465169240Sjfv/** 466169240Sjfv * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 467169589Sjfv * @hw: pointer to the HW structure 468169589Sjfv * @offset: offset of the register to read 469169589Sjfv * @data: pointer to the data returned from the operation 470169240Sjfv * 471185353Sjfv * Read the GG82563 PHY register. 472169240Sjfv **/ 473177867Sjfvstatic s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 474228386Sjfv u32 offset, u16 *data) 475169240Sjfv{ 476169240Sjfv s32 ret_val; 477169240Sjfv u32 page_select; 478169240Sjfv u16 temp; 479169240Sjfv 480169240Sjfv DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 481169240Sjfv 482176667Sjfv ret_val = e1000_acquire_phy_80003es2lan(hw); 483176667Sjfv if (ret_val) 484256200Sjfv return ret_val; 485176667Sjfv 486169240Sjfv /* Select Configuration Page */ 487173788Sjfv if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 488169240Sjfv page_select = GG82563_PHY_PAGE_SELECT; 489173788Sjfv } else { 490256200Sjfv /* Use Alternative Page Select register to access 491169240Sjfv * registers 30 and 31 492169240Sjfv */ 493169240Sjfv page_select = GG82563_PHY_PAGE_SELECT_ALT; 494169240Sjfv } 495169240Sjfv 496169240Sjfv temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 497176667Sjfv ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 498176667Sjfv if (ret_val) { 499176667Sjfv e1000_release_phy_80003es2lan(hw); 500256200Sjfv return ret_val; 501176667Sjfv } 502169240Sjfv 503256200Sjfv if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 504256200Sjfv /* The "ready" bit in the MDIC register may be incorrectly set 505200243Sjfv * before the device has completed the "Page Select" MDI 506200243Sjfv * transaction. So we wait 200us after each MDI command... 507200243Sjfv */ 508200243Sjfv usec_delay(200); 509169240Sjfv 510200243Sjfv /* ...and verify the command was successful. */ 511200243Sjfv ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 512169240Sjfv 513200243Sjfv if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 514200243Sjfv e1000_release_phy_80003es2lan(hw); 515256200Sjfv return -E1000_ERR_PHY; 516200243Sjfv } 517169240Sjfv 518200243Sjfv usec_delay(200); 519169240Sjfv 520200243Sjfv ret_val = e1000_read_phy_reg_mdic(hw, 521228386Sjfv MAX_PHY_REG_ADDRESS & offset, 522228386Sjfv data); 523169240Sjfv 524200243Sjfv usec_delay(200); 525200243Sjfv } else { 526200243Sjfv ret_val = e1000_read_phy_reg_mdic(hw, 527228386Sjfv MAX_PHY_REG_ADDRESS & offset, 528228386Sjfv data); 529200243Sjfv } 530200243Sjfv 531176667Sjfv e1000_release_phy_80003es2lan(hw); 532169240Sjfv 533169240Sjfv return ret_val; 534169240Sjfv} 535169240Sjfv 536169240Sjfv/** 537169240Sjfv * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 538169589Sjfv * @hw: pointer to the HW structure 539169589Sjfv * @offset: offset of the register to read 540169589Sjfv * @data: value to write to the register 541169240Sjfv * 542185353Sjfv * Write to the GG82563 PHY register. 543169240Sjfv **/ 544177867Sjfvstatic s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 545228386Sjfv u32 offset, u16 data) 546169240Sjfv{ 547169240Sjfv s32 ret_val; 548169240Sjfv u32 page_select; 549169240Sjfv u16 temp; 550169240Sjfv 551169240Sjfv DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 552169240Sjfv 553176667Sjfv ret_val = e1000_acquire_phy_80003es2lan(hw); 554176667Sjfv if (ret_val) 555256200Sjfv return ret_val; 556176667Sjfv 557169240Sjfv /* Select Configuration Page */ 558173788Sjfv if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 559169240Sjfv page_select = GG82563_PHY_PAGE_SELECT; 560173788Sjfv } else { 561256200Sjfv /* Use Alternative Page Select register to access 562169240Sjfv * registers 30 and 31 563169240Sjfv */ 564169240Sjfv page_select = GG82563_PHY_PAGE_SELECT_ALT; 565169240Sjfv } 566169240Sjfv 567169240Sjfv temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 568176667Sjfv ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 569176667Sjfv if (ret_val) { 570176667Sjfv e1000_release_phy_80003es2lan(hw); 571256200Sjfv return ret_val; 572176667Sjfv } 573169240Sjfv 574256200Sjfv if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 575256200Sjfv /* The "ready" bit in the MDIC register may be incorrectly set 576200243Sjfv * before the device has completed the "Page Select" MDI 577200243Sjfv * transaction. So we wait 200us after each MDI command... 578200243Sjfv */ 579200243Sjfv usec_delay(200); 580169240Sjfv 581200243Sjfv /* ...and verify the command was successful. */ 582200243Sjfv ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 583169240Sjfv 584200243Sjfv if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 585200243Sjfv e1000_release_phy_80003es2lan(hw); 586256200Sjfv return -E1000_ERR_PHY; 587200243Sjfv } 588169240Sjfv 589200243Sjfv usec_delay(200); 590169240Sjfv 591200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, 592228386Sjfv MAX_PHY_REG_ADDRESS & offset, 593228386Sjfv data); 594169240Sjfv 595200243Sjfv usec_delay(200); 596200243Sjfv } else { 597200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, 598228386Sjfv MAX_PHY_REG_ADDRESS & offset, 599228386Sjfv data); 600200243Sjfv } 601169240Sjfv 602176667Sjfv e1000_release_phy_80003es2lan(hw); 603169240Sjfv 604169240Sjfv return ret_val; 605169240Sjfv} 606169240Sjfv 607169240Sjfv/** 608169240Sjfv * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 609169589Sjfv * @hw: pointer to the HW structure 610169589Sjfv * @offset: offset of the register to read 611169589Sjfv * @words: number of words to write 612169589Sjfv * @data: buffer of data to write to the NVM 613169240Sjfv * 614185353Sjfv * Write "words" of data to the ESB2 NVM. 615169240Sjfv **/ 616177867Sjfvstatic s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 617228386Sjfv u16 words, u16 *data) 618169240Sjfv{ 619169240Sjfv DEBUGFUNC("e1000_write_nvm_80003es2lan"); 620169240Sjfv 621169240Sjfv return e1000_write_nvm_spi(hw, offset, words, data); 622169240Sjfv} 623169240Sjfv 624169240Sjfv/** 625169240Sjfv * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 626169589Sjfv * @hw: pointer to the HW structure 627169240Sjfv * 628169240Sjfv * Wait a specific amount of time for manageability processes to complete. 629169240Sjfv * This is a function pointer entry point called by the phy module. 630169240Sjfv **/ 631177867Sjfvstatic s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 632169240Sjfv{ 633169240Sjfv s32 timeout = PHY_CFG_TIMEOUT; 634169240Sjfv u32 mask = E1000_NVM_CFG_DONE_PORT_0; 635169240Sjfv 636169240Sjfv DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 637169240Sjfv 638169240Sjfv if (hw->bus.func == 1) 639169240Sjfv mask = E1000_NVM_CFG_DONE_PORT_1; 640169240Sjfv 641169240Sjfv while (timeout) { 642169240Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 643169240Sjfv break; 644169240Sjfv msec_delay(1); 645169240Sjfv timeout--; 646169240Sjfv } 647169240Sjfv if (!timeout) { 648169240Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 649256200Sjfv return -E1000_ERR_RESET; 650169240Sjfv } 651169240Sjfv 652256200Sjfv return E1000_SUCCESS; 653169240Sjfv} 654169240Sjfv 655169240Sjfv/** 656169240Sjfv * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 657169589Sjfv * @hw: pointer to the HW structure 658169240Sjfv * 659169240Sjfv * Force the speed and duplex settings onto the PHY. This is a 660169240Sjfv * function pointer entry point called by the phy module. 661169240Sjfv **/ 662177867Sjfvstatic s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 663169240Sjfv{ 664256200Sjfv s32 ret_val; 665169240Sjfv u16 phy_data; 666173788Sjfv bool link; 667169240Sjfv 668169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 669169240Sjfv 670177867Sjfv if (!(hw->phy.ops.read_reg)) 671256200Sjfv return E1000_SUCCESS; 672177867Sjfv 673256200Sjfv /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 674169240Sjfv * forced whenever speed and duplex are forced. 675169240Sjfv */ 676177867Sjfv ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 677169240Sjfv if (ret_val) 678256200Sjfv return ret_val; 679169240Sjfv 680169240Sjfv phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 681177867Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 682169240Sjfv if (ret_val) 683256200Sjfv return ret_val; 684169240Sjfv 685169240Sjfv DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 686169240Sjfv 687177867Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 688169240Sjfv if (ret_val) 689256200Sjfv return ret_val; 690169240Sjfv 691169240Sjfv e1000_phy_force_speed_duplex_setup(hw, &phy_data); 692169240Sjfv 693169240Sjfv /* Reset the phy to commit changes. */ 694169240Sjfv phy_data |= MII_CR_RESET; 695169240Sjfv 696177867Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 697169240Sjfv if (ret_val) 698256200Sjfv return ret_val; 699169240Sjfv 700169240Sjfv usec_delay(1); 701169240Sjfv 702173788Sjfv if (hw->phy.autoneg_wait_to_complete) { 703228386Sjfv DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); 704169240Sjfv 705169240Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 706228386Sjfv 100000, &link); 707169240Sjfv if (ret_val) 708256200Sjfv return ret_val; 709169240Sjfv 710169240Sjfv if (!link) { 711256200Sjfv /* We didn't get link. 712169240Sjfv * Reset the DSP and cross our fingers. 713169240Sjfv */ 714169240Sjfv ret_val = e1000_phy_reset_dsp_generic(hw); 715169240Sjfv if (ret_val) 716256200Sjfv return ret_val; 717169240Sjfv } 718169240Sjfv 719169240Sjfv /* Try once more */ 720169240Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 721228386Sjfv 100000, &link); 722169240Sjfv if (ret_val) 723256200Sjfv return ret_val; 724169240Sjfv } 725169240Sjfv 726228386Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 727228386Sjfv &phy_data); 728169240Sjfv if (ret_val) 729256200Sjfv return ret_val; 730169240Sjfv 731256200Sjfv /* Resetting the phy means we need to verify the TX_CLK corresponds 732169240Sjfv * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 733169240Sjfv */ 734169240Sjfv phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 735169240Sjfv if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 736169240Sjfv phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 737169240Sjfv else 738169240Sjfv phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 739169240Sjfv 740256200Sjfv /* In addition, we must re-enable CRS on Tx for both half and full 741169240Sjfv * duplex. 742169240Sjfv */ 743169240Sjfv phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 744228386Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 745228386Sjfv phy_data); 746169240Sjfv 747169240Sjfv return ret_val; 748169240Sjfv} 749169240Sjfv 750169240Sjfv/** 751169240Sjfv * e1000_get_cable_length_80003es2lan - Set approximate cable length 752169589Sjfv * @hw: pointer to the HW structure 753169240Sjfv * 754169240Sjfv * Find the approximate cable length as measured by the GG82563 PHY. 755169240Sjfv * This is a function pointer entry point called by the phy module. 756169240Sjfv **/ 757177867Sjfvstatic s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 758169240Sjfv{ 759169240Sjfv struct e1000_phy_info *phy = &hw->phy; 760256200Sjfv s32 ret_val; 761169240Sjfv u16 phy_data, index; 762169240Sjfv 763169240Sjfv DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 764169240Sjfv 765177867Sjfv if (!(hw->phy.ops.read_reg)) 766256200Sjfv return E1000_SUCCESS; 767177867Sjfv 768177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 769169240Sjfv if (ret_val) 770256200Sjfv return ret_val; 771169240Sjfv 772169240Sjfv index = phy_data & GG82563_DSPD_CABLE_LENGTH; 773169240Sjfv 774256200Sjfv if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 775256200Sjfv return -E1000_ERR_PHY; 776185353Sjfv 777190872Sjfv phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 778200243Sjfv phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 779190872Sjfv 780190872Sjfv phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 781190872Sjfv 782256200Sjfv return E1000_SUCCESS; 783169240Sjfv} 784169240Sjfv 785169240Sjfv/** 786169240Sjfv * e1000_get_link_up_info_80003es2lan - Report speed and duplex 787169589Sjfv * @hw: pointer to the HW structure 788169589Sjfv * @speed: pointer to speed buffer 789169589Sjfv * @duplex: pointer to duplex buffer 790169240Sjfv * 791169240Sjfv * Retrieve the current speed and duplex configuration. 792169240Sjfv **/ 793177867Sjfvstatic s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 794228386Sjfv u16 *duplex) 795169240Sjfv{ 796169240Sjfv s32 ret_val; 797169240Sjfv 798169240Sjfv DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 799169240Sjfv 800173788Sjfv if (hw->phy.media_type == e1000_media_type_copper) { 801228386Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 802228386Sjfv duplex); 803185353Sjfv hw->phy.ops.cfg_on_link_up(hw); 804173788Sjfv } else { 805169240Sjfv ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 806228386Sjfv speed, 807228386Sjfv duplex); 808173788Sjfv } 809169240Sjfv 810169240Sjfv return ret_val; 811169240Sjfv} 812169240Sjfv 813169240Sjfv/** 814169240Sjfv * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 815169589Sjfv * @hw: pointer to the HW structure 816169240Sjfv * 817169240Sjfv * Perform a global reset to the ESB2 controller. 818169240Sjfv **/ 819177867Sjfvstatic s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 820169240Sjfv{ 821218588Sjfv u32 ctrl; 822169240Sjfv s32 ret_val; 823256200Sjfv u16 kum_reg_data; 824169240Sjfv 825169240Sjfv DEBUGFUNC("e1000_reset_hw_80003es2lan"); 826169240Sjfv 827256200Sjfv /* Prevent the PCI-E bus from sticking if there is no TLP connection 828169240Sjfv * on the last TLP read/write transaction when MAC is reset. 829169240Sjfv */ 830169240Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 831185353Sjfv if (ret_val) 832169240Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 833169240Sjfv 834169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 835169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 836169240Sjfv 837169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 838169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 839169240Sjfv E1000_WRITE_FLUSH(hw); 840169240Sjfv 841169240Sjfv msec_delay(10); 842169240Sjfv 843169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 844169240Sjfv 845185353Sjfv ret_val = e1000_acquire_phy_80003es2lan(hw); 846256200Sjfv if (ret_val) 847256200Sjfv return ret_val; 848256200Sjfv 849169240Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 850169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 851185353Sjfv e1000_release_phy_80003es2lan(hw); 852169240Sjfv 853256200Sjfv /* Disable IBIST slave mode (far-end loopback) */ 854295323Serj ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 855295323Serj E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data); 856295323Serj if (!ret_val) { 857295323Serj kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 858295323Serj ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 859295323Serj E1000_KMRNCTRLSTA_INBAND_PARAM, 860295323Serj kum_reg_data); 861295323Serj if (ret_val) 862295323Serj DEBUGOUT("Error disabling far-end loopback\n"); 863295323Serj } else 864295323Serj DEBUGOUT("Error disabling far-end loopback\n"); 865256200Sjfv 866169240Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 867169240Sjfv if (ret_val) 868169240Sjfv /* We don't want to continue accessing MAC registers. */ 869256200Sjfv return ret_val; 870169240Sjfv 871169240Sjfv /* Clear any pending interrupt events. */ 872169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 873218588Sjfv E1000_READ_REG(hw, E1000_ICR); 874169240Sjfv 875256200Sjfv return e1000_check_alt_mac_addr_generic(hw); 876169240Sjfv} 877169240Sjfv 878169240Sjfv/** 879169240Sjfv * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 880169589Sjfv * @hw: pointer to the HW structure 881169240Sjfv * 882169240Sjfv * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 883169240Sjfv **/ 884177867Sjfvstatic s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 885169240Sjfv{ 886169240Sjfv struct e1000_mac_info *mac = &hw->mac; 887169240Sjfv u32 reg_data; 888169240Sjfv s32 ret_val; 889218588Sjfv u16 kum_reg_data; 890169240Sjfv u16 i; 891169240Sjfv 892169240Sjfv DEBUGFUNC("e1000_init_hw_80003es2lan"); 893169240Sjfv 894169240Sjfv e1000_initialize_hw_bits_80003es2lan(hw); 895169240Sjfv 896169240Sjfv /* Initialize identification LED */ 897190872Sjfv ret_val = mac->ops.id_led_init(hw); 898256200Sjfv /* An error is not fatal and we should not stop init due to this */ 899200243Sjfv if (ret_val) 900169240Sjfv DEBUGOUT("Error initializing identification LED\n"); 901169240Sjfv 902169240Sjfv /* Disabling VLAN filtering */ 903169240Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 904177867Sjfv mac->ops.clear_vfta(hw); 905169240Sjfv 906169240Sjfv /* Setup the receive address. */ 907169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 908169240Sjfv 909169240Sjfv /* Zero out the Multicast HASH table */ 910169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 911169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 912169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 913169240Sjfv 914169240Sjfv /* Setup link and flow control */ 915177867Sjfv ret_val = mac->ops.setup_link(hw); 916256200Sjfv if (ret_val) 917256200Sjfv return ret_val; 918169240Sjfv 919218588Sjfv /* Disable IBIST slave mode (far-end loopback) */ 920295323Serj ret_val = 921295323Serj e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 922295323Serj &kum_reg_data); 923295323Serj if (!ret_val) { 924295323Serj kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 925295323Serj ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 926295323Serj E1000_KMRNCTRLSTA_INBAND_PARAM, 927295323Serj kum_reg_data); 928295323Serj if (ret_val) 929295323Serj DEBUGOUT("Error disabling far-end loopback\n"); 930295323Serj } else 931295323Serj DEBUGOUT("Error disabling far-end loopback\n"); 932218588Sjfv 933169240Sjfv /* Set the transmit descriptor write-back policy */ 934173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 935256200Sjfv reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 936256200Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 937173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 938169240Sjfv 939169240Sjfv /* ...for both queues. */ 940173788Sjfv reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 941256200Sjfv reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 942256200Sjfv E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 943173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 944169240Sjfv 945169240Sjfv /* Enable retransmit on late collisions */ 946169240Sjfv reg_data = E1000_READ_REG(hw, E1000_TCTL); 947169240Sjfv reg_data |= E1000_TCTL_RTLC; 948169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 949169240Sjfv 950169240Sjfv /* Configure Gigabit Carry Extend Padding */ 951169240Sjfv reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 952169240Sjfv reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 953169240Sjfv reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 954169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 955169240Sjfv 956169240Sjfv /* Configure Transmit Inter-Packet Gap */ 957169240Sjfv reg_data = E1000_READ_REG(hw, E1000_TIPG); 958169240Sjfv reg_data &= ~E1000_TIPG_IPGT_MASK; 959169240Sjfv reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 960169240Sjfv E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 961169240Sjfv 962169240Sjfv reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 963169240Sjfv reg_data &= ~0x00100000; 964169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 965169240Sjfv 966200243Sjfv /* default to TRUE to enable the MDIC W/A */ 967200243Sjfv hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; 968200243Sjfv 969256200Sjfv ret_val = 970256200Sjfv e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> 971256200Sjfv E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); 972200243Sjfv if (!ret_val) { 973200243Sjfv if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 974200243Sjfv E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 975200243Sjfv hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE; 976200243Sjfv } 977200243Sjfv 978256200Sjfv /* Clear all of the statistics registers (clear on read). It is 979169240Sjfv * important that we do this after we have tried to establish link 980169240Sjfv * because the symbol error count will increment wildly if there 981169240Sjfv * is no link. 982169240Sjfv */ 983169240Sjfv e1000_clear_hw_cntrs_80003es2lan(hw); 984169240Sjfv 985169240Sjfv return ret_val; 986169240Sjfv} 987169240Sjfv 988169240Sjfv/** 989169240Sjfv * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 990169589Sjfv * @hw: pointer to the HW structure 991169240Sjfv * 992169240Sjfv * Initializes required hardware-dependent bits needed for normal operation. 993169240Sjfv **/ 994173788Sjfvstatic void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 995169240Sjfv{ 996169240Sjfv u32 reg; 997169240Sjfv 998169240Sjfv DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 999169240Sjfv 1000169240Sjfv /* Transmit Descriptor Control 0 */ 1001173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1002169240Sjfv reg |= (1 << 22); 1003173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1004169240Sjfv 1005169240Sjfv /* Transmit Descriptor Control 1 */ 1006173788Sjfv reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1007169240Sjfv reg |= (1 << 22); 1008173788Sjfv E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1009169240Sjfv 1010169240Sjfv /* Transmit Arbitration Control 0 */ 1011173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(0)); 1012169240Sjfv reg &= ~(0xF << 27); /* 30:27 */ 1013173788Sjfv if (hw->phy.media_type != e1000_media_type_copper) 1014169240Sjfv reg &= ~(1 << 20); 1015173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1016169240Sjfv 1017169240Sjfv /* Transmit Arbitration Control 1 */ 1018173788Sjfv reg = E1000_READ_REG(hw, E1000_TARC(1)); 1019169240Sjfv if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1020169240Sjfv reg &= ~(1 << 28); 1021169240Sjfv else 1022169240Sjfv reg |= (1 << 28); 1023173788Sjfv E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1024169240Sjfv 1025256200Sjfv /* Disable IPv6 extension header parsing because some malformed 1026256200Sjfv * IPv6 headers can hang the Rx. 1027256200Sjfv */ 1028256200Sjfv reg = E1000_READ_REG(hw, E1000_RFCTL); 1029256200Sjfv reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1030256200Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1031256200Sjfv 1032169240Sjfv return; 1033169240Sjfv} 1034169240Sjfv 1035169240Sjfv/** 1036169240Sjfv * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1037169589Sjfv * @hw: pointer to the HW structure 1038169240Sjfv * 1039169240Sjfv * Setup some GG82563 PHY registers for obtaining link 1040169240Sjfv **/ 1041173788Sjfvstatic s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1042169240Sjfv{ 1043176667Sjfv struct e1000_phy_info *phy = &hw->phy; 1044176667Sjfv s32 ret_val; 1045256200Sjfv u32 reg; 1046185353Sjfv u16 data; 1047169240Sjfv 1048169240Sjfv DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1049169240Sjfv 1050228386Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 1051203049Sjfv if (ret_val) 1052256200Sjfv return ret_val; 1053169240Sjfv 1054203049Sjfv data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1055203049Sjfv /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1056203049Sjfv data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1057169240Sjfv 1058228386Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 1059203049Sjfv if (ret_val) 1060256200Sjfv return ret_val; 1061169240Sjfv 1062256200Sjfv /* Options: 1063203049Sjfv * MDI/MDI-X = 0 (default) 1064203049Sjfv * 0 - Auto for all speeds 1065203049Sjfv * 1 - MDI mode 1066203049Sjfv * 2 - MDI-X mode 1067203049Sjfv * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1068203049Sjfv */ 1069203049Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1070203049Sjfv if (ret_val) 1071256200Sjfv return ret_val; 1072169240Sjfv 1073203049Sjfv data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1074169240Sjfv 1075203049Sjfv switch (phy->mdix) { 1076203049Sjfv case 1: 1077203049Sjfv data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1078203049Sjfv break; 1079203049Sjfv case 2: 1080203049Sjfv data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1081203049Sjfv break; 1082203049Sjfv case 0: 1083203049Sjfv default: 1084203049Sjfv data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1085203049Sjfv break; 1086203049Sjfv } 1087169240Sjfv 1088256200Sjfv /* Options: 1089203049Sjfv * disable_polarity_correction = 0 (default) 1090203049Sjfv * Automatic Correction for Reversed Cable Polarity 1091203049Sjfv * 0 - Disabled 1092203049Sjfv * 1 - Enabled 1093203049Sjfv */ 1094203049Sjfv data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1095203049Sjfv if (phy->disable_polarity_correction) 1096203049Sjfv data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1097169240Sjfv 1098203049Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1099203049Sjfv if (ret_val) 1100256200Sjfv return ret_val; 1101169240Sjfv 1102203049Sjfv /* SW Reset the PHY so all changes take effect */ 1103203049Sjfv ret_val = hw->phy.ops.commit(hw); 1104203049Sjfv if (ret_val) { 1105203049Sjfv DEBUGOUT("Error Resetting the PHY\n"); 1106256200Sjfv return ret_val; 1107169240Sjfv } 1108169240Sjfv 1109173788Sjfv /* Bypass Rx and Tx FIFO's */ 1110256200Sjfv reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; 1111256200Sjfv data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1112256200Sjfv E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1113256200Sjfv ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1114169240Sjfv if (ret_val) 1115256200Sjfv return ret_val; 1116169240Sjfv 1117256200Sjfv reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; 1118256200Sjfv ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); 1119173788Sjfv if (ret_val) 1120256200Sjfv return ret_val; 1121173788Sjfv data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1122256200Sjfv ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 1123173788Sjfv if (ret_val) 1124256200Sjfv return ret_val; 1125173788Sjfv 1126177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1127169240Sjfv if (ret_val) 1128256200Sjfv return ret_val; 1129169240Sjfv 1130169240Sjfv data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1131177867Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1132169240Sjfv if (ret_val) 1133256200Sjfv return ret_val; 1134169240Sjfv 1135256200Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1136256200Sjfv reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1137256200Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1138169240Sjfv 1139177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1140169240Sjfv if (ret_val) 1141256200Sjfv return ret_val; 1142169240Sjfv 1143256200Sjfv /* Do not init these registers when the HW is in IAMT mode, since the 1144169240Sjfv * firmware will have already initialized them. We only initialize 1145169240Sjfv * them if the HW is not in IAMT mode. 1146169240Sjfv */ 1147256200Sjfv if (!hw->mac.ops.check_mng_mode(hw)) { 1148169240Sjfv /* Enable Electrical Idle on the PHY */ 1149169240Sjfv data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1150190872Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1151228386Sjfv data); 1152169240Sjfv if (ret_val) 1153256200Sjfv return ret_val; 1154169240Sjfv 1155190872Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1156228386Sjfv &data); 1157190872Sjfv if (ret_val) 1158256200Sjfv return ret_val; 1159190872Sjfv 1160169240Sjfv data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1161190872Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1162228386Sjfv data); 1163169240Sjfv if (ret_val) 1164256200Sjfv return ret_val; 1165169240Sjfv } 1166169240Sjfv 1167256200Sjfv /* Workaround: Disable padding in Kumeran interface in the MAC 1168169240Sjfv * and in the PHY to avoid CRC errors. 1169169240Sjfv */ 1170177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1171169240Sjfv if (ret_val) 1172256200Sjfv return ret_val; 1173169240Sjfv 1174169240Sjfv data |= GG82563_ICR_DIS_PADDING; 1175177867Sjfv ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1176169240Sjfv if (ret_val) 1177256200Sjfv return ret_val; 1178169240Sjfv 1179256200Sjfv return E1000_SUCCESS; 1180169240Sjfv} 1181169240Sjfv 1182169240Sjfv/** 1183169240Sjfv * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1184169589Sjfv * @hw: pointer to the HW structure 1185169240Sjfv * 1186169240Sjfv * Essentially a wrapper for setting up all things "copper" related. 1187169240Sjfv * This is a function pointer entry point called by the mac module. 1188169240Sjfv **/ 1189177867Sjfvstatic s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1190169240Sjfv{ 1191169240Sjfv u32 ctrl; 1192185353Sjfv s32 ret_val; 1193169240Sjfv u16 reg_data; 1194169240Sjfv 1195169240Sjfv DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1196169240Sjfv 1197169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1198169240Sjfv ctrl |= E1000_CTRL_SLU; 1199169240Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1200169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1201169240Sjfv 1202256200Sjfv /* Set the mac to wait the maximum time between each 1203169240Sjfv * iteration and increase the max iterations when 1204173788Sjfv * polling the phy; this fixes erroneous timeouts at 10Mbps. 1205173788Sjfv */ 1206185353Sjfv ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1207228386Sjfv 0xFFFF); 1208169240Sjfv if (ret_val) 1209256200Sjfv return ret_val; 1210185353Sjfv ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1211228386Sjfv ®_data); 1212169240Sjfv if (ret_val) 1213256200Sjfv return ret_val; 1214169240Sjfv reg_data |= 0x3F; 1215185353Sjfv ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1216228386Sjfv reg_data); 1217169240Sjfv if (ret_val) 1218256200Sjfv return ret_val; 1219256200Sjfv ret_val = 1220256200Sjfv e1000_read_kmrn_reg_80003es2lan(hw, 1221256200Sjfv E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1222256200Sjfv ®_data); 1223169240Sjfv if (ret_val) 1224256200Sjfv return ret_val; 1225169240Sjfv reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1226256200Sjfv ret_val = 1227256200Sjfv e1000_write_kmrn_reg_80003es2lan(hw, 1228256200Sjfv E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1229256200Sjfv reg_data); 1230169240Sjfv if (ret_val) 1231256200Sjfv return ret_val; 1232169240Sjfv 1233169240Sjfv ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1234169240Sjfv if (ret_val) 1235256200Sjfv return ret_val; 1236169240Sjfv 1237256200Sjfv return e1000_setup_copper_link_generic(hw); 1238169240Sjfv} 1239169240Sjfv 1240169240Sjfv/** 1241185353Sjfv * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1242185353Sjfv * @hw: pointer to the HW structure 1243185353Sjfv * @duplex: current duplex setting 1244185353Sjfv * 1245185353Sjfv * Configure the KMRN interface by applying last minute quirks for 1246185353Sjfv * 10/100 operation. 1247185353Sjfv **/ 1248185353Sjfvstatic s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1249185353Sjfv{ 1250185353Sjfv s32 ret_val = E1000_SUCCESS; 1251185353Sjfv u16 speed; 1252185353Sjfv u16 duplex; 1253185353Sjfv 1254185353Sjfv DEBUGFUNC("e1000_configure_on_link_up"); 1255185353Sjfv 1256185353Sjfv if (hw->phy.media_type == e1000_media_type_copper) { 1257228386Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, 1258228386Sjfv &duplex); 1259185353Sjfv if (ret_val) 1260256200Sjfv return ret_val; 1261185353Sjfv 1262185353Sjfv if (speed == SPEED_1000) 1263185353Sjfv ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1264185353Sjfv else 1265185353Sjfv ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1266185353Sjfv } 1267185353Sjfv 1268185353Sjfv return ret_val; 1269185353Sjfv} 1270185353Sjfv 1271185353Sjfv/** 1272169240Sjfv * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1273169589Sjfv * @hw: pointer to the HW structure 1274169589Sjfv * @duplex: current duplex setting 1275169240Sjfv * 1276169240Sjfv * Configure the KMRN interface by applying last minute quirks for 1277169240Sjfv * 10/100 operation. 1278169240Sjfv **/ 1279173788Sjfvstatic s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1280169240Sjfv{ 1281256200Sjfv s32 ret_val; 1282169240Sjfv u32 tipg; 1283169589Sjfv u32 i = 0; 1284169589Sjfv u16 reg_data, reg_data2; 1285169240Sjfv 1286169240Sjfv DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1287169240Sjfv 1288169240Sjfv reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1289256200Sjfv ret_val = 1290256200Sjfv e1000_write_kmrn_reg_80003es2lan(hw, 1291256200Sjfv E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1292256200Sjfv reg_data); 1293169240Sjfv if (ret_val) 1294256200Sjfv return ret_val; 1295169240Sjfv 1296169240Sjfv /* Configure Transmit Inter-Packet Gap */ 1297169240Sjfv tipg = E1000_READ_REG(hw, E1000_TIPG); 1298169240Sjfv tipg &= ~E1000_TIPG_IPGT_MASK; 1299169240Sjfv tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1300169240Sjfv E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1301169240Sjfv 1302169589Sjfv do { 1303177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1304228386Sjfv ®_data); 1305169589Sjfv if (ret_val) 1306256200Sjfv return ret_val; 1307169589Sjfv 1308177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1309228386Sjfv ®_data2); 1310169589Sjfv if (ret_val) 1311256200Sjfv return ret_val; 1312169589Sjfv i++; 1313169589Sjfv } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1314169589Sjfv 1315169240Sjfv if (duplex == HALF_DUPLEX) 1316169240Sjfv reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1317169240Sjfv else 1318169240Sjfv reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1319169240Sjfv 1320256200Sjfv return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1321169240Sjfv} 1322169240Sjfv 1323169240Sjfv/** 1324169240Sjfv * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1325169589Sjfv * @hw: pointer to the HW structure 1326169240Sjfv * 1327169240Sjfv * Configure the KMRN interface by applying last minute quirks for 1328169240Sjfv * gigabit operation. 1329169240Sjfv **/ 1330173788Sjfvstatic s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1331169240Sjfv{ 1332256200Sjfv s32 ret_val; 1333169589Sjfv u16 reg_data, reg_data2; 1334169240Sjfv u32 tipg; 1335169589Sjfv u32 i = 0; 1336169240Sjfv 1337169240Sjfv DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1338169240Sjfv 1339169240Sjfv reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1340256200Sjfv ret_val = 1341256200Sjfv e1000_write_kmrn_reg_80003es2lan(hw, 1342256200Sjfv E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1343256200Sjfv reg_data); 1344169240Sjfv if (ret_val) 1345256200Sjfv return ret_val; 1346169240Sjfv 1347169240Sjfv /* Configure Transmit Inter-Packet Gap */ 1348169240Sjfv tipg = E1000_READ_REG(hw, E1000_TIPG); 1349169240Sjfv tipg &= ~E1000_TIPG_IPGT_MASK; 1350169240Sjfv tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1351169240Sjfv E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1352169240Sjfv 1353169589Sjfv do { 1354177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1355228386Sjfv ®_data); 1356169589Sjfv if (ret_val) 1357256200Sjfv return ret_val; 1358169589Sjfv 1359177867Sjfv ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1360228386Sjfv ®_data2); 1361169589Sjfv if (ret_val) 1362256200Sjfv return ret_val; 1363169589Sjfv i++; 1364169589Sjfv } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1365169589Sjfv 1366169240Sjfv reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1367169240Sjfv 1368256200Sjfv return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1369169240Sjfv} 1370169240Sjfv 1371169240Sjfv/** 1372185353Sjfv * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1373185353Sjfv * @hw: pointer to the HW structure 1374185353Sjfv * @offset: register offset to be read 1375185353Sjfv * @data: pointer to the read data 1376185353Sjfv * 1377185353Sjfv * Acquire semaphore, then read the PHY register at offset 1378185353Sjfv * using the kumeran interface. The information retrieved is stored in data. 1379185353Sjfv * Release the semaphore before exiting. 1380185353Sjfv **/ 1381190872Sjfvstatic s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1382228386Sjfv u16 *data) 1383185353Sjfv{ 1384185353Sjfv u32 kmrnctrlsta; 1385256200Sjfv s32 ret_val; 1386185353Sjfv 1387185353Sjfv DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1388185353Sjfv 1389185353Sjfv ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1390185353Sjfv if (ret_val) 1391256200Sjfv return ret_val; 1392185353Sjfv 1393185353Sjfv kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1394228386Sjfv E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1395185353Sjfv E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1396228386Sjfv E1000_WRITE_FLUSH(hw); 1397185353Sjfv 1398185353Sjfv usec_delay(2); 1399185353Sjfv 1400185353Sjfv kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1401185353Sjfv *data = (u16)kmrnctrlsta; 1402185353Sjfv 1403185353Sjfv e1000_release_mac_csr_80003es2lan(hw); 1404185353Sjfv 1405185353Sjfv return ret_val; 1406185353Sjfv} 1407185353Sjfv 1408185353Sjfv/** 1409185353Sjfv * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1410185353Sjfv * @hw: pointer to the HW structure 1411185353Sjfv * @offset: register offset to write to 1412185353Sjfv * @data: data to write at register offset 1413185353Sjfv * 1414185353Sjfv * Acquire semaphore, then write the data to PHY register 1415185353Sjfv * at the offset using the kumeran interface. Release semaphore 1416185353Sjfv * before exiting. 1417185353Sjfv **/ 1418190872Sjfvstatic s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1419228386Sjfv u16 data) 1420185353Sjfv{ 1421185353Sjfv u32 kmrnctrlsta; 1422256200Sjfv s32 ret_val; 1423185353Sjfv 1424185353Sjfv DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1425185353Sjfv 1426185353Sjfv ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1427185353Sjfv if (ret_val) 1428256200Sjfv return ret_val; 1429185353Sjfv 1430185353Sjfv kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1431228386Sjfv E1000_KMRNCTRLSTA_OFFSET) | data; 1432185353Sjfv E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1433228386Sjfv E1000_WRITE_FLUSH(hw); 1434185353Sjfv 1435185353Sjfv usec_delay(2); 1436185353Sjfv 1437185353Sjfv e1000_release_mac_csr_80003es2lan(hw); 1438185353Sjfv 1439185353Sjfv return ret_val; 1440185353Sjfv} 1441185353Sjfv 1442185353Sjfv/** 1443176667Sjfv * e1000_read_mac_addr_80003es2lan - Read device MAC address 1444176667Sjfv * @hw: pointer to the HW structure 1445176667Sjfv **/ 1446177867Sjfvstatic s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1447176667Sjfv{ 1448256200Sjfv s32 ret_val; 1449176667Sjfv 1450176667Sjfv DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1451176667Sjfv 1452256200Sjfv /* If there's an alternate MAC address place it in RAR0 1453190872Sjfv * so that it will override the Si installed default perm 1454190872Sjfv * address. 1455190872Sjfv */ 1456190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1457190872Sjfv if (ret_val) 1458256200Sjfv return ret_val; 1459190872Sjfv 1460256200Sjfv return e1000_read_mac_addr_generic(hw); 1461176667Sjfv} 1462176667Sjfv 1463176667Sjfv/** 1464173788Sjfv * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1465173788Sjfv * @hw: pointer to the HW structure 1466173788Sjfv * 1467173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 1468173788Sjfv * driver unload, or wake on lan is not enabled, remove the link. 1469173788Sjfv **/ 1470177867Sjfvstatic void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1471173788Sjfv{ 1472173788Sjfv /* If the management interface is not enabled, then power down */ 1473177867Sjfv if (!(hw->mac.ops.check_mng_mode(hw) || 1474177867Sjfv hw->phy.ops.check_reset_block(hw))) 1475173788Sjfv e1000_power_down_phy_copper(hw); 1476173788Sjfv 1477173788Sjfv return; 1478173788Sjfv} 1479173788Sjfv 1480173788Sjfv/** 1481169240Sjfv * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1482169589Sjfv * @hw: pointer to the HW structure 1483169240Sjfv * 1484169240Sjfv * Clears the hardware counters by reading the counter registers. 1485169240Sjfv **/ 1486177867Sjfvstatic void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1487169240Sjfv{ 1488169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1489169240Sjfv 1490169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 1491169240Sjfv 1492185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 1493185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 1494185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 1495185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 1496185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 1497185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 1498185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 1499185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 1500185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 1501185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 1502185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 1503185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 1504169240Sjfv 1505185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 1506185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 1507185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 1508185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 1509185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 1510185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 1511169240Sjfv 1512185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 1513185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 1514185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 1515169240Sjfv 1516185353Sjfv E1000_READ_REG(hw, E1000_IAC); 1517185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 1518169240Sjfv 1519185353Sjfv E1000_READ_REG(hw, E1000_ICRXPTC); 1520185353Sjfv E1000_READ_REG(hw, E1000_ICRXATC); 1521185353Sjfv E1000_READ_REG(hw, E1000_ICTXPTC); 1522185353Sjfv E1000_READ_REG(hw, E1000_ICTXATC); 1523185353Sjfv E1000_READ_REG(hw, E1000_ICTXQEC); 1524185353Sjfv E1000_READ_REG(hw, E1000_ICTXQMTC); 1525185353Sjfv E1000_READ_REG(hw, E1000_ICRXDMTC); 1526169240Sjfv} 1527