rs600.c revision 255573
1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell/* RS600 / Radeon X1250/X1270 integrated GPU 29254885Sdumbbell * 30254885Sdumbbell * This file gather function specific to RS600 which is the IGP of 31254885Sdumbbell * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32254885Sdumbbell * is the X1250/X1270 supporting AMD CPU). The display engine are 33254885Sdumbbell * the avivo one, bios is an atombios, 3D block are the one of the 34254885Sdumbbell * R4XX family. The GART is different from the RS400 one and is very 35254885Sdumbbell * close to the one of the R600 family (R600 likely being an evolution 36254885Sdumbbell * of the RS600 GART block). 37254885Sdumbbell */ 38254885Sdumbbell 39254885Sdumbbell#include <sys/cdefs.h> 40254885Sdumbbell__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/rs600.c 255573 2013-09-14 17:24:41Z dumbbell $"); 41254885Sdumbbell 42254885Sdumbbell#include <dev/drm2/drmP.h> 43254885Sdumbbell#include "radeon.h" 44254885Sdumbbell#include "radeon_asic.h" 45254885Sdumbbell#include "atom.h" 46254885Sdumbbell#include "rs600d.h" 47254885Sdumbbell 48254885Sdumbbell#include "rs600_reg_safe.h" 49254885Sdumbbell 50254885Sdumbbellstatic void rs600_gpu_init(struct radeon_device *rdev); 51254885Sdumbbell 52254885Sdumbbellstatic const u32 crtc_offsets[2] = 53254885Sdumbbell{ 54254885Sdumbbell 0, 55254885Sdumbbell AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 56254885Sdumbbell}; 57254885Sdumbbell 58254885Sdumbbellvoid avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 59254885Sdumbbell{ 60254885Sdumbbell int i; 61254885Sdumbbell 62254885Sdumbbell if (crtc >= rdev->num_crtc) 63254885Sdumbbell return; 64254885Sdumbbell 65254885Sdumbbell if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { 66254885Sdumbbell for (i = 0; i < rdev->usec_timeout; i++) { 67254885Sdumbbell if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) 68254885Sdumbbell break; 69254885Sdumbbell DRM_UDELAY(1); 70254885Sdumbbell } 71254885Sdumbbell for (i = 0; i < rdev->usec_timeout; i++) { 72254885Sdumbbell if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 73254885Sdumbbell break; 74254885Sdumbbell DRM_UDELAY(1); 75254885Sdumbbell } 76254885Sdumbbell } 77254885Sdumbbell} 78254885Sdumbbell 79254885Sdumbbellvoid rs600_pre_page_flip(struct radeon_device *rdev, int crtc) 80254885Sdumbbell{ 81254885Sdumbbell /* enable the pflip int */ 82254885Sdumbbell radeon_irq_kms_pflip_irq_get(rdev, crtc); 83254885Sdumbbell} 84254885Sdumbbell 85254885Sdumbbellvoid rs600_post_page_flip(struct radeon_device *rdev, int crtc) 86254885Sdumbbell{ 87254885Sdumbbell /* disable the pflip int */ 88254885Sdumbbell radeon_irq_kms_pflip_irq_put(rdev, crtc); 89254885Sdumbbell} 90254885Sdumbbell 91254885Sdumbbellu32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 92254885Sdumbbell{ 93254885Sdumbbell struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 94254885Sdumbbell u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 95254885Sdumbbell int i; 96254885Sdumbbell 97254885Sdumbbell /* Lock the graphics update lock */ 98254885Sdumbbell tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 99254885Sdumbbell WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 100254885Sdumbbell 101254885Sdumbbell /* update the scanout addresses */ 102254885Sdumbbell WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 103254885Sdumbbell (u32)crtc_base); 104254885Sdumbbell WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 105254885Sdumbbell (u32)crtc_base); 106254885Sdumbbell 107254885Sdumbbell /* Wait for update_pending to go high. */ 108254885Sdumbbell for (i = 0; i < rdev->usec_timeout; i++) { 109254885Sdumbbell if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 110254885Sdumbbell break; 111254885Sdumbbell DRM_UDELAY(1); 112254885Sdumbbell } 113254885Sdumbbell DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 114254885Sdumbbell 115254885Sdumbbell /* Unlock the lock, so double-buffering can take place inside vblank */ 116254885Sdumbbell tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 117254885Sdumbbell WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 118254885Sdumbbell 119254885Sdumbbell /* Return current update_pending status: */ 120254885Sdumbbell return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 121254885Sdumbbell} 122254885Sdumbbell 123254885Sdumbbellvoid rs600_pm_misc(struct radeon_device *rdev) 124254885Sdumbbell{ 125254885Sdumbbell int requested_index = rdev->pm.requested_power_state_index; 126254885Sdumbbell struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 127254885Sdumbbell struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 128254885Sdumbbell u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 129254885Sdumbbell u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 130254885Sdumbbell 131254885Sdumbbell if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 132254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 133254885Sdumbbell tmp = RREG32(voltage->gpio.reg); 134254885Sdumbbell if (voltage->active_high) 135254885Sdumbbell tmp |= voltage->gpio.mask; 136254885Sdumbbell else 137254885Sdumbbell tmp &= ~(voltage->gpio.mask); 138254885Sdumbbell WREG32(voltage->gpio.reg, tmp); 139254885Sdumbbell if (voltage->delay) 140254885Sdumbbell DRM_UDELAY(voltage->delay); 141254885Sdumbbell } else { 142254885Sdumbbell tmp = RREG32(voltage->gpio.reg); 143254885Sdumbbell if (voltage->active_high) 144254885Sdumbbell tmp &= ~voltage->gpio.mask; 145254885Sdumbbell else 146254885Sdumbbell tmp |= voltage->gpio.mask; 147254885Sdumbbell WREG32(voltage->gpio.reg, tmp); 148254885Sdumbbell if (voltage->delay) 149254885Sdumbbell DRM_UDELAY(voltage->delay); 150254885Sdumbbell } 151254885Sdumbbell } else if (voltage->type == VOLTAGE_VDDC) 152254885Sdumbbell radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 153254885Sdumbbell 154254885Sdumbbell dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 155254885Sdumbbell dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 156254885Sdumbbell dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 157254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 158254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 159254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 160254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 161254885Sdumbbell } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 162254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 163254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 164254885Sdumbbell } 165254885Sdumbbell } else { 166254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 167254885Sdumbbell dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 168254885Sdumbbell } 169254885Sdumbbell WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 170254885Sdumbbell 171254885Sdumbbell dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 172254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 173254885Sdumbbell dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 174254885Sdumbbell if (voltage->delay) { 175254885Sdumbbell dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 176254885Sdumbbell dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 177254885Sdumbbell } else 178254885Sdumbbell dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 179254885Sdumbbell } else 180254885Sdumbbell dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 181254885Sdumbbell WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 182254885Sdumbbell 183254885Sdumbbell hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 184254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 185254885Sdumbbell hdp_dyn_cntl &= ~HDP_FORCEON; 186254885Sdumbbell else 187254885Sdumbbell hdp_dyn_cntl |= HDP_FORCEON; 188254885Sdumbbell WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 189254885Sdumbbell#if 0 190254885Sdumbbell /* mc_host_dyn seems to cause hangs from time to time */ 191254885Sdumbbell mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 192254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 193254885Sdumbbell mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 194254885Sdumbbell else 195254885Sdumbbell mc_host_dyn_cntl |= MC_HOST_FORCEON; 196254885Sdumbbell WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 197254885Sdumbbell#endif 198254885Sdumbbell dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 199254885Sdumbbell if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 200254885Sdumbbell dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 201254885Sdumbbell else 202254885Sdumbbell dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 203254885Sdumbbell WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 204254885Sdumbbell 205254885Sdumbbell /* set pcie lanes */ 206254885Sdumbbell if ((rdev->flags & RADEON_IS_PCIE) && 207254885Sdumbbell !(rdev->flags & RADEON_IS_IGP) && 208254885Sdumbbell rdev->asic->pm.set_pcie_lanes && 209254885Sdumbbell (ps->pcie_lanes != 210254885Sdumbbell rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 211254885Sdumbbell radeon_set_pcie_lanes(rdev, 212254885Sdumbbell ps->pcie_lanes); 213254885Sdumbbell DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 214254885Sdumbbell } 215254885Sdumbbell} 216254885Sdumbbell 217254885Sdumbbellvoid rs600_pm_prepare(struct radeon_device *rdev) 218254885Sdumbbell{ 219254885Sdumbbell struct drm_device *ddev = rdev->ddev; 220254885Sdumbbell struct drm_crtc *crtc; 221254885Sdumbbell struct radeon_crtc *radeon_crtc; 222254885Sdumbbell u32 tmp; 223254885Sdumbbell 224254885Sdumbbell /* disable any active CRTCs */ 225254885Sdumbbell list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 226254885Sdumbbell radeon_crtc = to_radeon_crtc(crtc); 227254885Sdumbbell if (radeon_crtc->enabled) { 228254885Sdumbbell tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 229254885Sdumbbell tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 230254885Sdumbbell WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 231254885Sdumbbell } 232254885Sdumbbell } 233254885Sdumbbell} 234254885Sdumbbell 235254885Sdumbbellvoid rs600_pm_finish(struct radeon_device *rdev) 236254885Sdumbbell{ 237254885Sdumbbell struct drm_device *ddev = rdev->ddev; 238254885Sdumbbell struct drm_crtc *crtc; 239254885Sdumbbell struct radeon_crtc *radeon_crtc; 240254885Sdumbbell u32 tmp; 241254885Sdumbbell 242254885Sdumbbell /* enable any active CRTCs */ 243254885Sdumbbell list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 244254885Sdumbbell radeon_crtc = to_radeon_crtc(crtc); 245254885Sdumbbell if (radeon_crtc->enabled) { 246254885Sdumbbell tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 247254885Sdumbbell tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 248254885Sdumbbell WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 249254885Sdumbbell } 250254885Sdumbbell } 251254885Sdumbbell} 252254885Sdumbbell 253254885Sdumbbell/* hpd for digital panel detect/disconnect */ 254254885Sdumbbellbool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 255254885Sdumbbell{ 256254885Sdumbbell u32 tmp; 257254885Sdumbbell bool connected = false; 258254885Sdumbbell 259254885Sdumbbell switch (hpd) { 260254885Sdumbbell case RADEON_HPD_1: 261254885Sdumbbell tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 262254885Sdumbbell if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 263254885Sdumbbell connected = true; 264254885Sdumbbell break; 265254885Sdumbbell case RADEON_HPD_2: 266254885Sdumbbell tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 267254885Sdumbbell if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 268254885Sdumbbell connected = true; 269254885Sdumbbell break; 270254885Sdumbbell default: 271254885Sdumbbell break; 272254885Sdumbbell } 273254885Sdumbbell return connected; 274254885Sdumbbell} 275254885Sdumbbell 276254885Sdumbbellvoid rs600_hpd_set_polarity(struct radeon_device *rdev, 277254885Sdumbbell enum radeon_hpd_id hpd) 278254885Sdumbbell{ 279254885Sdumbbell u32 tmp; 280254885Sdumbbell bool connected = rs600_hpd_sense(rdev, hpd); 281254885Sdumbbell 282254885Sdumbbell switch (hpd) { 283254885Sdumbbell case RADEON_HPD_1: 284254885Sdumbbell tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 285254885Sdumbbell if (connected) 286254885Sdumbbell tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 287254885Sdumbbell else 288254885Sdumbbell tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 289254885Sdumbbell WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 290254885Sdumbbell break; 291254885Sdumbbell case RADEON_HPD_2: 292254885Sdumbbell tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 293254885Sdumbbell if (connected) 294254885Sdumbbell tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 295254885Sdumbbell else 296254885Sdumbbell tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 297254885Sdumbbell WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 298254885Sdumbbell break; 299254885Sdumbbell default: 300254885Sdumbbell break; 301254885Sdumbbell } 302254885Sdumbbell} 303254885Sdumbbell 304254885Sdumbbellvoid rs600_hpd_init(struct radeon_device *rdev) 305254885Sdumbbell{ 306254885Sdumbbell struct drm_device *dev = rdev->ddev; 307254885Sdumbbell struct drm_connector *connector; 308254885Sdumbbell unsigned enable = 0; 309254885Sdumbbell 310254885Sdumbbell list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 311254885Sdumbbell struct radeon_connector *radeon_connector = to_radeon_connector(connector); 312254885Sdumbbell switch (radeon_connector->hpd.hpd) { 313254885Sdumbbell case RADEON_HPD_1: 314254885Sdumbbell WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 315254885Sdumbbell S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 316254885Sdumbbell break; 317254885Sdumbbell case RADEON_HPD_2: 318254885Sdumbbell WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 319254885Sdumbbell S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 320254885Sdumbbell break; 321254885Sdumbbell default: 322254885Sdumbbell break; 323254885Sdumbbell } 324254885Sdumbbell enable |= 1 << radeon_connector->hpd.hpd; 325254885Sdumbbell radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 326254885Sdumbbell } 327254885Sdumbbell radeon_irq_kms_enable_hpd(rdev, enable); 328254885Sdumbbell} 329254885Sdumbbell 330254885Sdumbbellvoid rs600_hpd_fini(struct radeon_device *rdev) 331254885Sdumbbell{ 332254885Sdumbbell struct drm_device *dev = rdev->ddev; 333254885Sdumbbell struct drm_connector *connector; 334254885Sdumbbell unsigned disable = 0; 335254885Sdumbbell 336254885Sdumbbell list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 337254885Sdumbbell struct radeon_connector *radeon_connector = to_radeon_connector(connector); 338254885Sdumbbell switch (radeon_connector->hpd.hpd) { 339254885Sdumbbell case RADEON_HPD_1: 340254885Sdumbbell WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 341254885Sdumbbell S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 342254885Sdumbbell break; 343254885Sdumbbell case RADEON_HPD_2: 344254885Sdumbbell WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 345254885Sdumbbell S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 346254885Sdumbbell break; 347254885Sdumbbell default: 348254885Sdumbbell break; 349254885Sdumbbell } 350254885Sdumbbell disable |= 1 << radeon_connector->hpd.hpd; 351254885Sdumbbell } 352254885Sdumbbell radeon_irq_kms_disable_hpd(rdev, disable); 353254885Sdumbbell} 354254885Sdumbbell 355254885Sdumbbellint rs600_asic_reset(struct radeon_device *rdev) 356254885Sdumbbell{ 357254885Sdumbbell struct rv515_mc_save save; 358254885Sdumbbell u32 status, tmp; 359254885Sdumbbell int ret = 0; 360254885Sdumbbell 361254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 362254885Sdumbbell if (!G_000E40_GUI_ACTIVE(status)) { 363254885Sdumbbell return 0; 364254885Sdumbbell } 365254885Sdumbbell /* Stops all mc clients */ 366254885Sdumbbell rv515_mc_stop(rdev, &save); 367254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 368254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 369254885Sdumbbell /* stop CP */ 370254885Sdumbbell WREG32(RADEON_CP_CSQ_CNTL, 0); 371254885Sdumbbell tmp = RREG32(RADEON_CP_RB_CNTL); 372254885Sdumbbell WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 373254885Sdumbbell WREG32(RADEON_CP_RB_RPTR_WR, 0); 374254885Sdumbbell WREG32(RADEON_CP_RB_WPTR, 0); 375254885Sdumbbell WREG32(RADEON_CP_RB_CNTL, tmp); 376255573Sdumbbell pci_save_state(device_get_parent(rdev->dev)); 377254885Sdumbbell /* disable bus mastering */ 378254885Sdumbbell pci_disable_busmaster(rdev->dev); 379254885Sdumbbell DRM_MDELAY(1); 380254885Sdumbbell /* reset GA+VAP */ 381254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 382254885Sdumbbell S_0000F0_SOFT_RESET_GA(1)); 383254885Sdumbbell RREG32(R_0000F0_RBBM_SOFT_RESET); 384254885Sdumbbell DRM_MDELAY(500); 385254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 386254885Sdumbbell DRM_MDELAY(1); 387254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 388254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 389254885Sdumbbell /* reset CP */ 390254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 391254885Sdumbbell RREG32(R_0000F0_RBBM_SOFT_RESET); 392254885Sdumbbell DRM_MDELAY(500); 393254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 394254885Sdumbbell DRM_MDELAY(1); 395254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 396254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 397254885Sdumbbell /* reset MC */ 398254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 399254885Sdumbbell RREG32(R_0000F0_RBBM_SOFT_RESET); 400254885Sdumbbell DRM_MDELAY(500); 401254885Sdumbbell WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 402254885Sdumbbell DRM_MDELAY(1); 403254885Sdumbbell status = RREG32(R_000E40_RBBM_STATUS); 404254885Sdumbbell dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 405254885Sdumbbell /* restore PCI & busmastering */ 406255573Sdumbbell pci_restore_state(device_get_parent(rdev->dev)); 407254885Sdumbbell /* Check if GPU is idle */ 408254885Sdumbbell if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 409254885Sdumbbell dev_err(rdev->dev, "failed to reset GPU\n"); 410254885Sdumbbell ret = -1; 411254885Sdumbbell } else 412254885Sdumbbell dev_info(rdev->dev, "GPU reset succeed\n"); 413254885Sdumbbell rv515_mc_resume(rdev, &save); 414254885Sdumbbell return ret; 415254885Sdumbbell} 416254885Sdumbbell 417254885Sdumbbell/* 418254885Sdumbbell * GART. 419254885Sdumbbell */ 420254885Sdumbbellvoid rs600_gart_tlb_flush(struct radeon_device *rdev) 421254885Sdumbbell{ 422254885Sdumbbell uint32_t tmp; 423254885Sdumbbell 424254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 425254885Sdumbbell tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 426254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 427254885Sdumbbell 428254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 429254885Sdumbbell tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 430254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 431254885Sdumbbell 432254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 433254885Sdumbbell tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 434254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 435254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 436254885Sdumbbell} 437254885Sdumbbell 438254885Sdumbbellstatic int rs600_gart_init(struct radeon_device *rdev) 439254885Sdumbbell{ 440254885Sdumbbell int r; 441254885Sdumbbell 442254885Sdumbbell if (rdev->gart.robj) { 443254885Sdumbbell DRM_ERROR("RS600 GART already initialized\n"); 444254885Sdumbbell return 0; 445254885Sdumbbell } 446254885Sdumbbell /* Initialize common gart structure */ 447254885Sdumbbell r = radeon_gart_init(rdev); 448254885Sdumbbell if (r) { 449254885Sdumbbell return r; 450254885Sdumbbell } 451254885Sdumbbell rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 452254885Sdumbbell return radeon_gart_table_vram_alloc(rdev); 453254885Sdumbbell} 454254885Sdumbbell 455254885Sdumbbellstatic int rs600_gart_enable(struct radeon_device *rdev) 456254885Sdumbbell{ 457254885Sdumbbell u32 tmp; 458254885Sdumbbell int r, i; 459254885Sdumbbell 460254885Sdumbbell if (rdev->gart.robj == NULL) { 461254885Sdumbbell dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 462254885Sdumbbell return -EINVAL; 463254885Sdumbbell } 464254885Sdumbbell r = radeon_gart_table_vram_pin(rdev); 465254885Sdumbbell if (r) 466254885Sdumbbell return r; 467254885Sdumbbell radeon_gart_restore(rdev); 468254885Sdumbbell /* Enable bus master */ 469254885Sdumbbell tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 470254885Sdumbbell WREG32(RADEON_BUS_CNTL, tmp); 471254885Sdumbbell /* FIXME: setup default page */ 472254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, 473254885Sdumbbell (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 474254885Sdumbbell S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 475254885Sdumbbell 476254885Sdumbbell for (i = 0; i < 19; i++) { 477254885Sdumbbell WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 478254885Sdumbbell S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 479254885Sdumbbell S_00016C_SYSTEM_ACCESS_MODE_MASK( 480254885Sdumbbell V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 481254885Sdumbbell S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 482254885Sdumbbell V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 483254885Sdumbbell S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 484254885Sdumbbell S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 485254885Sdumbbell S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 486254885Sdumbbell } 487254885Sdumbbell /* enable first context */ 488254885Sdumbbell WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 489254885Sdumbbell S_000102_ENABLE_PAGE_TABLE(1) | 490254885Sdumbbell S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 491254885Sdumbbell 492254885Sdumbbell /* disable all other contexts */ 493254885Sdumbbell for (i = 1; i < 8; i++) 494254885Sdumbbell WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 495254885Sdumbbell 496254885Sdumbbell /* setup the page table */ 497254885Sdumbbell WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 498254885Sdumbbell rdev->gart.table_addr); 499254885Sdumbbell WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 500254885Sdumbbell WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 501254885Sdumbbell WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 502254885Sdumbbell 503254885Sdumbbell /* System context maps to VRAM space */ 504254885Sdumbbell WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 505254885Sdumbbell WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 506254885Sdumbbell 507254885Sdumbbell /* enable page tables */ 508254885Sdumbbell tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 509254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 510254885Sdumbbell tmp = RREG32_MC(R_000009_MC_CNTL1); 511254885Sdumbbell WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 512254885Sdumbbell rs600_gart_tlb_flush(rdev); 513254885Sdumbbell DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 514254885Sdumbbell (unsigned)(rdev->mc.gtt_size >> 20), 515254885Sdumbbell (unsigned long long)rdev->gart.table_addr); 516254885Sdumbbell rdev->gart.ready = true; 517254885Sdumbbell return 0; 518254885Sdumbbell} 519254885Sdumbbell 520254885Sdumbbellstatic void rs600_gart_disable(struct radeon_device *rdev) 521254885Sdumbbell{ 522254885Sdumbbell u32 tmp; 523254885Sdumbbell 524254885Sdumbbell /* FIXME: disable out of gart access */ 525254885Sdumbbell WREG32_MC(R_000100_MC_PT0_CNTL, 0); 526254885Sdumbbell tmp = RREG32_MC(R_000009_MC_CNTL1); 527254885Sdumbbell WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 528254885Sdumbbell radeon_gart_table_vram_unpin(rdev); 529254885Sdumbbell} 530254885Sdumbbell 531254885Sdumbbellstatic void rs600_gart_fini(struct radeon_device *rdev) 532254885Sdumbbell{ 533254885Sdumbbell radeon_gart_fini(rdev); 534254885Sdumbbell rs600_gart_disable(rdev); 535254885Sdumbbell radeon_gart_table_vram_free(rdev); 536254885Sdumbbell} 537254885Sdumbbell 538254885Sdumbbell#define R600_PTE_VALID (1 << 0) 539254885Sdumbbell#define R600_PTE_SYSTEM (1 << 1) 540254885Sdumbbell#define R600_PTE_SNOOPED (1 << 2) 541254885Sdumbbell#define R600_PTE_READABLE (1 << 5) 542254885Sdumbbell#define R600_PTE_WRITEABLE (1 << 6) 543254885Sdumbbell 544254885Sdumbbellint rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 545254885Sdumbbell{ 546254885Sdumbbell uint64_t *ptr = rdev->gart.ptr; 547254885Sdumbbell 548254885Sdumbbell if (i < 0 || i > rdev->gart.num_gpu_pages) { 549254885Sdumbbell return -EINVAL; 550254885Sdumbbell } 551254885Sdumbbell addr = addr & 0xFFFFFFFFFFFFF000ULL; 552254885Sdumbbell addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 553254885Sdumbbell addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 554254885Sdumbbell ptr[i] = addr; 555254885Sdumbbell return 0; 556254885Sdumbbell} 557254885Sdumbbell 558254885Sdumbbellint rs600_irq_set(struct radeon_device *rdev) 559254885Sdumbbell{ 560254885Sdumbbell uint32_t tmp = 0; 561254885Sdumbbell uint32_t mode_int = 0; 562254885Sdumbbell u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 563254885Sdumbbell ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 564254885Sdumbbell u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 565254885Sdumbbell ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 566254885Sdumbbell u32 hdmi0; 567254885Sdumbbell if (ASIC_IS_DCE2(rdev)) 568254885Sdumbbell hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 569254885Sdumbbell ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 570254885Sdumbbell else 571254885Sdumbbell hdmi0 = 0; 572254885Sdumbbell 573254885Sdumbbell if (!rdev->irq.installed) { 574254885Sdumbbell DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n"); 575254885Sdumbbell WREG32(R_000040_GEN_INT_CNTL, 0); 576254885Sdumbbell return -EINVAL; 577254885Sdumbbell } 578254885Sdumbbell if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 579254885Sdumbbell tmp |= S_000040_SW_INT_EN(1); 580254885Sdumbbell } 581254885Sdumbbell if (rdev->irq.crtc_vblank_int[0] || 582254885Sdumbbell atomic_read(&rdev->irq.pflip[0])) { 583254885Sdumbbell mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 584254885Sdumbbell } 585254885Sdumbbell if (rdev->irq.crtc_vblank_int[1] || 586254885Sdumbbell atomic_read(&rdev->irq.pflip[1])) { 587254885Sdumbbell mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 588254885Sdumbbell } 589254885Sdumbbell if (rdev->irq.hpd[0]) { 590254885Sdumbbell hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 591254885Sdumbbell } 592254885Sdumbbell if (rdev->irq.hpd[1]) { 593254885Sdumbbell hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 594254885Sdumbbell } 595254885Sdumbbell if (rdev->irq.afmt[0]) { 596254885Sdumbbell hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 597254885Sdumbbell } 598254885Sdumbbell WREG32(R_000040_GEN_INT_CNTL, tmp); 599254885Sdumbbell WREG32(R_006540_DxMODE_INT_MASK, mode_int); 600254885Sdumbbell WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 601254885Sdumbbell WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 602254885Sdumbbell if (ASIC_IS_DCE2(rdev)) 603254885Sdumbbell WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 604254885Sdumbbell return 0; 605254885Sdumbbell} 606254885Sdumbbell 607254885Sdumbbellstatic inline u32 rs600_irq_ack(struct radeon_device *rdev) 608254885Sdumbbell{ 609254885Sdumbbell uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 610254885Sdumbbell uint32_t irq_mask = S_000044_SW_INT(1); 611254885Sdumbbell u32 tmp; 612254885Sdumbbell 613254885Sdumbbell if (G_000044_DISPLAY_INT_STAT(irqs)) { 614254885Sdumbbell rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 615254885Sdumbbell if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 616254885Sdumbbell WREG32(R_006534_D1MODE_VBLANK_STATUS, 617254885Sdumbbell S_006534_D1MODE_VBLANK_ACK(1)); 618254885Sdumbbell } 619254885Sdumbbell if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 620254885Sdumbbell WREG32(R_006D34_D2MODE_VBLANK_STATUS, 621254885Sdumbbell S_006D34_D2MODE_VBLANK_ACK(1)); 622254885Sdumbbell } 623254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 624254885Sdumbbell tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 625254885Sdumbbell tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 626254885Sdumbbell WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 627254885Sdumbbell } 628254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 629254885Sdumbbell tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 630254885Sdumbbell tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 631254885Sdumbbell WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 632254885Sdumbbell } 633254885Sdumbbell } else { 634254885Sdumbbell rdev->irq.stat_regs.r500.disp_int = 0; 635254885Sdumbbell } 636254885Sdumbbell 637254885Sdumbbell if (ASIC_IS_DCE2(rdev)) { 638254885Sdumbbell rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 639254885Sdumbbell S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 640254885Sdumbbell if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 641254885Sdumbbell tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 642254885Sdumbbell tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 643254885Sdumbbell WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 644254885Sdumbbell } 645254885Sdumbbell } else 646254885Sdumbbell rdev->irq.stat_regs.r500.hdmi0_status = 0; 647254885Sdumbbell 648254885Sdumbbell if (irqs) { 649254885Sdumbbell WREG32(R_000044_GEN_INT_STATUS, irqs); 650254885Sdumbbell } 651254885Sdumbbell return irqs & irq_mask; 652254885Sdumbbell} 653254885Sdumbbell 654254885Sdumbbellvoid rs600_irq_disable(struct radeon_device *rdev) 655254885Sdumbbell{ 656254885Sdumbbell u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 657254885Sdumbbell ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 658254885Sdumbbell WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 659254885Sdumbbell WREG32(R_000040_GEN_INT_CNTL, 0); 660254885Sdumbbell WREG32(R_006540_DxMODE_INT_MASK, 0); 661254885Sdumbbell /* Wait and acknowledge irq */ 662254885Sdumbbell DRM_MDELAY(1); 663254885Sdumbbell rs600_irq_ack(rdev); 664254885Sdumbbell} 665254885Sdumbbell 666254885Sdumbbellirqreturn_t rs600_irq_process(struct radeon_device *rdev) 667254885Sdumbbell{ 668254885Sdumbbell u32 status, msi_rearm; 669254885Sdumbbell bool queue_hotplug = false; 670254885Sdumbbell bool queue_hdmi = false; 671254885Sdumbbell 672254885Sdumbbell status = rs600_irq_ack(rdev); 673254885Sdumbbell if (!status && 674254885Sdumbbell !rdev->irq.stat_regs.r500.disp_int && 675254885Sdumbbell !rdev->irq.stat_regs.r500.hdmi0_status) { 676254885Sdumbbell return IRQ_NONE; 677254885Sdumbbell } 678254885Sdumbbell while (status || 679254885Sdumbbell rdev->irq.stat_regs.r500.disp_int || 680254885Sdumbbell rdev->irq.stat_regs.r500.hdmi0_status) { 681254885Sdumbbell /* SW interrupt */ 682254885Sdumbbell if (G_000044_SW_INT(status)) { 683254885Sdumbbell radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 684254885Sdumbbell } 685254885Sdumbbell /* Vertical blank interrupts */ 686254885Sdumbbell if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 687254885Sdumbbell if (rdev->irq.crtc_vblank_int[0]) { 688254885Sdumbbell drm_handle_vblank(rdev->ddev, 0); 689254885Sdumbbell rdev->pm.vblank_sync = true; 690254885Sdumbbell DRM_WAKEUP(&rdev->irq.vblank_queue); 691254885Sdumbbell } 692254885Sdumbbell if (atomic_read(&rdev->irq.pflip[0])) 693254885Sdumbbell radeon_crtc_handle_flip(rdev, 0); 694254885Sdumbbell } 695254885Sdumbbell if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 696254885Sdumbbell if (rdev->irq.crtc_vblank_int[1]) { 697254885Sdumbbell drm_handle_vblank(rdev->ddev, 1); 698254885Sdumbbell rdev->pm.vblank_sync = true; 699254885Sdumbbell DRM_WAKEUP(&rdev->irq.vblank_queue); 700254885Sdumbbell } 701254885Sdumbbell if (atomic_read(&rdev->irq.pflip[1])) 702254885Sdumbbell radeon_crtc_handle_flip(rdev, 1); 703254885Sdumbbell } 704254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 705254885Sdumbbell queue_hotplug = true; 706254885Sdumbbell DRM_DEBUG("HPD1\n"); 707254885Sdumbbell } 708254885Sdumbbell if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 709254885Sdumbbell queue_hotplug = true; 710254885Sdumbbell DRM_DEBUG("HPD2\n"); 711254885Sdumbbell } 712254885Sdumbbell if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 713254885Sdumbbell queue_hdmi = true; 714254885Sdumbbell DRM_DEBUG("HDMI0\n"); 715254885Sdumbbell } 716254885Sdumbbell status = rs600_irq_ack(rdev); 717254885Sdumbbell } 718254885Sdumbbell if (queue_hotplug) 719254885Sdumbbell taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); 720254885Sdumbbell if (queue_hdmi) 721254885Sdumbbell taskqueue_enqueue(rdev->tq, &rdev->audio_work); 722254885Sdumbbell if (rdev->msi_enabled) { 723254885Sdumbbell switch (rdev->family) { 724254885Sdumbbell case CHIP_RS600: 725254885Sdumbbell case CHIP_RS690: 726254885Sdumbbell case CHIP_RS740: 727254885Sdumbbell msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 728254885Sdumbbell WREG32(RADEON_BUS_CNTL, msi_rearm); 729254885Sdumbbell WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 730254885Sdumbbell break; 731254885Sdumbbell default: 732254885Sdumbbell WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 733254885Sdumbbell break; 734254885Sdumbbell } 735254885Sdumbbell } 736254885Sdumbbell return IRQ_HANDLED; 737254885Sdumbbell} 738254885Sdumbbell 739254885Sdumbbellu32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 740254885Sdumbbell{ 741254885Sdumbbell if (crtc == 0) 742254885Sdumbbell return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 743254885Sdumbbell else 744254885Sdumbbell return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 745254885Sdumbbell} 746254885Sdumbbell 747254885Sdumbbellint rs600_mc_wait_for_idle(struct radeon_device *rdev) 748254885Sdumbbell{ 749254885Sdumbbell unsigned i; 750254885Sdumbbell 751254885Sdumbbell for (i = 0; i < rdev->usec_timeout; i++) { 752254885Sdumbbell if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 753254885Sdumbbell return 0; 754254885Sdumbbell DRM_UDELAY(1); 755254885Sdumbbell } 756254885Sdumbbell return -1; 757254885Sdumbbell} 758254885Sdumbbell 759254885Sdumbbellstatic void rs600_gpu_init(struct radeon_device *rdev) 760254885Sdumbbell{ 761254885Sdumbbell r420_pipes_init(rdev); 762254885Sdumbbell /* Wait for mc idle */ 763254885Sdumbbell if (rs600_mc_wait_for_idle(rdev)) 764254885Sdumbbell dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 765254885Sdumbbell} 766254885Sdumbbell 767254885Sdumbbellstatic void rs600_mc_init(struct radeon_device *rdev) 768254885Sdumbbell{ 769254885Sdumbbell u64 base; 770254885Sdumbbell 771254885Sdumbbell rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 772254885Sdumbbell rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 773254885Sdumbbell rdev->mc.vram_is_ddr = true; 774254885Sdumbbell rdev->mc.vram_width = 128; 775254885Sdumbbell rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 776254885Sdumbbell rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 777254885Sdumbbell rdev->mc.visible_vram_size = rdev->mc.aper_size; 778254885Sdumbbell rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 779254885Sdumbbell base = RREG32_MC(R_000004_MC_FB_LOCATION); 780254885Sdumbbell base = G_000004_MC_FB_START(base) << 16; 781254885Sdumbbell radeon_vram_location(rdev, &rdev->mc, base); 782254885Sdumbbell rdev->mc.gtt_base_align = 0; 783254885Sdumbbell radeon_gtt_location(rdev, &rdev->mc); 784254885Sdumbbell radeon_update_bandwidth_info(rdev); 785254885Sdumbbell} 786254885Sdumbbell 787254885Sdumbbellvoid rs600_bandwidth_update(struct radeon_device *rdev) 788254885Sdumbbell{ 789254885Sdumbbell struct drm_display_mode *mode0 = NULL; 790254885Sdumbbell struct drm_display_mode *mode1 = NULL; 791254885Sdumbbell u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 792254885Sdumbbell /* FIXME: implement full support */ 793254885Sdumbbell 794254885Sdumbbell radeon_update_display_priority(rdev); 795254885Sdumbbell 796254885Sdumbbell if (rdev->mode_info.crtcs[0]->base.enabled) 797254885Sdumbbell mode0 = &rdev->mode_info.crtcs[0]->base.mode; 798254885Sdumbbell if (rdev->mode_info.crtcs[1]->base.enabled) 799254885Sdumbbell mode1 = &rdev->mode_info.crtcs[1]->base.mode; 800254885Sdumbbell 801254885Sdumbbell rs690_line_buffer_adjust(rdev, mode0, mode1); 802254885Sdumbbell 803254885Sdumbbell if (rdev->disp_priority == 2) { 804254885Sdumbbell d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 805254885Sdumbbell d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 806254885Sdumbbell d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 807254885Sdumbbell d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 808254885Sdumbbell WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 809254885Sdumbbell WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 810254885Sdumbbell WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 811254885Sdumbbell WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 812254885Sdumbbell } 813254885Sdumbbell} 814254885Sdumbbell 815254885Sdumbbelluint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 816254885Sdumbbell{ 817254885Sdumbbell WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 818254885Sdumbbell S_000070_MC_IND_CITF_ARB0(1)); 819254885Sdumbbell return RREG32(R_000074_MC_IND_DATA); 820254885Sdumbbell} 821254885Sdumbbell 822254885Sdumbbellvoid rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 823254885Sdumbbell{ 824254885Sdumbbell WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 825254885Sdumbbell S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 826254885Sdumbbell WREG32(R_000074_MC_IND_DATA, v); 827254885Sdumbbell} 828254885Sdumbbell 829254885Sdumbbellstatic void rs600_debugfs(struct radeon_device *rdev) 830254885Sdumbbell{ 831254885Sdumbbell if (r100_debugfs_rbbm_init(rdev)) 832254885Sdumbbell DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 833254885Sdumbbell} 834254885Sdumbbell 835254885Sdumbbellvoid rs600_set_safe_registers(struct radeon_device *rdev) 836254885Sdumbbell{ 837254885Sdumbbell rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 838254885Sdumbbell rdev->config.r300.reg_safe_bm_size = DRM_ARRAY_SIZE(rs600_reg_safe_bm); 839254885Sdumbbell} 840254885Sdumbbell 841254885Sdumbbellstatic void rs600_mc_program(struct radeon_device *rdev) 842254885Sdumbbell{ 843254885Sdumbbell struct rv515_mc_save save; 844254885Sdumbbell 845254885Sdumbbell /* Stops all mc clients */ 846254885Sdumbbell rv515_mc_stop(rdev, &save); 847254885Sdumbbell 848254885Sdumbbell /* Wait for mc idle */ 849254885Sdumbbell if (rs600_mc_wait_for_idle(rdev)) 850254885Sdumbbell dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 851254885Sdumbbell 852254885Sdumbbell /* FIXME: What does AGP means for such chipset ? */ 853254885Sdumbbell WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 854254885Sdumbbell WREG32_MC(R_000006_AGP_BASE, 0); 855254885Sdumbbell WREG32_MC(R_000007_AGP_BASE_2, 0); 856254885Sdumbbell /* Program MC */ 857254885Sdumbbell WREG32_MC(R_000004_MC_FB_LOCATION, 858254885Sdumbbell S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 859254885Sdumbbell S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 860254885Sdumbbell WREG32(R_000134_HDP_FB_LOCATION, 861254885Sdumbbell S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 862254885Sdumbbell 863254885Sdumbbell rv515_mc_resume(rdev, &save); 864254885Sdumbbell} 865254885Sdumbbell 866254885Sdumbbellstatic int rs600_startup(struct radeon_device *rdev) 867254885Sdumbbell{ 868254885Sdumbbell int r; 869254885Sdumbbell 870254885Sdumbbell rs600_mc_program(rdev); 871254885Sdumbbell /* Resume clock */ 872254885Sdumbbell rv515_clock_startup(rdev); 873254885Sdumbbell /* Initialize GPU configuration (# pipes, ...) */ 874254885Sdumbbell rs600_gpu_init(rdev); 875254885Sdumbbell /* Initialize GART (initialize after TTM so we can allocate 876254885Sdumbbell * memory through TTM but finalize after TTM) */ 877254885Sdumbbell r = rs600_gart_enable(rdev); 878254885Sdumbbell if (r) 879254885Sdumbbell return r; 880254885Sdumbbell 881254885Sdumbbell /* allocate wb buffer */ 882254885Sdumbbell r = radeon_wb_init(rdev); 883254885Sdumbbell if (r) 884254885Sdumbbell return r; 885254885Sdumbbell 886254885Sdumbbell r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 887254885Sdumbbell if (r) { 888254885Sdumbbell dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 889254885Sdumbbell return r; 890254885Sdumbbell } 891254885Sdumbbell 892254885Sdumbbell /* Enable IRQ */ 893254885Sdumbbell rs600_irq_set(rdev); 894254885Sdumbbell rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 895254885Sdumbbell /* 1M ring buffer */ 896254885Sdumbbell r = r100_cp_init(rdev, 1024 * 1024); 897254885Sdumbbell if (r) { 898254885Sdumbbell dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 899254885Sdumbbell return r; 900254885Sdumbbell } 901254885Sdumbbell 902254885Sdumbbell r = radeon_ib_pool_init(rdev); 903254885Sdumbbell if (r) { 904254885Sdumbbell dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 905254885Sdumbbell return r; 906254885Sdumbbell } 907254885Sdumbbell 908254885Sdumbbell r = r600_audio_init(rdev); 909254885Sdumbbell if (r) { 910254885Sdumbbell dev_err(rdev->dev, "failed initializing audio\n"); 911254885Sdumbbell return r; 912254885Sdumbbell } 913254885Sdumbbell 914254885Sdumbbell return 0; 915254885Sdumbbell} 916254885Sdumbbell 917254885Sdumbbellint rs600_resume(struct radeon_device *rdev) 918254885Sdumbbell{ 919254885Sdumbbell int r; 920254885Sdumbbell 921254885Sdumbbell /* Make sur GART are not working */ 922254885Sdumbbell rs600_gart_disable(rdev); 923254885Sdumbbell /* Resume clock before doing reset */ 924254885Sdumbbell rv515_clock_startup(rdev); 925254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 926254885Sdumbbell if (radeon_asic_reset(rdev)) { 927254885Sdumbbell dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 928254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 929254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 930254885Sdumbbell } 931254885Sdumbbell /* post */ 932254885Sdumbbell atom_asic_init(rdev->mode_info.atom_context); 933254885Sdumbbell /* Resume clock after posting */ 934254885Sdumbbell rv515_clock_startup(rdev); 935254885Sdumbbell /* Initialize surface registers */ 936254885Sdumbbell radeon_surface_init(rdev); 937254885Sdumbbell 938254885Sdumbbell rdev->accel_working = true; 939254885Sdumbbell r = rs600_startup(rdev); 940254885Sdumbbell if (r) { 941254885Sdumbbell rdev->accel_working = false; 942254885Sdumbbell } 943254885Sdumbbell return r; 944254885Sdumbbell} 945254885Sdumbbell 946254885Sdumbbellint rs600_suspend(struct radeon_device *rdev) 947254885Sdumbbell{ 948254885Sdumbbell r600_audio_fini(rdev); 949254885Sdumbbell r100_cp_disable(rdev); 950254885Sdumbbell radeon_wb_disable(rdev); 951254885Sdumbbell rs600_irq_disable(rdev); 952254885Sdumbbell rs600_gart_disable(rdev); 953254885Sdumbbell return 0; 954254885Sdumbbell} 955254885Sdumbbell 956254885Sdumbbellvoid rs600_fini(struct radeon_device *rdev) 957254885Sdumbbell{ 958254885Sdumbbell r600_audio_fini(rdev); 959254885Sdumbbell r100_cp_fini(rdev); 960254885Sdumbbell radeon_wb_fini(rdev); 961254885Sdumbbell radeon_ib_pool_fini(rdev); 962254885Sdumbbell radeon_gem_fini(rdev); 963254885Sdumbbell rs600_gart_fini(rdev); 964254885Sdumbbell radeon_irq_kms_fini(rdev); 965254885Sdumbbell radeon_fence_driver_fini(rdev); 966254885Sdumbbell radeon_bo_fini(rdev); 967254885Sdumbbell radeon_atombios_fini(rdev); 968254885Sdumbbell free(rdev->bios, DRM_MEM_DRIVER); 969254885Sdumbbell rdev->bios = NULL; 970254885Sdumbbell} 971254885Sdumbbell 972254885Sdumbbellint rs600_init(struct radeon_device *rdev) 973254885Sdumbbell{ 974254885Sdumbbell int r; 975254885Sdumbbell 976254885Sdumbbell /* Disable VGA */ 977254885Sdumbbell rv515_vga_render_disable(rdev); 978254885Sdumbbell /* Initialize scratch registers */ 979254885Sdumbbell radeon_scratch_init(rdev); 980254885Sdumbbell /* Initialize surface registers */ 981254885Sdumbbell radeon_surface_init(rdev); 982254885Sdumbbell /* restore some register to sane defaults */ 983254885Sdumbbell r100_restore_sanity(rdev); 984254885Sdumbbell /* BIOS */ 985254885Sdumbbell if (!radeon_get_bios(rdev)) { 986254885Sdumbbell if (ASIC_IS_AVIVO(rdev)) 987254885Sdumbbell return -EINVAL; 988254885Sdumbbell } 989254885Sdumbbell if (rdev->is_atom_bios) { 990254885Sdumbbell r = radeon_atombios_init(rdev); 991254885Sdumbbell if (r) 992254885Sdumbbell return r; 993254885Sdumbbell } else { 994254885Sdumbbell dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 995254885Sdumbbell return -EINVAL; 996254885Sdumbbell } 997254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 998254885Sdumbbell if (radeon_asic_reset(rdev)) { 999254885Sdumbbell dev_warn(rdev->dev, 1000254885Sdumbbell "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1001254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 1002254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 1003254885Sdumbbell } 1004254885Sdumbbell /* check if cards are posted or not */ 1005254885Sdumbbell if (radeon_boot_test_post_card(rdev) == false) 1006254885Sdumbbell return -EINVAL; 1007254885Sdumbbell 1008254885Sdumbbell /* Initialize clocks */ 1009254885Sdumbbell radeon_get_clock_info(rdev->ddev); 1010254885Sdumbbell /* initialize memory controller */ 1011254885Sdumbbell rs600_mc_init(rdev); 1012254885Sdumbbell rs600_debugfs(rdev); 1013254885Sdumbbell /* Fence driver */ 1014254885Sdumbbell r = radeon_fence_driver_init(rdev); 1015254885Sdumbbell if (r) 1016254885Sdumbbell return r; 1017254885Sdumbbell r = radeon_irq_kms_init(rdev); 1018254885Sdumbbell if (r) 1019254885Sdumbbell return r; 1020254885Sdumbbell /* Memory manager */ 1021254885Sdumbbell r = radeon_bo_init(rdev); 1022254885Sdumbbell if (r) 1023254885Sdumbbell return r; 1024254885Sdumbbell r = rs600_gart_init(rdev); 1025254885Sdumbbell if (r) 1026254885Sdumbbell return r; 1027254885Sdumbbell rs600_set_safe_registers(rdev); 1028254885Sdumbbell 1029254885Sdumbbell rdev->accel_working = true; 1030254885Sdumbbell r = rs600_startup(rdev); 1031254885Sdumbbell if (r) { 1032254885Sdumbbell /* Somethings want wront with the accel init stop accel */ 1033254885Sdumbbell dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1034254885Sdumbbell r100_cp_fini(rdev); 1035254885Sdumbbell radeon_wb_fini(rdev); 1036254885Sdumbbell radeon_ib_pool_fini(rdev); 1037254885Sdumbbell rs600_gart_fini(rdev); 1038254885Sdumbbell radeon_irq_kms_fini(rdev); 1039254885Sdumbbell rdev->accel_working = false; 1040254885Sdumbbell } 1041254885Sdumbbell return 0; 1042254885Sdumbbell} 1043