radeon_mode.h revision 254885
1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3254885Sdumbbell * VA Linux Systems Inc., Fremont, California. 4254885Sdumbbell * Copyright 2008 Red Hat Inc. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Original Authors: 25254885Sdumbbell * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26254885Sdumbbell * 27254885Sdumbbell * Kernel port Author: Dave Airlie 28254885Sdumbbell */ 29254885Sdumbbell 30254885Sdumbbell#include <sys/cdefs.h> 31254885Sdumbbell__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/radeon_mode.h 254885 2013-08-25 19:37:15Z dumbbell $"); 32254885Sdumbbell 33254885Sdumbbell#ifndef RADEON_MODE_H 34254885Sdumbbell#define RADEON_MODE_H 35254885Sdumbbell 36254885Sdumbbell#include <dev/drm2/drm_crtc.h> 37254885Sdumbbell#include <dev/drm2/drm_edid.h> 38254885Sdumbbell#include <dev/drm2/drm_dp_helper.h> 39254885Sdumbbell#include <dev/drm2/drm_fixed.h> 40254885Sdumbbell#include <dev/drm2/drm_crtc_helper.h> 41254885Sdumbbell 42254885Sdumbbellstruct radeon_bo; 43254885Sdumbbellstruct radeon_device; 44254885Sdumbbell 45254885Sdumbbell#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46254885Sdumbbell#define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47254885Sdumbbell#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48254885Sdumbbell#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49254885Sdumbbell 50254885Sdumbbellenum radeon_rmx_type { 51254885Sdumbbell RMX_OFF, 52254885Sdumbbell RMX_FULL, 53254885Sdumbbell RMX_CENTER, 54254885Sdumbbell RMX_ASPECT 55254885Sdumbbell}; 56254885Sdumbbell 57254885Sdumbbellenum radeon_tv_std { 58254885Sdumbbell TV_STD_NTSC, 59254885Sdumbbell TV_STD_PAL, 60254885Sdumbbell TV_STD_PAL_M, 61254885Sdumbbell TV_STD_PAL_60, 62254885Sdumbbell TV_STD_NTSC_J, 63254885Sdumbbell TV_STD_SCART_PAL, 64254885Sdumbbell TV_STD_SECAM, 65254885Sdumbbell TV_STD_PAL_CN, 66254885Sdumbbell TV_STD_PAL_N, 67254885Sdumbbell}; 68254885Sdumbbell 69254885Sdumbbellenum radeon_underscan_type { 70254885Sdumbbell UNDERSCAN_OFF, 71254885Sdumbbell UNDERSCAN_ON, 72254885Sdumbbell UNDERSCAN_AUTO, 73254885Sdumbbell}; 74254885Sdumbbell 75254885Sdumbbellenum radeon_hpd_id { 76254885Sdumbbell RADEON_HPD_1 = 0, 77254885Sdumbbell RADEON_HPD_2, 78254885Sdumbbell RADEON_HPD_3, 79254885Sdumbbell RADEON_HPD_4, 80254885Sdumbbell RADEON_HPD_5, 81254885Sdumbbell RADEON_HPD_6, 82254885Sdumbbell RADEON_HPD_NONE = 0xff, 83254885Sdumbbell}; 84254885Sdumbbell 85254885Sdumbbell#define RADEON_MAX_I2C_BUS 16 86254885Sdumbbell 87254885Sdumbbell/* radeon gpio-based i2c 88254885Sdumbbell * 1. "mask" reg and bits 89254885Sdumbbell * grabs the gpio pins for software use 90254885Sdumbbell * 0=not held 1=held 91254885Sdumbbell * 2. "a" reg and bits 92254885Sdumbbell * output pin value 93254885Sdumbbell * 0=low 1=high 94254885Sdumbbell * 3. "en" reg and bits 95254885Sdumbbell * sets the pin direction 96254885Sdumbbell * 0=input 1=output 97254885Sdumbbell * 4. "y" reg and bits 98254885Sdumbbell * input pin value 99254885Sdumbbell * 0=low 1=high 100254885Sdumbbell */ 101254885Sdumbbellstruct radeon_i2c_bus_rec { 102254885Sdumbbell bool valid; 103254885Sdumbbell /* id used by atom */ 104254885Sdumbbell uint8_t i2c_id; 105254885Sdumbbell /* id used by atom */ 106254885Sdumbbell enum radeon_hpd_id hpd; 107254885Sdumbbell /* can be used with hw i2c engine */ 108254885Sdumbbell bool hw_capable; 109254885Sdumbbell /* uses multi-media i2c engine */ 110254885Sdumbbell bool mm_i2c; 111254885Sdumbbell /* regs and bits */ 112254885Sdumbbell uint32_t mask_clk_reg; 113254885Sdumbbell uint32_t mask_data_reg; 114254885Sdumbbell uint32_t a_clk_reg; 115254885Sdumbbell uint32_t a_data_reg; 116254885Sdumbbell uint32_t en_clk_reg; 117254885Sdumbbell uint32_t en_data_reg; 118254885Sdumbbell uint32_t y_clk_reg; 119254885Sdumbbell uint32_t y_data_reg; 120254885Sdumbbell uint32_t mask_clk_mask; 121254885Sdumbbell uint32_t mask_data_mask; 122254885Sdumbbell uint32_t a_clk_mask; 123254885Sdumbbell uint32_t a_data_mask; 124254885Sdumbbell uint32_t en_clk_mask; 125254885Sdumbbell uint32_t en_data_mask; 126254885Sdumbbell uint32_t y_clk_mask; 127254885Sdumbbell uint32_t y_data_mask; 128254885Sdumbbell}; 129254885Sdumbbell 130254885Sdumbbellstruct radeon_tmds_pll { 131254885Sdumbbell uint32_t freq; 132254885Sdumbbell uint32_t value; 133254885Sdumbbell}; 134254885Sdumbbell 135254885Sdumbbell#define RADEON_MAX_BIOS_CONNECTOR 16 136254885Sdumbbell 137254885Sdumbbell/* pll flags */ 138254885Sdumbbell#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 139254885Sdumbbell#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 140254885Sdumbbell#define RADEON_PLL_USE_REF_DIV (1 << 2) 141254885Sdumbbell#define RADEON_PLL_LEGACY (1 << 3) 142254885Sdumbbell#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 143254885Sdumbbell#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 144254885Sdumbbell#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 145254885Sdumbbell#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 146254885Sdumbbell#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 147254885Sdumbbell#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 148254885Sdumbbell#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 149254885Sdumbbell#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 150254885Sdumbbell#define RADEON_PLL_USE_POST_DIV (1 << 12) 151254885Sdumbbell#define RADEON_PLL_IS_LCD (1 << 13) 152254885Sdumbbell#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 153254885Sdumbbell 154254885Sdumbbellstruct radeon_pll { 155254885Sdumbbell /* reference frequency */ 156254885Sdumbbell uint32_t reference_freq; 157254885Sdumbbell 158254885Sdumbbell /* fixed dividers */ 159254885Sdumbbell uint32_t reference_div; 160254885Sdumbbell uint32_t post_div; 161254885Sdumbbell 162254885Sdumbbell /* pll in/out limits */ 163254885Sdumbbell uint32_t pll_in_min; 164254885Sdumbbell uint32_t pll_in_max; 165254885Sdumbbell uint32_t pll_out_min; 166254885Sdumbbell uint32_t pll_out_max; 167254885Sdumbbell uint32_t lcd_pll_out_min; 168254885Sdumbbell uint32_t lcd_pll_out_max; 169254885Sdumbbell uint32_t best_vco; 170254885Sdumbbell 171254885Sdumbbell /* divider limits */ 172254885Sdumbbell uint32_t min_ref_div; 173254885Sdumbbell uint32_t max_ref_div; 174254885Sdumbbell uint32_t min_post_div; 175254885Sdumbbell uint32_t max_post_div; 176254885Sdumbbell uint32_t min_feedback_div; 177254885Sdumbbell uint32_t max_feedback_div; 178254885Sdumbbell uint32_t min_frac_feedback_div; 179254885Sdumbbell uint32_t max_frac_feedback_div; 180254885Sdumbbell 181254885Sdumbbell /* flags for the current clock */ 182254885Sdumbbell uint32_t flags; 183254885Sdumbbell 184254885Sdumbbell /* pll id */ 185254885Sdumbbell uint32_t id; 186254885Sdumbbell}; 187254885Sdumbbell 188254885Sdumbbellstruct radeon_i2c_chan { 189254885Sdumbbell device_t adapter; 190254885Sdumbbell device_t iic_bus; 191254885Sdumbbell struct drm_device *dev; 192254885Sdumbbell struct radeon_i2c_bus_rec rec; 193254885Sdumbbell char name[48]; 194254885Sdumbbell}; 195254885Sdumbbell 196254885Sdumbbell/* mostly for macs, but really any system without connector tables */ 197254885Sdumbbellenum radeon_connector_table { 198254885Sdumbbell CT_NONE = 0, 199254885Sdumbbell CT_GENERIC, 200254885Sdumbbell CT_IBOOK, 201254885Sdumbbell CT_POWERBOOK_EXTERNAL, 202254885Sdumbbell CT_POWERBOOK_INTERNAL, 203254885Sdumbbell CT_POWERBOOK_VGA, 204254885Sdumbbell CT_MINI_EXTERNAL, 205254885Sdumbbell CT_MINI_INTERNAL, 206254885Sdumbbell CT_IMAC_G5_ISIGHT, 207254885Sdumbbell CT_EMAC, 208254885Sdumbbell CT_RN50_POWER, 209254885Sdumbbell CT_MAC_X800, 210254885Sdumbbell CT_MAC_G5_9600, 211254885Sdumbbell CT_SAM440EP, 212254885Sdumbbell CT_MAC_G4_SILVER 213254885Sdumbbell}; 214254885Sdumbbell 215254885Sdumbbellenum radeon_dvo_chip { 216254885Sdumbbell DVO_SIL164, 217254885Sdumbbell DVO_SIL1178, 218254885Sdumbbell}; 219254885Sdumbbell 220254885Sdumbbellstruct radeon_fbdev; 221254885Sdumbbell 222254885Sdumbbellstruct radeon_afmt { 223254885Sdumbbell bool enabled; 224254885Sdumbbell int offset; 225254885Sdumbbell bool last_buffer_filled_status; 226254885Sdumbbell int id; 227254885Sdumbbell}; 228254885Sdumbbell 229254885Sdumbbellstruct radeon_mode_info { 230254885Sdumbbell struct atom_context *atom_context; 231254885Sdumbbell struct card_info *atom_card_info; 232254885Sdumbbell enum radeon_connector_table connector_table; 233254885Sdumbbell bool mode_config_initialized; 234254885Sdumbbell struct radeon_crtc *crtcs[6]; 235254885Sdumbbell struct radeon_afmt *afmt[6]; 236254885Sdumbbell /* DVI-I properties */ 237254885Sdumbbell struct drm_property *coherent_mode_property; 238254885Sdumbbell /* DAC enable load detect */ 239254885Sdumbbell struct drm_property *load_detect_property; 240254885Sdumbbell /* TV standard */ 241254885Sdumbbell struct drm_property *tv_std_property; 242254885Sdumbbell /* legacy TMDS PLL detect */ 243254885Sdumbbell struct drm_property *tmds_pll_property; 244254885Sdumbbell /* underscan */ 245254885Sdumbbell struct drm_property *underscan_property; 246254885Sdumbbell struct drm_property *underscan_hborder_property; 247254885Sdumbbell struct drm_property *underscan_vborder_property; 248254885Sdumbbell /* hardcoded DFP edid from BIOS */ 249254885Sdumbbell struct edid *bios_hardcoded_edid; 250254885Sdumbbell int bios_hardcoded_edid_size; 251254885Sdumbbell 252254885Sdumbbell /* pointer to fbdev info structure */ 253254885Sdumbbell struct radeon_fbdev *rfbdev; 254254885Sdumbbell /* firmware flags */ 255254885Sdumbbell u16 firmware_flags; 256254885Sdumbbell /* pointer to backlight encoder */ 257254885Sdumbbell struct radeon_encoder *bl_encoder; 258254885Sdumbbell}; 259254885Sdumbbell 260254885Sdumbbell#define RADEON_MAX_BL_LEVEL 0xFF 261254885Sdumbbell 262254885Sdumbbell#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 263254885Sdumbbell 264254885Sdumbbellstruct radeon_backlight_privdata { 265254885Sdumbbell struct radeon_encoder *encoder; 266254885Sdumbbell uint8_t negative; 267254885Sdumbbell}; 268254885Sdumbbell 269254885Sdumbbell#endif 270254885Sdumbbell 271254885Sdumbbell#define MAX_H_CODE_TIMING_LEN 32 272254885Sdumbbell#define MAX_V_CODE_TIMING_LEN 32 273254885Sdumbbell 274254885Sdumbbell/* need to store these as reading 275254885Sdumbbell back code tables is excessive */ 276254885Sdumbbellstruct radeon_tv_regs { 277254885Sdumbbell uint32_t tv_uv_adr; 278254885Sdumbbell uint32_t timing_cntl; 279254885Sdumbbell uint32_t hrestart; 280254885Sdumbbell uint32_t vrestart; 281254885Sdumbbell uint32_t frestart; 282254885Sdumbbell uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 283254885Sdumbbell uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 284254885Sdumbbell}; 285254885Sdumbbell 286254885Sdumbbellstruct radeon_atom_ss { 287254885Sdumbbell uint16_t percentage; 288254885Sdumbbell uint8_t type; 289254885Sdumbbell uint16_t step; 290254885Sdumbbell uint8_t delay; 291254885Sdumbbell uint8_t range; 292254885Sdumbbell uint8_t refdiv; 293254885Sdumbbell /* asic_ss */ 294254885Sdumbbell uint16_t rate; 295254885Sdumbbell uint16_t amount; 296254885Sdumbbell}; 297254885Sdumbbell 298254885Sdumbbellstruct radeon_crtc { 299254885Sdumbbell struct drm_crtc base; 300254885Sdumbbell int crtc_id; 301254885Sdumbbell u16 lut_r[256], lut_g[256], lut_b[256]; 302254885Sdumbbell bool enabled; 303254885Sdumbbell bool can_tile; 304254885Sdumbbell bool in_mode_set; 305254885Sdumbbell uint32_t crtc_offset; 306254885Sdumbbell struct drm_gem_object *cursor_bo; 307254885Sdumbbell uint64_t cursor_addr; 308254885Sdumbbell int cursor_width; 309254885Sdumbbell int cursor_height; 310254885Sdumbbell uint32_t legacy_display_base_addr; 311254885Sdumbbell uint32_t legacy_cursor_offset; 312254885Sdumbbell enum radeon_rmx_type rmx_type; 313254885Sdumbbell u8 h_border; 314254885Sdumbbell u8 v_border; 315254885Sdumbbell fixed20_12 vsc; 316254885Sdumbbell fixed20_12 hsc; 317254885Sdumbbell struct drm_display_mode native_mode; 318254885Sdumbbell int pll_id; 319254885Sdumbbell /* page flipping */ 320254885Sdumbbell struct radeon_unpin_work *unpin_work; 321254885Sdumbbell int deferred_flip_completion; 322254885Sdumbbell /* pll sharing */ 323254885Sdumbbell struct radeon_atom_ss ss; 324254885Sdumbbell bool ss_enabled; 325254885Sdumbbell u32 adjusted_clock; 326254885Sdumbbell int bpc; 327254885Sdumbbell u32 pll_reference_div; 328254885Sdumbbell u32 pll_post_div; 329254885Sdumbbell u32 pll_flags; 330254885Sdumbbell struct drm_encoder *encoder; 331254885Sdumbbell struct drm_connector *connector; 332254885Sdumbbell}; 333254885Sdumbbell 334254885Sdumbbellstruct radeon_encoder_primary_dac { 335254885Sdumbbell /* legacy primary dac */ 336254885Sdumbbell uint32_t ps2_pdac_adj; 337254885Sdumbbell}; 338254885Sdumbbell 339254885Sdumbbellstruct radeon_encoder_lvds { 340254885Sdumbbell /* legacy lvds */ 341254885Sdumbbell uint16_t panel_vcc_delay; 342254885Sdumbbell uint8_t panel_pwr_delay; 343254885Sdumbbell uint8_t panel_digon_delay; 344254885Sdumbbell uint8_t panel_blon_delay; 345254885Sdumbbell uint16_t panel_ref_divider; 346254885Sdumbbell uint8_t panel_post_divider; 347254885Sdumbbell uint16_t panel_fb_divider; 348254885Sdumbbell bool use_bios_dividers; 349254885Sdumbbell uint32_t lvds_gen_cntl; 350254885Sdumbbell /* panel mode */ 351254885Sdumbbell struct drm_display_mode native_mode; 352254885Sdumbbell struct backlight_device *bl_dev; 353254885Sdumbbell int dpms_mode; 354254885Sdumbbell uint8_t backlight_level; 355254885Sdumbbell}; 356254885Sdumbbell 357254885Sdumbbellstruct radeon_encoder_tv_dac { 358254885Sdumbbell /* legacy tv dac */ 359254885Sdumbbell uint32_t ps2_tvdac_adj; 360254885Sdumbbell uint32_t ntsc_tvdac_adj; 361254885Sdumbbell uint32_t pal_tvdac_adj; 362254885Sdumbbell 363254885Sdumbbell int h_pos; 364254885Sdumbbell int v_pos; 365254885Sdumbbell int h_size; 366254885Sdumbbell int supported_tv_stds; 367254885Sdumbbell bool tv_on; 368254885Sdumbbell enum radeon_tv_std tv_std; 369254885Sdumbbell struct radeon_tv_regs tv; 370254885Sdumbbell}; 371254885Sdumbbell 372254885Sdumbbellstruct radeon_encoder_int_tmds { 373254885Sdumbbell /* legacy int tmds */ 374254885Sdumbbell struct radeon_tmds_pll tmds_pll[4]; 375254885Sdumbbell}; 376254885Sdumbbell 377254885Sdumbbellstruct radeon_encoder_ext_tmds { 378254885Sdumbbell /* tmds over dvo */ 379254885Sdumbbell struct radeon_i2c_chan *i2c_bus; 380254885Sdumbbell uint8_t slave_addr; 381254885Sdumbbell enum radeon_dvo_chip dvo_chip; 382254885Sdumbbell}; 383254885Sdumbbell 384254885Sdumbbell/* spread spectrum */ 385254885Sdumbbellstruct radeon_encoder_atom_dig { 386254885Sdumbbell bool linkb; 387254885Sdumbbell /* atom dig */ 388254885Sdumbbell bool coherent_mode; 389254885Sdumbbell int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 390254885Sdumbbell /* atom lvds/edp */ 391254885Sdumbbell uint32_t lcd_misc; 392254885Sdumbbell uint16_t panel_pwr_delay; 393254885Sdumbbell uint32_t lcd_ss_id; 394254885Sdumbbell /* panel mode */ 395254885Sdumbbell struct drm_display_mode native_mode; 396254885Sdumbbell struct backlight_device *bl_dev; 397254885Sdumbbell int dpms_mode; 398254885Sdumbbell uint8_t backlight_level; 399254885Sdumbbell int panel_mode; 400254885Sdumbbell struct radeon_afmt *afmt; 401254885Sdumbbell}; 402254885Sdumbbell 403254885Sdumbbellstruct radeon_encoder_atom_dac { 404254885Sdumbbell enum radeon_tv_std tv_std; 405254885Sdumbbell}; 406254885Sdumbbell 407254885Sdumbbellstruct radeon_encoder { 408254885Sdumbbell struct drm_encoder base; 409254885Sdumbbell uint32_t encoder_enum; 410254885Sdumbbell uint32_t encoder_id; 411254885Sdumbbell uint32_t devices; 412254885Sdumbbell uint32_t active_device; 413254885Sdumbbell uint32_t flags; 414254885Sdumbbell uint32_t pixel_clock; 415254885Sdumbbell enum radeon_rmx_type rmx_type; 416254885Sdumbbell enum radeon_underscan_type underscan_type; 417254885Sdumbbell uint32_t underscan_hborder; 418254885Sdumbbell uint32_t underscan_vborder; 419254885Sdumbbell struct drm_display_mode native_mode; 420254885Sdumbbell void *enc_priv; 421254885Sdumbbell int audio_polling_active; 422254885Sdumbbell bool is_ext_encoder; 423254885Sdumbbell u16 caps; 424254885Sdumbbell}; 425254885Sdumbbell 426254885Sdumbbellstruct radeon_connector_atom_dig { 427254885Sdumbbell uint32_t igp_lane_info; 428254885Sdumbbell /* displayport */ 429254885Sdumbbell struct radeon_i2c_chan *dp_i2c_bus; 430254885Sdumbbell u8 dpcd[DP_RECEIVER_CAP_SIZE]; 431254885Sdumbbell u8 dp_sink_type; 432254885Sdumbbell int dp_clock; 433254885Sdumbbell int dp_lane_count; 434254885Sdumbbell bool edp_on; 435254885Sdumbbell}; 436254885Sdumbbell 437254885Sdumbbellstruct radeon_gpio_rec { 438254885Sdumbbell bool valid; 439254885Sdumbbell u8 id; 440254885Sdumbbell u32 reg; 441254885Sdumbbell u32 mask; 442254885Sdumbbell}; 443254885Sdumbbell 444254885Sdumbbellstruct radeon_hpd { 445254885Sdumbbell enum radeon_hpd_id hpd; 446254885Sdumbbell u8 plugged_state; 447254885Sdumbbell struct radeon_gpio_rec gpio; 448254885Sdumbbell}; 449254885Sdumbbell 450254885Sdumbbellstruct radeon_router { 451254885Sdumbbell u32 router_id; 452254885Sdumbbell struct radeon_i2c_bus_rec i2c_info; 453254885Sdumbbell u8 i2c_addr; 454254885Sdumbbell /* i2c mux */ 455254885Sdumbbell bool ddc_valid; 456254885Sdumbbell u8 ddc_mux_type; 457254885Sdumbbell u8 ddc_mux_control_pin; 458254885Sdumbbell u8 ddc_mux_state; 459254885Sdumbbell /* clock/data mux */ 460254885Sdumbbell bool cd_valid; 461254885Sdumbbell u8 cd_mux_type; 462254885Sdumbbell u8 cd_mux_control_pin; 463254885Sdumbbell u8 cd_mux_state; 464254885Sdumbbell}; 465254885Sdumbbell 466254885Sdumbbellstruct radeon_connector { 467254885Sdumbbell struct drm_connector base; 468254885Sdumbbell uint32_t connector_id; 469254885Sdumbbell uint32_t devices; 470254885Sdumbbell struct radeon_i2c_chan *ddc_bus; 471254885Sdumbbell /* some systems have an hdmi and vga port with a shared ddc line */ 472254885Sdumbbell bool shared_ddc; 473254885Sdumbbell bool use_digital; 474254885Sdumbbell /* we need to mind the EDID between detect 475254885Sdumbbell and get modes due to analog/digital/tvencoder */ 476254885Sdumbbell struct edid *edid; 477254885Sdumbbell void *con_priv; 478254885Sdumbbell bool dac_load_detect; 479254885Sdumbbell bool detected_by_load; /* if the connection status was determined by load */ 480254885Sdumbbell uint16_t connector_object_id; 481254885Sdumbbell struct radeon_hpd hpd; 482254885Sdumbbell struct radeon_router router; 483254885Sdumbbell struct radeon_i2c_chan *router_bus; 484254885Sdumbbell}; 485254885Sdumbbell 486254885Sdumbbellstruct radeon_framebuffer { 487254885Sdumbbell struct drm_framebuffer base; 488254885Sdumbbell struct drm_gem_object *obj; 489254885Sdumbbell}; 490254885Sdumbbell 491254885Sdumbbell#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 492254885Sdumbbell ((em) == ATOM_ENCODER_MODE_DP_MST)) 493254885Sdumbbell 494254885Sdumbbellextern enum radeon_tv_std 495254885Sdumbbellradeon_combios_get_tv_info(struct radeon_device *rdev); 496254885Sdumbbellextern enum radeon_tv_std 497254885Sdumbbellradeon_atombios_get_tv_info(struct radeon_device *rdev); 498254885Sdumbbell 499254885Sdumbbellextern struct drm_connector * 500254885Sdumbbellradeon_get_connector_for_encoder(struct drm_encoder *encoder); 501254885Sdumbbellextern struct drm_connector * 502254885Sdumbbellradeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 503254885Sdumbbellextern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 504254885Sdumbbell u32 pixel_clock); 505254885Sdumbbell 506254885Sdumbbellextern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 507254885Sdumbbellextern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 508254885Sdumbbellextern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 509254885Sdumbbellextern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 510254885Sdumbbellextern int radeon_get_monitor_bpc(struct drm_connector *connector); 511254885Sdumbbell 512254885Sdumbbellextern void radeon_connector_hotplug(struct drm_connector *connector); 513254885Sdumbbellextern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 514254885Sdumbbell struct drm_display_mode *mode); 515254885Sdumbbellextern void radeon_dp_set_link_config(struct drm_connector *connector, 516254885Sdumbbell const struct drm_display_mode *mode); 517254885Sdumbbellextern void radeon_dp_link_train(struct drm_encoder *encoder, 518254885Sdumbbell struct drm_connector *connector); 519254885Sdumbbellextern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 520254885Sdumbbellextern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 521254885Sdumbbellextern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 522254885Sdumbbellextern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 523254885Sdumbbell struct drm_connector *connector); 524254885Sdumbbellextern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 525254885Sdumbbellextern void radeon_atom_encoder_init(struct radeon_device *rdev); 526254885Sdumbbellextern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 527254885Sdumbbellextern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 528254885Sdumbbell int action, uint8_t lane_num, 529254885Sdumbbell uint8_t lane_set); 530254885Sdumbbellextern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 531254885Sdumbbellextern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 532254885Sdumbbellextern int radeon_dp_i2c_aux_ch(device_t dev, int mode, 533254885Sdumbbell u8 write_byte, u8 *read_byte); 534254885Sdumbbell 535254885Sdumbbellextern void radeon_i2c_init(struct radeon_device *rdev); 536254885Sdumbbellextern void radeon_i2c_fini(struct radeon_device *rdev); 537254885Sdumbbellextern void radeon_combios_i2c_init(struct radeon_device *rdev); 538254885Sdumbbellextern void radeon_atombios_i2c_init(struct radeon_device *rdev); 539254885Sdumbbellextern void radeon_i2c_add(struct radeon_device *rdev, 540254885Sdumbbell struct radeon_i2c_bus_rec *rec, 541254885Sdumbbell const char *name); 542254885Sdumbbellextern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 543254885Sdumbbell struct radeon_i2c_bus_rec *i2c_bus); 544254885Sdumbbellextern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 545254885Sdumbbell struct radeon_i2c_bus_rec *rec, 546254885Sdumbbell const char *name); 547254885Sdumbbellextern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 548254885Sdumbbell struct radeon_i2c_bus_rec *rec, 549254885Sdumbbell const char *name); 550254885Sdumbbellextern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 551254885Sdumbbellextern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 552254885Sdumbbell u8 slave_addr, 553254885Sdumbbell u8 addr, 554254885Sdumbbell u8 *val); 555254885Sdumbbellextern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 556254885Sdumbbell u8 slave_addr, 557254885Sdumbbell u8 addr, 558254885Sdumbbell u8 val); 559254885Sdumbbellextern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 560254885Sdumbbellextern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 561254885Sdumbbellextern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 562254885Sdumbbellextern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 563254885Sdumbbell 564254885Sdumbbellextern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 565254885Sdumbbell 566254885Sdumbbellextern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 567254885Sdumbbell struct radeon_atom_ss *ss, 568254885Sdumbbell int id); 569254885Sdumbbellextern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 570254885Sdumbbell struct radeon_atom_ss *ss, 571254885Sdumbbell int id, u32 clock); 572254885Sdumbbell 573254885Sdumbbellextern void radeon_compute_pll_legacy(struct radeon_pll *pll, 574254885Sdumbbell uint64_t freq, 575254885Sdumbbell uint32_t *dot_clock_p, 576254885Sdumbbell uint32_t *fb_div_p, 577254885Sdumbbell uint32_t *frac_fb_div_p, 578254885Sdumbbell uint32_t *ref_div_p, 579254885Sdumbbell uint32_t *post_div_p); 580254885Sdumbbell 581254885Sdumbbellextern void radeon_compute_pll_avivo(struct radeon_pll *pll, 582254885Sdumbbell u32 freq, 583254885Sdumbbell u32 *dot_clock_p, 584254885Sdumbbell u32 *fb_div_p, 585254885Sdumbbell u32 *frac_fb_div_p, 586254885Sdumbbell u32 *ref_div_p, 587254885Sdumbbell u32 *post_div_p); 588254885Sdumbbell 589254885Sdumbbellextern void radeon_setup_encoder_clones(struct drm_device *dev); 590254885Sdumbbell 591254885Sdumbbellstruct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 592254885Sdumbbellstruct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 593254885Sdumbbellstruct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 594254885Sdumbbellstruct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 595254885Sdumbbellstruct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 596254885Sdumbbellextern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 597254885Sdumbbellextern void atombios_digital_setup(struct drm_encoder *encoder, int action); 598254885Sdumbbellextern int atombios_get_encoder_mode(struct drm_encoder *encoder); 599254885Sdumbbellextern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 600254885Sdumbbellextern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 601254885Sdumbbell 602254885Sdumbbellextern void radeon_crtc_load_lut(struct drm_crtc *crtc); 603254885Sdumbbellextern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 604254885Sdumbbell struct drm_framebuffer *old_fb); 605254885Sdumbbellextern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 606254885Sdumbbell struct drm_framebuffer *fb, 607254885Sdumbbell int x, int y, 608254885Sdumbbell enum mode_set_atomic state); 609254885Sdumbbellextern int atombios_crtc_mode_set(struct drm_crtc *crtc, 610254885Sdumbbell struct drm_display_mode *mode, 611254885Sdumbbell struct drm_display_mode *adjusted_mode, 612254885Sdumbbell int x, int y, 613254885Sdumbbell struct drm_framebuffer *old_fb); 614254885Sdumbbellextern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 615254885Sdumbbell 616254885Sdumbbellextern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 617254885Sdumbbell struct drm_framebuffer *old_fb); 618254885Sdumbbellextern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 619254885Sdumbbell struct drm_framebuffer *fb, 620254885Sdumbbell int x, int y, 621254885Sdumbbell enum mode_set_atomic state); 622254885Sdumbbellextern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 623254885Sdumbbell struct drm_framebuffer *fb, 624254885Sdumbbell int x, int y, int atomic); 625254885Sdumbbellextern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 626254885Sdumbbell struct drm_file *file_priv, 627254885Sdumbbell uint32_t handle, 628254885Sdumbbell uint32_t width, 629254885Sdumbbell uint32_t height); 630254885Sdumbbellextern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 631254885Sdumbbell int x, int y); 632254885Sdumbbell 633254885Sdumbbellextern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 634254885Sdumbbell int *vpos, int *hpos); 635254885Sdumbbell 636254885Sdumbbellextern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 637254885Sdumbbellextern struct edid * 638254885Sdumbbellradeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 639254885Sdumbbellextern bool radeon_atom_get_clock_info(struct drm_device *dev); 640254885Sdumbbellextern bool radeon_combios_get_clock_info(struct drm_device *dev); 641254885Sdumbbellextern struct radeon_encoder_atom_dig * 642254885Sdumbbellradeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 643254885Sdumbbellextern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 644254885Sdumbbell struct radeon_encoder_int_tmds *tmds); 645254885Sdumbbellextern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 646254885Sdumbbell struct radeon_encoder_int_tmds *tmds); 647254885Sdumbbellextern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 648254885Sdumbbell struct radeon_encoder_int_tmds *tmds); 649254885Sdumbbellextern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 650254885Sdumbbell struct radeon_encoder_ext_tmds *tmds); 651254885Sdumbbellextern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 652254885Sdumbbell struct radeon_encoder_ext_tmds *tmds); 653254885Sdumbbellextern struct radeon_encoder_primary_dac * 654254885Sdumbbellradeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 655254885Sdumbbellextern struct radeon_encoder_tv_dac * 656254885Sdumbbellradeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 657254885Sdumbbellextern struct radeon_encoder_lvds * 658254885Sdumbbellradeon_combios_get_lvds_info(struct radeon_encoder *encoder); 659254885Sdumbbellextern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 660254885Sdumbbellextern struct radeon_encoder_tv_dac * 661254885Sdumbbellradeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 662254885Sdumbbellextern struct radeon_encoder_primary_dac * 663254885Sdumbbellradeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 664254885Sdumbbellextern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 665254885Sdumbbellextern void radeon_external_tmds_setup(struct drm_encoder *encoder); 666254885Sdumbbellextern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 667254885Sdumbbellextern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 668254885Sdumbbellextern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 669254885Sdumbbellextern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 670254885Sdumbbellextern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 671254885Sdumbbellextern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 672254885Sdumbbellextern void 673254885Sdumbbellradeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 674254885Sdumbbellextern void 675254885Sdumbbellradeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 676254885Sdumbbellextern void 677254885Sdumbbellradeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 678254885Sdumbbellextern void 679254885Sdumbbellradeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 680254885Sdumbbellextern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 681254885Sdumbbell u16 blue, int regno); 682254885Sdumbbellextern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 683254885Sdumbbell u16 *blue, int regno); 684254885Sdumbbellint radeon_framebuffer_init(struct drm_device *dev, 685254885Sdumbbell struct radeon_framebuffer *rfb, 686254885Sdumbbell struct drm_mode_fb_cmd2 *mode_cmd, 687254885Sdumbbell struct drm_gem_object *obj); 688254885Sdumbbell 689254885Sdumbbellint radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 690254885Sdumbbellbool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 691254885Sdumbbellbool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 692254885Sdumbbellvoid radeon_atombios_init_crtc(struct drm_device *dev, 693254885Sdumbbell struct radeon_crtc *radeon_crtc); 694254885Sdumbbellvoid radeon_legacy_init_crtc(struct drm_device *dev, 695254885Sdumbbell struct radeon_crtc *radeon_crtc); 696254885Sdumbbell 697254885Sdumbbellvoid radeon_get_clock_info(struct drm_device *dev); 698254885Sdumbbell 699254885Sdumbbellextern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 700254885Sdumbbellextern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 701254885Sdumbbell 702254885Sdumbbellvoid radeon_enc_destroy(struct drm_encoder *encoder); 703254885Sdumbbellvoid radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 704254885Sdumbbellvoid radeon_combios_asic_init(struct drm_device *dev); 705254885Sdumbbellbool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 706254885Sdumbbell const struct drm_display_mode *mode, 707254885Sdumbbell struct drm_display_mode *adjusted_mode); 708254885Sdumbbellvoid radeon_panel_mode_fixup(struct drm_encoder *encoder, 709254885Sdumbbell struct drm_display_mode *adjusted_mode); 710254885Sdumbbellvoid atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 711254885Sdumbbell 712254885Sdumbbell/* legacy tv */ 713254885Sdumbbellvoid radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 714254885Sdumbbell uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 715254885Sdumbbell uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 716254885Sdumbbellvoid radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 717254885Sdumbbell uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 718254885Sdumbbell uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 719254885Sdumbbellvoid radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 720254885Sdumbbell uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 721254885Sdumbbell uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 722254885Sdumbbellvoid radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 723254885Sdumbbell struct drm_display_mode *mode, 724254885Sdumbbell struct drm_display_mode *adjusted_mode); 725254885Sdumbbell 726254885Sdumbbell/* fbdev layer */ 727254885Sdumbbellint radeon_fbdev_init(struct radeon_device *rdev); 728254885Sdumbbellvoid radeon_fbdev_fini(struct radeon_device *rdev); 729254885Sdumbbellvoid radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 730254885Sdumbbellint radeon_fbdev_total_size(struct radeon_device *rdev); 731254885Sdumbbellbool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 732254885Sdumbbell 733254885Sdumbbellvoid radeon_fb_output_poll_changed(struct radeon_device *rdev); 734254885Sdumbbell 735254885Sdumbbellvoid radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 736254885Sdumbbell 737254885Sdumbbellint radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 738254885Sdumbbell#endif 739