1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 *     Alex Deucher <alexander.deucher@amd.com>
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include <dev/drm2/drmP.h>
31
32/*
33 * R6xx+ cards need to use the 3D engine to blit data which requires
34 * quite a bit of hw state setup.  Rather than pull the whole 3D driver
35 * (which normally generates the 3D state) into the DRM, we opt to use
36 * statically generated state tables.  The regsiter state and shaders
37 * were hand generated to support blitting functionality.  See the 3D
38 * driver or documentation for descriptions of the registers and
39 * shader instructions.
40 */
41
42const u32 r6xx_default_state[] =
43{
44	0xc0002400, /* START_3D_CMDBUF */
45	0x00000000,
46
47	0xc0012800, /* CONTEXT_CONTROL */
48	0x80000000,
49	0x80000000,
50
51	0xc0016800,
52	0x00000010,
53	0x00008000, /* WAIT_UNTIL */
54
55	0xc0016800,
56	0x00000542,
57	0x07000003, /* TA_CNTL_AUX */
58
59	0xc0016800,
60	0x000005c5,
61	0x00000000, /* VC_ENHANCE */
62
63	0xc0016800,
64	0x00000363,
65	0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
66
67	0xc0016800,
68	0x0000060c,
69	0x82000000, /* DB_DEBUG */
70
71	0xc0016800,
72	0x0000060e,
73	0x01020204, /* DB_WATERMARKS */
74
75	0xc0026f00,
76	0x00000000,
77	0x00000000, /* SQ_VTX_BASE_VTX_LOC */
78	0x00000000, /* SQ_VTX_START_INST_LOC */
79
80	0xc0096900,
81	0x0000022a,
82	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
83	0x00000000,
84	0x00000000,
85	0x00000000,
86	0x00000000,
87	0x00000000,
88	0x00000000,
89	0x00000000,
90	0x00000000,
91
92	0xc0016900,
93	0x00000004,
94	0x00000000, /* DB_DEPTH_INFO */
95
96	0xc0026900,
97	0x0000000a,
98	0x00000000, /* DB_STENCIL_CLEAR */
99	0x00000000, /* DB_DEPTH_CLEAR */
100
101	0xc0016900,
102	0x00000200,
103	0x00000000, /* DB_DEPTH_CONTROL */
104
105	0xc0026900,
106	0x00000343,
107	0x00000060, /* DB_RENDER_CONTROL */
108	0x00000040, /* DB_RENDER_OVERRIDE */
109
110	0xc0016900,
111	0x00000351,
112	0x0000aa00, /* DB_ALPHA_TO_MASK */
113
114	0xc00f6900,
115	0x00000100,
116	0x00000800, /* VGT_MAX_VTX_INDX */
117	0x00000000, /* VGT_MIN_VTX_INDX */
118	0x00000000, /* VGT_INDX_OFFSET */
119	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
120	0x00000000, /* SX_ALPHA_TEST_CONTROL */
121	0x00000000, /* CB_BLEND_RED */
122	0x00000000,
123	0x00000000,
124	0x00000000,
125	0x00000000, /* CB_FOG_RED */
126	0x00000000,
127	0x00000000,
128	0x00000000, /* DB_STENCILREFMASK */
129	0x00000000, /* DB_STENCILREFMASK_BF */
130	0x00000000, /* SX_ALPHA_REF */
131
132	0xc0046900,
133	0x0000030c,
134	0x01000000, /* CB_CLRCMP_CNTL */
135	0x00000000,
136	0x00000000,
137	0x00000000,
138
139	0xc0046900,
140	0x00000048,
141	0x3f800000, /* CB_CLEAR_RED */
142	0x00000000,
143	0x3f800000,
144	0x3f800000,
145
146	0xc0016900,
147	0x00000080,
148	0x00000000, /* PA_SC_WINDOW_OFFSET */
149
150	0xc00a6900,
151	0x00000083,
152	0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
153	0x00000000, /* PA_SC_CLIPRECT_0_TL */
154	0x20002000,
155	0x00000000,
156	0x20002000,
157	0x00000000,
158	0x20002000,
159	0x00000000,
160	0x20002000,
161	0x00000000, /* PA_SC_EDGERULE */
162
163	0xc0406900,
164	0x00000094,
165	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
166	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
167	0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
168	0x20002000,
169	0x80000000,
170	0x20002000,
171	0x80000000,
172	0x20002000,
173	0x80000000,
174	0x20002000,
175	0x80000000,
176	0x20002000,
177	0x80000000,
178	0x20002000,
179	0x80000000,
180	0x20002000,
181	0x80000000,
182	0x20002000,
183	0x80000000,
184	0x20002000,
185	0x80000000,
186	0x20002000,
187	0x80000000,
188	0x20002000,
189	0x80000000,
190	0x20002000,
191	0x80000000,
192	0x20002000,
193	0x80000000,
194	0x20002000,
195	0x80000000,
196	0x20002000,
197	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
198	0x3f800000,
199	0x00000000,
200	0x3f800000,
201	0x00000000,
202	0x3f800000,
203	0x00000000,
204	0x3f800000,
205	0x00000000,
206	0x3f800000,
207	0x00000000,
208	0x3f800000,
209	0x00000000,
210	0x3f800000,
211	0x00000000,
212	0x3f800000,
213	0x00000000,
214	0x3f800000,
215	0x00000000,
216	0x3f800000,
217	0x00000000,
218	0x3f800000,
219	0x00000000,
220	0x3f800000,
221	0x00000000,
222	0x3f800000,
223	0x00000000,
224	0x3f800000,
225	0x00000000,
226	0x3f800000,
227	0x00000000,
228	0x3f800000,
229
230	0xc0026900,
231	0x00000292,
232	0x00000000, /* PA_SC_MPASS_PS_CNTL */
233	0x00004010, /* PA_SC_MODE_CNTL */
234
235	0xc0096900,
236	0x00000300,
237	0x00000000, /* PA_SC_LINE_CNTL */
238	0x00000000, /* PA_SC_AA_CONFIG */
239	0x0000002d, /* PA_SU_VTX_CNTL */
240	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
241	0x3f800000,
242	0x3f800000,
243	0x3f800000,
244	0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
245	0x00000000,
246
247	0xc0016900,
248	0x00000312,
249	0xffffffff, /* PA_SC_AA_MASK */
250
251	0xc0066900,
252	0x0000037e,
253	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
254	0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
255	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
256	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
257	0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
258	0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
259
260	0xc0046900,
261	0x000001b6,
262	0x00000000, /* SPI_INPUT_Z */
263	0x00000000, /* SPI_FOG_CNTL */
264	0x00000000, /* SPI_FOG_FUNC_SCALE */
265	0x00000000, /* SPI_FOG_FUNC_BIAS */
266
267	0xc0016900,
268	0x00000225,
269	0x00000000, /* SQ_PGM_START_FS */
270
271	0xc0016900,
272	0x00000229,
273	0x00000000, /* SQ_PGM_RESOURCES_FS */
274
275	0xc0016900,
276	0x00000237,
277	0x00000000, /* SQ_PGM_CF_OFFSET_FS */
278
279	0xc0026900,
280	0x000002a8,
281	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
282	0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
283
284	0xc0116900,
285	0x00000280,
286	0x00000000, /* PA_SU_POINT_SIZE */
287	0x00000000, /* PA_SU_POINT_MINMAX */
288	0x00000008, /* PA_SU_LINE_CNTL */
289	0x00000000, /* PA_SC_LINE_STIPPLE */
290	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
291	0x00000000, /* VGT_HOS_CNTL */
292	0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
293	0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
294	0x00000000, /* VGT_HOS_REUSE_DEPTH */
295	0x00000000, /* VGT_GROUP_PRIM_TYPE */
296	0x00000000, /* VGT_GROUP_FIRST_DECR */
297	0x00000000, /* VGT_GROUP_DECR */
298	0x00000000, /* VGT_GROUP_VECT_0_CNTL */
299	0x00000000, /* VGT_GROUP_VECT_1_CNTL */
300	0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
301	0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
302	0x00000000, /* VGT_GS_MODE */
303
304	0xc0016900,
305	0x000002a1,
306	0x00000000, /* VGT_PRIMITIVEID_EN */
307
308	0xc0016900,
309	0x000002a5,
310	0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
311
312	0xc0036900,
313	0x000002ac,
314	0x00000000, /* VGT_STRMOUT_EN */
315	0x00000000, /* VGT_REUSE_OFF */
316	0x00000000, /* VGT_VTX_CNT_EN */
317
318	0xc0016900,
319	0x000000d4,
320	0x00000000, /* SX_MISC */
321
322	0xc0016900,
323	0x000002c8,
324	0x00000000, /* VGT_STRMOUT_BUFFER_EN */
325
326	0xc0076900,
327	0x00000202,
328	0x00cc0000, /* CB_COLOR_CONTROL */
329	0x00000210, /* DB_SHADER_CNTL */
330	0x00010000, /* PA_CL_CLIP_CNTL */
331	0x00000244, /* PA_SU_SC_MODE_CNTL */
332	0x00000100, /* PA_CL_VTE_CNTL */
333	0x00000000, /* PA_CL_VS_OUT_CNTL */
334	0x00000000, /* PA_CL_NANINF_CNTL */
335
336	0xc0026900,
337	0x0000008e,
338	0x0000000f, /* CB_TARGET_MASK */
339	0x0000000f, /* CB_SHADER_MASK */
340
341	0xc0016900,
342	0x000001e8,
343	0x00000001, /* CB_SHADER_CONTROL */
344
345	0xc0016900,
346	0x00000185,
347	0x00000000, /* SPI_VS_OUT_ID_0 */
348
349	0xc0016900,
350	0x00000191,
351	0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
352
353	0xc0056900,
354	0x000001b1,
355	0x00000000, /* SPI_VS_OUT_CONFIG */
356	0x00000000, /* SPI_THREAD_GROUPING */
357	0x00000001, /* SPI_PS_IN_CONTROL_0 */
358	0x00000000, /* SPI_PS_IN_CONTROL_1 */
359	0x00000000, /* SPI_INTERP_CONTROL_0 */
360
361	0xc0036e00, /* SET_SAMPLER */
362	0x00000000,
363	0x00000012,
364	0x00000000,
365	0x00000000,
366};
367
368const u32 r7xx_default_state[] =
369{
370	0xc0012800, /* CONTEXT_CONTROL */
371	0x80000000,
372	0x80000000,
373
374	0xc0016800,
375	0x00000010,
376	0x00008000, /* WAIT_UNTIL */
377
378	0xc0016800,
379	0x00000542,
380	0x07000002, /* TA_CNTL_AUX */
381
382	0xc0016800,
383	0x000005c5,
384	0x00000000, /* VC_ENHANCE */
385
386	0xc0016800,
387	0x00000363,
388	0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
389
390	0xc0016800,
391	0x0000060c,
392	0x00000000, /* DB_DEBUG */
393
394	0xc0016800,
395	0x0000060e,
396	0x00420204, /* DB_WATERMARKS */
397
398	0xc0026f00,
399	0x00000000,
400	0x00000000, /* SQ_VTX_BASE_VTX_LOC */
401	0x00000000, /* SQ_VTX_START_INST_LOC */
402
403	0xc0096900,
404	0x0000022a,
405	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
406	0x00000000,
407	0x00000000,
408	0x00000000,
409	0x00000000,
410	0x00000000,
411	0x00000000,
412	0x00000000,
413	0x00000000,
414
415	0xc0016900,
416	0x00000004,
417	0x00000000, /* DB_DEPTH_INFO */
418
419	0xc0026900,
420	0x0000000a,
421	0x00000000, /* DB_STENCIL_CLEAR */
422	0x00000000, /* DB_DEPTH_CLEAR */
423
424	0xc0016900,
425	0x00000200,
426	0x00000000, /* DB_DEPTH_CONTROL */
427
428	0xc0026900,
429	0x00000343,
430	0x00000060, /* DB_RENDER_CONTROL */
431	0x00000000, /* DB_RENDER_OVERRIDE */
432
433	0xc0016900,
434	0x00000351,
435	0x0000aa00, /* DB_ALPHA_TO_MASK */
436
437	0xc0096900,
438	0x00000100,
439	0x00000800, /* VGT_MAX_VTX_INDX */
440	0x00000000, /* VGT_MIN_VTX_INDX */
441	0x00000000, /* VGT_INDX_OFFSET */
442	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
443	0x00000000, /* SX_ALPHA_TEST_CONTROL */
444	0x00000000, /* CB_BLEND_RED */
445	0x00000000,
446	0x00000000,
447	0x00000000,
448
449	0xc0036900,
450	0x0000010c,
451	0x00000000, /* DB_STENCILREFMASK */
452	0x00000000, /* DB_STENCILREFMASK_BF */
453	0x00000000, /* SX_ALPHA_REF */
454
455	0xc0046900,
456	0x0000030c, /* CB_CLRCMP_CNTL */
457	0x01000000,
458	0x00000000,
459	0x00000000,
460	0x00000000,
461
462	0xc0016900,
463	0x00000080,
464	0x00000000, /* PA_SC_WINDOW_OFFSET */
465
466	0xc00a6900,
467	0x00000083,
468	0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
469	0x00000000, /* PA_SC_CLIPRECT_0_TL */
470	0x20002000,
471	0x00000000,
472	0x20002000,
473	0x00000000,
474	0x20002000,
475	0x00000000,
476	0x20002000,
477	0xaaaaaaaa, /* PA_SC_EDGERULE */
478
479	0xc0406900,
480	0x00000094,
481	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
482	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
483	0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
484	0x20002000,
485	0x80000000,
486	0x20002000,
487	0x80000000,
488	0x20002000,
489	0x80000000,
490	0x20002000,
491	0x80000000,
492	0x20002000,
493	0x80000000,
494	0x20002000,
495	0x80000000,
496	0x20002000,
497	0x80000000,
498	0x20002000,
499	0x80000000,
500	0x20002000,
501	0x80000000,
502	0x20002000,
503	0x80000000,
504	0x20002000,
505	0x80000000,
506	0x20002000,
507	0x80000000,
508	0x20002000,
509	0x80000000,
510	0x20002000,
511	0x80000000,
512	0x20002000,
513	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
514	0x3f800000,
515	0x00000000,
516	0x3f800000,
517	0x00000000,
518	0x3f800000,
519	0x00000000,
520	0x3f800000,
521	0x00000000,
522	0x3f800000,
523	0x00000000,
524	0x3f800000,
525	0x00000000,
526	0x3f800000,
527	0x00000000,
528	0x3f800000,
529	0x00000000,
530	0x3f800000,
531	0x00000000,
532	0x3f800000,
533	0x00000000,
534	0x3f800000,
535	0x00000000,
536	0x3f800000,
537	0x00000000,
538	0x3f800000,
539	0x00000000,
540	0x3f800000,
541	0x00000000,
542	0x3f800000,
543	0x00000000,
544	0x3f800000,
545
546	0xc0026900,
547	0x00000292,
548	0x00000000, /* PA_SC_MPASS_PS_CNTL */
549	0x00514000, /* PA_SC_MODE_CNTL */
550
551	0xc0096900,
552	0x00000300,
553	0x00000000, /* PA_SC_LINE_CNTL */
554	0x00000000, /* PA_SC_AA_CONFIG */
555	0x0000002d, /* PA_SU_VTX_CNTL */
556	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
557	0x3f800000,
558	0x3f800000,
559	0x3f800000,
560	0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
561	0x00000000,
562
563	0xc0016900,
564	0x00000312,
565	0xffffffff, /* PA_SC_AA_MASK */
566
567	0xc0066900,
568	0x0000037e,
569	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
570	0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
571	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
572	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
573	0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
574	0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
575
576	0xc0046900,
577	0x000001b6,
578	0x00000000, /* SPI_INPUT_Z */
579	0x00000000, /* SPI_FOG_CNTL */
580	0x00000000, /* SPI_FOG_FUNC_SCALE */
581	0x00000000, /* SPI_FOG_FUNC_BIAS */
582
583	0xc0016900,
584	0x00000225,
585	0x00000000, /* SQ_PGM_START_FS */
586
587	0xc0016900,
588	0x00000229,
589	0x00000000, /* SQ_PGM_RESOURCES_FS */
590
591	0xc0016900,
592	0x00000237,
593	0x00000000, /* SQ_PGM_CF_OFFSET_FS */
594
595	0xc0026900,
596	0x000002a8,
597	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
598	0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
599
600	0xc0116900,
601	0x00000280,
602	0x00000000, /* PA_SU_POINT_SIZE */
603	0x00000000, /* PA_SU_POINT_MINMAX */
604	0x00000008, /* PA_SU_LINE_CNTL */
605	0x00000000, /* PA_SC_LINE_STIPPLE */
606	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
607	0x00000000, /* VGT_HOS_CNTL */
608	0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
609	0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
610	0x00000000, /* VGT_HOS_REUSE_DEPTH */
611	0x00000000, /* VGT_GROUP_PRIM_TYPE */
612	0x00000000, /* VGT_GROUP_FIRST_DECR */
613	0x00000000, /* VGT_GROUP_DECR */
614	0x00000000, /* VGT_GROUP_VECT_0_CNTL */
615	0x00000000, /* VGT_GROUP_VECT_1_CNTL */
616	0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
617	0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
618	0x00000000, /* VGT_GS_MODE */
619
620	0xc0016900,
621	0x000002a1,
622	0x00000000, /* VGT_PRIMITIVEID_EN */
623
624	0xc0016900,
625	0x000002a5,
626	0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
627
628	0xc0036900,
629	0x000002ac,
630	0x00000000, /* VGT_STRMOUT_EN */
631	0x00000000, /* VGT_REUSE_OFF */
632	0x00000000, /* VGT_VTX_CNT_EN */
633
634	0xc0016900,
635	0x000000d4,
636	0x00000000, /* SX_MISC */
637
638	0xc0016900,
639	0x000002c8,
640	0x00000000, /* VGT_STRMOUT_BUFFER_EN */
641
642	0xc0076900,
643	0x00000202,
644	0x00cc0000, /* CB_COLOR_CONTROL */
645	0x00000210, /* DB_SHADER_CNTL */
646	0x00010000, /* PA_CL_CLIP_CNTL */
647	0x00000244, /* PA_SU_SC_MODE_CNTL */
648	0x00000100, /* PA_CL_VTE_CNTL */
649	0x00000000, /* PA_CL_VS_OUT_CNTL */
650	0x00000000, /* PA_CL_NANINF_CNTL */
651
652	0xc0026900,
653	0x0000008e,
654	0x0000000f, /* CB_TARGET_MASK */
655	0x0000000f, /* CB_SHADER_MASK */
656
657	0xc0016900,
658	0x000001e8,
659	0x00000001, /* CB_SHADER_CONTROL */
660
661	0xc0016900,
662	0x00000185,
663	0x00000000, /* SPI_VS_OUT_ID_0 */
664
665	0xc0016900,
666	0x00000191,
667	0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
668
669	0xc0056900,
670	0x000001b1,
671	0x00000000, /* SPI_VS_OUT_CONFIG */
672	0x00000001, /* SPI_THREAD_GROUPING */
673	0x00000001, /* SPI_PS_IN_CONTROL_0 */
674	0x00000000, /* SPI_PS_IN_CONTROL_1 */
675	0x00000000, /* SPI_INTERP_CONTROL_0 */
676
677	0xc0036e00, /* SET_SAMPLER */
678	0x00000000,
679	0x00000012,
680	0x00000000,
681	0x00000000,
682};
683
684/* same for r6xx/r7xx */
685const u32 r6xx_vs[] =
686{
687	0x00000004,
688	0x81000000,
689	0x0000203c,
690	0x94000b08,
691	0x00004000,
692	0x14200b1a,
693	0x00000000,
694	0x00000000,
695	0x3c000000,
696	0x68cd1000,
697#ifdef __BIG_ENDIAN
698	0x000a0000,
699#else
700	0x00080000,
701#endif
702	0x00000000,
703};
704
705const u32 r6xx_ps[] =
706{
707	0x00000002,
708	0x80800000,
709	0x00000000,
710	0x94200688,
711	0x00000010,
712	0x000d1000,
713	0xb0800000,
714	0x00000000,
715};
716
717const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
718const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
719const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
720const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
721