1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell 29254885Sdumbbell#include <sys/cdefs.h> 30254885Sdumbbell__FBSDID("$FreeBSD$"); 31254885Sdumbbell 32254885Sdumbbell#include <dev/drm2/drmP.h> 33254885Sdumbbell#include "radeon_reg.h" 34254885Sdumbbell#include "radeon.h" 35254885Sdumbbell#include "radeon_asic.h" 36254885Sdumbbell#include "atom.h" 37254885Sdumbbell#include "r100d.h" 38254885Sdumbbell#include "r420d.h" 39254885Sdumbbell#include "r420_reg_safe.h" 40254885Sdumbbell 41254885Sdumbbellvoid r420_pm_init_profile(struct radeon_device *rdev) 42254885Sdumbbell{ 43254885Sdumbbell /* default */ 44254885Sdumbbell rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 45254885Sdumbbell rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 46254885Sdumbbell rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 47254885Sdumbbell rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 48254885Sdumbbell /* low sh */ 49254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 50254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 51254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 52254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 53254885Sdumbbell /* mid sh */ 54254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 55254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 56254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 57254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 58254885Sdumbbell /* high sh */ 59254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 60254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 61254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 62254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 63254885Sdumbbell /* low mh */ 64254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 65254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 66254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 67254885Sdumbbell rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 68254885Sdumbbell /* mid mh */ 69254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 70254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 71254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 72254885Sdumbbell rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 73254885Sdumbbell /* high mh */ 74254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 75254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 76254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 77254885Sdumbbell rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 78254885Sdumbbell} 79254885Sdumbbell 80254885Sdumbbellstatic void r420_set_reg_safe(struct radeon_device *rdev) 81254885Sdumbbell{ 82254885Sdumbbell rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 83280183Sdumbbell rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 84254885Sdumbbell} 85254885Sdumbbell 86254885Sdumbbellvoid r420_pipes_init(struct radeon_device *rdev) 87254885Sdumbbell{ 88254885Sdumbbell unsigned tmp; 89254885Sdumbbell unsigned gb_pipe_select; 90254885Sdumbbell unsigned num_pipes; 91254885Sdumbbell 92254885Sdumbbell /* GA_ENHANCE workaround TCL deadlock issue */ 93254885Sdumbbell WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 94254885Sdumbbell (1 << 2) | (1 << 3)); 95254885Sdumbbell /* add idle wait as per freedesktop.org bug 24041 */ 96254885Sdumbbell if (r100_gui_wait_for_idle(rdev)) { 97254885Sdumbbell DRM_ERROR("Failed to wait GUI idle while " 98254885Sdumbbell "programming pipes. Bad things might happen.\n"); 99254885Sdumbbell } 100254885Sdumbbell /* get max number of pipes */ 101254885Sdumbbell gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 102254885Sdumbbell num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 103254885Sdumbbell 104254885Sdumbbell /* SE chips have 1 pipe */ 105254885Sdumbbell if ((rdev->ddev->pci_device == 0x5e4c) || 106254885Sdumbbell (rdev->ddev->pci_device == 0x5e4f)) 107254885Sdumbbell num_pipes = 1; 108254885Sdumbbell 109254885Sdumbbell rdev->num_gb_pipes = num_pipes; 110254885Sdumbbell tmp = 0; 111254885Sdumbbell switch (num_pipes) { 112254885Sdumbbell default: 113254885Sdumbbell /* force to 1 pipe */ 114254885Sdumbbell num_pipes = 1; 115254885Sdumbbell case 1: 116254885Sdumbbell tmp = (0 << 1); 117254885Sdumbbell break; 118254885Sdumbbell case 2: 119254885Sdumbbell tmp = (3 << 1); 120254885Sdumbbell break; 121254885Sdumbbell case 3: 122254885Sdumbbell tmp = (6 << 1); 123254885Sdumbbell break; 124254885Sdumbbell case 4: 125254885Sdumbbell tmp = (7 << 1); 126254885Sdumbbell break; 127254885Sdumbbell } 128254885Sdumbbell WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 129254885Sdumbbell /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 130254885Sdumbbell tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 131254885Sdumbbell WREG32(R300_GB_TILE_CONFIG, tmp); 132254885Sdumbbell if (r100_gui_wait_for_idle(rdev)) { 133254885Sdumbbell DRM_ERROR("Failed to wait GUI idle while " 134254885Sdumbbell "programming pipes. Bad things might happen.\n"); 135254885Sdumbbell } 136254885Sdumbbell 137254885Sdumbbell tmp = RREG32(R300_DST_PIPE_CONFIG); 138254885Sdumbbell WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 139254885Sdumbbell 140254885Sdumbbell WREG32(R300_RB2D_DSTCACHE_MODE, 141254885Sdumbbell RREG32(R300_RB2D_DSTCACHE_MODE) | 142254885Sdumbbell R300_DC_AUTOFLUSH_ENABLE | 143254885Sdumbbell R300_DC_DC_DISABLE_IGNORE_PE); 144254885Sdumbbell 145254885Sdumbbell if (r100_gui_wait_for_idle(rdev)) { 146254885Sdumbbell DRM_ERROR("Failed to wait GUI idle while " 147254885Sdumbbell "programming pipes. Bad things might happen.\n"); 148254885Sdumbbell } 149254885Sdumbbell 150254885Sdumbbell if (rdev->family == CHIP_RV530) { 151254885Sdumbbell tmp = RREG32(RV530_GB_PIPE_SELECT2); 152254885Sdumbbell if ((tmp & 3) == 3) 153254885Sdumbbell rdev->num_z_pipes = 2; 154254885Sdumbbell else 155254885Sdumbbell rdev->num_z_pipes = 1; 156254885Sdumbbell } else 157254885Sdumbbell rdev->num_z_pipes = 1; 158254885Sdumbbell 159254885Sdumbbell DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 160254885Sdumbbell rdev->num_gb_pipes, rdev->num_z_pipes); 161254885Sdumbbell} 162254885Sdumbbell 163254885Sdumbbellu32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 164254885Sdumbbell{ 165254885Sdumbbell u32 r; 166254885Sdumbbell 167254885Sdumbbell WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 168254885Sdumbbell r = RREG32(R_0001FC_MC_IND_DATA); 169254885Sdumbbell return r; 170254885Sdumbbell} 171254885Sdumbbell 172254885Sdumbbellvoid r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 173254885Sdumbbell{ 174254885Sdumbbell WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 175254885Sdumbbell S_0001F8_MC_IND_WR_EN(1)); 176254885Sdumbbell WREG32(R_0001FC_MC_IND_DATA, v); 177254885Sdumbbell} 178254885Sdumbbell 179254885Sdumbbellstatic void r420_debugfs(struct radeon_device *rdev) 180254885Sdumbbell{ 181254885Sdumbbell if (r100_debugfs_rbbm_init(rdev)) { 182254885Sdumbbell DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 183254885Sdumbbell } 184254885Sdumbbell if (r420_debugfs_pipes_info_init(rdev)) { 185254885Sdumbbell DRM_ERROR("Failed to register debugfs file for pipes !\n"); 186254885Sdumbbell } 187254885Sdumbbell} 188254885Sdumbbell 189254885Sdumbbellstatic void r420_clock_resume(struct radeon_device *rdev) 190254885Sdumbbell{ 191254885Sdumbbell u32 sclk_cntl; 192254885Sdumbbell 193254885Sdumbbell if (radeon_dynclks != -1 && radeon_dynclks) 194254885Sdumbbell radeon_atom_set_clock_gating(rdev, 1); 195254885Sdumbbell sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 196254885Sdumbbell sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 197254885Sdumbbell if (rdev->family == CHIP_R420) 198254885Sdumbbell sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 199254885Sdumbbell WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 200254885Sdumbbell} 201254885Sdumbbell 202254885Sdumbbellstatic void r420_cp_errata_init(struct radeon_device *rdev) 203254885Sdumbbell{ 204254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 205254885Sdumbbell 206254885Sdumbbell /* RV410 and R420 can lock up if CP DMA to host memory happens 207254885Sdumbbell * while the 2D engine is busy. 208254885Sdumbbell * 209254885Sdumbbell * The proper workaround is to queue a RESYNC at the beginning 210254885Sdumbbell * of the CP init, apparently. 211254885Sdumbbell */ 212254885Sdumbbell radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 213254885Sdumbbell radeon_ring_lock(rdev, ring, 8); 214254885Sdumbbell radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 215254885Sdumbbell radeon_ring_write(ring, rdev->config.r300.resync_scratch); 216254885Sdumbbell radeon_ring_write(ring, 0xDEADBEEF); 217254885Sdumbbell radeon_ring_unlock_commit(rdev, ring); 218254885Sdumbbell} 219254885Sdumbbell 220254885Sdumbbellstatic void r420_cp_errata_fini(struct radeon_device *rdev) 221254885Sdumbbell{ 222254885Sdumbbell struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 223254885Sdumbbell 224254885Sdumbbell /* Catch the RESYNC we dispatched all the way back, 225254885Sdumbbell * at the very beginning of the CP init. 226254885Sdumbbell */ 227254885Sdumbbell radeon_ring_lock(rdev, ring, 8); 228254885Sdumbbell radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 229254885Sdumbbell radeon_ring_write(ring, R300_RB3D_DC_FINISH); 230254885Sdumbbell radeon_ring_unlock_commit(rdev, ring); 231254885Sdumbbell radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 232254885Sdumbbell} 233254885Sdumbbell 234254885Sdumbbellstatic int r420_startup(struct radeon_device *rdev) 235254885Sdumbbell{ 236254885Sdumbbell int r; 237254885Sdumbbell 238254885Sdumbbell /* set common regs */ 239254885Sdumbbell r100_set_common_regs(rdev); 240254885Sdumbbell /* program mc */ 241254885Sdumbbell r300_mc_program(rdev); 242254885Sdumbbell /* Resume clock */ 243254885Sdumbbell r420_clock_resume(rdev); 244254885Sdumbbell /* Initialize GART (initialize after TTM so we can allocate 245254885Sdumbbell * memory through TTM but finalize after TTM) */ 246254885Sdumbbell if (rdev->flags & RADEON_IS_PCIE) { 247254885Sdumbbell r = rv370_pcie_gart_enable(rdev); 248254885Sdumbbell if (r) 249254885Sdumbbell return r; 250254885Sdumbbell } 251254885Sdumbbell if (rdev->flags & RADEON_IS_PCI) { 252254885Sdumbbell r = r100_pci_gart_enable(rdev); 253254885Sdumbbell if (r) 254254885Sdumbbell return r; 255254885Sdumbbell } 256254885Sdumbbell r420_pipes_init(rdev); 257254885Sdumbbell 258254885Sdumbbell /* allocate wb buffer */ 259254885Sdumbbell r = radeon_wb_init(rdev); 260254885Sdumbbell if (r) 261254885Sdumbbell return r; 262254885Sdumbbell 263254885Sdumbbell r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 264254885Sdumbbell if (r) { 265254885Sdumbbell dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 266254885Sdumbbell return r; 267254885Sdumbbell } 268254885Sdumbbell 269254885Sdumbbell /* Enable IRQ */ 270254885Sdumbbell r100_irq_set(rdev); 271254885Sdumbbell rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 272254885Sdumbbell /* 1M ring buffer */ 273254885Sdumbbell r = r100_cp_init(rdev, 1024 * 1024); 274254885Sdumbbell if (r) { 275254885Sdumbbell dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 276254885Sdumbbell return r; 277254885Sdumbbell } 278254885Sdumbbell r420_cp_errata_init(rdev); 279254885Sdumbbell 280254885Sdumbbell r = radeon_ib_pool_init(rdev); 281254885Sdumbbell if (r) { 282254885Sdumbbell dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 283254885Sdumbbell return r; 284254885Sdumbbell } 285254885Sdumbbell 286254885Sdumbbell return 0; 287254885Sdumbbell} 288254885Sdumbbell 289254885Sdumbbellint r420_resume(struct radeon_device *rdev) 290254885Sdumbbell{ 291254885Sdumbbell int r; 292254885Sdumbbell 293254885Sdumbbell /* Make sur GART are not working */ 294254885Sdumbbell if (rdev->flags & RADEON_IS_PCIE) 295254885Sdumbbell rv370_pcie_gart_disable(rdev); 296254885Sdumbbell if (rdev->flags & RADEON_IS_PCI) 297254885Sdumbbell r100_pci_gart_disable(rdev); 298254885Sdumbbell /* Resume clock before doing reset */ 299254885Sdumbbell r420_clock_resume(rdev); 300254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 301254885Sdumbbell if (radeon_asic_reset(rdev)) { 302254885Sdumbbell dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 303254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 304254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 305254885Sdumbbell } 306254885Sdumbbell /* check if cards are posted or not */ 307254885Sdumbbell if (rdev->is_atom_bios) { 308254885Sdumbbell atom_asic_init(rdev->mode_info.atom_context); 309254885Sdumbbell } else { 310254885Sdumbbell radeon_combios_asic_init(rdev->ddev); 311254885Sdumbbell } 312254885Sdumbbell /* Resume clock after posting */ 313254885Sdumbbell r420_clock_resume(rdev); 314254885Sdumbbell /* Initialize surface registers */ 315254885Sdumbbell radeon_surface_init(rdev); 316254885Sdumbbell 317254885Sdumbbell rdev->accel_working = true; 318254885Sdumbbell r = r420_startup(rdev); 319254885Sdumbbell if (r) { 320254885Sdumbbell rdev->accel_working = false; 321254885Sdumbbell } 322254885Sdumbbell return r; 323254885Sdumbbell} 324254885Sdumbbell 325254885Sdumbbellint r420_suspend(struct radeon_device *rdev) 326254885Sdumbbell{ 327254885Sdumbbell r420_cp_errata_fini(rdev); 328254885Sdumbbell r100_cp_disable(rdev); 329254885Sdumbbell radeon_wb_disable(rdev); 330254885Sdumbbell r100_irq_disable(rdev); 331254885Sdumbbell if (rdev->flags & RADEON_IS_PCIE) 332254885Sdumbbell rv370_pcie_gart_disable(rdev); 333254885Sdumbbell if (rdev->flags & RADEON_IS_PCI) 334254885Sdumbbell r100_pci_gart_disable(rdev); 335254885Sdumbbell return 0; 336254885Sdumbbell} 337254885Sdumbbell 338254885Sdumbbellvoid r420_fini(struct radeon_device *rdev) 339254885Sdumbbell{ 340254885Sdumbbell r100_cp_fini(rdev); 341254885Sdumbbell radeon_wb_fini(rdev); 342254885Sdumbbell radeon_ib_pool_fini(rdev); 343254885Sdumbbell radeon_gem_fini(rdev); 344254885Sdumbbell if (rdev->flags & RADEON_IS_PCIE) 345254885Sdumbbell rv370_pcie_gart_fini(rdev); 346254885Sdumbbell if (rdev->flags & RADEON_IS_PCI) 347254885Sdumbbell r100_pci_gart_fini(rdev); 348254885Sdumbbell radeon_agp_fini(rdev); 349254885Sdumbbell radeon_irq_kms_fini(rdev); 350254885Sdumbbell radeon_fence_driver_fini(rdev); 351254885Sdumbbell radeon_bo_fini(rdev); 352254885Sdumbbell if (rdev->is_atom_bios) { 353254885Sdumbbell radeon_atombios_fini(rdev); 354254885Sdumbbell } else { 355254885Sdumbbell radeon_combios_fini(rdev); 356254885Sdumbbell } 357254885Sdumbbell free(rdev->bios, DRM_MEM_DRIVER); 358254885Sdumbbell rdev->bios = NULL; 359254885Sdumbbell} 360254885Sdumbbell 361254885Sdumbbellint r420_init(struct radeon_device *rdev) 362254885Sdumbbell{ 363254885Sdumbbell int r; 364254885Sdumbbell 365254885Sdumbbell /* Initialize scratch registers */ 366254885Sdumbbell radeon_scratch_init(rdev); 367254885Sdumbbell /* Initialize surface registers */ 368254885Sdumbbell radeon_surface_init(rdev); 369254885Sdumbbell /* TODO: disable VGA need to use VGA request */ 370254885Sdumbbell /* restore some register to sane defaults */ 371254885Sdumbbell r100_restore_sanity(rdev); 372254885Sdumbbell /* BIOS*/ 373254885Sdumbbell if (!radeon_get_bios(rdev)) { 374254885Sdumbbell if (ASIC_IS_AVIVO(rdev)) 375254885Sdumbbell return -EINVAL; 376254885Sdumbbell } 377254885Sdumbbell if (rdev->is_atom_bios) { 378254885Sdumbbell r = radeon_atombios_init(rdev); 379254885Sdumbbell if (r) { 380254885Sdumbbell return r; 381254885Sdumbbell } 382254885Sdumbbell } else { 383254885Sdumbbell r = radeon_combios_init(rdev); 384254885Sdumbbell if (r) { 385254885Sdumbbell return r; 386254885Sdumbbell } 387254885Sdumbbell } 388254885Sdumbbell /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 389254885Sdumbbell if (radeon_asic_reset(rdev)) { 390254885Sdumbbell dev_warn(rdev->dev, 391254885Sdumbbell "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 392254885Sdumbbell RREG32(R_000E40_RBBM_STATUS), 393254885Sdumbbell RREG32(R_0007C0_CP_STAT)); 394254885Sdumbbell } 395254885Sdumbbell /* check if cards are posted or not */ 396254885Sdumbbell if (radeon_boot_test_post_card(rdev) == false) 397254885Sdumbbell return -EINVAL; 398254885Sdumbbell 399254885Sdumbbell /* Initialize clocks */ 400254885Sdumbbell radeon_get_clock_info(rdev->ddev); 401254885Sdumbbell /* initialize AGP */ 402254885Sdumbbell if (rdev->flags & RADEON_IS_AGP) { 403254885Sdumbbell r = radeon_agp_init(rdev); 404254885Sdumbbell if (r) { 405254885Sdumbbell radeon_agp_disable(rdev); 406254885Sdumbbell } 407254885Sdumbbell } 408254885Sdumbbell /* initialize memory controller */ 409254885Sdumbbell r300_mc_init(rdev); 410254885Sdumbbell r420_debugfs(rdev); 411254885Sdumbbell /* Fence driver */ 412254885Sdumbbell r = radeon_fence_driver_init(rdev); 413254885Sdumbbell if (r) { 414254885Sdumbbell return r; 415254885Sdumbbell } 416254885Sdumbbell r = radeon_irq_kms_init(rdev); 417254885Sdumbbell if (r) { 418254885Sdumbbell return r; 419254885Sdumbbell } 420254885Sdumbbell /* Memory manager */ 421254885Sdumbbell r = radeon_bo_init(rdev); 422254885Sdumbbell if (r) { 423254885Sdumbbell return r; 424254885Sdumbbell } 425254885Sdumbbell if (rdev->family == CHIP_R420) 426254885Sdumbbell r100_enable_bm(rdev); 427254885Sdumbbell 428254885Sdumbbell if (rdev->flags & RADEON_IS_PCIE) { 429254885Sdumbbell r = rv370_pcie_gart_init(rdev); 430254885Sdumbbell if (r) 431254885Sdumbbell return r; 432254885Sdumbbell } 433254885Sdumbbell if (rdev->flags & RADEON_IS_PCI) { 434254885Sdumbbell r = r100_pci_gart_init(rdev); 435254885Sdumbbell if (r) 436254885Sdumbbell return r; 437254885Sdumbbell } 438254885Sdumbbell r420_set_reg_safe(rdev); 439254885Sdumbbell 440254885Sdumbbell rdev->accel_working = true; 441254885Sdumbbell r = r420_startup(rdev); 442254885Sdumbbell if (r) { 443254885Sdumbbell /* Somethings want wront with the accel init stop accel */ 444254885Sdumbbell dev_err(rdev->dev, "Disabling GPU acceleration\n"); 445254885Sdumbbell r100_cp_fini(rdev); 446254885Sdumbbell radeon_wb_fini(rdev); 447254885Sdumbbell radeon_ib_pool_fini(rdev); 448254885Sdumbbell radeon_irq_kms_fini(rdev); 449254885Sdumbbell if (rdev->flags & RADEON_IS_PCIE) 450254885Sdumbbell rv370_pcie_gart_fini(rdev); 451254885Sdumbbell if (rdev->flags & RADEON_IS_PCI) 452254885Sdumbbell r100_pci_gart_fini(rdev); 453254885Sdumbbell radeon_agp_fini(rdev); 454254885Sdumbbell rdev->accel_working = false; 455254885Sdumbbell } 456254885Sdumbbell return 0; 457254885Sdumbbell} 458254885Sdumbbell 459254885Sdumbbell/* 460254885Sdumbbell * Debugfs info 461254885Sdumbbell */ 462254885Sdumbbell#if defined(CONFIG_DEBUG_FS) 463254885Sdumbbellstatic int r420_debugfs_pipes_info(struct seq_file *m, void *data) 464254885Sdumbbell{ 465254885Sdumbbell struct drm_info_node *node = (struct drm_info_node *) m->private; 466254885Sdumbbell struct drm_device *dev = node->minor->dev; 467254885Sdumbbell struct radeon_device *rdev = dev->dev_private; 468254885Sdumbbell uint32_t tmp; 469254885Sdumbbell 470254885Sdumbbell tmp = RREG32(R400_GB_PIPE_SELECT); 471254885Sdumbbell seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 472254885Sdumbbell tmp = RREG32(R300_GB_TILE_CONFIG); 473254885Sdumbbell seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 474254885Sdumbbell tmp = RREG32(R300_DST_PIPE_CONFIG); 475254885Sdumbbell seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 476254885Sdumbbell return 0; 477254885Sdumbbell} 478254885Sdumbbell 479254885Sdumbbellstatic struct drm_info_list r420_pipes_info_list[] = { 480254885Sdumbbell {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 481254885Sdumbbell}; 482254885Sdumbbell#endif 483254885Sdumbbell 484254885Sdumbbellint r420_debugfs_pipes_info_init(struct radeon_device *rdev) 485254885Sdumbbell{ 486254885Sdumbbell#if defined(CONFIG_DEBUG_FS) 487254885Sdumbbell return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 488254885Sdumbbell#else 489254885Sdumbbell return 0; 490254885Sdumbbell#endif 491254885Sdumbbell} 492