atombios.h revision 298955
1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2006-2007 Advanced Micro Devices, Inc. 3254885Sdumbbell * 4254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 5254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 6254885Sdumbbell * to deal in the Software without restriction, including without limitation 7254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 9254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 10254885Sdumbbell * 11254885Sdumbbell * The above copyright notice and this permission notice shall be included in 12254885Sdumbbell * all copies or substantial portions of the Software. 13254885Sdumbbell * 14254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 21254885Sdumbbell */ 22254885Sdumbbell 23254885Sdumbbell#include <sys/cdefs.h> 24254885Sdumbbell__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/atombios.h 298955 2016-05-03 03:41:25Z pfg $"); 25254885Sdumbbell 26254885Sdumbbell 27254885Sdumbbell/****************************************************************************/ 28254885Sdumbbell/*Portion I: Definitions shared between VBIOS and Driver */ 29254885Sdumbbell/****************************************************************************/ 30254885Sdumbbell 31254885Sdumbbell 32254885Sdumbbell#ifndef _ATOMBIOS_H 33254885Sdumbbell#define _ATOMBIOS_H 34254885Sdumbbell 35254885Sdumbbell#define ATOM_VERSION_MAJOR 0x00020000 36254885Sdumbbell#define ATOM_VERSION_MINOR 0x00000002 37254885Sdumbbell 38254885Sdumbbell#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 39254885Sdumbbell 40254885Sdumbbell/* Endianness should be specified before inclusion, 41254885Sdumbbell * default to little endian 42254885Sdumbbell */ 43254885Sdumbbell#ifndef ATOM_BIG_ENDIAN 44254885Sdumbbell#error Endian not specified 45254885Sdumbbell#endif 46254885Sdumbbell 47254885Sdumbbell#ifdef _H2INC 48254885Sdumbbell #ifndef ULONG 49254885Sdumbbell typedef unsigned long ULONG; 50254885Sdumbbell #endif 51254885Sdumbbell 52254885Sdumbbell #ifndef UCHAR 53254885Sdumbbell typedef unsigned char UCHAR; 54254885Sdumbbell #endif 55254885Sdumbbell 56254885Sdumbbell #ifndef USHORT 57254885Sdumbbell typedef unsigned short USHORT; 58254885Sdumbbell #endif 59254885Sdumbbell#endif 60254885Sdumbbell 61254885Sdumbbell#define ATOM_DAC_A 0 62254885Sdumbbell#define ATOM_DAC_B 1 63254885Sdumbbell#define ATOM_EXT_DAC 2 64254885Sdumbbell 65254885Sdumbbell#define ATOM_CRTC1 0 66254885Sdumbbell#define ATOM_CRTC2 1 67254885Sdumbbell#define ATOM_CRTC3 2 68254885Sdumbbell#define ATOM_CRTC4 3 69254885Sdumbbell#define ATOM_CRTC5 4 70254885Sdumbbell#define ATOM_CRTC6 5 71254885Sdumbbell#define ATOM_CRTC_INVALID 0xFF 72254885Sdumbbell 73254885Sdumbbell#define ATOM_DIGA 0 74254885Sdumbbell#define ATOM_DIGB 1 75254885Sdumbbell 76254885Sdumbbell#define ATOM_PPLL1 0 77254885Sdumbbell#define ATOM_PPLL2 1 78254885Sdumbbell#define ATOM_DCPLL 2 79254885Sdumbbell#define ATOM_PPLL0 2 80254885Sdumbbell#define ATOM_EXT_PLL1 8 81254885Sdumbbell#define ATOM_EXT_PLL2 9 82254885Sdumbbell#define ATOM_EXT_CLOCK 10 83254885Sdumbbell#define ATOM_PPLL_INVALID 0xFF 84254885Sdumbbell 85254885Sdumbbell#define ENCODER_REFCLK_SRC_P1PLL 0 86254885Sdumbbell#define ENCODER_REFCLK_SRC_P2PLL 1 87254885Sdumbbell#define ENCODER_REFCLK_SRC_DCPLL 2 88254885Sdumbbell#define ENCODER_REFCLK_SRC_EXTCLK 3 89254885Sdumbbell#define ENCODER_REFCLK_SRC_INVALID 0xFF 90254885Sdumbbell 91254885Sdumbbell#define ATOM_SCALER1 0 92254885Sdumbbell#define ATOM_SCALER2 1 93254885Sdumbbell 94254885Sdumbbell#define ATOM_SCALER_DISABLE 0 95254885Sdumbbell#define ATOM_SCALER_CENTER 1 96254885Sdumbbell#define ATOM_SCALER_EXPANSION 2 97254885Sdumbbell#define ATOM_SCALER_MULTI_EX 3 98254885Sdumbbell 99254885Sdumbbell#define ATOM_DISABLE 0 100254885Sdumbbell#define ATOM_ENABLE 1 101254885Sdumbbell#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 102254885Sdumbbell#define ATOM_LCD_BLON (ATOM_ENABLE+2) 103254885Sdumbbell#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 104254885Sdumbbell#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 105254885Sdumbbell#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 106254885Sdumbbell#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 107254885Sdumbbell#define ATOM_INIT (ATOM_DISABLE+7) 108254885Sdumbbell#define ATOM_GET_STATUS (ATOM_DISABLE+8) 109254885Sdumbbell 110254885Sdumbbell#define ATOM_BLANKING 1 111254885Sdumbbell#define ATOM_BLANKING_OFF 0 112254885Sdumbbell 113254885Sdumbbell#define ATOM_CURSOR1 0 114254885Sdumbbell#define ATOM_CURSOR2 1 115254885Sdumbbell 116254885Sdumbbell#define ATOM_ICON1 0 117254885Sdumbbell#define ATOM_ICON2 1 118254885Sdumbbell 119254885Sdumbbell#define ATOM_CRT1 0 120254885Sdumbbell#define ATOM_CRT2 1 121254885Sdumbbell 122254885Sdumbbell#define ATOM_TV_NTSC 1 123254885Sdumbbell#define ATOM_TV_NTSCJ 2 124254885Sdumbbell#define ATOM_TV_PAL 3 125254885Sdumbbell#define ATOM_TV_PALM 4 126254885Sdumbbell#define ATOM_TV_PALCN 5 127254885Sdumbbell#define ATOM_TV_PALN 6 128254885Sdumbbell#define ATOM_TV_PAL60 7 129254885Sdumbbell#define ATOM_TV_SECAM 8 130254885Sdumbbell#define ATOM_TV_CV 16 131254885Sdumbbell 132254885Sdumbbell#define ATOM_DAC1_PS2 1 133254885Sdumbbell#define ATOM_DAC1_CV 2 134254885Sdumbbell#define ATOM_DAC1_NTSC 3 135254885Sdumbbell#define ATOM_DAC1_PAL 4 136254885Sdumbbell 137254885Sdumbbell#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 138254885Sdumbbell#define ATOM_DAC2_CV ATOM_DAC1_CV 139254885Sdumbbell#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 140254885Sdumbbell#define ATOM_DAC2_PAL ATOM_DAC1_PAL 141254885Sdumbbell 142254885Sdumbbell#define ATOM_PM_ON 0 143254885Sdumbbell#define ATOM_PM_STANDBY 1 144254885Sdumbbell#define ATOM_PM_SUSPEND 2 145254885Sdumbbell#define ATOM_PM_OFF 3 146254885Sdumbbell 147254885Sdumbbell/* Bit0:{=0:single, =1:dual}, 148254885Sdumbbell Bit1 {=0:666RGB, =1:888RGB}, 149254885Sdumbbell Bit2:3:{Grey level} 150254885Sdumbbell Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 151254885Sdumbbell 152254885Sdumbbell#define ATOM_PANEL_MISC_DUAL 0x00000001 153254885Sdumbbell#define ATOM_PANEL_MISC_888RGB 0x00000002 154254885Sdumbbell#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 155254885Sdumbbell#define ATOM_PANEL_MISC_FPDI 0x00000010 156254885Sdumbbell#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 157254885Sdumbbell#define ATOM_PANEL_MISC_SPATIAL 0x00000020 158254885Sdumbbell#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 159254885Sdumbbell#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 160254885Sdumbbell 161254885Sdumbbell 162254885Sdumbbell#define MEMTYPE_DDR1 "DDR1" 163254885Sdumbbell#define MEMTYPE_DDR2 "DDR2" 164254885Sdumbbell#define MEMTYPE_DDR3 "DDR3" 165254885Sdumbbell#define MEMTYPE_DDR4 "DDR4" 166254885Sdumbbell 167254885Sdumbbell#define ASIC_BUS_TYPE_PCI "PCI" 168254885Sdumbbell#define ASIC_BUS_TYPE_AGP "AGP" 169254885Sdumbbell#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 170254885Sdumbbell 171254885Sdumbbell/* Maximum size of that FireGL flag string */ 172254885Sdumbbell 173254885Sdumbbell#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 174254885Sdumbbell#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 175254885Sdumbbell 176254885Sdumbbell#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 177254885Sdumbbell#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 178254885Sdumbbell 179254885Sdumbbell#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 180254885Sdumbbell#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 181254885Sdumbbell 182254885Sdumbbell#define HW_ASSISTED_I2C_STATUS_FAILURE 2 183254885Sdumbbell#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 184254885Sdumbbell 185254885Sdumbbell#pragma pack(1) /* BIOS data must use byte aligment */ 186254885Sdumbbell 187254885Sdumbbell/* Define offset to location of ROM header. */ 188254885Sdumbbell 189254885Sdumbbell#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 190254885Sdumbbell#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 191254885Sdumbbell 192254885Sdumbbell#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 193254885Sdumbbell#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 194254885Sdumbbell#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 195254885Sdumbbell#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 196254885Sdumbbell 197254885Sdumbbell/* Common header for all ROM Data tables. 198254885Sdumbbell Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 199254885Sdumbbell And the pointer actually points to this header. */ 200254885Sdumbbell 201254885Sdumbbelltypedef struct _ATOM_COMMON_TABLE_HEADER 202254885Sdumbbell{ 203254885Sdumbbell USHORT usStructureSize; 204254885Sdumbbell UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 205254885Sdumbbell UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 206254885Sdumbbell /*Image can't be updated, while Driver needs to carry the new table! */ 207254885Sdumbbell}ATOM_COMMON_TABLE_HEADER; 208254885Sdumbbell 209254885Sdumbbell/****************************************************************************/ 210254885Sdumbbell// Structure stores the ROM header. 211254885Sdumbbell/****************************************************************************/ 212254885Sdumbbelltypedef struct _ATOM_ROM_HEADER 213254885Sdumbbell{ 214254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 215254885Sdumbbell UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 216254885Sdumbbell atombios should init it as "ATOM", don't change the position */ 217254885Sdumbbell USHORT usBiosRuntimeSegmentAddress; 218254885Sdumbbell USHORT usProtectedModeInfoOffset; 219254885Sdumbbell USHORT usConfigFilenameOffset; 220254885Sdumbbell USHORT usCRC_BlockOffset; 221254885Sdumbbell USHORT usBIOS_BootupMessageOffset; 222254885Sdumbbell USHORT usInt10Offset; 223254885Sdumbbell USHORT usPciBusDevInitCode; 224254885Sdumbbell USHORT usIoBaseAddress; 225254885Sdumbbell USHORT usSubsystemVendorID; 226254885Sdumbbell USHORT usSubsystemID; 227254885Sdumbbell USHORT usPCI_InfoOffset; 228254885Sdumbbell USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 229254885Sdumbbell USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 230254885Sdumbbell UCHAR ucExtendedFunctionCode; 231254885Sdumbbell UCHAR ucReserved; 232254885Sdumbbell}ATOM_ROM_HEADER; 233254885Sdumbbell 234254885Sdumbbell/*==============================Command Table Portion==================================== */ 235254885Sdumbbell 236254885Sdumbbell#ifdef UEFI_BUILD 237254885Sdumbbell #define UTEMP USHORT 238254885Sdumbbell #define USHORT void* 239254885Sdumbbell#endif 240254885Sdumbbell 241254885Sdumbbell/****************************************************************************/ 242254885Sdumbbell// Structures used in Command.mtb 243254885Sdumbbell/****************************************************************************/ 244254885Sdumbbelltypedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 245254885Sdumbbell USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 246254885Sdumbbell USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 247254885Sdumbbell USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 248254885Sdumbbell USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 249254885Sdumbbell USHORT DIGxEncoderControl; //Only used by Bios 250254885Sdumbbell USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 251254885Sdumbbell USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 252254885Sdumbbell USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 253254885Sdumbbell USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 254254885Sdumbbell USHORT GPIOPinControl; //Atomic Table, only used by Bios 255254885Sdumbbell USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 256254885Sdumbbell USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 257254885Sdumbbell USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 258254885Sdumbbell USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 259254885Sdumbbell USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 260254885Sdumbbell USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 261254885Sdumbbell USHORT MemoryPLLInit; //Atomic Table, used only by Bios 262254885Sdumbbell USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 263254885Sdumbbell USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 264254885Sdumbbell USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 265254885Sdumbbell USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios 266254885Sdumbbell USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 267254885Sdumbbell USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 268254885Sdumbbell USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 269254885Sdumbbell USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 270254885Sdumbbell USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 271254885Sdumbbell USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 272254885Sdumbbell USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 273254885Sdumbbell USHORT GetConditionalGoldenSetting; //Only used by Bios 274254885Sdumbbell USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 275254885Sdumbbell USHORT PatchMCSetting; //only used by BIOS 276254885Sdumbbell USHORT MC_SEQ_Control; //only used by BIOS 277254885Sdumbbell USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 278254885Sdumbbell USHORT EnableScaler; //Atomic Table, used only by Bios 279254885Sdumbbell USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 280254885Sdumbbell USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 281254885Sdumbbell USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 282254885Sdumbbell USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 283254885Sdumbbell USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 284254885Sdumbbell USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 285254885Sdumbbell USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 286254885Sdumbbell USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 287254885Sdumbbell USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 288254885Sdumbbell USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 289254885Sdumbbell USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 290254885Sdumbbell USHORT LUT_AutoFill; //Atomic Table, only used by Bios 291254885Sdumbbell USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 292254885Sdumbbell USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 293254885Sdumbbell USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 294254885Sdumbbell USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 295254885Sdumbbell USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 296254885Sdumbbell USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 297254885Sdumbbell USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 298254885Sdumbbell USHORT MemoryCleanUp; //Atomic Table, only used by Bios 299254885Sdumbbell USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 300254885Sdumbbell USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 301254885Sdumbbell USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 302254885Sdumbbell USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 303254885Sdumbbell USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 304254885Sdumbbell USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 305254885Sdumbbell USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 306254885Sdumbbell USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 307254885Sdumbbell USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 308254885Sdumbbell USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 309254885Sdumbbell USHORT MemoryTraining; //Atomic Table, used only by Bios 310254885Sdumbbell USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 311254885Sdumbbell USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 312254885Sdumbbell USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 313254885Sdumbbell USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 314254885Sdumbbell USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 315254885Sdumbbell USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 316254885Sdumbbell USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 317254885Sdumbbell USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 318254885Sdumbbell USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 319254885Sdumbbell USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 320254885Sdumbbell USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 321254885Sdumbbell USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 322254885Sdumbbell USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 323254885Sdumbbell USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 324254885Sdumbbell USHORT DPEncoderService; //Function Table,only used by Bios 325254885Sdumbbell USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 326254885Sdumbbell}ATOM_MASTER_LIST_OF_COMMAND_TABLES; 327254885Sdumbbell 328254885Sdumbbell// For backward compatible 329254885Sdumbbell#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 330254885Sdumbbell#define DPTranslatorControl DIG2EncoderControl 331254885Sdumbbell#define UNIPHYTransmitterControl DIG1TransmitterControl 332254885Sdumbbell#define LVTMATransmitterControl DIG2TransmitterControl 333254885Sdumbbell#define SetCRTC_DPM_State GetConditionalGoldenSetting 334254885Sdumbbell#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange 335254885Sdumbbell#define HPDInterruptService ReadHWAssistedI2CStatus 336254885Sdumbbell#define EnableVGA_Access GetSCLKOverMCLKRatio 337254885Sdumbbell#define EnableYUV GetDispObjectInfo 338254885Sdumbbell#define DynamicClockGating EnableDispPowerGating 339254885Sdumbbell#define SetupHWAssistedI2CStatus ComputeMemoryClockParam 340254885Sdumbbell 341254885Sdumbbell#define TMDSAEncoderControl PatchMCSetting 342254885Sdumbbell#define LVDSEncoderControl MC_SEQ_Control 343254885Sdumbbell#define LCD1OutputControl HW_Misc_Operation 344254885Sdumbbell 345254885Sdumbbell 346254885Sdumbbelltypedef struct _ATOM_MASTER_COMMAND_TABLE 347254885Sdumbbell{ 348254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 349254885Sdumbbell ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 350254885Sdumbbell}ATOM_MASTER_COMMAND_TABLE; 351254885Sdumbbell 352254885Sdumbbell/****************************************************************************/ 353254885Sdumbbell// Structures used in every command table 354254885Sdumbbell/****************************************************************************/ 355254885Sdumbbelltypedef struct _ATOM_TABLE_ATTRIBUTE 356254885Sdumbbell{ 357254885Sdumbbell#if ATOM_BIG_ENDIAN 358254885Sdumbbell USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 359254885Sdumbbell USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 360254885Sdumbbell USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 361254885Sdumbbell#else 362254885Sdumbbell USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 363254885Sdumbbell USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 364254885Sdumbbell USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 365254885Sdumbbell#endif 366254885Sdumbbell}ATOM_TABLE_ATTRIBUTE; 367254885Sdumbbell 368254885Sdumbbelltypedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 369254885Sdumbbell{ 370254885Sdumbbell ATOM_TABLE_ATTRIBUTE sbfAccess; 371254885Sdumbbell USHORT susAccess; 372254885Sdumbbell}ATOM_TABLE_ATTRIBUTE_ACCESS; 373254885Sdumbbell 374254885Sdumbbell/****************************************************************************/ 375254885Sdumbbell// Common header for all command tables. 376254885Sdumbbell// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 377254885Sdumbbell// And the pointer actually points to this header. 378254885Sdumbbell/****************************************************************************/ 379254885Sdumbbelltypedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 380254885Sdumbbell{ 381254885Sdumbbell ATOM_COMMON_TABLE_HEADER CommonHeader; 382254885Sdumbbell ATOM_TABLE_ATTRIBUTE TableAttribute; 383254885Sdumbbell}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 384254885Sdumbbell 385254885Sdumbbell/****************************************************************************/ 386254885Sdumbbell// Structures used by ComputeMemoryEnginePLLTable 387254885Sdumbbell/****************************************************************************/ 388254885Sdumbbell#define COMPUTE_MEMORY_PLL_PARAM 1 389254885Sdumbbell#define COMPUTE_ENGINE_PLL_PARAM 2 390254885Sdumbbell#define ADJUST_MC_SETTING_PARAM 3 391254885Sdumbbell 392254885Sdumbbell/****************************************************************************/ 393254885Sdumbbell// Structures used by AdjustMemoryControllerTable 394254885Sdumbbell/****************************************************************************/ 395254885Sdumbbelltypedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 396254885Sdumbbell{ 397254885Sdumbbell#if ATOM_BIG_ENDIAN 398254885Sdumbbell ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 399254885Sdumbbell ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 400254885Sdumbbell ULONG ulClockFreq:24; 401254885Sdumbbell#else 402254885Sdumbbell ULONG ulClockFreq:24; 403254885Sdumbbell ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 404254885Sdumbbell ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 405254885Sdumbbell#endif 406254885Sdumbbell}ATOM_ADJUST_MEMORY_CLOCK_FREQ; 407254885Sdumbbell#define POINTER_RETURN_FLAG 0x80 408254885Sdumbbell 409254885Sdumbbelltypedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 410254885Sdumbbell{ 411254885Sdumbbell ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 412254885Sdumbbell UCHAR ucAction; //0:reserved //1:Memory //2:Engine 413254885Sdumbbell UCHAR ucReserved; //may expand to return larger Fbdiv later 414254885Sdumbbell UCHAR ucFbDiv; //return value 415254885Sdumbbell UCHAR ucPostDiv; //return value 416254885Sdumbbell}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 417254885Sdumbbell 418254885Sdumbbelltypedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 419254885Sdumbbell{ 420254885Sdumbbell ULONG ulClock; //When return, [23:0] return real clock 421254885Sdumbbell UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 422254885Sdumbbell USHORT usFbDiv; //return Feedback value to be written to register 423254885Sdumbbell UCHAR ucPostDiv; //return post div to be written to register 424254885Sdumbbell}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 425254885Sdumbbell#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 426254885Sdumbbell 427254885Sdumbbell 428254885Sdumbbell#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 429254885Sdumbbell#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 430254885Sdumbbell#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 431254885Sdumbbell#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 432254885Sdumbbell#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 433254885Sdumbbell#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 434254885Sdumbbell#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 435254885Sdumbbell 436254885Sdumbbell#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 437254885Sdumbbell#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 438254885Sdumbbell#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 439254885Sdumbbell#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 440254885Sdumbbell#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 441254885Sdumbbell 442254885Sdumbbelltypedef struct _ATOM_COMPUTE_CLOCK_FREQ 443254885Sdumbbell{ 444254885Sdumbbell#if ATOM_BIG_ENDIAN 445254885Sdumbbell ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 446254885Sdumbbell ULONG ulClockFreq:24; // in unit of 10kHz 447254885Sdumbbell#else 448254885Sdumbbell ULONG ulClockFreq:24; // in unit of 10kHz 449254885Sdumbbell ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 450254885Sdumbbell#endif 451254885Sdumbbell}ATOM_COMPUTE_CLOCK_FREQ; 452254885Sdumbbell 453254885Sdumbbelltypedef struct _ATOM_S_MPLL_FB_DIVIDER 454254885Sdumbbell{ 455254885Sdumbbell USHORT usFbDivFrac; 456254885Sdumbbell USHORT usFbDiv; 457254885Sdumbbell}ATOM_S_MPLL_FB_DIVIDER; 458254885Sdumbbell 459254885Sdumbbelltypedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 460254885Sdumbbell{ 461254885Sdumbbell union 462254885Sdumbbell { 463254885Sdumbbell ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 464254885Sdumbbell ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 465254885Sdumbbell }; 466254885Sdumbbell UCHAR ucRefDiv; //Output Parameter 467254885Sdumbbell UCHAR ucPostDiv; //Output Parameter 468254885Sdumbbell UCHAR ucCntlFlag; //Output Parameter 469254885Sdumbbell UCHAR ucReserved; 470254885Sdumbbell}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 471254885Sdumbbell 472254885Sdumbbell// ucCntlFlag 473254885Sdumbbell#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 474254885Sdumbbell#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 475254885Sdumbbell#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 476254885Sdumbbell#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 477254885Sdumbbell 478254885Sdumbbell 479254885Sdumbbell// V4 are only used for APU which PLL outside GPU 480254885Sdumbbelltypedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 481254885Sdumbbell{ 482254885Sdumbbell#if ATOM_BIG_ENDIAN 483254885Sdumbbell ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 484254885Sdumbbell ULONG ulClock:24; //Input= target clock, output = actual clock 485254885Sdumbbell#else 486254885Sdumbbell ULONG ulClock:24; //Input= target clock, output = actual clock 487254885Sdumbbell ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 488254885Sdumbbell#endif 489254885Sdumbbell}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 490254885Sdumbbell 491254885Sdumbbelltypedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 492254885Sdumbbell{ 493254885Sdumbbell union 494254885Sdumbbell { 495254885Sdumbbell ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 496254885Sdumbbell ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 497254885Sdumbbell }; 498254885Sdumbbell UCHAR ucRefDiv; //Output Parameter 499254885Sdumbbell UCHAR ucPostDiv; //Output Parameter 500254885Sdumbbell union 501254885Sdumbbell { 502254885Sdumbbell UCHAR ucCntlFlag; //Output Flags 503254885Sdumbbell UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 504254885Sdumbbell }; 505254885Sdumbbell UCHAR ucReserved; 506254885Sdumbbell}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 507254885Sdumbbell 508254885Sdumbbell// ucInputFlag 509254885Sdumbbell#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 510254885Sdumbbell 511254885Sdumbbell// use for ComputeMemoryClockParamTable 512254885Sdumbbelltypedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 513254885Sdumbbell{ 514254885Sdumbbell union 515254885Sdumbbell { 516254885Sdumbbell ULONG ulClock; 517254885Sdumbbell ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 518254885Sdumbbell }; 519254885Sdumbbell UCHAR ucDllSpeed; //Output 520254885Sdumbbell UCHAR ucPostDiv; //Output 521254885Sdumbbell union{ 522254885Sdumbbell UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 523254885Sdumbbell UCHAR ucPllCntlFlag; //Output: 524254885Sdumbbell }; 525254885Sdumbbell UCHAR ucBWCntl; 526254885Sdumbbell}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 527254885Sdumbbell 528254885Sdumbbell// definition of ucInputFlag 529254885Sdumbbell#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 530254885Sdumbbell// definition of ucPllCntlFlag 531254885Sdumbbell#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 532254885Sdumbbell#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 533254885Sdumbbell#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 534254885Sdumbbell#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 535254885Sdumbbell 536254885Sdumbbell//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 537254885Sdumbbell#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 538254885Sdumbbell 539254885Sdumbbelltypedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 540254885Sdumbbell{ 541254885Sdumbbell ATOM_COMPUTE_CLOCK_FREQ ulClock; 542254885Sdumbbell ULONG ulReserved[2]; 543254885Sdumbbell}DYNAMICE_MEMORY_SETTINGS_PARAMETER; 544254885Sdumbbell 545254885Sdumbbelltypedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 546254885Sdumbbell{ 547254885Sdumbbell ATOM_COMPUTE_CLOCK_FREQ ulClock; 548254885Sdumbbell ULONG ulMemoryClock; 549254885Sdumbbell ULONG ulReserved; 550254885Sdumbbell}DYNAMICE_ENGINE_SETTINGS_PARAMETER; 551254885Sdumbbell 552254885Sdumbbell/****************************************************************************/ 553254885Sdumbbell// Structures used by SetEngineClockTable 554254885Sdumbbell/****************************************************************************/ 555254885Sdumbbelltypedef struct _SET_ENGINE_CLOCK_PARAMETERS 556254885Sdumbbell{ 557254885Sdumbbell ULONG ulTargetEngineClock; //In 10Khz unit 558254885Sdumbbell}SET_ENGINE_CLOCK_PARAMETERS; 559254885Sdumbbell 560254885Sdumbbelltypedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 561254885Sdumbbell{ 562254885Sdumbbell ULONG ulTargetEngineClock; //In 10Khz unit 563254885Sdumbbell COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 564254885Sdumbbell}SET_ENGINE_CLOCK_PS_ALLOCATION; 565254885Sdumbbell 566254885Sdumbbell/****************************************************************************/ 567254885Sdumbbell// Structures used by SetMemoryClockTable 568254885Sdumbbell/****************************************************************************/ 569254885Sdumbbelltypedef struct _SET_MEMORY_CLOCK_PARAMETERS 570254885Sdumbbell{ 571254885Sdumbbell ULONG ulTargetMemoryClock; //In 10Khz unit 572254885Sdumbbell}SET_MEMORY_CLOCK_PARAMETERS; 573254885Sdumbbell 574254885Sdumbbelltypedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 575254885Sdumbbell{ 576254885Sdumbbell ULONG ulTargetMemoryClock; //In 10Khz unit 577254885Sdumbbell COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 578254885Sdumbbell}SET_MEMORY_CLOCK_PS_ALLOCATION; 579254885Sdumbbell 580254885Sdumbbell/****************************************************************************/ 581254885Sdumbbell// Structures used by ASIC_Init.ctb 582254885Sdumbbell/****************************************************************************/ 583254885Sdumbbelltypedef struct _ASIC_INIT_PARAMETERS 584254885Sdumbbell{ 585254885Sdumbbell ULONG ulDefaultEngineClock; //In 10Khz unit 586254885Sdumbbell ULONG ulDefaultMemoryClock; //In 10Khz unit 587254885Sdumbbell}ASIC_INIT_PARAMETERS; 588254885Sdumbbell 589254885Sdumbbelltypedef struct _ASIC_INIT_PS_ALLOCATION 590254885Sdumbbell{ 591254885Sdumbbell ASIC_INIT_PARAMETERS sASICInitClocks; 592254885Sdumbbell SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 593254885Sdumbbell}ASIC_INIT_PS_ALLOCATION; 594254885Sdumbbell 595254885Sdumbbell/****************************************************************************/ 596254885Sdumbbell// Structure used by DynamicClockGatingTable.ctb 597254885Sdumbbell/****************************************************************************/ 598254885Sdumbbelltypedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 599254885Sdumbbell{ 600254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 601254885Sdumbbell UCHAR ucPadding[3]; 602254885Sdumbbell}DYNAMIC_CLOCK_GATING_PARAMETERS; 603254885Sdumbbell#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 604254885Sdumbbell 605254885Sdumbbell/****************************************************************************/ 606254885Sdumbbell// Structure used by EnableDispPowerGatingTable.ctb 607254885Sdumbbell/****************************************************************************/ 608254885Sdumbbelltypedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 609254885Sdumbbell{ 610254885Sdumbbell UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 611254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 612254885Sdumbbell UCHAR ucPadding[2]; 613254885Sdumbbell}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 614254885Sdumbbell 615254885Sdumbbell/****************************************************************************/ 616254885Sdumbbell// Structure used by EnableASIC_StaticPwrMgtTable.ctb 617254885Sdumbbell/****************************************************************************/ 618254885Sdumbbelltypedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 619254885Sdumbbell{ 620254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 621254885Sdumbbell UCHAR ucPadding[3]; 622254885Sdumbbell}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 623254885Sdumbbell#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 624254885Sdumbbell 625254885Sdumbbell/****************************************************************************/ 626254885Sdumbbell// Structures used by DAC_LoadDetectionTable.ctb 627254885Sdumbbell/****************************************************************************/ 628254885Sdumbbelltypedef struct _DAC_LOAD_DETECTION_PARAMETERS 629254885Sdumbbell{ 630254885Sdumbbell USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 631254885Sdumbbell UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 632254885Sdumbbell UCHAR ucMisc; //Valid only when table revision =1.3 and above 633254885Sdumbbell}DAC_LOAD_DETECTION_PARAMETERS; 634254885Sdumbbell 635254885Sdumbbell// DAC_LOAD_DETECTION_PARAMETERS.ucMisc 636254885Sdumbbell#define DAC_LOAD_MISC_YPrPb 0x01 637254885Sdumbbell 638254885Sdumbbelltypedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 639254885Sdumbbell{ 640254885Sdumbbell DAC_LOAD_DETECTION_PARAMETERS sDacload; 641254885Sdumbbell ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 642254885Sdumbbell}DAC_LOAD_DETECTION_PS_ALLOCATION; 643254885Sdumbbell 644254885Sdumbbell/****************************************************************************/ 645254885Sdumbbell// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 646254885Sdumbbell/****************************************************************************/ 647254885Sdumbbelltypedef struct _DAC_ENCODER_CONTROL_PARAMETERS 648254885Sdumbbell{ 649254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 650254885Sdumbbell UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 651254885Sdumbbell UCHAR ucAction; // 0: turn off encoder 652254885Sdumbbell // 1: setup and turn on encoder 653254885Sdumbbell // 7: ATOM_ENCODER_INIT Initialize DAC 654254885Sdumbbell}DAC_ENCODER_CONTROL_PARAMETERS; 655254885Sdumbbell 656254885Sdumbbell#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 657254885Sdumbbell 658254885Sdumbbell/****************************************************************************/ 659254885Sdumbbell// Structures used by DIG1EncoderControlTable 660254885Sdumbbell// DIG2EncoderControlTable 661254885Sdumbbell// ExternalEncoderControlTable 662254885Sdumbbell/****************************************************************************/ 663254885Sdumbbelltypedef struct _DIG_ENCODER_CONTROL_PARAMETERS 664254885Sdumbbell{ 665254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 666254885Sdumbbell UCHAR ucConfig; 667254885Sdumbbell // [2] Link Select: 668254885Sdumbbell // =0: PHY linkA if bfLane<3 669254885Sdumbbell // =1: PHY linkB if bfLanes<3 670254885Sdumbbell // =0: PHY linkA+B if bfLanes=3 671254885Sdumbbell // [3] Transmitter Sel 672254885Sdumbbell // =0: UNIPHY or PCIEPHY 673254885Sdumbbell // =1: LVTMA 674254885Sdumbbell UCHAR ucAction; // =0: turn off encoder 675254885Sdumbbell // =1: turn on encoder 676254885Sdumbbell UCHAR ucEncoderMode; 677254885Sdumbbell // =0: DP encoder 678254885Sdumbbell // =1: LVDS encoder 679254885Sdumbbell // =2: DVI encoder 680254885Sdumbbell // =3: HDMI encoder 681254885Sdumbbell // =4: SDVO encoder 682254885Sdumbbell UCHAR ucLaneNum; // how many lanes to enable 683254885Sdumbbell UCHAR ucReserved[2]; 684254885Sdumbbell}DIG_ENCODER_CONTROL_PARAMETERS; 685254885Sdumbbell#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 686254885Sdumbbell#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 687254885Sdumbbell 688254885Sdumbbell//ucConfig 689254885Sdumbbell#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 690254885Sdumbbell#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 691254885Sdumbbell#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 692254885Sdumbbell#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 693254885Sdumbbell#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 694254885Sdumbbell#define ATOM_ENCODER_CONFIG_LINKA 0x00 695254885Sdumbbell#define ATOM_ENCODER_CONFIG_LINKB 0x04 696254885Sdumbbell#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 697254885Sdumbbell#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 698254885Sdumbbell#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 699254885Sdumbbell#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 700254885Sdumbbell#define ATOM_ENCODER_CONFIG_LVTMA 0x08 701254885Sdumbbell#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 702254885Sdumbbell#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 703254885Sdumbbell#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 704254885Sdumbbell// ucAction 705254885Sdumbbell// ATOM_ENABLE: Enable Encoder 706254885Sdumbbell// ATOM_DISABLE: Disable Encoder 707254885Sdumbbell 708254885Sdumbbell//ucEncoderMode 709254885Sdumbbell#define ATOM_ENCODER_MODE_DP 0 710254885Sdumbbell#define ATOM_ENCODER_MODE_LVDS 1 711254885Sdumbbell#define ATOM_ENCODER_MODE_DVI 2 712254885Sdumbbell#define ATOM_ENCODER_MODE_HDMI 3 713254885Sdumbbell#define ATOM_ENCODER_MODE_SDVO 4 714254885Sdumbbell#define ATOM_ENCODER_MODE_DP_AUDIO 5 715254885Sdumbbell#define ATOM_ENCODER_MODE_TV 13 716254885Sdumbbell#define ATOM_ENCODER_MODE_CV 14 717254885Sdumbbell#define ATOM_ENCODER_MODE_CRT 15 718254885Sdumbbell#define ATOM_ENCODER_MODE_DVO 16 719254885Sdumbbell#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 720254885Sdumbbell#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 721254885Sdumbbell 722254885Sdumbbelltypedef struct _ATOM_DIG_ENCODER_CONFIG_V2 723254885Sdumbbell{ 724254885Sdumbbell#if ATOM_BIG_ENDIAN 725254885Sdumbbell UCHAR ucReserved1:2; 726254885Sdumbbell UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 727254885Sdumbbell UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 728254885Sdumbbell UCHAR ucReserved:1; 729254885Sdumbbell UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 730254885Sdumbbell#else 731254885Sdumbbell UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 732254885Sdumbbell UCHAR ucReserved:1; 733254885Sdumbbell UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 734254885Sdumbbell UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 735254885Sdumbbell UCHAR ucReserved1:2; 736254885Sdumbbell#endif 737254885Sdumbbell}ATOM_DIG_ENCODER_CONFIG_V2; 738254885Sdumbbell 739254885Sdumbbell 740254885Sdumbbelltypedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 741254885Sdumbbell{ 742254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 743254885Sdumbbell ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 744254885Sdumbbell UCHAR ucAction; 745254885Sdumbbell UCHAR ucEncoderMode; 746254885Sdumbbell // =0: DP encoder 747254885Sdumbbell // =1: LVDS encoder 748254885Sdumbbell // =2: DVI encoder 749254885Sdumbbell // =3: HDMI encoder 750254885Sdumbbell // =4: SDVO encoder 751254885Sdumbbell UCHAR ucLaneNum; // how many lanes to enable 752254885Sdumbbell UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 753254885Sdumbbell UCHAR ucReserved; 754254885Sdumbbell}DIG_ENCODER_CONTROL_PARAMETERS_V2; 755254885Sdumbbell 756254885Sdumbbell//ucConfig 757254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 758254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 759254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 760254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 761254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 762254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 763254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 764254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 765254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 766254885Sdumbbell#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 767254885Sdumbbell 768254885Sdumbbell// ucAction: 769254885Sdumbbell// ATOM_DISABLE 770254885Sdumbbell// ATOM_ENABLE 771254885Sdumbbell#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 772254885Sdumbbell#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 773254885Sdumbbell#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 774254885Sdumbbell#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 775254885Sdumbbell#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 776254885Sdumbbell#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 777254885Sdumbbell#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 778254885Sdumbbell#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 779254885Sdumbbell#define ATOM_ENCODER_CMD_SETUP 0x0f 780254885Sdumbbell#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 781254885Sdumbbell 782254885Sdumbbell// ucStatus 783254885Sdumbbell#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 784254885Sdumbbell#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 785254885Sdumbbell 786254885Sdumbbell//ucTableFormatRevision=1 787254885Sdumbbell//ucTableContentRevision=3 788254885Sdumbbell// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 789254885Sdumbbelltypedef struct _ATOM_DIG_ENCODER_CONFIG_V3 790254885Sdumbbell{ 791254885Sdumbbell#if ATOM_BIG_ENDIAN 792254885Sdumbbell UCHAR ucReserved1:1; 793254885Sdumbbell UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 794254885Sdumbbell UCHAR ucReserved:3; 795254885Sdumbbell UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 796254885Sdumbbell#else 797254885Sdumbbell UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 798254885Sdumbbell UCHAR ucReserved:3; 799254885Sdumbbell UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 800254885Sdumbbell UCHAR ucReserved1:1; 801254885Sdumbbell#endif 802254885Sdumbbell}ATOM_DIG_ENCODER_CONFIG_V3; 803254885Sdumbbell 804254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 805254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 806254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 807254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 808254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 809254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 810254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 811254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 812254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 813254885Sdumbbell#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 814254885Sdumbbell 815254885Sdumbbelltypedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 816254885Sdumbbell{ 817254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 818254885Sdumbbell ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 819254885Sdumbbell UCHAR ucAction; 820254885Sdumbbell union { 821254885Sdumbbell UCHAR ucEncoderMode; 822254885Sdumbbell // =0: DP encoder 823254885Sdumbbell // =1: LVDS encoder 824254885Sdumbbell // =2: DVI encoder 825254885Sdumbbell // =3: HDMI encoder 826254885Sdumbbell // =4: SDVO encoder 827254885Sdumbbell // =5: DP audio 828254885Sdumbbell UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 829254885Sdumbbell // =0: external DP 830254885Sdumbbell // =1: internal DP2 831254885Sdumbbell // =0x11: internal DP1 for NutMeg/Travis DP translator 832254885Sdumbbell }; 833254885Sdumbbell UCHAR ucLaneNum; // how many lanes to enable 834254885Sdumbbell UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 835254885Sdumbbell UCHAR ucReserved; 836254885Sdumbbell}DIG_ENCODER_CONTROL_PARAMETERS_V3; 837254885Sdumbbell 838254885Sdumbbell//ucTableFormatRevision=1 839254885Sdumbbell//ucTableContentRevision=4 840254885Sdumbbell// start from NI 841254885Sdumbbell// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 842254885Sdumbbelltypedef struct _ATOM_DIG_ENCODER_CONFIG_V4 843254885Sdumbbell{ 844254885Sdumbbell#if ATOM_BIG_ENDIAN 845254885Sdumbbell UCHAR ucReserved1:1; 846254885Sdumbbell UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 847254885Sdumbbell UCHAR ucReserved:2; 848254885Sdumbbell UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 849254885Sdumbbell#else 850254885Sdumbbell UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 851254885Sdumbbell UCHAR ucReserved:2; 852254885Sdumbbell UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 853254885Sdumbbell UCHAR ucReserved1:1; 854254885Sdumbbell#endif 855254885Sdumbbell}ATOM_DIG_ENCODER_CONFIG_V4; 856254885Sdumbbell 857254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 858254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 859254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 860254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 861254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 862254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 863254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 864254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 865254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 866254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 867254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 868254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 869254885Sdumbbell#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 870254885Sdumbbell 871254885Sdumbbelltypedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 872254885Sdumbbell{ 873254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 874254885Sdumbbell union{ 875254885Sdumbbell ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 876254885Sdumbbell UCHAR ucConfig; 877254885Sdumbbell }; 878254885Sdumbbell UCHAR ucAction; 879254885Sdumbbell union { 880254885Sdumbbell UCHAR ucEncoderMode; 881254885Sdumbbell // =0: DP encoder 882254885Sdumbbell // =1: LVDS encoder 883254885Sdumbbell // =2: DVI encoder 884254885Sdumbbell // =3: HDMI encoder 885254885Sdumbbell // =4: SDVO encoder 886254885Sdumbbell // =5: DP audio 887254885Sdumbbell UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 888254885Sdumbbell // =0: external DP 889254885Sdumbbell // =1: internal DP2 890254885Sdumbbell // =0x11: internal DP1 for NutMeg/Travis DP translator 891254885Sdumbbell }; 892254885Sdumbbell UCHAR ucLaneNum; // how many lanes to enable 893254885Sdumbbell UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 894254885Sdumbbell UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 895254885Sdumbbell}DIG_ENCODER_CONTROL_PARAMETERS_V4; 896254885Sdumbbell 897254885Sdumbbell// define ucBitPerColor: 898254885Sdumbbell#define PANEL_BPC_UNDEFINE 0x00 899254885Sdumbbell#define PANEL_6BIT_PER_COLOR 0x01 900254885Sdumbbell#define PANEL_8BIT_PER_COLOR 0x02 901254885Sdumbbell#define PANEL_10BIT_PER_COLOR 0x03 902254885Sdumbbell#define PANEL_12BIT_PER_COLOR 0x04 903254885Sdumbbell#define PANEL_16BIT_PER_COLOR 0x05 904254885Sdumbbell 905254885Sdumbbell//define ucPanelMode 906254885Sdumbbell#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 907254885Sdumbbell#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 908254885Sdumbbell#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 909254885Sdumbbell 910254885Sdumbbell/****************************************************************************/ 911254885Sdumbbell// Structures used by UNIPHYTransmitterControlTable 912254885Sdumbbell// LVTMATransmitterControlTable 913254885Sdumbbell// DVOOutputControlTable 914254885Sdumbbell/****************************************************************************/ 915254885Sdumbbelltypedef struct _ATOM_DP_VS_MODE 916254885Sdumbbell{ 917254885Sdumbbell UCHAR ucLaneSel; 918254885Sdumbbell UCHAR ucLaneSet; 919254885Sdumbbell}ATOM_DP_VS_MODE; 920254885Sdumbbell 921254885Sdumbbelltypedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 922254885Sdumbbell{ 923254885Sdumbbell union 924254885Sdumbbell { 925254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 926254885Sdumbbell USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 927254885Sdumbbell ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 928254885Sdumbbell }; 929254885Sdumbbell UCHAR ucConfig; 930254885Sdumbbell // [0]=0: 4 lane Link, 931254885Sdumbbell // =1: 8 lane Link ( Dual Links TMDS ) 932254885Sdumbbell // [1]=0: InCoherent mode 933254885Sdumbbell // =1: Coherent Mode 934254885Sdumbbell // [2] Link Select: 935254885Sdumbbell // =0: PHY linkA if bfLane<3 936254885Sdumbbell // =1: PHY linkB if bfLanes<3 937254885Sdumbbell // =0: PHY linkA+B if bfLanes=3 938254885Sdumbbell // [5:4]PCIE lane Sel 939254885Sdumbbell // =0: lane 0~3 or 0~7 940254885Sdumbbell // =1: lane 4~7 941254885Sdumbbell // =2: lane 8~11 or 8~15 942254885Sdumbbell // =3: lane 12~15 943254885Sdumbbell UCHAR ucAction; // =0: turn off encoder 944254885Sdumbbell // =1: turn on encoder 945254885Sdumbbell UCHAR ucReserved[4]; 946254885Sdumbbell}DIG_TRANSMITTER_CONTROL_PARAMETERS; 947254885Sdumbbell 948254885Sdumbbell#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 949254885Sdumbbell 950254885Sdumbbell//ucInitInfo 951254885Sdumbbell#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 952254885Sdumbbell 953254885Sdumbbell//ucConfig 954254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 955254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 956254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 957254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 958254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 959254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 960254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 961254885Sdumbbell 962254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 963254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 964254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 965254885Sdumbbell 966254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 967254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 968254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 969254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 970254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 971254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 972254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 973254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 974254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 975254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 976254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 977254885Sdumbbell 978254885Sdumbbell//ucAction 979254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_DISABLE 0 980254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_ENABLE 1 981254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 982254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 983254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 984254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 985254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 986254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_INIT 7 987254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 988254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 989254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_SETUP 10 990254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 991254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 992254885Sdumbbell#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 993254885Sdumbbell 994254885Sdumbbell// Following are used for DigTransmitterControlTable ver1.2 995254885Sdumbbelltypedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 996254885Sdumbbell{ 997254885Sdumbbell#if ATOM_BIG_ENDIAN 998254885Sdumbbell UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 999254885Sdumbbell // =1 Dig Transmitter 2 ( Uniphy CD ) 1000254885Sdumbbell // =2 Dig Transmitter 3 ( Uniphy EF ) 1001254885Sdumbbell UCHAR ucReserved:1; 1002254885Sdumbbell UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1003254885Sdumbbell UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1004254885Sdumbbell UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1005254885Sdumbbell // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1006254885Sdumbbell 1007254885Sdumbbell UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1008254885Sdumbbell UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1009254885Sdumbbell#else 1010254885Sdumbbell UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1011254885Sdumbbell UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1012254885Sdumbbell UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1013254885Sdumbbell // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1014254885Sdumbbell UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1015254885Sdumbbell UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1016254885Sdumbbell UCHAR ucReserved:1; 1017254885Sdumbbell UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1018254885Sdumbbell // =1 Dig Transmitter 2 ( Uniphy CD ) 1019254885Sdumbbell // =2 Dig Transmitter 3 ( Uniphy EF ) 1020254885Sdumbbell#endif 1021254885Sdumbbell}ATOM_DIG_TRANSMITTER_CONFIG_V2; 1022254885Sdumbbell 1023254885Sdumbbell//ucConfig 1024254885Sdumbbell//Bit0 1025254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1026254885Sdumbbell 1027254885Sdumbbell//Bit1 1028254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1029254885Sdumbbell 1030254885Sdumbbell//Bit2 1031254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1032254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1033254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1034254885Sdumbbell 1035254885Sdumbbell// Bit3 1036254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1037254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1038254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1039254885Sdumbbell 1040254885Sdumbbell// Bit4 1041254885Sdumbbell#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1042254885Sdumbbell 1043254885Sdumbbell// Bit7:6 1044254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1045254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1046254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1047254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1048254885Sdumbbell 1049254885Sdumbbelltypedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1050254885Sdumbbell{ 1051254885Sdumbbell union 1052254885Sdumbbell { 1053254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 1054254885Sdumbbell USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1055254885Sdumbbell ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1056254885Sdumbbell }; 1057254885Sdumbbell ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1058254885Sdumbbell UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1059254885Sdumbbell UCHAR ucReserved[4]; 1060254885Sdumbbell}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1061254885Sdumbbell 1062254885Sdumbbelltypedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1063254885Sdumbbell{ 1064254885Sdumbbell#if ATOM_BIG_ENDIAN 1065254885Sdumbbell UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1066254885Sdumbbell // =1 Dig Transmitter 2 ( Uniphy CD ) 1067254885Sdumbbell // =2 Dig Transmitter 3 ( Uniphy EF ) 1068254885Sdumbbell UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1069254885Sdumbbell UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1070254885Sdumbbell UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1071254885Sdumbbell // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1072254885Sdumbbell UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1073254885Sdumbbell UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1074254885Sdumbbell#else 1075254885Sdumbbell UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1076254885Sdumbbell UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1077254885Sdumbbell UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1078254885Sdumbbell // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1079254885Sdumbbell UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1080254885Sdumbbell UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1081254885Sdumbbell UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1082254885Sdumbbell // =1 Dig Transmitter 2 ( Uniphy CD ) 1083254885Sdumbbell // =2 Dig Transmitter 3 ( Uniphy EF ) 1084254885Sdumbbell#endif 1085254885Sdumbbell}ATOM_DIG_TRANSMITTER_CONFIG_V3; 1086254885Sdumbbell 1087254885Sdumbbell 1088254885Sdumbbelltypedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1089254885Sdumbbell{ 1090254885Sdumbbell union 1091254885Sdumbbell { 1092254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 1093254885Sdumbbell USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1094254885Sdumbbell ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1095254885Sdumbbell }; 1096254885Sdumbbell ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1097254885Sdumbbell UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1098254885Sdumbbell UCHAR ucLaneNum; 1099254885Sdumbbell UCHAR ucReserved[3]; 1100254885Sdumbbell}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1101254885Sdumbbell 1102254885Sdumbbell//ucConfig 1103254885Sdumbbell//Bit0 1104254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1105254885Sdumbbell 1106254885Sdumbbell//Bit1 1107254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1108254885Sdumbbell 1109254885Sdumbbell//Bit2 1110254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1111254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1112254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1113254885Sdumbbell 1114254885Sdumbbell// Bit3 1115254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1116254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1117254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1118254885Sdumbbell 1119254885Sdumbbell// Bit5:4 1120254885Sdumbbell#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1121254885Sdumbbell#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1122254885Sdumbbell#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1123254885Sdumbbell#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1124254885Sdumbbell 1125254885Sdumbbell// Bit7:6 1126254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1127254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1128254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1129254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1130254885Sdumbbell 1131254885Sdumbbell 1132254885Sdumbbell/****************************************************************************/ 1133254885Sdumbbell// Structures used by UNIPHYTransmitterControlTable V1.4 1134254885Sdumbbell// ASIC Families: NI 1135254885Sdumbbell// ucTableFormatRevision=1 1136254885Sdumbbell// ucTableContentRevision=4 1137254885Sdumbbell/****************************************************************************/ 1138254885Sdumbbelltypedef struct _ATOM_DP_VS_MODE_V4 1139254885Sdumbbell{ 1140254885Sdumbbell UCHAR ucLaneSel; 1141254885Sdumbbell union 1142254885Sdumbbell { 1143254885Sdumbbell UCHAR ucLaneSet; 1144254885Sdumbbell struct { 1145254885Sdumbbell#if ATOM_BIG_ENDIAN 1146254885Sdumbbell UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1147254885Sdumbbell UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1148254885Sdumbbell UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1149254885Sdumbbell#else 1150254885Sdumbbell UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1151254885Sdumbbell UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1152254885Sdumbbell UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1153254885Sdumbbell#endif 1154254885Sdumbbell }; 1155254885Sdumbbell }; 1156254885Sdumbbell}ATOM_DP_VS_MODE_V4; 1157254885Sdumbbell 1158254885Sdumbbelltypedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1159254885Sdumbbell{ 1160254885Sdumbbell#if ATOM_BIG_ENDIAN 1161254885Sdumbbell UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1162254885Sdumbbell // =1 Dig Transmitter 2 ( Uniphy CD ) 1163254885Sdumbbell // =2 Dig Transmitter 3 ( Uniphy EF ) 1164254885Sdumbbell UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1165254885Sdumbbell UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1166254885Sdumbbell UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1167254885Sdumbbell // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1168254885Sdumbbell UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1169254885Sdumbbell UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1170254885Sdumbbell#else 1171254885Sdumbbell UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1172254885Sdumbbell UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1173254885Sdumbbell UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1174254885Sdumbbell // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1175254885Sdumbbell UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1176254885Sdumbbell UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1177254885Sdumbbell UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1178254885Sdumbbell // =1 Dig Transmitter 2 ( Uniphy CD ) 1179254885Sdumbbell // =2 Dig Transmitter 3 ( Uniphy EF ) 1180254885Sdumbbell#endif 1181254885Sdumbbell}ATOM_DIG_TRANSMITTER_CONFIG_V4; 1182254885Sdumbbell 1183254885Sdumbbelltypedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1184254885Sdumbbell{ 1185254885Sdumbbell union 1186254885Sdumbbell { 1187254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 1188254885Sdumbbell USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1189254885Sdumbbell ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1190254885Sdumbbell }; 1191254885Sdumbbell union 1192254885Sdumbbell { 1193254885Sdumbbell ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1194254885Sdumbbell UCHAR ucConfig; 1195254885Sdumbbell }; 1196254885Sdumbbell UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1197254885Sdumbbell UCHAR ucLaneNum; 1198254885Sdumbbell UCHAR ucReserved[3]; 1199254885Sdumbbell}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1200254885Sdumbbell 1201254885Sdumbbell//ucConfig 1202254885Sdumbbell//Bit0 1203254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1204254885Sdumbbell//Bit1 1205254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1206254885Sdumbbell//Bit2 1207254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1208254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1209254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1210254885Sdumbbell// Bit3 1211254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1212254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1213254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1214254885Sdumbbell// Bit5:4 1215254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1216254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1217254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1218254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1219254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1220254885Sdumbbell// Bit7:6 1221254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1222254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1223254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1224254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1225254885Sdumbbell 1226254885Sdumbbell 1227254885Sdumbbelltypedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1228254885Sdumbbell{ 1229254885Sdumbbell#if ATOM_BIG_ENDIAN 1230254885Sdumbbell UCHAR ucReservd1:1; 1231254885Sdumbbell UCHAR ucHPDSel:3; 1232254885Sdumbbell UCHAR ucPhyClkSrcId:2; 1233254885Sdumbbell UCHAR ucCoherentMode:1; 1234254885Sdumbbell UCHAR ucReserved:1; 1235254885Sdumbbell#else 1236254885Sdumbbell UCHAR ucReserved:1; 1237254885Sdumbbell UCHAR ucCoherentMode:1; 1238254885Sdumbbell UCHAR ucPhyClkSrcId:2; 1239254885Sdumbbell UCHAR ucHPDSel:3; 1240254885Sdumbbell UCHAR ucReservd1:1; 1241254885Sdumbbell#endif 1242254885Sdumbbell}ATOM_DIG_TRANSMITTER_CONFIG_V5; 1243254885Sdumbbell 1244254885Sdumbbelltypedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1245254885Sdumbbell{ 1246254885Sdumbbell USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1247254885Sdumbbell UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1248254885Sdumbbell UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1249254885Sdumbbell UCHAR ucLaneNum; // indicate lane number 1-8 1250254885Sdumbbell UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1251254885Sdumbbell UCHAR ucDigMode; // indicate DIG mode 1252254885Sdumbbell union{ 1253254885Sdumbbell ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1254254885Sdumbbell UCHAR ucConfig; 1255254885Sdumbbell }; 1256254885Sdumbbell UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1257254885Sdumbbell UCHAR ucDPLaneSet; 1258254885Sdumbbell UCHAR ucReserved; 1259254885Sdumbbell UCHAR ucReserved1; 1260254885Sdumbbell}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1261254885Sdumbbell 1262254885Sdumbbell//ucPhyId 1263254885Sdumbbell#define ATOM_PHY_ID_UNIPHYA 0 1264254885Sdumbbell#define ATOM_PHY_ID_UNIPHYB 1 1265254885Sdumbbell#define ATOM_PHY_ID_UNIPHYC 2 1266254885Sdumbbell#define ATOM_PHY_ID_UNIPHYD 3 1267254885Sdumbbell#define ATOM_PHY_ID_UNIPHYE 4 1268254885Sdumbbell#define ATOM_PHY_ID_UNIPHYF 5 1269254885Sdumbbell#define ATOM_PHY_ID_UNIPHYG 6 1270254885Sdumbbell 1271254885Sdumbbell// ucDigEncoderSel 1272254885Sdumbbell#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1273254885Sdumbbell#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1274254885Sdumbbell#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1275254885Sdumbbell#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1276254885Sdumbbell#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1277254885Sdumbbell#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1278254885Sdumbbell#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1279254885Sdumbbell 1280254885Sdumbbell// ucDigMode 1281254885Sdumbbell#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1282254885Sdumbbell#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1283254885Sdumbbell#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1284254885Sdumbbell#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1285254885Sdumbbell#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1286254885Sdumbbell#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1287254885Sdumbbell 1288254885Sdumbbell// ucDPLaneSet 1289254885Sdumbbell#define DP_LANE_SET__0DB_0_4V 0x00 1290254885Sdumbbell#define DP_LANE_SET__0DB_0_6V 0x01 1291254885Sdumbbell#define DP_LANE_SET__0DB_0_8V 0x02 1292254885Sdumbbell#define DP_LANE_SET__0DB_1_2V 0x03 1293254885Sdumbbell#define DP_LANE_SET__3_5DB_0_4V 0x08 1294254885Sdumbbell#define DP_LANE_SET__3_5DB_0_6V 0x09 1295254885Sdumbbell#define DP_LANE_SET__3_5DB_0_8V 0x0a 1296254885Sdumbbell#define DP_LANE_SET__6DB_0_4V 0x10 1297254885Sdumbbell#define DP_LANE_SET__6DB_0_6V 0x11 1298254885Sdumbbell#define DP_LANE_SET__9_5DB_0_4V 0x18 1299254885Sdumbbell 1300254885Sdumbbell// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1301254885Sdumbbell// Bit1 1302254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1303254885Sdumbbell 1304254885Sdumbbell// Bit3:2 1305254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1306254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1307254885Sdumbbell 1308254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1309254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1310254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1311254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1312254885Sdumbbell// Bit6:4 1313254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1314254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1315254885Sdumbbell 1316254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1317254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1318254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1319254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1320254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1321254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1322254885Sdumbbell#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1323254885Sdumbbell 1324254885Sdumbbell#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1325254885Sdumbbell 1326254885Sdumbbell 1327254885Sdumbbell/****************************************************************************/ 1328254885Sdumbbell// Structures used by ExternalEncoderControlTable V1.3 1329254885Sdumbbell// ASIC Families: Evergreen, Llano, NI 1330254885Sdumbbell// ucTableFormatRevision=1 1331254885Sdumbbell// ucTableContentRevision=3 1332254885Sdumbbell/****************************************************************************/ 1333254885Sdumbbell 1334254885Sdumbbelltypedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1335254885Sdumbbell{ 1336254885Sdumbbell union{ 1337254885Sdumbbell USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1338254885Sdumbbell USHORT usConnectorId; // connector id, valid when ucAction = INIT 1339254885Sdumbbell }; 1340254885Sdumbbell UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1341254885Sdumbbell UCHAR ucAction; // 1342254885Sdumbbell UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1343254885Sdumbbell UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1344254885Sdumbbell UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1345254885Sdumbbell UCHAR ucReserved; 1346254885Sdumbbell}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1347254885Sdumbbell 1348254885Sdumbbell// ucAction 1349254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1350254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1351254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1352254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1353254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1354254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1355254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1356254885Sdumbbell#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1357254885Sdumbbell 1358254885Sdumbbell// ucConfig 1359254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1360254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1361254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1362254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1363254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 1364254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1365254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1366254885Sdumbbell#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1367254885Sdumbbell 1368254885Sdumbbelltypedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1369254885Sdumbbell{ 1370254885Sdumbbell EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1371254885Sdumbbell ULONG ulReserved[2]; 1372254885Sdumbbell}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1373254885Sdumbbell 1374254885Sdumbbell 1375254885Sdumbbell/****************************************************************************/ 1376254885Sdumbbell// Structures used by DAC1OuputControlTable 1377254885Sdumbbell// DAC2OuputControlTable 1378254885Sdumbbell// LVTMAOutputControlTable (Before DEC30) 1379254885Sdumbbell// TMDSAOutputControlTable (Before DEC30) 1380254885Sdumbbell/****************************************************************************/ 1381254885Sdumbbelltypedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1382254885Sdumbbell{ 1383254885Sdumbbell UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1384254885Sdumbbell // When the display is LCD, in addition to above: 1385254885Sdumbbell // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1386254885Sdumbbell // ATOM_LCD_SELFTEST_STOP 1387254885Sdumbbell 1388254885Sdumbbell UCHAR aucPadding[3]; // padding to DWORD aligned 1389254885Sdumbbell}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1390254885Sdumbbell 1391254885Sdumbbell#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1392254885Sdumbbell 1393254885Sdumbbell 1394254885Sdumbbell#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1395254885Sdumbbell#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1396254885Sdumbbell 1397254885Sdumbbell#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1398254885Sdumbbell#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1399254885Sdumbbell 1400254885Sdumbbell#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1401254885Sdumbbell#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1402254885Sdumbbell 1403254885Sdumbbell#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1404254885Sdumbbell#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1405254885Sdumbbell 1406254885Sdumbbell#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1407254885Sdumbbell#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1408254885Sdumbbell 1409254885Sdumbbell#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1410254885Sdumbbell#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1411254885Sdumbbell 1412254885Sdumbbell#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1413254885Sdumbbell#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1414254885Sdumbbell 1415254885Sdumbbell#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1416254885Sdumbbell#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1417254885Sdumbbell#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1418254885Sdumbbell 1419254885Sdumbbell/****************************************************************************/ 1420254885Sdumbbell// Structures used by BlankCRTCTable 1421254885Sdumbbell/****************************************************************************/ 1422254885Sdumbbelltypedef struct _BLANK_CRTC_PARAMETERS 1423254885Sdumbbell{ 1424254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1425254885Sdumbbell UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1426254885Sdumbbell USHORT usBlackColorRCr; 1427254885Sdumbbell USHORT usBlackColorGY; 1428254885Sdumbbell USHORT usBlackColorBCb; 1429254885Sdumbbell}BLANK_CRTC_PARAMETERS; 1430254885Sdumbbell#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1431254885Sdumbbell 1432254885Sdumbbell/****************************************************************************/ 1433254885Sdumbbell// Structures used by EnableCRTCTable 1434254885Sdumbbell// EnableCRTCMemReqTable 1435254885Sdumbbell// UpdateCRTC_DoubleBufferRegistersTable 1436254885Sdumbbell/****************************************************************************/ 1437254885Sdumbbelltypedef struct _ENABLE_CRTC_PARAMETERS 1438254885Sdumbbell{ 1439254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1440254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1441254885Sdumbbell UCHAR ucPadding[2]; 1442254885Sdumbbell}ENABLE_CRTC_PARAMETERS; 1443254885Sdumbbell#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1444254885Sdumbbell 1445254885Sdumbbell/****************************************************************************/ 1446254885Sdumbbell// Structures used by SetCRTC_OverScanTable 1447254885Sdumbbell/****************************************************************************/ 1448254885Sdumbbelltypedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1449254885Sdumbbell{ 1450254885Sdumbbell USHORT usOverscanRight; // right 1451254885Sdumbbell USHORT usOverscanLeft; // left 1452254885Sdumbbell USHORT usOverscanBottom; // bottom 1453254885Sdumbbell USHORT usOverscanTop; // top 1454254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1455254885Sdumbbell UCHAR ucPadding[3]; 1456254885Sdumbbell}SET_CRTC_OVERSCAN_PARAMETERS; 1457254885Sdumbbell#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1458254885Sdumbbell 1459254885Sdumbbell/****************************************************************************/ 1460254885Sdumbbell// Structures used by SetCRTC_ReplicationTable 1461254885Sdumbbell/****************************************************************************/ 1462254885Sdumbbelltypedef struct _SET_CRTC_REPLICATION_PARAMETERS 1463254885Sdumbbell{ 1464254885Sdumbbell UCHAR ucH_Replication; // horizontal replication 1465254885Sdumbbell UCHAR ucV_Replication; // vertical replication 1466254885Sdumbbell UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1467254885Sdumbbell UCHAR ucPadding; 1468254885Sdumbbell}SET_CRTC_REPLICATION_PARAMETERS; 1469254885Sdumbbell#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1470254885Sdumbbell 1471254885Sdumbbell/****************************************************************************/ 1472254885Sdumbbell// Structures used by SelectCRTC_SourceTable 1473254885Sdumbbell/****************************************************************************/ 1474254885Sdumbbelltypedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1475254885Sdumbbell{ 1476254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1477254885Sdumbbell UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1478254885Sdumbbell UCHAR ucPadding[2]; 1479254885Sdumbbell}SELECT_CRTC_SOURCE_PARAMETERS; 1480254885Sdumbbell#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1481254885Sdumbbell 1482254885Sdumbbelltypedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1483254885Sdumbbell{ 1484254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1485254885Sdumbbell UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1486254885Sdumbbell UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1487254885Sdumbbell UCHAR ucPadding; 1488254885Sdumbbell}SELECT_CRTC_SOURCE_PARAMETERS_V2; 1489254885Sdumbbell 1490254885Sdumbbell//ucEncoderID 1491254885Sdumbbell//#define ASIC_INT_DAC1_ENCODER_ID 0x00 1492254885Sdumbbell//#define ASIC_INT_TV_ENCODER_ID 0x02 1493254885Sdumbbell//#define ASIC_INT_DIG1_ENCODER_ID 0x03 1494254885Sdumbbell//#define ASIC_INT_DAC2_ENCODER_ID 0x04 1495254885Sdumbbell//#define ASIC_EXT_TV_ENCODER_ID 0x06 1496254885Sdumbbell//#define ASIC_INT_DVO_ENCODER_ID 0x07 1497254885Sdumbbell//#define ASIC_INT_DIG2_ENCODER_ID 0x09 1498254885Sdumbbell//#define ASIC_EXT_DIG_ENCODER_ID 0x05 1499254885Sdumbbell 1500254885Sdumbbell//ucEncodeMode 1501254885Sdumbbell//#define ATOM_ENCODER_MODE_DP 0 1502254885Sdumbbell//#define ATOM_ENCODER_MODE_LVDS 1 1503254885Sdumbbell//#define ATOM_ENCODER_MODE_DVI 2 1504254885Sdumbbell//#define ATOM_ENCODER_MODE_HDMI 3 1505254885Sdumbbell//#define ATOM_ENCODER_MODE_SDVO 4 1506254885Sdumbbell//#define ATOM_ENCODER_MODE_TV 13 1507254885Sdumbbell//#define ATOM_ENCODER_MODE_CV 14 1508254885Sdumbbell//#define ATOM_ENCODER_MODE_CRT 15 1509254885Sdumbbell 1510254885Sdumbbell/****************************************************************************/ 1511254885Sdumbbell// Structures used by SetPixelClockTable 1512254885Sdumbbell// GetPixelClockTable 1513254885Sdumbbell/****************************************************************************/ 1514254885Sdumbbell//Major revision=1., Minor revision=1 1515254885Sdumbbelltypedef struct _PIXEL_CLOCK_PARAMETERS 1516254885Sdumbbell{ 1517254885Sdumbbell USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1518254885Sdumbbell // 0 means disable PPLL 1519254885Sdumbbell USHORT usRefDiv; // Reference divider 1520254885Sdumbbell USHORT usFbDiv; // feedback divider 1521254885Sdumbbell UCHAR ucPostDiv; // post divider 1522254885Sdumbbell UCHAR ucFracFbDiv; // fractional feedback divider 1523254885Sdumbbell UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1524254885Sdumbbell UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1525254885Sdumbbell UCHAR ucCRTC; // Which CRTC uses this Ppll 1526254885Sdumbbell UCHAR ucPadding; 1527254885Sdumbbell}PIXEL_CLOCK_PARAMETERS; 1528254885Sdumbbell 1529254885Sdumbbell//Major revision=1., Minor revision=2, add ucMiscIfno 1530254885Sdumbbell//ucMiscInfo: 1531254885Sdumbbell#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1532254885Sdumbbell#define MISC_DEVICE_INDEX_MASK 0xF0 1533254885Sdumbbell#define MISC_DEVICE_INDEX_SHIFT 4 1534254885Sdumbbell 1535254885Sdumbbelltypedef struct _PIXEL_CLOCK_PARAMETERS_V2 1536254885Sdumbbell{ 1537254885Sdumbbell USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1538254885Sdumbbell // 0 means disable PPLL 1539254885Sdumbbell USHORT usRefDiv; // Reference divider 1540254885Sdumbbell USHORT usFbDiv; // feedback divider 1541254885Sdumbbell UCHAR ucPostDiv; // post divider 1542254885Sdumbbell UCHAR ucFracFbDiv; // fractional feedback divider 1543254885Sdumbbell UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1544254885Sdumbbell UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1545254885Sdumbbell UCHAR ucCRTC; // Which CRTC uses this Ppll 1546254885Sdumbbell UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1547254885Sdumbbell}PIXEL_CLOCK_PARAMETERS_V2; 1548254885Sdumbbell 1549254885Sdumbbell//Major revision=1., Minor revision=3, structure/definition change 1550254885Sdumbbell//ucEncoderMode: 1551254885Sdumbbell//ATOM_ENCODER_MODE_DP 1552254885Sdumbbell//ATOM_ENOCDER_MODE_LVDS 1553254885Sdumbbell//ATOM_ENOCDER_MODE_DVI 1554254885Sdumbbell//ATOM_ENOCDER_MODE_HDMI 1555254885Sdumbbell//ATOM_ENOCDER_MODE_SDVO 1556254885Sdumbbell//ATOM_ENCODER_MODE_TV 13 1557254885Sdumbbell//ATOM_ENCODER_MODE_CV 14 1558254885Sdumbbell//ATOM_ENCODER_MODE_CRT 15 1559254885Sdumbbell 1560254885Sdumbbell//ucDVOConfig 1561254885Sdumbbell//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1562254885Sdumbbell//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1563254885Sdumbbell//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1564254885Sdumbbell//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1565254885Sdumbbell//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1566254885Sdumbbell//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1567254885Sdumbbell//#define DVO_ENCODER_CONFIG_24BIT 0x08 1568254885Sdumbbell 1569254885Sdumbbell//ucMiscInfo: also changed, see below 1570254885Sdumbbell#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1571254885Sdumbbell#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1572254885Sdumbbell#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1573254885Sdumbbell#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1574254885Sdumbbell#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1575254885Sdumbbell#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1576254885Sdumbbell#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1577254885Sdumbbell// V1.4 for RoadRunner 1578254885Sdumbbell#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1579254885Sdumbbell#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1580254885Sdumbbell 1581254885Sdumbbell 1582254885Sdumbbelltypedef struct _PIXEL_CLOCK_PARAMETERS_V3 1583254885Sdumbbell{ 1584254885Sdumbbell USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1585254885Sdumbbell // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1586254885Sdumbbell USHORT usRefDiv; // Reference divider 1587254885Sdumbbell USHORT usFbDiv; // feedback divider 1588254885Sdumbbell UCHAR ucPostDiv; // post divider 1589254885Sdumbbell UCHAR ucFracFbDiv; // fractional feedback divider 1590254885Sdumbbell UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1591254885Sdumbbell UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1592254885Sdumbbell union 1593254885Sdumbbell { 1594254885Sdumbbell UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1595254885Sdumbbell UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1596254885Sdumbbell }; 1597254885Sdumbbell UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1598254885Sdumbbell // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1599254885Sdumbbell // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1600254885Sdumbbell}PIXEL_CLOCK_PARAMETERS_V3; 1601254885Sdumbbell 1602254885Sdumbbell#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1603254885Sdumbbell#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1604254885Sdumbbell 1605254885Sdumbbelltypedef struct _PIXEL_CLOCK_PARAMETERS_V5 1606254885Sdumbbell{ 1607254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1608254885Sdumbbell // drive the pixel clock. not used for DCPLL case. 1609254885Sdumbbell union{ 1610254885Sdumbbell UCHAR ucReserved; 1611254885Sdumbbell UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1612254885Sdumbbell }; 1613254885Sdumbbell USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1614254885Sdumbbell // 0 means disable PPLL/DCPLL. 1615254885Sdumbbell USHORT usFbDiv; // feedback divider integer part. 1616254885Sdumbbell UCHAR ucPostDiv; // post divider. 1617254885Sdumbbell UCHAR ucRefDiv; // Reference divider 1618254885Sdumbbell UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1619254885Sdumbbell UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1620254885Sdumbbell // indicate which graphic encoder will be used. 1621254885Sdumbbell UCHAR ucEncoderMode; // Encoder mode: 1622254885Sdumbbell UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1623254885Sdumbbell // bit[1]= when VGA timing is used. 1624254885Sdumbbell // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1625254885Sdumbbell // bit[4]= RefClock source for PPLL. 1626254885Sdumbbell // =0: XTLAIN( default mode ) 1627254885Sdumbbell // =1: other external clock source, which is pre-defined 1628254885Sdumbbell // by VBIOS depend on the feature required. 1629254885Sdumbbell // bit[7:5]: reserved. 1630254885Sdumbbell ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1631254885Sdumbbell 1632254885Sdumbbell}PIXEL_CLOCK_PARAMETERS_V5; 1633254885Sdumbbell 1634254885Sdumbbell#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1635254885Sdumbbell#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1636254885Sdumbbell#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1637254885Sdumbbell#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1638254885Sdumbbell#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1639254885Sdumbbell#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1640254885Sdumbbell#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1641254885Sdumbbell 1642254885Sdumbbelltypedef struct _CRTC_PIXEL_CLOCK_FREQ 1643254885Sdumbbell{ 1644254885Sdumbbell#if ATOM_BIG_ENDIAN 1645254885Sdumbbell ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1646254885Sdumbbell // drive the pixel clock. not used for DCPLL case. 1647254885Sdumbbell ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1648254885Sdumbbell // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1649254885Sdumbbell#else 1650254885Sdumbbell ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1651254885Sdumbbell // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1652254885Sdumbbell ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1653254885Sdumbbell // drive the pixel clock. not used for DCPLL case. 1654254885Sdumbbell#endif 1655254885Sdumbbell}CRTC_PIXEL_CLOCK_FREQ; 1656254885Sdumbbell 1657254885Sdumbbelltypedef struct _PIXEL_CLOCK_PARAMETERS_V6 1658254885Sdumbbell{ 1659254885Sdumbbell union{ 1660254885Sdumbbell CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1661254885Sdumbbell ULONG ulDispEngClkFreq; // dispclk frequency 1662254885Sdumbbell }; 1663254885Sdumbbell USHORT usFbDiv; // feedback divider integer part. 1664254885Sdumbbell UCHAR ucPostDiv; // post divider. 1665254885Sdumbbell UCHAR ucRefDiv; // Reference divider 1666254885Sdumbbell UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1667254885Sdumbbell UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1668254885Sdumbbell // indicate which graphic encoder will be used. 1669254885Sdumbbell UCHAR ucEncoderMode; // Encoder mode: 1670254885Sdumbbell UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1671254885Sdumbbell // bit[1]= when VGA timing is used. 1672254885Sdumbbell // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1673254885Sdumbbell // bit[4]= RefClock source for PPLL. 1674254885Sdumbbell // =0: XTLAIN( default mode ) 1675254885Sdumbbell // =1: other external clock source, which is pre-defined 1676254885Sdumbbell // by VBIOS depend on the feature required. 1677254885Sdumbbell // bit[7:5]: reserved. 1678254885Sdumbbell ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1679254885Sdumbbell 1680254885Sdumbbell}PIXEL_CLOCK_PARAMETERS_V6; 1681254885Sdumbbell 1682254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1683254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1684254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1685254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1686254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1687254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1688254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1689254885Sdumbbell#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1690254885Sdumbbell 1691254885Sdumbbelltypedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1692254885Sdumbbell{ 1693254885Sdumbbell PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1694254885Sdumbbell}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1695254885Sdumbbell 1696254885Sdumbbelltypedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1697254885Sdumbbell{ 1698254885Sdumbbell UCHAR ucStatus; 1699254885Sdumbbell UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1700254885Sdumbbell UCHAR ucReserved[2]; 1701254885Sdumbbell}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1702254885Sdumbbell 1703254885Sdumbbelltypedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1704254885Sdumbbell{ 1705254885Sdumbbell PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1706254885Sdumbbell}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1707254885Sdumbbell 1708254885Sdumbbell/****************************************************************************/ 1709254885Sdumbbell// Structures used by AdjustDisplayPllTable 1710254885Sdumbbell/****************************************************************************/ 1711254885Sdumbbelltypedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1712254885Sdumbbell{ 1713254885Sdumbbell USHORT usPixelClock; 1714254885Sdumbbell UCHAR ucTransmitterID; 1715254885Sdumbbell UCHAR ucEncodeMode; 1716254885Sdumbbell union 1717254885Sdumbbell { 1718254885Sdumbbell UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1719254885Sdumbbell UCHAR ucConfig; //if none DVO, not defined yet 1720254885Sdumbbell }; 1721254885Sdumbbell UCHAR ucReserved[3]; 1722254885Sdumbbell}ADJUST_DISPLAY_PLL_PARAMETERS; 1723254885Sdumbbell 1724254885Sdumbbell#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1725254885Sdumbbell#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1726254885Sdumbbell 1727254885Sdumbbelltypedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1728254885Sdumbbell{ 1729254885Sdumbbell USHORT usPixelClock; // target pixel clock 1730254885Sdumbbell UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1731254885Sdumbbell UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1732254885Sdumbbell UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1733254885Sdumbbell UCHAR ucExtTransmitterID; // external encoder id. 1734254885Sdumbbell UCHAR ucReserved[2]; 1735254885Sdumbbell}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1736254885Sdumbbell 1737254885Sdumbbell// usDispPllConfig v1.2 for RoadRunner 1738254885Sdumbbell#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1739254885Sdumbbell#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1740254885Sdumbbell#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1741254885Sdumbbell#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1742254885Sdumbbell#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1743254885Sdumbbell#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1744254885Sdumbbell#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1745254885Sdumbbell#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1746254885Sdumbbell#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1747254885Sdumbbell#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1748254885Sdumbbell 1749254885Sdumbbell 1750254885Sdumbbelltypedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1751254885Sdumbbell{ 1752254885Sdumbbell ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1753254885Sdumbbell UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1754254885Sdumbbell UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1755254885Sdumbbell UCHAR ucReserved[2]; 1756254885Sdumbbell}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1757254885Sdumbbell 1758254885Sdumbbelltypedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1759254885Sdumbbell{ 1760254885Sdumbbell union 1761254885Sdumbbell { 1762254885Sdumbbell ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1763254885Sdumbbell ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1764254885Sdumbbell }; 1765254885Sdumbbell} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1766254885Sdumbbell 1767254885Sdumbbell/****************************************************************************/ 1768254885Sdumbbell// Structures used by EnableYUVTable 1769254885Sdumbbell/****************************************************************************/ 1770254885Sdumbbelltypedef struct _ENABLE_YUV_PARAMETERS 1771254885Sdumbbell{ 1772254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1773254885Sdumbbell UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1774254885Sdumbbell UCHAR ucPadding[2]; 1775254885Sdumbbell}ENABLE_YUV_PARAMETERS; 1776254885Sdumbbell#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1777254885Sdumbbell 1778254885Sdumbbell/****************************************************************************/ 1779254885Sdumbbell// Structures used by GetMemoryClockTable 1780254885Sdumbbell/****************************************************************************/ 1781254885Sdumbbelltypedef struct _GET_MEMORY_CLOCK_PARAMETERS 1782254885Sdumbbell{ 1783254885Sdumbbell ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1784254885Sdumbbell} GET_MEMORY_CLOCK_PARAMETERS; 1785254885Sdumbbell#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1786254885Sdumbbell 1787254885Sdumbbell/****************************************************************************/ 1788254885Sdumbbell// Structures used by GetEngineClockTable 1789254885Sdumbbell/****************************************************************************/ 1790254885Sdumbbelltypedef struct _GET_ENGINE_CLOCK_PARAMETERS 1791254885Sdumbbell{ 1792254885Sdumbbell ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1793254885Sdumbbell} GET_ENGINE_CLOCK_PARAMETERS; 1794254885Sdumbbell#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1795254885Sdumbbell 1796254885Sdumbbell/****************************************************************************/ 1797254885Sdumbbell// Following Structures and constant may be obsolete 1798254885Sdumbbell/****************************************************************************/ 1799254885Sdumbbell//Maxium 8 bytes,the data read in will be placed in the parameter space. 1800298955Spfg//Read operaion successeful when the parameter space is non-zero, otherwise read operation failed 1801254885Sdumbbelltypedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1802254885Sdumbbell{ 1803254885Sdumbbell USHORT usPrescale; //Ratio between Engine clock and I2C clock 1804254885Sdumbbell USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID 1805254885Sdumbbell USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1806254885Sdumbbell //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1807254885Sdumbbell UCHAR ucSlaveAddr; //Read from which slave 1808254885Sdumbbell UCHAR ucLineNumber; //Read from which HW assisted line 1809254885Sdumbbell}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1810254885Sdumbbell#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1811254885Sdumbbell 1812254885Sdumbbell 1813254885Sdumbbell#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1814254885Sdumbbell#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1815254885Sdumbbell#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1816254885Sdumbbell#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1817254885Sdumbbell#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1818254885Sdumbbell 1819254885Sdumbbelltypedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1820254885Sdumbbell{ 1821254885Sdumbbell USHORT usPrescale; //Ratio between Engine clock and I2C clock 1822254885Sdumbbell USHORT usByteOffset; //Write to which byte 1823254885Sdumbbell //Upper portion of usByteOffset is Format of data 1824254885Sdumbbell //1bytePS+offsetPS 1825254885Sdumbbell //2bytesPS+offsetPS 1826254885Sdumbbell //blockID+offsetPS 1827254885Sdumbbell //blockID+offsetID 1828254885Sdumbbell //blockID+counterID+offsetID 1829254885Sdumbbell UCHAR ucData; //PS data1 1830254885Sdumbbell UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1831254885Sdumbbell UCHAR ucSlaveAddr; //Write to which slave 1832254885Sdumbbell UCHAR ucLineNumber; //Write from which HW assisted line 1833254885Sdumbbell}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1834254885Sdumbbell 1835254885Sdumbbell#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1836254885Sdumbbell 1837254885Sdumbbelltypedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1838254885Sdumbbell{ 1839254885Sdumbbell USHORT usPrescale; //Ratio between Engine clock and I2C clock 1840254885Sdumbbell UCHAR ucSlaveAddr; //Write to which slave 1841254885Sdumbbell UCHAR ucLineNumber; //Write from which HW assisted line 1842254885Sdumbbell}SET_UP_HW_I2C_DATA_PARAMETERS; 1843254885Sdumbbell 1844254885Sdumbbell 1845254885Sdumbbell/**************************************************************************/ 1846254885Sdumbbell#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1847254885Sdumbbell 1848254885Sdumbbell 1849254885Sdumbbell/****************************************************************************/ 1850254885Sdumbbell// Structures used by PowerConnectorDetectionTable 1851254885Sdumbbell/****************************************************************************/ 1852254885Sdumbbelltypedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1853254885Sdumbbell{ 1854254885Sdumbbell UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1855254885Sdumbbell UCHAR ucPwrBehaviorId; 1856254885Sdumbbell USHORT usPwrBudget; //how much power currently boot to in unit of watt 1857254885Sdumbbell}POWER_CONNECTOR_DETECTION_PARAMETERS; 1858254885Sdumbbell 1859254885Sdumbbelltypedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1860254885Sdumbbell{ 1861254885Sdumbbell UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1862254885Sdumbbell UCHAR ucReserved; 1863254885Sdumbbell USHORT usPwrBudget; //how much power currently boot to in unit of watt 1864254885Sdumbbell WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1865254885Sdumbbell}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1866254885Sdumbbell 1867254885Sdumbbell/****************************LVDS SS Command Table Definitions**********************/ 1868254885Sdumbbell 1869254885Sdumbbell/****************************************************************************/ 1870254885Sdumbbell// Structures used by EnableSpreadSpectrumOnPPLLTable 1871254885Sdumbbell/****************************************************************************/ 1872254885Sdumbbelltypedef struct _ENABLE_LVDS_SS_PARAMETERS 1873254885Sdumbbell{ 1874254885Sdumbbell USHORT usSpreadSpectrumPercentage; 1875254885Sdumbbell UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1876254885Sdumbbell UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1877254885Sdumbbell UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1878254885Sdumbbell UCHAR ucPadding[3]; 1879254885Sdumbbell}ENABLE_LVDS_SS_PARAMETERS; 1880254885Sdumbbell 1881254885Sdumbbell//ucTableFormatRevision=1,ucTableContentRevision=2 1882254885Sdumbbelltypedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1883254885Sdumbbell{ 1884254885Sdumbbell USHORT usSpreadSpectrumPercentage; 1885254885Sdumbbell UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1886254885Sdumbbell UCHAR ucSpreadSpectrumStep; // 1887254885Sdumbbell UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1888254885Sdumbbell UCHAR ucSpreadSpectrumDelay; 1889254885Sdumbbell UCHAR ucSpreadSpectrumRange; 1890254885Sdumbbell UCHAR ucPadding; 1891254885Sdumbbell}ENABLE_LVDS_SS_PARAMETERS_V2; 1892254885Sdumbbell 1893254885Sdumbbell//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1894254885Sdumbbelltypedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1895254885Sdumbbell{ 1896254885Sdumbbell USHORT usSpreadSpectrumPercentage; 1897254885Sdumbbell UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1898254885Sdumbbell UCHAR ucSpreadSpectrumStep; // 1899254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1900254885Sdumbbell UCHAR ucSpreadSpectrumDelay; 1901254885Sdumbbell UCHAR ucSpreadSpectrumRange; 1902254885Sdumbbell UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1903254885Sdumbbell}ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1904254885Sdumbbell 1905254885Sdumbbelltypedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1906254885Sdumbbell{ 1907254885Sdumbbell USHORT usSpreadSpectrumPercentage; 1908254885Sdumbbell UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1909254885Sdumbbell // Bit[1]: 1-Ext. 0-Int. 1910254885Sdumbbell // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1911254885Sdumbbell // Bits[7:4] reserved 1912254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1913254885Sdumbbell USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1914254885Sdumbbell USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1915254885Sdumbbell}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1916254885Sdumbbell 1917254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1918254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1919254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1920254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1921254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1922254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1923254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1924254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1925254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1926254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1927254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1928254885Sdumbbell 1929254885Sdumbbell// Used by DCE5.0 1930254885Sdumbbell typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 1931254885Sdumbbell{ 1932254885Sdumbbell USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 1933254885Sdumbbell UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1934254885Sdumbbell // Bit[1]: 1-Ext. 0-Int. 1935254885Sdumbbell // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1936254885Sdumbbell // Bits[7:4] reserved 1937254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1938254885Sdumbbell USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1939254885Sdumbbell USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1940254885Sdumbbell}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 1941254885Sdumbbell 1942254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 1943254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 1944254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 1945254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 1946254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 1947254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 1948254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 1949254885Sdumbbell#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 1950254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 1951254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 1952254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 1953254885Sdumbbell#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 1954254885Sdumbbell 1955254885Sdumbbell#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1956254885Sdumbbell 1957254885Sdumbbell/**************************************************************************/ 1958254885Sdumbbell 1959254885Sdumbbelltypedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1960254885Sdumbbell{ 1961254885Sdumbbell PIXEL_CLOCK_PARAMETERS sPCLKInput; 1962254885Sdumbbell ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1963254885Sdumbbell}SET_PIXEL_CLOCK_PS_ALLOCATION; 1964254885Sdumbbell 1965254885Sdumbbell#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1966254885Sdumbbell 1967254885Sdumbbell/****************************************************************************/ 1968254885Sdumbbell// Structures used by ### 1969254885Sdumbbell/****************************************************************************/ 1970254885Sdumbbelltypedef struct _MEMORY_TRAINING_PARAMETERS 1971254885Sdumbbell{ 1972254885Sdumbbell ULONG ulTargetMemoryClock; //In 10Khz unit 1973254885Sdumbbell}MEMORY_TRAINING_PARAMETERS; 1974254885Sdumbbell#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 1975254885Sdumbbell 1976254885Sdumbbell 1977254885Sdumbbell/****************************LVDS and other encoder command table definitions **********************/ 1978254885Sdumbbell 1979254885Sdumbbell 1980254885Sdumbbell/****************************************************************************/ 1981254885Sdumbbell// Structures used by LVDSEncoderControlTable (Before DCE30) 1982254885Sdumbbell// LVTMAEncoderControlTable (Before DCE30) 1983254885Sdumbbell// TMDSAEncoderControlTable (Before DCE30) 1984254885Sdumbbell/****************************************************************************/ 1985254885Sdumbbelltypedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 1986254885Sdumbbell{ 1987254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 1988254885Sdumbbell UCHAR ucMisc; // bit0=0: Enable single link 1989254885Sdumbbell // =1: Enable dual link 1990254885Sdumbbell // Bit1=0: 666RGB 1991254885Sdumbbell // =1: 888RGB 1992254885Sdumbbell UCHAR ucAction; // 0: turn off encoder 1993254885Sdumbbell // 1: setup and turn on encoder 1994254885Sdumbbell}LVDS_ENCODER_CONTROL_PARAMETERS; 1995254885Sdumbbell 1996254885Sdumbbell#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 1997254885Sdumbbell 1998254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 1999254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2000254885Sdumbbell 2001254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2002254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2003254885Sdumbbell 2004254885Sdumbbell 2005254885Sdumbbell//ucTableFormatRevision=1,ucTableContentRevision=2 2006254885Sdumbbelltypedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2007254885Sdumbbell{ 2008254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 2009254885Sdumbbell UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2010254885Sdumbbell UCHAR ucAction; // 0: turn off encoder 2011254885Sdumbbell // 1: setup and turn on encoder 2012254885Sdumbbell UCHAR ucTruncate; // bit0=0: Disable truncate 2013254885Sdumbbell // =1: Enable truncate 2014254885Sdumbbell // bit4=0: 666RGB 2015254885Sdumbbell // =1: 888RGB 2016254885Sdumbbell UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2017254885Sdumbbell // =1: Enable spatial dithering 2018254885Sdumbbell // bit4=0: 666RGB 2019254885Sdumbbell // =1: 888RGB 2020254885Sdumbbell UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2021254885Sdumbbell // =1: Enable temporal dithering 2022254885Sdumbbell // bit4=0: 666RGB 2023254885Sdumbbell // =1: 888RGB 2024254885Sdumbbell // bit5=0: Gray level 2 2025254885Sdumbbell // =1: Gray level 4 2026254885Sdumbbell UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2027254885Sdumbbell // =1: 25FRC_SEL pattern F 2028254885Sdumbbell // bit6:5=0: 50FRC_SEL pattern A 2029254885Sdumbbell // =1: 50FRC_SEL pattern B 2030254885Sdumbbell // =2: 50FRC_SEL pattern C 2031254885Sdumbbell // =3: 50FRC_SEL pattern D 2032254885Sdumbbell // bit7=0: 75FRC_SEL pattern E 2033254885Sdumbbell // =1: 75FRC_SEL pattern F 2034254885Sdumbbell}LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2035254885Sdumbbell 2036254885Sdumbbell#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2037254885Sdumbbell 2038254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2039254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2040254885Sdumbbell 2041254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2042254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2043254885Sdumbbell 2044254885Sdumbbell#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2045254885Sdumbbell#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2046254885Sdumbbell 2047254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2048254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2049254885Sdumbbell 2050254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2051254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2052254885Sdumbbell 2053254885Sdumbbell/****************************************************************************/ 2054254885Sdumbbell// Structures used by ### 2055254885Sdumbbell/****************************************************************************/ 2056254885Sdumbbelltypedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2057254885Sdumbbell{ 2058254885Sdumbbell UCHAR ucEnable; // Enable or Disable External TMDS encoder 2059254885Sdumbbell UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2060254885Sdumbbell UCHAR ucPadding[2]; 2061254885Sdumbbell}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2062254885Sdumbbell 2063254885Sdumbbelltypedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2064254885Sdumbbell{ 2065254885Sdumbbell ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2066254885Sdumbbell WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2067254885Sdumbbell}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2068254885Sdumbbell 2069254885Sdumbbell#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2070254885Sdumbbell 2071254885Sdumbbelltypedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2072254885Sdumbbell{ 2073254885Sdumbbell ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2074254885Sdumbbell WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2075254885Sdumbbell}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2076254885Sdumbbell 2077254885Sdumbbelltypedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2078254885Sdumbbell{ 2079254885Sdumbbell DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2080254885Sdumbbell WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2081254885Sdumbbell}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2082254885Sdumbbell 2083254885Sdumbbell/****************************************************************************/ 2084254885Sdumbbell// Structures used by DVOEncoderControlTable 2085254885Sdumbbell/****************************************************************************/ 2086254885Sdumbbell//ucTableFormatRevision=1,ucTableContentRevision=3 2087254885Sdumbbell 2088254885Sdumbbell//ucDVOConfig: 2089254885Sdumbbell#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2090254885Sdumbbell#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2091254885Sdumbbell#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2092254885Sdumbbell#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2093254885Sdumbbell#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2094254885Sdumbbell#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2095254885Sdumbbell#define DVO_ENCODER_CONFIG_24BIT 0x08 2096254885Sdumbbell 2097254885Sdumbbelltypedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2098254885Sdumbbell{ 2099254885Sdumbbell USHORT usPixelClock; 2100254885Sdumbbell UCHAR ucDVOConfig; 2101254885Sdumbbell UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2102254885Sdumbbell UCHAR ucReseved[4]; 2103254885Sdumbbell}DVO_ENCODER_CONTROL_PARAMETERS_V3; 2104254885Sdumbbell#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2105254885Sdumbbell 2106254885Sdumbbell//ucTableFormatRevision=1 2107254885Sdumbbell//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2108254885Sdumbbell// bit1=0: non-coherent mode 2109254885Sdumbbell// =1: coherent mode 2110254885Sdumbbell 2111254885Sdumbbell//========================================================================================== 2112254885Sdumbbell//Only change is here next time when changing encoder parameter definitions again! 2113254885Sdumbbell#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2114254885Sdumbbell#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2115254885Sdumbbell 2116254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2117254885Sdumbbell#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2118254885Sdumbbell 2119254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2120254885Sdumbbell#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2121254885Sdumbbell 2122254885Sdumbbell#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2123254885Sdumbbell#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2124254885Sdumbbell 2125254885Sdumbbell//========================================================================================== 2126254885Sdumbbell#define PANEL_ENCODER_MISC_DUAL 0x01 2127254885Sdumbbell#define PANEL_ENCODER_MISC_COHERENT 0x02 2128254885Sdumbbell#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2129254885Sdumbbell#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2130254885Sdumbbell 2131254885Sdumbbell#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2132254885Sdumbbell#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2133254885Sdumbbell#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2134254885Sdumbbell 2135254885Sdumbbell#define PANEL_ENCODER_TRUNCATE_EN 0x01 2136254885Sdumbbell#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2137254885Sdumbbell#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2138254885Sdumbbell#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2139254885Sdumbbell#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2140254885Sdumbbell#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2141254885Sdumbbell#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2142254885Sdumbbell#define PANEL_ENCODER_25FRC_MASK 0x10 2143254885Sdumbbell#define PANEL_ENCODER_25FRC_E 0x00 2144254885Sdumbbell#define PANEL_ENCODER_25FRC_F 0x10 2145254885Sdumbbell#define PANEL_ENCODER_50FRC_MASK 0x60 2146254885Sdumbbell#define PANEL_ENCODER_50FRC_A 0x00 2147254885Sdumbbell#define PANEL_ENCODER_50FRC_B 0x20 2148254885Sdumbbell#define PANEL_ENCODER_50FRC_C 0x40 2149254885Sdumbbell#define PANEL_ENCODER_50FRC_D 0x60 2150254885Sdumbbell#define PANEL_ENCODER_75FRC_MASK 0x80 2151254885Sdumbbell#define PANEL_ENCODER_75FRC_E 0x00 2152254885Sdumbbell#define PANEL_ENCODER_75FRC_F 0x80 2153254885Sdumbbell 2154254885Sdumbbell/****************************************************************************/ 2155254885Sdumbbell// Structures used by SetVoltageTable 2156254885Sdumbbell/****************************************************************************/ 2157254885Sdumbbell#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2158254885Sdumbbell#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2159254885Sdumbbell#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2160254885Sdumbbell#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2161254885Sdumbbell#define SET_VOLTAGE_INIT_MODE 5 2162254885Sdumbbell#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2163254885Sdumbbell 2164254885Sdumbbell#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2165254885Sdumbbell#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2166254885Sdumbbell#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2167254885Sdumbbell 2168254885Sdumbbell#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2169254885Sdumbbell#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2170254885Sdumbbell#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2171254885Sdumbbell 2172254885Sdumbbelltypedef struct _SET_VOLTAGE_PARAMETERS 2173254885Sdumbbell{ 2174254885Sdumbbell UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2175254885Sdumbbell UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2176254885Sdumbbell UCHAR ucVoltageIndex; // An index to tell which voltage level 2177254885Sdumbbell UCHAR ucReserved; 2178254885Sdumbbell}SET_VOLTAGE_PARAMETERS; 2179254885Sdumbbell 2180254885Sdumbbelltypedef struct _SET_VOLTAGE_PARAMETERS_V2 2181254885Sdumbbell{ 2182254885Sdumbbell UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2183254885Sdumbbell UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2184254885Sdumbbell USHORT usVoltageLevel; // real voltage level 2185254885Sdumbbell}SET_VOLTAGE_PARAMETERS_V2; 2186254885Sdumbbell 2187254885Sdumbbell 2188254885Sdumbbelltypedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2189254885Sdumbbell{ 2190254885Sdumbbell UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2191254885Sdumbbell UCHAR ucVoltageMode; // Indicate action: Set voltage level 2192254885Sdumbbell USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2193254885Sdumbbell}SET_VOLTAGE_PARAMETERS_V1_3; 2194254885Sdumbbell 2195254885Sdumbbell//ucVoltageType 2196254885Sdumbbell#define VOLTAGE_TYPE_VDDC 1 2197254885Sdumbbell#define VOLTAGE_TYPE_MVDDC 2 2198254885Sdumbbell#define VOLTAGE_TYPE_MVDDQ 3 2199254885Sdumbbell#define VOLTAGE_TYPE_VDDCI 4 2200254885Sdumbbell 2201254885Sdumbbell//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2202254885Sdumbbell#define ATOM_SET_VOLTAGE 0 //Set voltage Level 2203254885Sdumbbell#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2204254885Sdumbbell#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase 2205254885Sdumbbell#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3 2206254885Sdumbbell#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID 2207254885Sdumbbell 2208254885Sdumbbell// define vitual voltage id in usVoltageLevel 2209254885Sdumbbell#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2210254885Sdumbbell#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2211254885Sdumbbell#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2212254885Sdumbbell#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2213254885Sdumbbell 2214254885Sdumbbelltypedef struct _SET_VOLTAGE_PS_ALLOCATION 2215254885Sdumbbell{ 2216254885Sdumbbell SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2217254885Sdumbbell WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2218254885Sdumbbell}SET_VOLTAGE_PS_ALLOCATION; 2219254885Sdumbbell 2220254885Sdumbbell// New Added from SI for GetVoltageInfoTable, input parameter structure 2221254885Sdumbbelltypedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2222254885Sdumbbell{ 2223254885Sdumbbell UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2224254885Sdumbbell UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2225254885Sdumbbell USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2226254885Sdumbbell ULONG ulReserved; 2227254885Sdumbbell}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2228254885Sdumbbell 2229254885Sdumbbell// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2230254885Sdumbbelltypedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2231254885Sdumbbell{ 2232254885Sdumbbell ULONG ulVotlageGpioState; 2233254885Sdumbbell ULONG ulVoltageGPioMask; 2234254885Sdumbbell}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2235254885Sdumbbell 2236254885Sdumbbell// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2237254885Sdumbbelltypedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2238254885Sdumbbell{ 2239254885Sdumbbell USHORT usVoltageLevel; 2240254885Sdumbbell USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2241254885Sdumbbell ULONG ulReseved; 2242254885Sdumbbell}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2243254885Sdumbbell 2244254885Sdumbbell 2245254885Sdumbbell// GetVoltageInfo v1.1 ucVoltageMode 2246254885Sdumbbell#define ATOM_GET_VOLTAGE_VID 0x00 2247254885Sdumbbell#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2248254885Sdumbbell#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2249254885Sdumbbell// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2250254885Sdumbbell#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2251254885Sdumbbell 2252254885Sdumbbell// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2253254885Sdumbbell#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2254254885Sdumbbell// undefined power state 2255254885Sdumbbell#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2256254885Sdumbbell#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2257254885Sdumbbell 2258254885Sdumbbell/****************************************************************************/ 2259254885Sdumbbell// Structures used by TVEncoderControlTable 2260254885Sdumbbell/****************************************************************************/ 2261254885Sdumbbelltypedef struct _TV_ENCODER_CONTROL_PARAMETERS 2262254885Sdumbbell{ 2263254885Sdumbbell USHORT usPixelClock; // in 10KHz; for bios convenient 2264254885Sdumbbell UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2265254885Sdumbbell UCHAR ucAction; // 0: turn off encoder 2266254885Sdumbbell // 1: setup and turn on encoder 2267254885Sdumbbell}TV_ENCODER_CONTROL_PARAMETERS; 2268254885Sdumbbell 2269254885Sdumbbelltypedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2270254885Sdumbbell{ 2271254885Sdumbbell TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2272254885Sdumbbell WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2273254885Sdumbbell}TV_ENCODER_CONTROL_PS_ALLOCATION; 2274254885Sdumbbell 2275254885Sdumbbell//==============================Data Table Portion==================================== 2276254885Sdumbbell 2277254885Sdumbbell/****************************************************************************/ 2278254885Sdumbbell// Structure used in Data.mtb 2279254885Sdumbbell/****************************************************************************/ 2280254885Sdumbbelltypedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2281254885Sdumbbell{ 2282254885Sdumbbell USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2283254885Sdumbbell USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2284254885Sdumbbell USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2285254885Sdumbbell USHORT StandardVESA_Timing; // Only used by Bios 2286254885Sdumbbell USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2287254885Sdumbbell USHORT PaletteData; // Only used by BIOS 2288254885Sdumbbell USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2289254885Sdumbbell USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2290254885Sdumbbell USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2291254885Sdumbbell USHORT SupportedDevicesInfo; // Will be obsolete from R600 2292254885Sdumbbell USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2293254885Sdumbbell USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2294254885Sdumbbell USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2295254885Sdumbbell USHORT VESA_ToInternalModeLUT; // Only used by Bios 2296254885Sdumbbell USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2297254885Sdumbbell USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2298254885Sdumbbell USHORT CompassionateData; // Will be obsolete from R600 2299254885Sdumbbell USHORT SaveRestoreInfo; // Only used by Bios 2300254885Sdumbbell USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2301254885Sdumbbell USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2302254885Sdumbbell USHORT XTMDS_Info; // Will be obsolete from R600 2303254885Sdumbbell USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2304254885Sdumbbell USHORT Object_Header; // Shared by various SW components,latest version 1.1 2305254885Sdumbbell USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2306254885Sdumbbell USHORT MC_InitParameter; // Only used by command table 2307254885Sdumbbell USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2308254885Sdumbbell USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2309254885Sdumbbell USHORT TV_VideoMode; // Only used by command table 2310254885Sdumbbell USHORT VRAM_Info; // Only used by command table, latest version 1.3 2311254885Sdumbbell USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2312254885Sdumbbell USHORT IntegratedSystemInfo; // Shared by various SW components 2313254885Sdumbbell USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2314254885Sdumbbell USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2315254885Sdumbbell USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2316254885Sdumbbell}ATOM_MASTER_LIST_OF_DATA_TABLES; 2317254885Sdumbbell 2318254885Sdumbbelltypedef struct _ATOM_MASTER_DATA_TABLE 2319254885Sdumbbell{ 2320254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2321254885Sdumbbell ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2322254885Sdumbbell}ATOM_MASTER_DATA_TABLE; 2323254885Sdumbbell 2324254885Sdumbbell// For backward compatible 2325254885Sdumbbell#define LVDS_Info LCD_Info 2326254885Sdumbbell#define DAC_Info PaletteData 2327254885Sdumbbell#define TMDS_Info DIGTransmitterInfo 2328254885Sdumbbell 2329254885Sdumbbell/****************************************************************************/ 2330254885Sdumbbell// Structure used in MultimediaCapabilityInfoTable 2331254885Sdumbbell/****************************************************************************/ 2332254885Sdumbbelltypedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2333254885Sdumbbell{ 2334254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2335254885Sdumbbell ULONG ulSignature; // HW info table signature string "$ATI" 2336254885Sdumbbell UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2337254885Sdumbbell UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2338254885Sdumbbell UCHAR ucVideoPortInfo; // Provides the video port capabilities 2339254885Sdumbbell UCHAR ucHostPortInfo; // Provides host port configuration information 2340254885Sdumbbell}ATOM_MULTIMEDIA_CAPABILITY_INFO; 2341254885Sdumbbell 2342254885Sdumbbell/****************************************************************************/ 2343254885Sdumbbell// Structure used in MultimediaConfigInfoTable 2344254885Sdumbbell/****************************************************************************/ 2345254885Sdumbbelltypedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2346254885Sdumbbell{ 2347254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2348254885Sdumbbell ULONG ulSignature; // MM info table signature sting "$MMT" 2349254885Sdumbbell UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2350254885Sdumbbell UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2351254885Sdumbbell UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2352254885Sdumbbell UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2353254885Sdumbbell UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2354254885Sdumbbell UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2355254885Sdumbbell UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2356254885Sdumbbell UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2357254885Sdumbbell UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2358254885Sdumbbell UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2359254885Sdumbbell UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2360254885Sdumbbell UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2361254885Sdumbbell}ATOM_MULTIMEDIA_CONFIG_INFO; 2362254885Sdumbbell 2363254885Sdumbbell 2364254885Sdumbbell/****************************************************************************/ 2365254885Sdumbbell// Structures used in FirmwareInfoTable 2366254885Sdumbbell/****************************************************************************/ 2367254885Sdumbbell 2368254885Sdumbbell// usBIOSCapability Definition: 2369254885Sdumbbell// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2370254885Sdumbbell// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2371254885Sdumbbell// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2372254885Sdumbbell// Others: Reserved 2373254885Sdumbbell#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2374254885Sdumbbell#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2375254885Sdumbbell#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2376254885Sdumbbell#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2377254885Sdumbbell#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2378254885Sdumbbell#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2379254885Sdumbbell#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2380254885Sdumbbell#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2381254885Sdumbbell#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2382254885Sdumbbell#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2383254885Sdumbbell#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2384254885Sdumbbell#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2385254885Sdumbbell#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2386254885Sdumbbell#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2387254885Sdumbbell 2388254885Sdumbbell#ifndef _H2INC 2389254885Sdumbbell 2390254885Sdumbbell//Please don't add or expand this bitfield structure below, this one will retire soon.! 2391254885Sdumbbelltypedef struct _ATOM_FIRMWARE_CAPABILITY 2392254885Sdumbbell{ 2393254885Sdumbbell#if ATOM_BIG_ENDIAN 2394254885Sdumbbell USHORT Reserved:1; 2395254885Sdumbbell USHORT SCL2Redefined:1; 2396254885Sdumbbell USHORT PostWithoutModeSet:1; 2397254885Sdumbbell USHORT HyperMemory_Size:4; 2398254885Sdumbbell USHORT HyperMemory_Support:1; 2399254885Sdumbbell USHORT PPMode_Assigned:1; 2400254885Sdumbbell USHORT WMI_SUPPORT:1; 2401254885Sdumbbell USHORT GPUControlsBL:1; 2402254885Sdumbbell USHORT EngineClockSS_Support:1; 2403254885Sdumbbell USHORT MemoryClockSS_Support:1; 2404254885Sdumbbell USHORT ExtendedDesktopSupport:1; 2405254885Sdumbbell USHORT DualCRTC_Support:1; 2406254885Sdumbbell USHORT FirmwarePosted:1; 2407254885Sdumbbell#else 2408254885Sdumbbell USHORT FirmwarePosted:1; 2409254885Sdumbbell USHORT DualCRTC_Support:1; 2410254885Sdumbbell USHORT ExtendedDesktopSupport:1; 2411254885Sdumbbell USHORT MemoryClockSS_Support:1; 2412254885Sdumbbell USHORT EngineClockSS_Support:1; 2413254885Sdumbbell USHORT GPUControlsBL:1; 2414254885Sdumbbell USHORT WMI_SUPPORT:1; 2415254885Sdumbbell USHORT PPMode_Assigned:1; 2416254885Sdumbbell USHORT HyperMemory_Support:1; 2417254885Sdumbbell USHORT HyperMemory_Size:4; 2418254885Sdumbbell USHORT PostWithoutModeSet:1; 2419254885Sdumbbell USHORT SCL2Redefined:1; 2420254885Sdumbbell USHORT Reserved:1; 2421254885Sdumbbell#endif 2422254885Sdumbbell}ATOM_FIRMWARE_CAPABILITY; 2423254885Sdumbbell 2424254885Sdumbbelltypedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2425254885Sdumbbell{ 2426254885Sdumbbell ATOM_FIRMWARE_CAPABILITY sbfAccess; 2427254885Sdumbbell USHORT susAccess; 2428254885Sdumbbell}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2429254885Sdumbbell 2430254885Sdumbbell#else 2431254885Sdumbbell 2432254885Sdumbbelltypedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2433254885Sdumbbell{ 2434254885Sdumbbell USHORT susAccess; 2435254885Sdumbbell}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2436254885Sdumbbell 2437254885Sdumbbell#endif 2438254885Sdumbbell 2439254885Sdumbbelltypedef struct _ATOM_FIRMWARE_INFO 2440254885Sdumbbell{ 2441254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2442254885Sdumbbell ULONG ulFirmwareRevision; 2443254885Sdumbbell ULONG ulDefaultEngineClock; //In 10Khz unit 2444254885Sdumbbell ULONG ulDefaultMemoryClock; //In 10Khz unit 2445254885Sdumbbell ULONG ulDriverTargetEngineClock; //In 10Khz unit 2446254885Sdumbbell ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2447254885Sdumbbell ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2448254885Sdumbbell ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2449254885Sdumbbell ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2450254885Sdumbbell ULONG ulASICMaxEngineClock; //In 10Khz unit 2451254885Sdumbbell ULONG ulASICMaxMemoryClock; //In 10Khz unit 2452254885Sdumbbell UCHAR ucASICMaxTemperature; 2453254885Sdumbbell UCHAR ucPadding[3]; //Don't use them 2454254885Sdumbbell ULONG aulReservedForBIOS[3]; //Don't use them 2455254885Sdumbbell USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2456254885Sdumbbell USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2457254885Sdumbbell USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2458254885Sdumbbell USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2459254885Sdumbbell USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2460254885Sdumbbell USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2461254885Sdumbbell USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2462254885Sdumbbell USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2463254885Sdumbbell USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2464254885Sdumbbell USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2465254885Sdumbbell ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2466254885Sdumbbell USHORT usReferenceClock; //In 10Khz unit 2467254885Sdumbbell USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2468254885Sdumbbell UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2469254885Sdumbbell UCHAR ucDesign_ID; //Indicate what is the board design 2470254885Sdumbbell UCHAR ucMemoryModule_ID; //Indicate what is the board design 2471254885Sdumbbell}ATOM_FIRMWARE_INFO; 2472254885Sdumbbell 2473254885Sdumbbelltypedef struct _ATOM_FIRMWARE_INFO_V1_2 2474254885Sdumbbell{ 2475254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2476254885Sdumbbell ULONG ulFirmwareRevision; 2477254885Sdumbbell ULONG ulDefaultEngineClock; //In 10Khz unit 2478254885Sdumbbell ULONG ulDefaultMemoryClock; //In 10Khz unit 2479254885Sdumbbell ULONG ulDriverTargetEngineClock; //In 10Khz unit 2480254885Sdumbbell ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2481254885Sdumbbell ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2482254885Sdumbbell ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2483254885Sdumbbell ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2484254885Sdumbbell ULONG ulASICMaxEngineClock; //In 10Khz unit 2485254885Sdumbbell ULONG ulASICMaxMemoryClock; //In 10Khz unit 2486254885Sdumbbell UCHAR ucASICMaxTemperature; 2487254885Sdumbbell UCHAR ucMinAllowedBL_Level; 2488254885Sdumbbell UCHAR ucPadding[2]; //Don't use them 2489254885Sdumbbell ULONG aulReservedForBIOS[2]; //Don't use them 2490254885Sdumbbell ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2491254885Sdumbbell USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2492254885Sdumbbell USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2493254885Sdumbbell USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2494254885Sdumbbell USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2495254885Sdumbbell USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2496254885Sdumbbell USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2497254885Sdumbbell USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2498254885Sdumbbell USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2499254885Sdumbbell USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2500254885Sdumbbell USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2501254885Sdumbbell ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2502254885Sdumbbell USHORT usReferenceClock; //In 10Khz unit 2503254885Sdumbbell USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2504254885Sdumbbell UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2505254885Sdumbbell UCHAR ucDesign_ID; //Indicate what is the board design 2506254885Sdumbbell UCHAR ucMemoryModule_ID; //Indicate what is the board design 2507254885Sdumbbell}ATOM_FIRMWARE_INFO_V1_2; 2508254885Sdumbbell 2509254885Sdumbbelltypedef struct _ATOM_FIRMWARE_INFO_V1_3 2510254885Sdumbbell{ 2511254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2512254885Sdumbbell ULONG ulFirmwareRevision; 2513254885Sdumbbell ULONG ulDefaultEngineClock; //In 10Khz unit 2514254885Sdumbbell ULONG ulDefaultMemoryClock; //In 10Khz unit 2515254885Sdumbbell ULONG ulDriverTargetEngineClock; //In 10Khz unit 2516254885Sdumbbell ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2517254885Sdumbbell ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2518254885Sdumbbell ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2519254885Sdumbbell ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2520254885Sdumbbell ULONG ulASICMaxEngineClock; //In 10Khz unit 2521254885Sdumbbell ULONG ulASICMaxMemoryClock; //In 10Khz unit 2522254885Sdumbbell UCHAR ucASICMaxTemperature; 2523254885Sdumbbell UCHAR ucMinAllowedBL_Level; 2524254885Sdumbbell UCHAR ucPadding[2]; //Don't use them 2525254885Sdumbbell ULONG aulReservedForBIOS; //Don't use them 2526254885Sdumbbell ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2527254885Sdumbbell ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2528254885Sdumbbell USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2529254885Sdumbbell USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2530254885Sdumbbell USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2531254885Sdumbbell USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2532254885Sdumbbell USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2533254885Sdumbbell USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2534254885Sdumbbell USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2535254885Sdumbbell USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2536254885Sdumbbell USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2537254885Sdumbbell USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2538254885Sdumbbell ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2539254885Sdumbbell USHORT usReferenceClock; //In 10Khz unit 2540254885Sdumbbell USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2541254885Sdumbbell UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2542254885Sdumbbell UCHAR ucDesign_ID; //Indicate what is the board design 2543254885Sdumbbell UCHAR ucMemoryModule_ID; //Indicate what is the board design 2544254885Sdumbbell}ATOM_FIRMWARE_INFO_V1_3; 2545254885Sdumbbell 2546254885Sdumbbelltypedef struct _ATOM_FIRMWARE_INFO_V1_4 2547254885Sdumbbell{ 2548254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2549254885Sdumbbell ULONG ulFirmwareRevision; 2550254885Sdumbbell ULONG ulDefaultEngineClock; //In 10Khz unit 2551254885Sdumbbell ULONG ulDefaultMemoryClock; //In 10Khz unit 2552254885Sdumbbell ULONG ulDriverTargetEngineClock; //In 10Khz unit 2553254885Sdumbbell ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2554254885Sdumbbell ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2555254885Sdumbbell ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2556254885Sdumbbell ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2557254885Sdumbbell ULONG ulASICMaxEngineClock; //In 10Khz unit 2558254885Sdumbbell ULONG ulASICMaxMemoryClock; //In 10Khz unit 2559254885Sdumbbell UCHAR ucASICMaxTemperature; 2560254885Sdumbbell UCHAR ucMinAllowedBL_Level; 2561254885Sdumbbell USHORT usBootUpVDDCVoltage; //In MV unit 2562254885Sdumbbell USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2563254885Sdumbbell USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2564254885Sdumbbell ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2565254885Sdumbbell ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2566254885Sdumbbell USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2567254885Sdumbbell USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2568254885Sdumbbell USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2569254885Sdumbbell USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2570254885Sdumbbell USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2571254885Sdumbbell USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2572254885Sdumbbell USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2573254885Sdumbbell USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2574254885Sdumbbell USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2575254885Sdumbbell USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2576254885Sdumbbell ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2577254885Sdumbbell USHORT usReferenceClock; //In 10Khz unit 2578254885Sdumbbell USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2579254885Sdumbbell UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2580254885Sdumbbell UCHAR ucDesign_ID; //Indicate what is the board design 2581254885Sdumbbell UCHAR ucMemoryModule_ID; //Indicate what is the board design 2582254885Sdumbbell}ATOM_FIRMWARE_INFO_V1_4; 2583254885Sdumbbell 2584254885Sdumbbell//the structure below to be used from Cypress 2585254885Sdumbbelltypedef struct _ATOM_FIRMWARE_INFO_V2_1 2586254885Sdumbbell{ 2587254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2588254885Sdumbbell ULONG ulFirmwareRevision; 2589254885Sdumbbell ULONG ulDefaultEngineClock; //In 10Khz unit 2590254885Sdumbbell ULONG ulDefaultMemoryClock; //In 10Khz unit 2591254885Sdumbbell ULONG ulReserved1; 2592254885Sdumbbell ULONG ulReserved2; 2593254885Sdumbbell ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2594254885Sdumbbell ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2595254885Sdumbbell ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2596254885Sdumbbell ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2597254885Sdumbbell ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2598254885Sdumbbell UCHAR ucReserved1; //Was ucASICMaxTemperature; 2599254885Sdumbbell UCHAR ucMinAllowedBL_Level; 2600254885Sdumbbell USHORT usBootUpVDDCVoltage; //In MV unit 2601254885Sdumbbell USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2602254885Sdumbbell USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2603254885Sdumbbell ULONG ulReserved4; //Was ulAsicMaximumVoltage 2604254885Sdumbbell ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2605254885Sdumbbell USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2606254885Sdumbbell USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2607254885Sdumbbell USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2608254885Sdumbbell USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2609254885Sdumbbell USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2610254885Sdumbbell USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2611254885Sdumbbell USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2612254885Sdumbbell USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2613254885Sdumbbell USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2614254885Sdumbbell USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2615254885Sdumbbell ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2616254885Sdumbbell USHORT usCoreReferenceClock; //In 10Khz unit 2617254885Sdumbbell USHORT usMemoryReferenceClock; //In 10Khz unit 2618254885Sdumbbell USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2619254885Sdumbbell UCHAR ucMemoryModule_ID; //Indicate what is the board design 2620254885Sdumbbell UCHAR ucReserved4[3]; 2621254885Sdumbbell}ATOM_FIRMWARE_INFO_V2_1; 2622254885Sdumbbell 2623254885Sdumbbell//the structure below to be used from NI 2624254885Sdumbbell//ucTableFormatRevision=2 2625254885Sdumbbell//ucTableContentRevision=2 2626254885Sdumbbelltypedef struct _ATOM_FIRMWARE_INFO_V2_2 2627254885Sdumbbell{ 2628254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2629254885Sdumbbell ULONG ulFirmwareRevision; 2630254885Sdumbbell ULONG ulDefaultEngineClock; //In 10Khz unit 2631254885Sdumbbell ULONG ulDefaultMemoryClock; //In 10Khz unit 2632254885Sdumbbell ULONG ulReserved[2]; 2633254885Sdumbbell ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2634254885Sdumbbell ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2635254885Sdumbbell ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2636254885Sdumbbell ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2637254885Sdumbbell ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2638254885Sdumbbell UCHAR ucReserved3; //Was ucASICMaxTemperature; 2639254885Sdumbbell UCHAR ucMinAllowedBL_Level; 2640254885Sdumbbell USHORT usBootUpVDDCVoltage; //In MV unit 2641254885Sdumbbell USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2642254885Sdumbbell USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2643254885Sdumbbell ULONG ulReserved4; //Was ulAsicMaximumVoltage 2644254885Sdumbbell ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2645254885Sdumbbell UCHAR ucRemoteDisplayConfig; 2646254885Sdumbbell UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2647254885Sdumbbell ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2648254885Sdumbbell ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2649254885Sdumbbell USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2650254885Sdumbbell USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2651254885Sdumbbell USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2652254885Sdumbbell USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2653254885Sdumbbell ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2654254885Sdumbbell USHORT usCoreReferenceClock; //In 10Khz unit 2655254885Sdumbbell USHORT usMemoryReferenceClock; //In 10Khz unit 2656254885Sdumbbell USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2657254885Sdumbbell UCHAR ucMemoryModule_ID; //Indicate what is the board design 2658254885Sdumbbell UCHAR ucReserved9[3]; 2659254885Sdumbbell USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2660254885Sdumbbell USHORT usReserved12; 2661254885Sdumbbell ULONG ulReserved10[3]; // New added comparing to previous version 2662254885Sdumbbell}ATOM_FIRMWARE_INFO_V2_2; 2663254885Sdumbbell 2664254885Sdumbbell#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2665254885Sdumbbell 2666254885Sdumbbell 2667254885Sdumbbell// definition of ucRemoteDisplayConfig 2668254885Sdumbbell#define REMOTE_DISPLAY_DISABLE 0x00 2669254885Sdumbbell#define REMOTE_DISPLAY_ENABLE 0x01 2670254885Sdumbbell 2671254885Sdumbbell/****************************************************************************/ 2672254885Sdumbbell// Structures used in IntegratedSystemInfoTable 2673254885Sdumbbell/****************************************************************************/ 2674254885Sdumbbell#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2675254885Sdumbbell#define IGP_CAP_FLAG_AC_CARD 0x4 2676254885Sdumbbell#define IGP_CAP_FLAG_SDVO_CARD 0x8 2677254885Sdumbbell#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2678254885Sdumbbell 2679254885Sdumbbelltypedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2680254885Sdumbbell{ 2681254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2682254885Sdumbbell ULONG ulBootUpEngineClock; //in 10kHz unit 2683254885Sdumbbell ULONG ulBootUpMemoryClock; //in 10kHz unit 2684254885Sdumbbell ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2685254885Sdumbbell ULONG ulMinSystemMemoryClock; //in 10kHz unit 2686254885Sdumbbell UCHAR ucNumberOfCyclesInPeriodHi; 2687254885Sdumbbell UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2688254885Sdumbbell USHORT usReserved1; 2689254885Sdumbbell USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2690254885Sdumbbell USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2691254885Sdumbbell ULONG ulReserved[2]; 2692254885Sdumbbell 2693254885Sdumbbell USHORT usFSBClock; //In MHz unit 2694254885Sdumbbell USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2695254885Sdumbbell //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2696254885Sdumbbell //Bit[4]==1: P/2 mode, ==0: P/1 mode 2697254885Sdumbbell USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2698254885Sdumbbell USHORT usK8MemoryClock; //in MHz unit 2699254885Sdumbbell USHORT usK8SyncStartDelay; //in 0.01 us unit 2700254885Sdumbbell USHORT usK8DataReturnTime; //in 0.01 us unit 2701254885Sdumbbell UCHAR ucMaxNBVoltage; 2702254885Sdumbbell UCHAR ucMinNBVoltage; 2703254885Sdumbbell UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2704254885Sdumbbell UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2705254885Sdumbbell UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2706254885Sdumbbell UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2707254885Sdumbbell UCHAR ucMaxNBVoltageHigh; 2708254885Sdumbbell UCHAR ucMinNBVoltageHigh; 2709254885Sdumbbell}ATOM_INTEGRATED_SYSTEM_INFO; 2710254885Sdumbbell 2711254885Sdumbbell/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2712254885SdumbbellulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2713254885Sdumbbell For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2714254885SdumbbellulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2715254885Sdumbbell For AMD IGP,for now this can be 0 2716254885SdumbbellulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2717254885Sdumbbell For AMD IGP,for now this can be 0 2718254885Sdumbbell 2719254885SdumbbellusFSBClock: For Intel IGP,it's FSB Freq 2720254885Sdumbbell For AMD IGP,it's HT Link Speed 2721254885Sdumbbell 2722254885SdumbbellusK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2723254885SdumbbellusK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2724254885SdumbbellusK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2725254885Sdumbbell 2726254885SdumbbellVC:Voltage Control 2727254885SdumbbellucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2728254885SdumbbellucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2729254885Sdumbbell 2730254885SdumbbellucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2731254885SdumbbellucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2732254885Sdumbbell 2733254885SdumbbellucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2734254885SdumbbellucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2735254885Sdumbbell 2736254885Sdumbbell 2737254885SdumbbellusInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2738254885SdumbbellusInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2739254885Sdumbbell*/ 2740254885Sdumbbell 2741254885Sdumbbell 2742254885Sdumbbell/* 2743254885SdumbbellThe following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2744254885SdumbbellThen VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2745254885SdumbbellThe enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2746254885Sdumbbell 2747254885SdumbbellSW components can access the IGP system infor structure in the same way as before 2748254885Sdumbbell*/ 2749254885Sdumbbell 2750254885Sdumbbell 2751254885Sdumbbelltypedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2752254885Sdumbbell{ 2753254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2754254885Sdumbbell ULONG ulBootUpEngineClock; //in 10kHz unit 2755254885Sdumbbell ULONG ulReserved1[2]; //must be 0x0 for the reserved 2756254885Sdumbbell ULONG ulBootUpUMAClock; //in 10kHz unit 2757254885Sdumbbell ULONG ulBootUpSidePortClock; //in 10kHz unit 2758254885Sdumbbell ULONG ulMinSidePortClock; //in 10kHz unit 2759254885Sdumbbell ULONG ulReserved2[6]; //must be 0x0 for the reserved 2760254885Sdumbbell ULONG ulSystemConfig; //see explanation below 2761254885Sdumbbell ULONG ulBootUpReqDisplayVector; 2762254885Sdumbbell ULONG ulOtherDisplayMisc; 2763254885Sdumbbell ULONG ulDDISlot1Config; 2764254885Sdumbbell ULONG ulDDISlot2Config; 2765254885Sdumbbell UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2766254885Sdumbbell UCHAR ucUMAChannelNumber; 2767254885Sdumbbell UCHAR ucDockingPinBit; 2768254885Sdumbbell UCHAR ucDockingPinPolarity; 2769254885Sdumbbell ULONG ulDockingPinCFGInfo; 2770254885Sdumbbell ULONG ulCPUCapInfo; 2771254885Sdumbbell USHORT usNumberOfCyclesInPeriod; 2772254885Sdumbbell USHORT usMaxNBVoltage; 2773254885Sdumbbell USHORT usMinNBVoltage; 2774254885Sdumbbell USHORT usBootUpNBVoltage; 2775254885Sdumbbell ULONG ulHTLinkFreq; //in 10Khz 2776254885Sdumbbell USHORT usMinHTLinkWidth; 2777254885Sdumbbell USHORT usMaxHTLinkWidth; 2778254885Sdumbbell USHORT usUMASyncStartDelay; 2779254885Sdumbbell USHORT usUMADataReturnTime; 2780254885Sdumbbell USHORT usLinkStatusZeroTime; 2781254885Sdumbbell USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2782254885Sdumbbell ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2783254885Sdumbbell ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2784254885Sdumbbell USHORT usMaxUpStreamHTLinkWidth; 2785254885Sdumbbell USHORT usMaxDownStreamHTLinkWidth; 2786254885Sdumbbell USHORT usMinUpStreamHTLinkWidth; 2787254885Sdumbbell USHORT usMinDownStreamHTLinkWidth; 2788254885Sdumbbell USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2789254885Sdumbbell USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2790254885Sdumbbell ULONG ulReserved3[96]; //must be 0x0 2791254885Sdumbbell}ATOM_INTEGRATED_SYSTEM_INFO_V2; 2792254885Sdumbbell 2793254885Sdumbbell/* 2794254885SdumbbellulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2795254885SdumbbellulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2796254885SdumbbellulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2797254885Sdumbbell 2798254885SdumbbellulSystemConfig: 2799254885SdumbbellBit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2800254885SdumbbellBit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2801254885Sdumbbell =0: system boots up at driver control state. Power state depends on PowerPlay table. 2802254885SdumbbellBit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2803254885SdumbbellBit[3]=1: Only one power state(Performance) will be supported. 2804254885Sdumbbell =0: Multiple power states supported from PowerPlay table. 2805254885SdumbbellBit[4]=1: CLMC is supported and enabled on current system. 2806254885Sdumbbell =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2807254885SdumbbellBit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2808254885Sdumbbell =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2809254885SdumbbellBit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2810254885Sdumbbell =0: Voltage settings is determined by powerplay table. 2811254885SdumbbellBit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2812254885Sdumbbell =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2813254885SdumbbellBit[8]=1: CDLF is supported and enabled on current system. 2814254885Sdumbbell =0: CDLF is not supported or enabled on current system. 2815254885SdumbbellBit[9]=1: DLL Shut Down feature is enabled on current system. 2816254885Sdumbbell =0: DLL Shut Down feature is not enabled or supported on current system. 2817254885Sdumbbell 2818254885SdumbbellulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2819254885Sdumbbell 2820254885SdumbbellulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2821254885Sdumbbell [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; 2822254885Sdumbbell 2823254885SdumbbellulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2824254885Sdumbbell [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2825254885Sdumbbell [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2826254885Sdumbbell When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2827254885Sdumbbell in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2828254885Sdumbbell one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2829254885Sdumbbell 2830254885Sdumbbell [15:8] - Lane configuration attribute; 2831254885Sdumbbell [23:16]- Connector type, possible value: 2832254885Sdumbbell CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2833254885Sdumbbell CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2834254885Sdumbbell CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2835254885Sdumbbell CONNECTOR_OBJECT_ID_DISPLAYPORT 2836254885Sdumbbell CONNECTOR_OBJECT_ID_eDP 2837254885Sdumbbell [31:24]- Reserved 2838254885Sdumbbell 2839254885SdumbbellulDDISlot2Config: Same as Slot1. 2840254885SdumbbellucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2841254885SdumbbellFor IGP, Hypermemory is the only memory type showed in CCC. 2842254885Sdumbbell 2843254885SdumbbellucUMAChannelNumber: how many channels for the UMA; 2844254885Sdumbbell 2845254885SdumbbellulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2846254885SdumbbellucDockingPinBit: which bit in this register to read the pin status; 2847254885SdumbbellucDockingPinPolarity:Polarity of the pin when docked; 2848254885Sdumbbell 2849254885SdumbbellulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 2850254885Sdumbbell 2851254885SdumbbellusNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2852254885Sdumbbell 2853254885SdumbbellusMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 2854254885SdumbbellusMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 2855254885Sdumbbell GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 2856254885Sdumbbell PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 2857254885Sdumbbell GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 2858254885Sdumbbell 2859254885SdumbbellusBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 2860254885Sdumbbell 2861254885SdumbbellulHTLinkFreq: Bootup HT link Frequency in 10Khz. 2862254885SdumbbellusMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 2863254885Sdumbbell If CDLW enabled, both upstream and downstream width should be the same during bootup. 2864254885SdumbbellusMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 2865254885Sdumbbell If CDLW enabled, both upstream and downstream width should be the same during bootup. 2866254885Sdumbbell 2867254885SdumbbellusUMASyncStartDelay: Memory access latency, required for watermark calculation 2868254885SdumbbellusUMADataReturnTime: Memory access latency, required for watermark calculation 2869254885SdumbbellusLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 2870254885Sdumbbellfor Griffin or Greyhound. SBIOS needs to convert to actual time by: 2871254885Sdumbbell if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 2872254885Sdumbbell if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 2873254885Sdumbbell if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 2874254885Sdumbbell if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 2875254885Sdumbbell 2876254885SdumbbellulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 2877254885Sdumbbell This must be less than or equal to ulHTLinkFreq(bootup frequency). 2878254885SdumbbellulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 2879254885Sdumbbell This must be less than or equal to ulHighVoltageHTLinkFreq. 2880254885Sdumbbell 2881254885SdumbbellusMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 2882254885SdumbbellusMaxDownStreamHTLinkWidth: same as above. 2883254885SdumbbellusMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 2884254885SdumbbellusMinDownStreamHTLinkWidth: same as above. 2885254885Sdumbbell*/ 2886254885Sdumbbell 2887254885Sdumbbell// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 2888254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 2889254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 2890254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 2891254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 2892254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 2893254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 2894254885Sdumbbell 2895254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 2896254885Sdumbbell 2897254885Sdumbbell#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2898254885Sdumbbell#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2899254885Sdumbbell#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2900254885Sdumbbell#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2901254885Sdumbbell#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2902254885Sdumbbell#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2903254885Sdumbbell#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2904254885Sdumbbell#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2905254885Sdumbbell#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2906254885Sdumbbell#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2907254885Sdumbbell 2908254885Sdumbbell#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2909254885Sdumbbell 2910254885Sdumbbell#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2911254885Sdumbbell#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2912254885Sdumbbell#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2913254885Sdumbbell#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2914254885Sdumbbell#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2915254885Sdumbbell#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2916254885Sdumbbell 2917254885Sdumbbell#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2918254885Sdumbbell#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2919254885Sdumbbell#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2920254885Sdumbbell 2921254885Sdumbbell#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2922254885Sdumbbell 2923254885Sdumbbell// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2924254885Sdumbbelltypedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2925254885Sdumbbell{ 2926254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 2927254885Sdumbbell ULONG ulBootUpEngineClock; //in 10kHz unit 2928254885Sdumbbell ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2929254885Sdumbbell ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 2930254885Sdumbbell ULONG ulBootUpUMAClock; //in 10kHz unit 2931254885Sdumbbell ULONG ulReserved1[8]; //must be 0x0 for the reserved 2932254885Sdumbbell ULONG ulBootUpReqDisplayVector; 2933254885Sdumbbell ULONG ulOtherDisplayMisc; 2934254885Sdumbbell ULONG ulReserved2[4]; //must be 0x0 for the reserved 2935254885Sdumbbell ULONG ulSystemConfig; //TBD 2936254885Sdumbbell ULONG ulCPUCapInfo; //TBD 2937254885Sdumbbell USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2938254885Sdumbbell USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2939254885Sdumbbell USHORT usBootUpNBVoltage; //boot up NB voltage 2940254885Sdumbbell UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 2941254885Sdumbbell UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 2942254885Sdumbbell ULONG ulReserved3[4]; //must be 0x0 for the reserved 2943254885Sdumbbell ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 2944254885Sdumbbell ULONG ulDDISlot2Config; 2945254885Sdumbbell ULONG ulDDISlot3Config; 2946254885Sdumbbell ULONG ulDDISlot4Config; 2947254885Sdumbbell ULONG ulReserved4[4]; //must be 0x0 for the reserved 2948254885Sdumbbell UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2949254885Sdumbbell UCHAR ucUMAChannelNumber; 2950254885Sdumbbell USHORT usReserved; 2951254885Sdumbbell ULONG ulReserved5[4]; //must be 0x0 for the reserved 2952254885Sdumbbell ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 2953254885Sdumbbell ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 2954254885Sdumbbell ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 2955254885Sdumbbell ULONG ulReserved6[61]; //must be 0x0 2956254885Sdumbbell}ATOM_INTEGRATED_SYSTEM_INFO_V5; 2957254885Sdumbbell 2958254885Sdumbbell#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 2959254885Sdumbbell#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 2960254885Sdumbbell#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 2961254885Sdumbbell#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 2962254885Sdumbbell#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 2963254885Sdumbbell#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 2964254885Sdumbbell#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 2965254885Sdumbbell#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 2966254885Sdumbbell#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 2967254885Sdumbbell#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 2968254885Sdumbbell#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 2969254885Sdumbbell#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 2970254885Sdumbbell#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 2971254885Sdumbbell#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 2972254885Sdumbbell 2973254885Sdumbbell// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 2974254885Sdumbbell#define ASIC_INT_DAC1_ENCODER_ID 0x00 2975254885Sdumbbell#define ASIC_INT_TV_ENCODER_ID 0x02 2976254885Sdumbbell#define ASIC_INT_DIG1_ENCODER_ID 0x03 2977254885Sdumbbell#define ASIC_INT_DAC2_ENCODER_ID 0x04 2978254885Sdumbbell#define ASIC_EXT_TV_ENCODER_ID 0x06 2979254885Sdumbbell#define ASIC_INT_DVO_ENCODER_ID 0x07 2980254885Sdumbbell#define ASIC_INT_DIG2_ENCODER_ID 0x09 2981254885Sdumbbell#define ASIC_EXT_DIG_ENCODER_ID 0x05 2982254885Sdumbbell#define ASIC_EXT_DIG2_ENCODER_ID 0x08 2983254885Sdumbbell#define ASIC_INT_DIG3_ENCODER_ID 0x0a 2984254885Sdumbbell#define ASIC_INT_DIG4_ENCODER_ID 0x0b 2985254885Sdumbbell#define ASIC_INT_DIG5_ENCODER_ID 0x0c 2986254885Sdumbbell#define ASIC_INT_DIG6_ENCODER_ID 0x0d 2987254885Sdumbbell#define ASIC_INT_DIG7_ENCODER_ID 0x0e 2988254885Sdumbbell 2989254885Sdumbbell//define Encoder attribute 2990254885Sdumbbell#define ATOM_ANALOG_ENCODER 0 2991254885Sdumbbell#define ATOM_DIGITAL_ENCODER 1 2992254885Sdumbbell#define ATOM_DP_ENCODER 2 2993254885Sdumbbell 2994254885Sdumbbell#define ATOM_ENCODER_ENUM_MASK 0x70 2995254885Sdumbbell#define ATOM_ENCODER_ENUM_ID1 0x00 2996254885Sdumbbell#define ATOM_ENCODER_ENUM_ID2 0x10 2997254885Sdumbbell#define ATOM_ENCODER_ENUM_ID3 0x20 2998254885Sdumbbell#define ATOM_ENCODER_ENUM_ID4 0x30 2999254885Sdumbbell#define ATOM_ENCODER_ENUM_ID5 0x40 3000254885Sdumbbell#define ATOM_ENCODER_ENUM_ID6 0x50 3001254885Sdumbbell 3002254885Sdumbbell#define ATOM_DEVICE_CRT1_INDEX 0x00000000 3003254885Sdumbbell#define ATOM_DEVICE_LCD1_INDEX 0x00000001 3004254885Sdumbbell#define ATOM_DEVICE_TV1_INDEX 0x00000002 3005254885Sdumbbell#define ATOM_DEVICE_DFP1_INDEX 0x00000003 3006254885Sdumbbell#define ATOM_DEVICE_CRT2_INDEX 0x00000004 3007254885Sdumbbell#define ATOM_DEVICE_LCD2_INDEX 0x00000005 3008254885Sdumbbell#define ATOM_DEVICE_DFP6_INDEX 0x00000006 3009254885Sdumbbell#define ATOM_DEVICE_DFP2_INDEX 0x00000007 3010254885Sdumbbell#define ATOM_DEVICE_CV_INDEX 0x00000008 3011254885Sdumbbell#define ATOM_DEVICE_DFP3_INDEX 0x00000009 3012254885Sdumbbell#define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3013254885Sdumbbell#define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3014254885Sdumbbell 3015254885Sdumbbell#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3016254885Sdumbbell#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3017254885Sdumbbell#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3018254885Sdumbbell#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3019254885Sdumbbell#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3020254885Sdumbbell#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3021254885Sdumbbell#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3022254885Sdumbbell 3023254885Sdumbbell#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3024254885Sdumbbell 3025254885Sdumbbell#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3026254885Sdumbbell#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3027254885Sdumbbell#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3028254885Sdumbbell#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3029254885Sdumbbell#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3030254885Sdumbbell#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3031254885Sdumbbell#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3032254885Sdumbbell#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3033254885Sdumbbell#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3034254885Sdumbbell#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3035254885Sdumbbell#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3036254885Sdumbbell#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3037254885Sdumbbell 3038254885Sdumbbell#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3039254885Sdumbbell#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3040254885Sdumbbell#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 3041254885Sdumbbell#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3042254885Sdumbbell 3043254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3044254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3045254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3046254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3047254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3048254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3049254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3050254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3051254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3052254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3053254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3054254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3055254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3056254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3057254885Sdumbbell#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3058254885Sdumbbell 3059254885Sdumbbell 3060254885Sdumbbell#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3061254885Sdumbbell#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3062254885Sdumbbell#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3063254885Sdumbbell#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3064254885Sdumbbell#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3065254885Sdumbbell#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3066254885Sdumbbell 3067254885Sdumbbell#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3068254885Sdumbbell 3069254885Sdumbbell#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3070254885Sdumbbell#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3071254885Sdumbbell 3072254885Sdumbbell#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3073254885Sdumbbell#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3074254885Sdumbbell#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3075254885Sdumbbell#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3076254885Sdumbbell#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3077254885Sdumbbell#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3078254885Sdumbbell 3079254885Sdumbbell#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3080254885Sdumbbell#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3081254885Sdumbbell#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3082254885Sdumbbell#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3083254885Sdumbbell 3084254885Sdumbbell// usDeviceSupport: 3085254885Sdumbbell// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3086254885Sdumbbell// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3087254885Sdumbbell// Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3088254885Sdumbbell// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3089254885Sdumbbell// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3090254885Sdumbbell// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3091254885Sdumbbell// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3092254885Sdumbbell// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3093254885Sdumbbell// Bit 8 = 0 - no CV support= 1- CV is supported 3094254885Sdumbbell// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3095254885Sdumbbell// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 3096254885Sdumbbell// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 3097254885Sdumbbell// 3098254885Sdumbbell// 3099254885Sdumbbell 3100254885Sdumbbell/****************************************************************************/ 3101254885Sdumbbell/* Structure used in MclkSS_InfoTable */ 3102254885Sdumbbell/****************************************************************************/ 3103254885Sdumbbell// ucI2C_ConfigID 3104254885Sdumbbell// [7:0] - I2C LINE Associate ID 3105254885Sdumbbell// = 0 - no I2C 3106254885Sdumbbell// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3107254885Sdumbbell// = 0, [6:0]=SW assisted I2C ID 3108254885Sdumbbell// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3109254885Sdumbbell// = 2, HW engine for Multimedia use 3110254885Sdumbbell// = 3-7 Reserved for future I2C engines 3111254885Sdumbbell// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3112254885Sdumbbell 3113254885Sdumbbelltypedef struct _ATOM_I2C_ID_CONFIG 3114254885Sdumbbell{ 3115254885Sdumbbell#if ATOM_BIG_ENDIAN 3116254885Sdumbbell UCHAR bfHW_Capable:1; 3117254885Sdumbbell UCHAR bfHW_EngineID:3; 3118254885Sdumbbell UCHAR bfI2C_LineMux:4; 3119254885Sdumbbell#else 3120254885Sdumbbell UCHAR bfI2C_LineMux:4; 3121254885Sdumbbell UCHAR bfHW_EngineID:3; 3122254885Sdumbbell UCHAR bfHW_Capable:1; 3123254885Sdumbbell#endif 3124254885Sdumbbell}ATOM_I2C_ID_CONFIG; 3125254885Sdumbbell 3126254885Sdumbbelltypedef union _ATOM_I2C_ID_CONFIG_ACCESS 3127254885Sdumbbell{ 3128254885Sdumbbell ATOM_I2C_ID_CONFIG sbfAccess; 3129254885Sdumbbell UCHAR ucAccess; 3130254885Sdumbbell}ATOM_I2C_ID_CONFIG_ACCESS; 3131254885Sdumbbell 3132254885Sdumbbell 3133254885Sdumbbell/****************************************************************************/ 3134254885Sdumbbell// Structure used in GPIO_I2C_InfoTable 3135254885Sdumbbell/****************************************************************************/ 3136254885Sdumbbelltypedef struct _ATOM_GPIO_I2C_ASSIGMENT 3137254885Sdumbbell{ 3138254885Sdumbbell USHORT usClkMaskRegisterIndex; 3139254885Sdumbbell USHORT usClkEnRegisterIndex; 3140254885Sdumbbell USHORT usClkY_RegisterIndex; 3141254885Sdumbbell USHORT usClkA_RegisterIndex; 3142254885Sdumbbell USHORT usDataMaskRegisterIndex; 3143254885Sdumbbell USHORT usDataEnRegisterIndex; 3144254885Sdumbbell USHORT usDataY_RegisterIndex; 3145254885Sdumbbell USHORT usDataA_RegisterIndex; 3146254885Sdumbbell ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3147254885Sdumbbell UCHAR ucClkMaskShift; 3148254885Sdumbbell UCHAR ucClkEnShift; 3149254885Sdumbbell UCHAR ucClkY_Shift; 3150254885Sdumbbell UCHAR ucClkA_Shift; 3151254885Sdumbbell UCHAR ucDataMaskShift; 3152254885Sdumbbell UCHAR ucDataEnShift; 3153254885Sdumbbell UCHAR ucDataY_Shift; 3154254885Sdumbbell UCHAR ucDataA_Shift; 3155254885Sdumbbell UCHAR ucReserved1; 3156254885Sdumbbell UCHAR ucReserved2; 3157254885Sdumbbell}ATOM_GPIO_I2C_ASSIGMENT; 3158254885Sdumbbell 3159254885Sdumbbelltypedef struct _ATOM_GPIO_I2C_INFO 3160254885Sdumbbell{ 3161254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3162254885Sdumbbell ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3163254885Sdumbbell}ATOM_GPIO_I2C_INFO; 3164254885Sdumbbell 3165254885Sdumbbell/****************************************************************************/ 3166254885Sdumbbell// Common Structure used in other structures 3167254885Sdumbbell/****************************************************************************/ 3168254885Sdumbbell 3169254885Sdumbbell#ifndef _H2INC 3170254885Sdumbbell 3171254885Sdumbbell//Please don't add or expand this bitfield structure below, this one will retire soon.! 3172254885Sdumbbelltypedef struct _ATOM_MODE_MISC_INFO 3173254885Sdumbbell{ 3174254885Sdumbbell#if ATOM_BIG_ENDIAN 3175254885Sdumbbell USHORT Reserved:6; 3176254885Sdumbbell USHORT RGB888:1; 3177254885Sdumbbell USHORT DoubleClock:1; 3178254885Sdumbbell USHORT Interlace:1; 3179254885Sdumbbell USHORT CompositeSync:1; 3180254885Sdumbbell USHORT V_ReplicationBy2:1; 3181254885Sdumbbell USHORT H_ReplicationBy2:1; 3182254885Sdumbbell USHORT VerticalCutOff:1; 3183254885Sdumbbell USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3184254885Sdumbbell USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3185254885Sdumbbell USHORT HorizontalCutOff:1; 3186254885Sdumbbell#else 3187254885Sdumbbell USHORT HorizontalCutOff:1; 3188254885Sdumbbell USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3189254885Sdumbbell USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3190254885Sdumbbell USHORT VerticalCutOff:1; 3191254885Sdumbbell USHORT H_ReplicationBy2:1; 3192254885Sdumbbell USHORT V_ReplicationBy2:1; 3193254885Sdumbbell USHORT CompositeSync:1; 3194254885Sdumbbell USHORT Interlace:1; 3195254885Sdumbbell USHORT DoubleClock:1; 3196254885Sdumbbell USHORT RGB888:1; 3197254885Sdumbbell USHORT Reserved:6; 3198254885Sdumbbell#endif 3199254885Sdumbbell}ATOM_MODE_MISC_INFO; 3200254885Sdumbbell 3201254885Sdumbbelltypedef union _ATOM_MODE_MISC_INFO_ACCESS 3202254885Sdumbbell{ 3203254885Sdumbbell ATOM_MODE_MISC_INFO sbfAccess; 3204254885Sdumbbell USHORT usAccess; 3205254885Sdumbbell}ATOM_MODE_MISC_INFO_ACCESS; 3206254885Sdumbbell 3207254885Sdumbbell#else 3208254885Sdumbbell 3209254885Sdumbbelltypedef union _ATOM_MODE_MISC_INFO_ACCESS 3210254885Sdumbbell{ 3211254885Sdumbbell USHORT usAccess; 3212254885Sdumbbell}ATOM_MODE_MISC_INFO_ACCESS; 3213254885Sdumbbell 3214254885Sdumbbell#endif 3215254885Sdumbbell 3216254885Sdumbbell// usModeMiscInfo- 3217254885Sdumbbell#define ATOM_H_CUTOFF 0x01 3218254885Sdumbbell#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3219254885Sdumbbell#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3220254885Sdumbbell#define ATOM_V_CUTOFF 0x08 3221254885Sdumbbell#define ATOM_H_REPLICATIONBY2 0x10 3222254885Sdumbbell#define ATOM_V_REPLICATIONBY2 0x20 3223254885Sdumbbell#define ATOM_COMPOSITESYNC 0x40 3224254885Sdumbbell#define ATOM_INTERLACE 0x80 3225254885Sdumbbell#define ATOM_DOUBLE_CLOCK_MODE 0x100 3226254885Sdumbbell#define ATOM_RGB888_MODE 0x200 3227254885Sdumbbell 3228254885Sdumbbell//usRefreshRate- 3229254885Sdumbbell#define ATOM_REFRESH_43 43 3230254885Sdumbbell#define ATOM_REFRESH_47 47 3231254885Sdumbbell#define ATOM_REFRESH_56 56 3232254885Sdumbbell#define ATOM_REFRESH_60 60 3233254885Sdumbbell#define ATOM_REFRESH_65 65 3234254885Sdumbbell#define ATOM_REFRESH_70 70 3235254885Sdumbbell#define ATOM_REFRESH_72 72 3236254885Sdumbbell#define ATOM_REFRESH_75 75 3237254885Sdumbbell#define ATOM_REFRESH_85 85 3238254885Sdumbbell 3239254885Sdumbbell// ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3240254885Sdumbbell// Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3241254885Sdumbbell// 3242254885Sdumbbell// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3243254885Sdumbbell// = EDID_HA + EDID_HBL 3244254885Sdumbbell// VESA_HDISP = VESA_ACTIVE = EDID_HA 3245254885Sdumbbell// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3246254885Sdumbbell// = EDID_HA + EDID_HSO 3247254885Sdumbbell// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3248254885Sdumbbell// VESA_BORDER = EDID_BORDER 3249254885Sdumbbell 3250254885Sdumbbell/****************************************************************************/ 3251254885Sdumbbell// Structure used in SetCRTC_UsingDTDTimingTable 3252254885Sdumbbell/****************************************************************************/ 3253254885Sdumbbelltypedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3254254885Sdumbbell{ 3255254885Sdumbbell USHORT usH_Size; 3256254885Sdumbbell USHORT usH_Blanking_Time; 3257254885Sdumbbell USHORT usV_Size; 3258254885Sdumbbell USHORT usV_Blanking_Time; 3259254885Sdumbbell USHORT usH_SyncOffset; 3260254885Sdumbbell USHORT usH_SyncWidth; 3261254885Sdumbbell USHORT usV_SyncOffset; 3262254885Sdumbbell USHORT usV_SyncWidth; 3263254885Sdumbbell ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3264254885Sdumbbell UCHAR ucH_Border; // From DFP EDID 3265254885Sdumbbell UCHAR ucV_Border; 3266254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3267254885Sdumbbell UCHAR ucPadding[3]; 3268254885Sdumbbell}SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3269254885Sdumbbell 3270254885Sdumbbell/****************************************************************************/ 3271254885Sdumbbell// Structure used in SetCRTC_TimingTable 3272254885Sdumbbell/****************************************************************************/ 3273254885Sdumbbelltypedef struct _SET_CRTC_TIMING_PARAMETERS 3274254885Sdumbbell{ 3275254885Sdumbbell USHORT usH_Total; // horizontal total 3276254885Sdumbbell USHORT usH_Disp; // horizontal display 3277254885Sdumbbell USHORT usH_SyncStart; // horozontal Sync start 3278254885Sdumbbell USHORT usH_SyncWidth; // horizontal Sync width 3279254885Sdumbbell USHORT usV_Total; // vertical total 3280254885Sdumbbell USHORT usV_Disp; // vertical display 3281254885Sdumbbell USHORT usV_SyncStart; // vertical Sync start 3282254885Sdumbbell USHORT usV_SyncWidth; // vertical Sync width 3283254885Sdumbbell ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3284254885Sdumbbell UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3285254885Sdumbbell UCHAR ucOverscanRight; // right 3286254885Sdumbbell UCHAR ucOverscanLeft; // left 3287254885Sdumbbell UCHAR ucOverscanBottom; // bottom 3288254885Sdumbbell UCHAR ucOverscanTop; // top 3289254885Sdumbbell UCHAR ucReserved; 3290254885Sdumbbell}SET_CRTC_TIMING_PARAMETERS; 3291254885Sdumbbell#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3292254885Sdumbbell 3293254885Sdumbbell/****************************************************************************/ 3294254885Sdumbbell// Structure used in StandardVESA_TimingTable 3295254885Sdumbbell// AnalogTV_InfoTable 3296254885Sdumbbell// ComponentVideoInfoTable 3297254885Sdumbbell/****************************************************************************/ 3298254885Sdumbbelltypedef struct _ATOM_MODE_TIMING 3299254885Sdumbbell{ 3300254885Sdumbbell USHORT usCRTC_H_Total; 3301254885Sdumbbell USHORT usCRTC_H_Disp; 3302254885Sdumbbell USHORT usCRTC_H_SyncStart; 3303254885Sdumbbell USHORT usCRTC_H_SyncWidth; 3304254885Sdumbbell USHORT usCRTC_V_Total; 3305254885Sdumbbell USHORT usCRTC_V_Disp; 3306254885Sdumbbell USHORT usCRTC_V_SyncStart; 3307254885Sdumbbell USHORT usCRTC_V_SyncWidth; 3308254885Sdumbbell USHORT usPixelClock; //in 10Khz unit 3309254885Sdumbbell ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3310254885Sdumbbell USHORT usCRTC_OverscanRight; 3311254885Sdumbbell USHORT usCRTC_OverscanLeft; 3312254885Sdumbbell USHORT usCRTC_OverscanBottom; 3313254885Sdumbbell USHORT usCRTC_OverscanTop; 3314254885Sdumbbell USHORT usReserve; 3315254885Sdumbbell UCHAR ucInternalModeNumber; 3316254885Sdumbbell UCHAR ucRefreshRate; 3317254885Sdumbbell}ATOM_MODE_TIMING; 3318254885Sdumbbell 3319254885Sdumbbelltypedef struct _ATOM_DTD_FORMAT 3320254885Sdumbbell{ 3321254885Sdumbbell USHORT usPixClk; 3322254885Sdumbbell USHORT usHActive; 3323254885Sdumbbell USHORT usHBlanking_Time; 3324254885Sdumbbell USHORT usVActive; 3325254885Sdumbbell USHORT usVBlanking_Time; 3326254885Sdumbbell USHORT usHSyncOffset; 3327254885Sdumbbell USHORT usHSyncWidth; 3328254885Sdumbbell USHORT usVSyncOffset; 3329254885Sdumbbell USHORT usVSyncWidth; 3330254885Sdumbbell USHORT usImageHSize; 3331254885Sdumbbell USHORT usImageVSize; 3332254885Sdumbbell UCHAR ucHBorder; 3333254885Sdumbbell UCHAR ucVBorder; 3334254885Sdumbbell ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3335254885Sdumbbell UCHAR ucInternalModeNumber; 3336254885Sdumbbell UCHAR ucRefreshRate; 3337254885Sdumbbell}ATOM_DTD_FORMAT; 3338254885Sdumbbell 3339254885Sdumbbell/****************************************************************************/ 3340254885Sdumbbell// Structure used in LVDS_InfoTable 3341254885Sdumbbell// * Need a document to describe this table 3342254885Sdumbbell/****************************************************************************/ 3343254885Sdumbbell#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3344254885Sdumbbell#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3345254885Sdumbbell#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3346254885Sdumbbell#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3347254885Sdumbbell 3348254885Sdumbbell//ucTableFormatRevision=1 3349254885Sdumbbell//ucTableContentRevision=1 3350254885Sdumbbelltypedef struct _ATOM_LVDS_INFO 3351254885Sdumbbell{ 3352254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3353254885Sdumbbell ATOM_DTD_FORMAT sLCDTiming; 3354254885Sdumbbell USHORT usModePatchTableOffset; 3355254885Sdumbbell USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3356254885Sdumbbell USHORT usOffDelayInMs; 3357254885Sdumbbell UCHAR ucPowerSequenceDigOntoDEin10Ms; 3358254885Sdumbbell UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3359254885Sdumbbell UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3360254885Sdumbbell // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3361254885Sdumbbell // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3362254885Sdumbbell // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3363254885Sdumbbell UCHAR ucPanelDefaultRefreshRate; 3364254885Sdumbbell UCHAR ucPanelIdentification; 3365254885Sdumbbell UCHAR ucSS_Id; 3366254885Sdumbbell}ATOM_LVDS_INFO; 3367254885Sdumbbell 3368254885Sdumbbell//ucTableFormatRevision=1 3369254885Sdumbbell//ucTableContentRevision=2 3370254885Sdumbbelltypedef struct _ATOM_LVDS_INFO_V12 3371254885Sdumbbell{ 3372254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3373254885Sdumbbell ATOM_DTD_FORMAT sLCDTiming; 3374254885Sdumbbell USHORT usExtInfoTableOffset; 3375254885Sdumbbell USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3376254885Sdumbbell USHORT usOffDelayInMs; 3377254885Sdumbbell UCHAR ucPowerSequenceDigOntoDEin10Ms; 3378254885Sdumbbell UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3379254885Sdumbbell UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3380254885Sdumbbell // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3381254885Sdumbbell // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3382254885Sdumbbell // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3383254885Sdumbbell UCHAR ucPanelDefaultRefreshRate; 3384254885Sdumbbell UCHAR ucPanelIdentification; 3385254885Sdumbbell UCHAR ucSS_Id; 3386254885Sdumbbell USHORT usLCDVenderID; 3387254885Sdumbbell USHORT usLCDProductID; 3388254885Sdumbbell UCHAR ucLCDPanel_SpecialHandlingCap; 3389254885Sdumbbell UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3390254885Sdumbbell UCHAR ucReserved[2]; 3391254885Sdumbbell}ATOM_LVDS_INFO_V12; 3392254885Sdumbbell 3393254885Sdumbbell//Definitions for ucLCDPanel_SpecialHandlingCap: 3394254885Sdumbbell 3395254885Sdumbbell//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3396254885Sdumbbell//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3397254885Sdumbbell#define LCDPANEL_CAP_READ_EDID 0x1 3398254885Sdumbbell 3399254885Sdumbbell//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3400254885Sdumbbell//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3401254885Sdumbbell//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3402254885Sdumbbell#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3403254885Sdumbbell 3404254885Sdumbbell//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3405254885Sdumbbell#define LCDPANEL_CAP_eDP 0x4 3406254885Sdumbbell 3407254885Sdumbbell 3408254885Sdumbbell//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3409254885Sdumbbell//Bit 6 5 4 3410254885Sdumbbell // 0 0 0 - Color bit depth is undefined 3411254885Sdumbbell // 0 0 1 - 6 Bits per Primary Color 3412254885Sdumbbell // 0 1 0 - 8 Bits per Primary Color 3413254885Sdumbbell // 0 1 1 - 10 Bits per Primary Color 3414254885Sdumbbell // 1 0 0 - 12 Bits per Primary Color 3415254885Sdumbbell // 1 0 1 - 14 Bits per Primary Color 3416254885Sdumbbell // 1 1 0 - 16 Bits per Primary Color 3417254885Sdumbbell // 1 1 1 - Reserved 3418254885Sdumbbell 3419254885Sdumbbell#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3420254885Sdumbbell 3421254885Sdumbbell// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3422254885Sdumbbell#define PANEL_RANDOM_DITHER 0x80 3423254885Sdumbbell#define PANEL_RANDOM_DITHER_MASK 0x80 3424254885Sdumbbell 3425254885Sdumbbell#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3426254885Sdumbbell 3427254885Sdumbbell/****************************************************************************/ 3428254885Sdumbbell// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3429254885Sdumbbell// ASIC Families: NI 3430254885Sdumbbell// ucTableFormatRevision=1 3431254885Sdumbbell// ucTableContentRevision=3 3432254885Sdumbbell/****************************************************************************/ 3433254885Sdumbbelltypedef struct _ATOM_LCD_INFO_V13 3434254885Sdumbbell{ 3435254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3436254885Sdumbbell ATOM_DTD_FORMAT sLCDTiming; 3437254885Sdumbbell USHORT usExtInfoTableOffset; 3438254885Sdumbbell USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3439254885Sdumbbell ULONG ulReserved0; 3440254885Sdumbbell UCHAR ucLCD_Misc; // Reorganized in V13 3441254885Sdumbbell // Bit0: {=0:single, =1:dual}, 3442254885Sdumbbell // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3443254885Sdumbbell // Bit3:2: {Grey level} 3444254885Sdumbbell // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3445254885Sdumbbell // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3446254885Sdumbbell UCHAR ucPanelDefaultRefreshRate; 3447254885Sdumbbell UCHAR ucPanelIdentification; 3448254885Sdumbbell UCHAR ucSS_Id; 3449254885Sdumbbell USHORT usLCDVenderID; 3450254885Sdumbbell USHORT usLCDProductID; 3451254885Sdumbbell UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3452254885Sdumbbell // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3453254885Sdumbbell // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3454254885Sdumbbell // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3455254885Sdumbbell // Bit7-3: Reserved 3456254885Sdumbbell UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3457254885Sdumbbell USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3458254885Sdumbbell 3459254885Sdumbbell UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3460254885Sdumbbell UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3461254885Sdumbbell UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3462254885Sdumbbell UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3463254885Sdumbbell 3464254885Sdumbbell UCHAR ucOffDelay_in4Ms; 3465254885Sdumbbell UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3466254885Sdumbbell UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3467254885Sdumbbell UCHAR ucReserved1; 3468254885Sdumbbell 3469254885Sdumbbell UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3470254885Sdumbbell UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3471254885Sdumbbell UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3472254885Sdumbbell UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3473254885Sdumbbell 3474254885Sdumbbell USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3475254885Sdumbbell UCHAR uceDPToLVDSRxId; 3476254885Sdumbbell UCHAR ucLcdReservd; 3477254885Sdumbbell ULONG ulReserved[2]; 3478254885Sdumbbell}ATOM_LCD_INFO_V13; 3479254885Sdumbbell 3480254885Sdumbbell#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3481254885Sdumbbell 3482254885Sdumbbell//Definitions for ucLCD_Misc 3483254885Sdumbbell#define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3484254885Sdumbbell#define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3485254885Sdumbbell#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3486254885Sdumbbell#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3487254885Sdumbbell#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3488254885Sdumbbell#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3489254885Sdumbbell#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3490254885Sdumbbell 3491254885Sdumbbell//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3492254885Sdumbbell//Bit 6 5 4 3493254885Sdumbbell // 0 0 0 - Color bit depth is undefined 3494254885Sdumbbell // 0 0 1 - 6 Bits per Primary Color 3495254885Sdumbbell // 0 1 0 - 8 Bits per Primary Color 3496254885Sdumbbell // 0 1 1 - 10 Bits per Primary Color 3497254885Sdumbbell // 1 0 0 - 12 Bits per Primary Color 3498254885Sdumbbell // 1 0 1 - 14 Bits per Primary Color 3499254885Sdumbbell // 1 1 0 - 16 Bits per Primary Color 3500254885Sdumbbell // 1 1 1 - Reserved 3501254885Sdumbbell 3502254885Sdumbbell//Definitions for ucLCDPanel_SpecialHandlingCap: 3503254885Sdumbbell 3504254885Sdumbbell//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3505254885Sdumbbell//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3506254885Sdumbbell#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3507254885Sdumbbell 3508254885Sdumbbell//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3509254885Sdumbbell//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3510254885Sdumbbell//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3511254885Sdumbbell#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3512254885Sdumbbell 3513254885Sdumbbell//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3514254885Sdumbbell#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3515254885Sdumbbell 3516254885Sdumbbell//uceDPToLVDSRxId 3517254885Sdumbbell#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3518254885Sdumbbell#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3519254885Sdumbbell#define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init 3520254885Sdumbbell 3521254885Sdumbbelltypedef struct _ATOM_PATCH_RECORD_MODE 3522254885Sdumbbell{ 3523254885Sdumbbell UCHAR ucRecordType; 3524254885Sdumbbell USHORT usHDisp; 3525254885Sdumbbell USHORT usVDisp; 3526254885Sdumbbell}ATOM_PATCH_RECORD_MODE; 3527254885Sdumbbell 3528254885Sdumbbelltypedef struct _ATOM_LCD_RTS_RECORD 3529254885Sdumbbell{ 3530254885Sdumbbell UCHAR ucRecordType; 3531254885Sdumbbell UCHAR ucRTSValue; 3532254885Sdumbbell}ATOM_LCD_RTS_RECORD; 3533254885Sdumbbell 3534254885Sdumbbell//!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3535254885Sdumbbell// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3536254885Sdumbbelltypedef struct _ATOM_LCD_MODE_CONTROL_CAP 3537254885Sdumbbell{ 3538254885Sdumbbell UCHAR ucRecordType; 3539254885Sdumbbell USHORT usLCDCap; 3540254885Sdumbbell}ATOM_LCD_MODE_CONTROL_CAP; 3541254885Sdumbbell 3542254885Sdumbbell#define LCD_MODE_CAP_BL_OFF 1 3543254885Sdumbbell#define LCD_MODE_CAP_CRTC_OFF 2 3544254885Sdumbbell#define LCD_MODE_CAP_PANEL_OFF 4 3545254885Sdumbbell 3546254885Sdumbbelltypedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3547254885Sdumbbell{ 3548254885Sdumbbell UCHAR ucRecordType; 3549254885Sdumbbell UCHAR ucFakeEDIDLength; 3550254885Sdumbbell UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3551254885Sdumbbell} ATOM_FAKE_EDID_PATCH_RECORD; 3552254885Sdumbbell 3553254885Sdumbbelltypedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3554254885Sdumbbell{ 3555254885Sdumbbell UCHAR ucRecordType; 3556254885Sdumbbell USHORT usHSize; 3557254885Sdumbbell USHORT usVSize; 3558254885Sdumbbell}ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3559254885Sdumbbell 3560254885Sdumbbell#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3561254885Sdumbbell#define LCD_RTS_RECORD_TYPE 2 3562254885Sdumbbell#define LCD_CAP_RECORD_TYPE 3 3563254885Sdumbbell#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3564254885Sdumbbell#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3565254885Sdumbbell#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3566254885Sdumbbell#define ATOM_RECORD_END_TYPE 0xFF 3567254885Sdumbbell 3568254885Sdumbbell/****************************Spread Spectrum Info Table Definitions **********************/ 3569254885Sdumbbell 3570254885Sdumbbell//ucTableFormatRevision=1 3571254885Sdumbbell//ucTableContentRevision=2 3572254885Sdumbbelltypedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3573254885Sdumbbell{ 3574254885Sdumbbell USHORT usSpreadSpectrumPercentage; 3575254885Sdumbbell UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3576254885Sdumbbell UCHAR ucSS_Step; 3577254885Sdumbbell UCHAR ucSS_Delay; 3578254885Sdumbbell UCHAR ucSS_Id; 3579254885Sdumbbell UCHAR ucRecommendedRef_Div; 3580254885Sdumbbell UCHAR ucSS_Range; //it was reserved for V11 3581254885Sdumbbell}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3582254885Sdumbbell 3583254885Sdumbbell#define ATOM_MAX_SS_ENTRY 16 3584254885Sdumbbell#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3585254885Sdumbbell#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3586254885Sdumbbell#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3587254885Sdumbbell#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3588254885Sdumbbell 3589254885Sdumbbell 3590254885Sdumbbell#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3591254885Sdumbbell#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3592254885Sdumbbell#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3593254885Sdumbbell#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3594254885Sdumbbell#define ATOM_INTERNAL_SS_MASK 0x00000000 3595254885Sdumbbell#define ATOM_EXTERNAL_SS_MASK 0x00000002 3596254885Sdumbbell#define EXEC_SS_STEP_SIZE_SHIFT 2 3597254885Sdumbbell#define EXEC_SS_DELAY_SHIFT 4 3598254885Sdumbbell#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3599254885Sdumbbell 3600254885Sdumbbelltypedef struct _ATOM_SPREAD_SPECTRUM_INFO 3601254885Sdumbbell{ 3602254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3603254885Sdumbbell ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3604254885Sdumbbell}ATOM_SPREAD_SPECTRUM_INFO; 3605254885Sdumbbell 3606254885Sdumbbell/****************************************************************************/ 3607254885Sdumbbell// Structure used in AnalogTV_InfoTable (Top level) 3608254885Sdumbbell/****************************************************************************/ 3609254885Sdumbbell//ucTVBootUpDefaultStd definition: 3610254885Sdumbbell 3611254885Sdumbbell//ATOM_TV_NTSC 1 3612254885Sdumbbell//ATOM_TV_NTSCJ 2 3613254885Sdumbbell//ATOM_TV_PAL 3 3614254885Sdumbbell//ATOM_TV_PALM 4 3615254885Sdumbbell//ATOM_TV_PALCN 5 3616254885Sdumbbell//ATOM_TV_PALN 6 3617254885Sdumbbell//ATOM_TV_PAL60 7 3618254885Sdumbbell//ATOM_TV_SECAM 8 3619254885Sdumbbell 3620254885Sdumbbell//ucTVSupportedStd definition: 3621254885Sdumbbell#define NTSC_SUPPORT 0x1 3622254885Sdumbbell#define NTSCJ_SUPPORT 0x2 3623254885Sdumbbell 3624254885Sdumbbell#define PAL_SUPPORT 0x4 3625254885Sdumbbell#define PALM_SUPPORT 0x8 3626254885Sdumbbell#define PALCN_SUPPORT 0x10 3627254885Sdumbbell#define PALN_SUPPORT 0x20 3628254885Sdumbbell#define PAL60_SUPPORT 0x40 3629254885Sdumbbell#define SECAM_SUPPORT 0x80 3630254885Sdumbbell 3631254885Sdumbbell#define MAX_SUPPORTED_TV_TIMING 2 3632254885Sdumbbell 3633254885Sdumbbelltypedef struct _ATOM_ANALOG_TV_INFO 3634254885Sdumbbell{ 3635254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3636254885Sdumbbell UCHAR ucTV_SupportedStandard; 3637254885Sdumbbell UCHAR ucTV_BootUpDefaultStandard; 3638254885Sdumbbell UCHAR ucExt_TV_ASIC_ID; 3639254885Sdumbbell UCHAR ucExt_TV_ASIC_SlaveAddr; 3640254885Sdumbbell /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 3641254885Sdumbbell ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3642254885Sdumbbell}ATOM_ANALOG_TV_INFO; 3643254885Sdumbbell 3644254885Sdumbbell#define MAX_SUPPORTED_TV_TIMING_V1_2 3 3645254885Sdumbbell 3646254885Sdumbbelltypedef struct _ATOM_ANALOG_TV_INFO_V1_2 3647254885Sdumbbell{ 3648254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3649254885Sdumbbell UCHAR ucTV_SupportedStandard; 3650254885Sdumbbell UCHAR ucTV_BootUpDefaultStandard; 3651254885Sdumbbell UCHAR ucExt_TV_ASIC_ID; 3652254885Sdumbbell UCHAR ucExt_TV_ASIC_SlaveAddr; 3653254885Sdumbbell ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 3654254885Sdumbbell}ATOM_ANALOG_TV_INFO_V1_2; 3655254885Sdumbbell 3656254885Sdumbbelltypedef struct _ATOM_DPCD_INFO 3657254885Sdumbbell{ 3658254885Sdumbbell UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3659254885Sdumbbell UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3660254885Sdumbbell UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3661254885Sdumbbell UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3662254885Sdumbbell}ATOM_DPCD_INFO; 3663254885Sdumbbell 3664254885Sdumbbell#define ATOM_DPCD_MAX_LANE_MASK 0x1F 3665254885Sdumbbell 3666254885Sdumbbell/**************************************************************************/ 3667254885Sdumbbell// VRAM usage and their defintions 3668254885Sdumbbell 3669254885Sdumbbell// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3670254885Sdumbbell// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3671254885Sdumbbell// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3672254885Sdumbbell// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3673254885Sdumbbell// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3674254885Sdumbbell 3675254885Sdumbbell#ifndef VESA_MEMORY_IN_64K_BLOCK 3676254885Sdumbbell#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3677254885Sdumbbell#endif 3678254885Sdumbbell 3679254885Sdumbbell#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3680254885Sdumbbell#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3681254885Sdumbbell#define ATOM_HWICON_INFOTABLE_SIZE 32 3682254885Sdumbbell#define MAX_DTD_MODE_IN_VRAM 6 3683254885Sdumbbell#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3684254885Sdumbbell#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3685254885Sdumbbell//20 bytes for Encoder Type and DPCD in STD EDID area 3686254885Sdumbbell#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3687254885Sdumbbell#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3688254885Sdumbbell 3689254885Sdumbbell#define ATOM_HWICON1_SURFACE_ADDR 0 3690254885Sdumbbell#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3691254885Sdumbbell#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3692254885Sdumbbell#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3693254885Sdumbbell#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3694254885Sdumbbell#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3695254885Sdumbbell 3696254885Sdumbbell#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3697254885Sdumbbell#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3698254885Sdumbbell#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3699254885Sdumbbell 3700254885Sdumbbell#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3701254885Sdumbbell 3702254885Sdumbbell#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3703254885Sdumbbell#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3704254885Sdumbbell#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3705254885Sdumbbell 3706254885Sdumbbell#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3707254885Sdumbbell#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3708254885Sdumbbell#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3709254885Sdumbbell 3710254885Sdumbbell#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3711254885Sdumbbell#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3712254885Sdumbbell#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3713254885Sdumbbell 3714254885Sdumbbell#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3715254885Sdumbbell#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3716254885Sdumbbell#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3717254885Sdumbbell 3718254885Sdumbbell#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3719254885Sdumbbell#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3720254885Sdumbbell#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3721254885Sdumbbell 3722254885Sdumbbell#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3723254885Sdumbbell#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3724254885Sdumbbell#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3725254885Sdumbbell 3726254885Sdumbbell#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3727254885Sdumbbell#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3728254885Sdumbbell#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3729254885Sdumbbell 3730254885Sdumbbell#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3731254885Sdumbbell#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3732254885Sdumbbell#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3733254885Sdumbbell 3734254885Sdumbbell#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3735254885Sdumbbell#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3736254885Sdumbbell#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3737254885Sdumbbell 3738254885Sdumbbell#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3739254885Sdumbbell 3740254885Sdumbbell#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3741254885Sdumbbell#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3742254885Sdumbbell 3743254885Sdumbbell//The size below is in Kb! 3744254885Sdumbbell#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3745254885Sdumbbell 3746254885Sdumbbell#define ATOM_VRAM_RESERVE_V2_SIZE 32 3747254885Sdumbbell 3748254885Sdumbbell#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3749254885Sdumbbell#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3750254885Sdumbbell#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3751254885Sdumbbell#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3752254885Sdumbbell 3753254885Sdumbbell/***********************************************************************************/ 3754254885Sdumbbell// Structure used in VRAM_UsageByFirmwareTable 3755254885Sdumbbell// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3756254885Sdumbbell// at running time. 3757254885Sdumbbell// note2: From RV770, the memory is more than 32bit addressable, so we will change 3758254885Sdumbbell// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3759254885Sdumbbell// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3760254885Sdumbbell// (in offset to start of memory address) is KB aligned instead of byte aligend. 3761254885Sdumbbell/***********************************************************************************/ 3762254885Sdumbbell// Note3: 3763254885Sdumbbell/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 3764254885Sdumbbellfor CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3765254885Sdumbbell 3766254885SdumbbellIf (ulStartAddrUsedByFirmware!=0) 3767254885SdumbbellFBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3768254885SdumbbellReserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3769254885Sdumbbellelse //Non VGA case 3770254885Sdumbbell if (FB_Size<=2Gb) 3771254885Sdumbbell FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3772254885Sdumbbell else 3773254885Sdumbbell FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3774254885Sdumbbell 3775254885SdumbbellCAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3776254885Sdumbbell 3777254885Sdumbbell/***********************************************************************************/ 3778254885Sdumbbell#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3779254885Sdumbbell 3780254885Sdumbbelltypedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3781254885Sdumbbell{ 3782254885Sdumbbell ULONG ulStartAddrUsedByFirmware; 3783254885Sdumbbell USHORT usFirmwareUseInKb; 3784254885Sdumbbell USHORT usReserved; 3785254885Sdumbbell}ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3786254885Sdumbbell 3787254885Sdumbbelltypedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3788254885Sdumbbell{ 3789254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3790254885Sdumbbell ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3791254885Sdumbbell}ATOM_VRAM_USAGE_BY_FIRMWARE; 3792254885Sdumbbell 3793254885Sdumbbell// change verion to 1.5, when allow driver to allocate the vram area for command table access. 3794254885Sdumbbelltypedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3795254885Sdumbbell{ 3796254885Sdumbbell ULONG ulStartAddrUsedByFirmware; 3797254885Sdumbbell USHORT usFirmwareUseInKb; 3798254885Sdumbbell USHORT usFBUsedByDrvInKb; 3799254885Sdumbbell}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3800254885Sdumbbell 3801254885Sdumbbelltypedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3802254885Sdumbbell{ 3803254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3804254885Sdumbbell ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3805254885Sdumbbell}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3806254885Sdumbbell 3807254885Sdumbbell/****************************************************************************/ 3808254885Sdumbbell// Structure used in GPIO_Pin_LUTTable 3809254885Sdumbbell/****************************************************************************/ 3810254885Sdumbbelltypedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3811254885Sdumbbell{ 3812254885Sdumbbell USHORT usGpioPin_AIndex; 3813254885Sdumbbell UCHAR ucGpioPinBitShift; 3814254885Sdumbbell UCHAR ucGPIO_ID; 3815254885Sdumbbell}ATOM_GPIO_PIN_ASSIGNMENT; 3816254885Sdumbbell 3817254885Sdumbbelltypedef struct _ATOM_GPIO_PIN_LUT 3818254885Sdumbbell{ 3819254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3820254885Sdumbbell ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 3821254885Sdumbbell}ATOM_GPIO_PIN_LUT; 3822254885Sdumbbell 3823254885Sdumbbell/****************************************************************************/ 3824254885Sdumbbell// Structure used in ComponentVideoInfoTable 3825254885Sdumbbell/****************************************************************************/ 3826254885Sdumbbell#define GPIO_PIN_ACTIVE_HIGH 0x1 3827254885Sdumbbell 3828254885Sdumbbell#define MAX_SUPPORTED_CV_STANDARDS 5 3829254885Sdumbbell 3830254885Sdumbbell// definitions for ATOM_D_INFO.ucSettings 3831254885Sdumbbell#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 3832254885Sdumbbell#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 3833254885Sdumbbell#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3834254885Sdumbbell 3835254885Sdumbbelltypedef struct _ATOM_GPIO_INFO 3836254885Sdumbbell{ 3837254885Sdumbbell USHORT usAOffset; 3838254885Sdumbbell UCHAR ucSettings; 3839254885Sdumbbell UCHAR ucReserved; 3840254885Sdumbbell}ATOM_GPIO_INFO; 3841254885Sdumbbell 3842254885Sdumbbell// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3843254885Sdumbbell#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3844254885Sdumbbell 3845254885Sdumbbell// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3846254885Sdumbbell#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3847254885Sdumbbell#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3848254885Sdumbbell 3849254885Sdumbbell// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3850254885Sdumbbell//Line 3 out put 5V. 3851254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3852254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3853254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3854254885Sdumbbell 3855254885Sdumbbell//Line 3 out put 2.2V 3856254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3857254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3858254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3859254885Sdumbbell 3860254885Sdumbbell//Line 3 out put 0V 3861254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3862254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3863254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3864254885Sdumbbell 3865254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3866254885Sdumbbell 3867254885Sdumbbell#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3868254885Sdumbbell 3869254885Sdumbbell//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3870254885Sdumbbell#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3871254885Sdumbbell#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3872254885Sdumbbell 3873254885Sdumbbell 3874254885Sdumbbelltypedef struct _ATOM_COMPONENT_VIDEO_INFO 3875254885Sdumbbell{ 3876254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3877254885Sdumbbell USHORT usMask_PinRegisterIndex; 3878254885Sdumbbell USHORT usEN_PinRegisterIndex; 3879254885Sdumbbell USHORT usY_PinRegisterIndex; 3880254885Sdumbbell USHORT usA_PinRegisterIndex; 3881254885Sdumbbell UCHAR ucBitShift; 3882254885Sdumbbell UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3883254885Sdumbbell ATOM_DTD_FORMAT sReserved; // must be zeroed out 3884254885Sdumbbell UCHAR ucMiscInfo; 3885254885Sdumbbell UCHAR uc480i; 3886254885Sdumbbell UCHAR uc480p; 3887254885Sdumbbell UCHAR uc720p; 3888254885Sdumbbell UCHAR uc1080i; 3889254885Sdumbbell UCHAR ucLetterBoxMode; 3890254885Sdumbbell UCHAR ucReserved[3]; 3891254885Sdumbbell UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3892254885Sdumbbell ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3893254885Sdumbbell ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3894254885Sdumbbell}ATOM_COMPONENT_VIDEO_INFO; 3895254885Sdumbbell 3896254885Sdumbbell//ucTableFormatRevision=2 3897254885Sdumbbell//ucTableContentRevision=1 3898254885Sdumbbelltypedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3899254885Sdumbbell{ 3900254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3901254885Sdumbbell UCHAR ucMiscInfo; 3902254885Sdumbbell UCHAR uc480i; 3903254885Sdumbbell UCHAR uc480p; 3904254885Sdumbbell UCHAR uc720p; 3905254885Sdumbbell UCHAR uc1080i; 3906254885Sdumbbell UCHAR ucReserved; 3907254885Sdumbbell UCHAR ucLetterBoxMode; 3908254885Sdumbbell UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3909254885Sdumbbell ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3910254885Sdumbbell ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3911254885Sdumbbell}ATOM_COMPONENT_VIDEO_INFO_V21; 3912254885Sdumbbell 3913254885Sdumbbell#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3914254885Sdumbbell 3915254885Sdumbbell/****************************************************************************/ 3916254885Sdumbbell// Structure used in object_InfoTable 3917254885Sdumbbell/****************************************************************************/ 3918254885Sdumbbelltypedef struct _ATOM_OBJECT_HEADER 3919254885Sdumbbell{ 3920254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3921254885Sdumbbell USHORT usDeviceSupport; 3922254885Sdumbbell USHORT usConnectorObjectTableOffset; 3923254885Sdumbbell USHORT usRouterObjectTableOffset; 3924254885Sdumbbell USHORT usEncoderObjectTableOffset; 3925254885Sdumbbell USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3926254885Sdumbbell USHORT usDisplayPathTableOffset; 3927254885Sdumbbell}ATOM_OBJECT_HEADER; 3928254885Sdumbbell 3929254885Sdumbbelltypedef struct _ATOM_OBJECT_HEADER_V3 3930254885Sdumbbell{ 3931254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 3932254885Sdumbbell USHORT usDeviceSupport; 3933254885Sdumbbell USHORT usConnectorObjectTableOffset; 3934254885Sdumbbell USHORT usRouterObjectTableOffset; 3935254885Sdumbbell USHORT usEncoderObjectTableOffset; 3936254885Sdumbbell USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3937254885Sdumbbell USHORT usDisplayPathTableOffset; 3938254885Sdumbbell USHORT usMiscObjectTableOffset; 3939254885Sdumbbell}ATOM_OBJECT_HEADER_V3; 3940254885Sdumbbell 3941254885Sdumbbelltypedef struct _ATOM_DISPLAY_OBJECT_PATH 3942254885Sdumbbell{ 3943254885Sdumbbell USHORT usDeviceTag; //supported device 3944254885Sdumbbell USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3945254885Sdumbbell USHORT usConnObjectId; //Connector Object ID 3946254885Sdumbbell USHORT usGPUObjectId; //GPU ID 3947254885Sdumbbell USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 3948254885Sdumbbell}ATOM_DISPLAY_OBJECT_PATH; 3949254885Sdumbbell 3950254885Sdumbbelltypedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 3951254885Sdumbbell{ 3952254885Sdumbbell USHORT usDeviceTag; //supported device 3953254885Sdumbbell USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3954254885Sdumbbell USHORT usConnObjectId; //Connector Object ID 3955254885Sdumbbell USHORT usGPUObjectId; //GPU ID 3956254885Sdumbbell USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 3957254885Sdumbbell}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 3958254885Sdumbbell 3959254885Sdumbbelltypedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 3960254885Sdumbbell{ 3961254885Sdumbbell UCHAR ucNumOfDispPath; 3962254885Sdumbbell UCHAR ucVersion; 3963254885Sdumbbell UCHAR ucPadding[2]; 3964254885Sdumbbell ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 3965254885Sdumbbell}ATOM_DISPLAY_OBJECT_PATH_TABLE; 3966254885Sdumbbell 3967254885Sdumbbell 3968254885Sdumbbelltypedef struct _ATOM_OBJECT //each object has this structure 3969254885Sdumbbell{ 3970254885Sdumbbell USHORT usObjectID; 3971254885Sdumbbell USHORT usSrcDstTableOffset; 3972254885Sdumbbell USHORT usRecordOffset; //this pointing to a bunch of records defined below 3973254885Sdumbbell USHORT usReserved; 3974254885Sdumbbell}ATOM_OBJECT; 3975254885Sdumbbell 3976254885Sdumbbelltypedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 3977254885Sdumbbell{ 3978254885Sdumbbell UCHAR ucNumberOfObjects; 3979254885Sdumbbell UCHAR ucPadding[3]; 3980254885Sdumbbell ATOM_OBJECT asObjects[1]; 3981254885Sdumbbell}ATOM_OBJECT_TABLE; 3982254885Sdumbbell 3983254885Sdumbbelltypedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 3984254885Sdumbbell{ 3985254885Sdumbbell UCHAR ucNumberOfSrc; 3986254885Sdumbbell USHORT usSrcObjectID[1]; 3987254885Sdumbbell UCHAR ucNumberOfDst; 3988254885Sdumbbell USHORT usDstObjectID[1]; 3989254885Sdumbbell}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 3990254885Sdumbbell 3991254885Sdumbbell 3992254885Sdumbbell//Two definitions below are for OPM on MXM module designs 3993254885Sdumbbell 3994254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_0 0 3995254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_1 1 3996254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_2 2 3997254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_3 3 3998254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_4 4 3999254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_5 5 4000254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_6 6 4001254885Sdumbbell#define EXT_HPDPIN_LUTINDEX_7 7 4002254885Sdumbbell#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4003254885Sdumbbell 4004254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_0 0 4005254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_1 1 4006254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_2 2 4007254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_3 3 4008254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_4 4 4009254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_5 5 4010254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_6 6 4011254885Sdumbbell#define EXT_AUXDDC_LUTINDEX_7 7 4012254885Sdumbbell#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4013254885Sdumbbell 4014254885Sdumbbell//ucChannelMapping are defined as following 4015254885Sdumbbell//for DP connector, eDP, DP to VGA/LVDS 4016254885Sdumbbell//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4017254885Sdumbbell//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4018254885Sdumbbell//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4019254885Sdumbbell//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4020254885Sdumbbelltypedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4021254885Sdumbbell{ 4022254885Sdumbbell#if ATOM_BIG_ENDIAN 4023254885Sdumbbell UCHAR ucDP_Lane3_Source:2; 4024254885Sdumbbell UCHAR ucDP_Lane2_Source:2; 4025254885Sdumbbell UCHAR ucDP_Lane1_Source:2; 4026254885Sdumbbell UCHAR ucDP_Lane0_Source:2; 4027254885Sdumbbell#else 4028254885Sdumbbell UCHAR ucDP_Lane0_Source:2; 4029254885Sdumbbell UCHAR ucDP_Lane1_Source:2; 4030254885Sdumbbell UCHAR ucDP_Lane2_Source:2; 4031254885Sdumbbell UCHAR ucDP_Lane3_Source:2; 4032254885Sdumbbell#endif 4033254885Sdumbbell}ATOM_DP_CONN_CHANNEL_MAPPING; 4034254885Sdumbbell 4035254885Sdumbbell//for DVI/HDMI, in dual link case, both links have to have same mapping. 4036254885Sdumbbell//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4037254885Sdumbbell//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4038254885Sdumbbell//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4039254885Sdumbbell//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4040254885Sdumbbelltypedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4041254885Sdumbbell{ 4042254885Sdumbbell#if ATOM_BIG_ENDIAN 4043254885Sdumbbell UCHAR ucDVI_CLK_Source:2; 4044254885Sdumbbell UCHAR ucDVI_DATA0_Source:2; 4045254885Sdumbbell UCHAR ucDVI_DATA1_Source:2; 4046254885Sdumbbell UCHAR ucDVI_DATA2_Source:2; 4047254885Sdumbbell#else 4048254885Sdumbbell UCHAR ucDVI_DATA2_Source:2; 4049254885Sdumbbell UCHAR ucDVI_DATA1_Source:2; 4050254885Sdumbbell UCHAR ucDVI_DATA0_Source:2; 4051254885Sdumbbell UCHAR ucDVI_CLK_Source:2; 4052254885Sdumbbell#endif 4053254885Sdumbbell}ATOM_DVI_CONN_CHANNEL_MAPPING; 4054254885Sdumbbell 4055254885Sdumbbelltypedef struct _EXT_DISPLAY_PATH 4056254885Sdumbbell{ 4057254885Sdumbbell USHORT usDeviceTag; //A bit vector to show what devices are supported 4058254885Sdumbbell USHORT usDeviceACPIEnum; //16bit device ACPI id. 4059254885Sdumbbell USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4060254885Sdumbbell UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4061254885Sdumbbell UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4062254885Sdumbbell USHORT usExtEncoderObjId; //external encoder object id 4063254885Sdumbbell union{ 4064254885Sdumbbell UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4065254885Sdumbbell ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4066254885Sdumbbell ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4067254885Sdumbbell }; 4068254885Sdumbbell UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4069254885Sdumbbell USHORT usCaps; 4070254885Sdumbbell USHORT usReserved; 4071254885Sdumbbell}EXT_DISPLAY_PATH; 4072254885Sdumbbell 4073254885Sdumbbell#define NUMBER_OF_UCHAR_FOR_GUID 16 4074254885Sdumbbell#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4075254885Sdumbbell 4076254885Sdumbbell//usCaps 4077254885Sdumbbell#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4078254885Sdumbbell 4079254885Sdumbbelltypedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4080254885Sdumbbell{ 4081254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 4082254885Sdumbbell UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4083254885Sdumbbell EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4084254885Sdumbbell UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4085254885Sdumbbell UCHAR uc3DStereoPinId; // use for eDP panel 4086254885Sdumbbell UCHAR ucRemoteDisplayConfig; 4087254885Sdumbbell UCHAR uceDPToLVDSRxId; 4088254885Sdumbbell UCHAR Reserved[4]; // for potential expansion 4089254885Sdumbbell}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4090254885Sdumbbell 4091254885Sdumbbell//Related definitions, all records are different but they have a commond header 4092254885Sdumbbelltypedef struct _ATOM_COMMON_RECORD_HEADER 4093254885Sdumbbell{ 4094254885Sdumbbell UCHAR ucRecordType; //An emun to indicate the record type 4095254885Sdumbbell UCHAR ucRecordSize; //The size of the whole record in byte 4096254885Sdumbbell}ATOM_COMMON_RECORD_HEADER; 4097254885Sdumbbell 4098254885Sdumbbell 4099254885Sdumbbell#define ATOM_I2C_RECORD_TYPE 1 4100254885Sdumbbell#define ATOM_HPD_INT_RECORD_TYPE 2 4101254885Sdumbbell#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4102254885Sdumbbell#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4103254885Sdumbbell#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4104254885Sdumbbell#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4105254885Sdumbbell#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4106254885Sdumbbell#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4107254885Sdumbbell#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4108254885Sdumbbell#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4109254885Sdumbbell#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4110254885Sdumbbell#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4111254885Sdumbbell#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4112254885Sdumbbell#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4113254885Sdumbbell#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4114254885Sdumbbell#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4115254885Sdumbbell#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4116254885Sdumbbell#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4117254885Sdumbbell#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4118254885Sdumbbell#define ATOM_ENCODER_CAP_RECORD_TYPE 20 4119254885Sdumbbell 4120254885Sdumbbell 4121254885Sdumbbell//Must be updated when new record type is added,equal to that record definition! 4122254885Sdumbbell#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4123254885Sdumbbell 4124254885Sdumbbelltypedef struct _ATOM_I2C_RECORD 4125254885Sdumbbell{ 4126254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4127254885Sdumbbell ATOM_I2C_ID_CONFIG sucI2cId; 4128254885Sdumbbell UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4129254885Sdumbbell}ATOM_I2C_RECORD; 4130254885Sdumbbell 4131254885Sdumbbelltypedef struct _ATOM_HPD_INT_RECORD 4132254885Sdumbbell{ 4133254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4134254885Sdumbbell UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4135254885Sdumbbell UCHAR ucPlugged_PinState; 4136254885Sdumbbell}ATOM_HPD_INT_RECORD; 4137254885Sdumbbell 4138254885Sdumbbell 4139254885Sdumbbelltypedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4140254885Sdumbbell{ 4141254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4142254885Sdumbbell UCHAR ucProtectionFlag; 4143254885Sdumbbell UCHAR ucReserved; 4144254885Sdumbbell}ATOM_OUTPUT_PROTECTION_RECORD; 4145254885Sdumbbell 4146254885Sdumbbelltypedef struct _ATOM_CONNECTOR_DEVICE_TAG 4147254885Sdumbbell{ 4148254885Sdumbbell ULONG ulACPIDeviceEnum; //Reserved for now 4149254885Sdumbbell USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4150254885Sdumbbell USHORT usPadding; 4151254885Sdumbbell}ATOM_CONNECTOR_DEVICE_TAG; 4152254885Sdumbbell 4153254885Sdumbbelltypedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4154254885Sdumbbell{ 4155254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4156254885Sdumbbell UCHAR ucNumberOfDevice; 4157254885Sdumbbell UCHAR ucReserved; 4158254885Sdumbbell ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4159254885Sdumbbell}ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4160254885Sdumbbell 4161254885Sdumbbell 4162254885Sdumbbelltypedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4163254885Sdumbbell{ 4164254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4165254885Sdumbbell UCHAR ucConfigGPIOID; 4166254885Sdumbbell UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4167254885Sdumbbell UCHAR ucFlowinGPIPID; 4168254885Sdumbbell UCHAR ucExtInGPIPID; 4169254885Sdumbbell}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4170254885Sdumbbell 4171254885Sdumbbelltypedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4172254885Sdumbbell{ 4173254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4174254885Sdumbbell UCHAR ucCTL1GPIO_ID; 4175254885Sdumbbell UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4176254885Sdumbbell UCHAR ucCTL2GPIO_ID; 4177254885Sdumbbell UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4178254885Sdumbbell UCHAR ucCTL3GPIO_ID; 4179254885Sdumbbell UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4180254885Sdumbbell UCHAR ucCTLFPGA_IN_ID; 4181254885Sdumbbell UCHAR ucPadding[3]; 4182254885Sdumbbell}ATOM_ENCODER_FPGA_CONTROL_RECORD; 4183254885Sdumbbell 4184254885Sdumbbelltypedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4185254885Sdumbbell{ 4186254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4187254885Sdumbbell UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4188254885Sdumbbell UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4189254885Sdumbbell}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4190254885Sdumbbell 4191254885Sdumbbelltypedef struct _ATOM_JTAG_RECORD 4192254885Sdumbbell{ 4193254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4194254885Sdumbbell UCHAR ucTMSGPIO_ID; 4195254885Sdumbbell UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4196254885Sdumbbell UCHAR ucTCKGPIO_ID; 4197254885Sdumbbell UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4198254885Sdumbbell UCHAR ucTDOGPIO_ID; 4199254885Sdumbbell UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4200254885Sdumbbell UCHAR ucTDIGPIO_ID; 4201254885Sdumbbell UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4202254885Sdumbbell UCHAR ucPadding[2]; 4203254885Sdumbbell}ATOM_JTAG_RECORD; 4204254885Sdumbbell 4205254885Sdumbbell 4206254885Sdumbbell//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4207254885Sdumbbelltypedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4208254885Sdumbbell{ 4209254885Sdumbbell UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4210254885Sdumbbell UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4211254885Sdumbbell}ATOM_GPIO_PIN_CONTROL_PAIR; 4212254885Sdumbbell 4213254885Sdumbbelltypedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4214254885Sdumbbell{ 4215254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4216254885Sdumbbell UCHAR ucFlags; // Future expnadibility 4217254885Sdumbbell UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4218254885Sdumbbell ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4219254885Sdumbbell}ATOM_OBJECT_GPIO_CNTL_RECORD; 4220254885Sdumbbell 4221254885Sdumbbell//Definitions for GPIO pin state 4222254885Sdumbbell#define GPIO_PIN_TYPE_INPUT 0x00 4223254885Sdumbbell#define GPIO_PIN_TYPE_OUTPUT 0x10 4224254885Sdumbbell#define GPIO_PIN_TYPE_HW_CONTROL 0x20 4225254885Sdumbbell 4226254885Sdumbbell//For GPIO_PIN_TYPE_OUTPUT the following is defined 4227254885Sdumbbell#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4228254885Sdumbbell#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4229254885Sdumbbell#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4230254885Sdumbbell#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4231254885Sdumbbell 4232254885Sdumbbell// Indexes to GPIO array in GLSync record 4233254885Sdumbbell// GLSync record is for Frame Lock/Gen Lock feature. 4234254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4235254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4236254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4237254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4238254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4239254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4240254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4241254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4242254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4243254885Sdumbbell#define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4244254885Sdumbbell 4245254885Sdumbbelltypedef struct _ATOM_ENCODER_DVO_CF_RECORD 4246254885Sdumbbell{ 4247254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4248254885Sdumbbell ULONG ulStrengthControl; // DVOA strength control for CF 4249254885Sdumbbell UCHAR ucPadding[2]; 4250254885Sdumbbell}ATOM_ENCODER_DVO_CF_RECORD; 4251254885Sdumbbell 4252254885Sdumbbell// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4253254885Sdumbbell#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4254254885Sdumbbell#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4255254885Sdumbbell 4256254885Sdumbbelltypedef struct _ATOM_ENCODER_CAP_RECORD 4257254885Sdumbbell{ 4258254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4259254885Sdumbbell union { 4260254885Sdumbbell USHORT usEncoderCap; 4261254885Sdumbbell struct { 4262254885Sdumbbell#if ATOM_BIG_ENDIAN 4263254885Sdumbbell USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4264254885Sdumbbell USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4265254885Sdumbbell USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4266254885Sdumbbell#else 4267254885Sdumbbell USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4268254885Sdumbbell USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4269254885Sdumbbell USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4270254885Sdumbbell#endif 4271254885Sdumbbell }; 4272254885Sdumbbell }; 4273254885Sdumbbell}ATOM_ENCODER_CAP_RECORD; 4274254885Sdumbbell 4275254885Sdumbbell// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4276254885Sdumbbell#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4277254885Sdumbbell#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4278254885Sdumbbell 4279254885Sdumbbelltypedef struct _ATOM_CONNECTOR_CF_RECORD 4280254885Sdumbbell{ 4281254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4282254885Sdumbbell USHORT usMaxPixClk; 4283254885Sdumbbell UCHAR ucFlowCntlGpioId; 4284254885Sdumbbell UCHAR ucSwapCntlGpioId; 4285254885Sdumbbell UCHAR ucConnectedDvoBundle; 4286254885Sdumbbell UCHAR ucPadding; 4287254885Sdumbbell}ATOM_CONNECTOR_CF_RECORD; 4288254885Sdumbbell 4289254885Sdumbbelltypedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4290254885Sdumbbell{ 4291254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4292254885Sdumbbell ATOM_DTD_FORMAT asTiming; 4293254885Sdumbbell}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4294254885Sdumbbell 4295254885Sdumbbelltypedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4296254885Sdumbbell{ 4297254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4298254885Sdumbbell UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4299254885Sdumbbell UCHAR ucReserved; 4300254885Sdumbbell}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4301254885Sdumbbell 4302254885Sdumbbell 4303254885Sdumbbelltypedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4304254885Sdumbbell{ 4305254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4306254885Sdumbbell UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4307254885Sdumbbell UCHAR ucMuxControlPin; 4308254885Sdumbbell UCHAR ucMuxState[2]; //for alligment purpose 4309254885Sdumbbell}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4310254885Sdumbbell 4311254885Sdumbbelltypedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4312254885Sdumbbell{ 4313254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4314254885Sdumbbell UCHAR ucMuxType; 4315254885Sdumbbell UCHAR ucMuxControlPin; 4316254885Sdumbbell UCHAR ucMuxState[2]; //for alligment purpose 4317254885Sdumbbell}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4318254885Sdumbbell 4319254885Sdumbbell// define ucMuxType 4320254885Sdumbbell#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4321254885Sdumbbell#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4322254885Sdumbbell 4323254885Sdumbbelltypedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4324254885Sdumbbell{ 4325254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4326254885Sdumbbell UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4327254885Sdumbbell}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4328254885Sdumbbell 4329254885Sdumbbelltypedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4330254885Sdumbbell{ 4331254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4332254885Sdumbbell ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4333254885Sdumbbell}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4334254885Sdumbbell 4335254885Sdumbbelltypedef struct _ATOM_OBJECT_LINK_RECORD 4336254885Sdumbbell{ 4337254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4338254885Sdumbbell USHORT usObjectID; //could be connector, encorder or other object in object.h 4339254885Sdumbbell}ATOM_OBJECT_LINK_RECORD; 4340254885Sdumbbell 4341254885Sdumbbelltypedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4342254885Sdumbbell{ 4343254885Sdumbbell ATOM_COMMON_RECORD_HEADER sheader; 4344254885Sdumbbell USHORT usReserved; 4345254885Sdumbbell}ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4346254885Sdumbbell 4347254885Sdumbbell/****************************************************************************/ 4348254885Sdumbbell// ASIC voltage data table 4349254885Sdumbbell/****************************************************************************/ 4350254885Sdumbbelltypedef struct _ATOM_VOLTAGE_INFO_HEADER 4351254885Sdumbbell{ 4352254885Sdumbbell USHORT usVDDCBaseLevel; //In number of 50mv unit 4353254885Sdumbbell USHORT usReserved; //For possible extension table offset 4354254885Sdumbbell UCHAR ucNumOfVoltageEntries; 4355254885Sdumbbell UCHAR ucBytesPerVoltageEntry; 4356254885Sdumbbell UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4357254885Sdumbbell UCHAR ucDefaultVoltageEntry; 4358254885Sdumbbell UCHAR ucVoltageControlI2cLine; 4359254885Sdumbbell UCHAR ucVoltageControlAddress; 4360254885Sdumbbell UCHAR ucVoltageControlOffset; 4361254885Sdumbbell}ATOM_VOLTAGE_INFO_HEADER; 4362254885Sdumbbell 4363254885Sdumbbelltypedef struct _ATOM_VOLTAGE_INFO 4364254885Sdumbbell{ 4365254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 4366254885Sdumbbell ATOM_VOLTAGE_INFO_HEADER viHeader; 4367254885Sdumbbell UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4368254885Sdumbbell}ATOM_VOLTAGE_INFO; 4369254885Sdumbbell 4370254885Sdumbbell 4371254885Sdumbbelltypedef struct _ATOM_VOLTAGE_FORMULA 4372254885Sdumbbell{ 4373254885Sdumbbell USHORT usVoltageBaseLevel; // In number of 1mv unit 4374254885Sdumbbell USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4375254885Sdumbbell UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4376254885Sdumbbell UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4377254885Sdumbbell UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4378254885Sdumbbell UCHAR ucReserved; 4379254885Sdumbbell UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4380254885Sdumbbell}ATOM_VOLTAGE_FORMULA; 4381254885Sdumbbell 4382254885Sdumbbelltypedef struct _VOLTAGE_LUT_ENTRY 4383254885Sdumbbell{ 4384254885Sdumbbell USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4385254885Sdumbbell USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4386254885Sdumbbell}VOLTAGE_LUT_ENTRY; 4387254885Sdumbbell 4388254885Sdumbbelltypedef struct _ATOM_VOLTAGE_FORMULA_V2 4389254885Sdumbbell{ 4390254885Sdumbbell UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4391254885Sdumbbell UCHAR ucReserved[3]; 4392254885Sdumbbell VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4393254885Sdumbbell}ATOM_VOLTAGE_FORMULA_V2; 4394254885Sdumbbell 4395254885Sdumbbelltypedef struct _ATOM_VOLTAGE_CONTROL 4396254885Sdumbbell{ 4397254885Sdumbbell UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4398254885Sdumbbell UCHAR ucVoltageControlI2cLine; 4399254885Sdumbbell UCHAR ucVoltageControlAddress; 4400254885Sdumbbell UCHAR ucVoltageControlOffset; 4401254885Sdumbbell USHORT usGpioPin_AIndex; //GPIO_PAD register index 4402254885Sdumbbell UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4403254885Sdumbbell UCHAR ucReserved; 4404254885Sdumbbell}ATOM_VOLTAGE_CONTROL; 4405254885Sdumbbell 4406254885Sdumbbell// Define ucVoltageControlId 4407254885Sdumbbell#define VOLTAGE_CONTROLLED_BY_HW 0x00 4408254885Sdumbbell#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4409254885Sdumbbell#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4410254885Sdumbbell#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4411254885Sdumbbell#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4412254885Sdumbbell#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4413254885Sdumbbell#define VOLTAGE_CONTROL_ID_DS4402 0x04 4414254885Sdumbbell#define VOLTAGE_CONTROL_ID_UP6266 0x05 4415254885Sdumbbell#define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4416254885Sdumbbell#define VOLTAGE_CONTROL_ID_VT1556M 0x07 4417254885Sdumbbell#define VOLTAGE_CONTROL_ID_CHL822x 0x08 4418254885Sdumbbell#define VOLTAGE_CONTROL_ID_VT1586M 0x09 4419254885Sdumbbell#define VOLTAGE_CONTROL_ID_UP1637 0x0A 4420254885Sdumbbell 4421254885Sdumbbelltypedef struct _ATOM_VOLTAGE_OBJECT 4422254885Sdumbbell{ 4423254885Sdumbbell UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4424254885Sdumbbell UCHAR ucSize; //Size of Object 4425254885Sdumbbell ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4426254885Sdumbbell ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4427254885Sdumbbell}ATOM_VOLTAGE_OBJECT; 4428254885Sdumbbell 4429254885Sdumbbelltypedef struct _ATOM_VOLTAGE_OBJECT_V2 4430254885Sdumbbell{ 4431254885Sdumbbell UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4432254885Sdumbbell UCHAR ucSize; //Size of Object 4433254885Sdumbbell ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4434254885Sdumbbell ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4435254885Sdumbbell}ATOM_VOLTAGE_OBJECT_V2; 4436254885Sdumbbell 4437254885Sdumbbelltypedef struct _ATOM_VOLTAGE_OBJECT_INFO 4438254885Sdumbbell{ 4439254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 4440254885Sdumbbell ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4441254885Sdumbbell}ATOM_VOLTAGE_OBJECT_INFO; 4442254885Sdumbbell 4443254885Sdumbbelltypedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4444254885Sdumbbell{ 4445254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 4446254885Sdumbbell ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4447254885Sdumbbell}ATOM_VOLTAGE_OBJECT_INFO_V2; 4448254885Sdumbbell 4449254885Sdumbbelltypedef struct _ATOM_LEAKID_VOLTAGE 4450254885Sdumbbell{ 4451254885Sdumbbell UCHAR ucLeakageId; 4452254885Sdumbbell UCHAR ucReserved; 4453254885Sdumbbell USHORT usVoltage; 4454254885Sdumbbell}ATOM_LEAKID_VOLTAGE; 4455254885Sdumbbell 4456254885Sdumbbelltypedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4457254885Sdumbbell UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4458254885Sdumbbell UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4459254885Sdumbbell USHORT usSize; //Size of Object 4460254885Sdumbbell}ATOM_VOLTAGE_OBJECT_HEADER_V3; 4461254885Sdumbbell 4462254885Sdumbbelltypedef struct _VOLTAGE_LUT_ENTRY_V2 4463254885Sdumbbell{ 4464254885Sdumbbell ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4465254885Sdumbbell USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4466254885Sdumbbell}VOLTAGE_LUT_ENTRY_V2; 4467254885Sdumbbell 4468254885Sdumbbelltypedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4469254885Sdumbbell{ 4470254885Sdumbbell USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4471254885Sdumbbell USHORT usVoltageId; 4472254885Sdumbbell USHORT usLeakageId; // The corresponding Voltage Value, in mV 4473254885Sdumbbell}LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4474254885Sdumbbell 4475254885Sdumbbelltypedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4476254885Sdumbbell{ 4477254885Sdumbbell ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4478254885Sdumbbell UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4479254885Sdumbbell UCHAR ucVoltageControlI2cLine; 4480254885Sdumbbell UCHAR ucVoltageControlAddress; 4481254885Sdumbbell UCHAR ucVoltageControlOffset; 4482254885Sdumbbell ULONG ulReserved; 4483254885Sdumbbell VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4484254885Sdumbbell}ATOM_I2C_VOLTAGE_OBJECT_V3; 4485254885Sdumbbell 4486254885Sdumbbelltypedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4487254885Sdumbbell{ 4488254885Sdumbbell ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4489254885Sdumbbell UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4490254885Sdumbbell UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4491254885Sdumbbell UCHAR ucPhaseDelay; // phase delay in unit of micro second 4492254885Sdumbbell UCHAR ucReserved; 4493254885Sdumbbell ULONG ulGpioMaskVal; // GPIO Mask value 4494254885Sdumbbell VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 4495254885Sdumbbell}ATOM_GPIO_VOLTAGE_OBJECT_V3; 4496254885Sdumbbell 4497254885Sdumbbelltypedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4498254885Sdumbbell{ 4499254885Sdumbbell ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4500254885Sdumbbell UCHAR ucLeakageCntlId; // default is 0 4501254885Sdumbbell UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4502254885Sdumbbell UCHAR ucReserved[2]; 4503254885Sdumbbell ULONG ulMaxVoltageLevel; 4504254885Sdumbbell LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 4505254885Sdumbbell}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4506254885Sdumbbell 4507254885Sdumbbelltypedef union _ATOM_VOLTAGE_OBJECT_V3{ 4508254885Sdumbbell ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4509254885Sdumbbell ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4510254885Sdumbbell ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4511254885Sdumbbell}ATOM_VOLTAGE_OBJECT_V3; 4512254885Sdumbbell 4513254885Sdumbbelltypedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4514254885Sdumbbell{ 4515254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 4516254885Sdumbbell ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4517254885Sdumbbell}ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4518254885Sdumbbell 4519254885Sdumbbelltypedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4520254885Sdumbbell{ 4521254885Sdumbbell UCHAR ucProfileId; 4522254885Sdumbbell UCHAR ucReserved; 4523254885Sdumbbell USHORT usSize; 4524254885Sdumbbell USHORT usEfuseSpareStartAddr; 4525254885Sdumbbell USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4526254885Sdumbbell ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4527254885Sdumbbell}ATOM_ASIC_PROFILE_VOLTAGE; 4528254885Sdumbbell 4529254885Sdumbbell//ucProfileId 4530254885Sdumbbell#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4531254885Sdumbbell#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4532254885Sdumbbell#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4533254885Sdumbbell 4534254885Sdumbbelltypedef struct _ATOM_ASIC_PROFILING_INFO 4535254885Sdumbbell{ 4536254885Sdumbbell ATOM_COMMON_TABLE_HEADER asHeader; 4537254885Sdumbbell ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4538254885Sdumbbell}ATOM_ASIC_PROFILING_INFO; 4539254885Sdumbbell 4540254885Sdumbbelltypedef struct _ATOM_POWER_SOURCE_OBJECT 4541254885Sdumbbell{ 4542254885Sdumbbell UCHAR ucPwrSrcId; // Power source 4543254885Sdumbbell UCHAR ucPwrSensorType; // GPIO, I2C or none 4544254885Sdumbbell UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4545254885Sdumbbell UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4546254885Sdumbbell UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 4547254885Sdumbbell UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 4548254885Sdumbbell UCHAR ucPwrSensActiveState; // high active or low active 4549254885Sdumbbell UCHAR ucReserve[3]; // reserve 4550254885Sdumbbell USHORT usSensPwr; // in unit of watt 4551254885Sdumbbell}ATOM_POWER_SOURCE_OBJECT; 4552254885Sdumbbell 4553254885Sdumbbelltypedef struct _ATOM_POWER_SOURCE_INFO 4554254885Sdumbbell{ 4555254885Sdumbbell ATOM_COMMON_TABLE_HEADER asHeader; 4556254885Sdumbbell UCHAR asPwrbehave[16]; 4557254885Sdumbbell ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 4558254885Sdumbbell}ATOM_POWER_SOURCE_INFO; 4559254885Sdumbbell 4560254885Sdumbbell 4561254885Sdumbbell//Define ucPwrSrcId 4562254885Sdumbbell#define POWERSOURCE_PCIE_ID1 0x00 4563254885Sdumbbell#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 4564254885Sdumbbell#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 4565254885Sdumbbell#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 4566254885Sdumbbell#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 4567254885Sdumbbell 4568254885Sdumbbell//define ucPwrSensorId 4569254885Sdumbbell#define POWER_SENSOR_ALWAYS 0x00 4570254885Sdumbbell#define POWER_SENSOR_GPIO 0x01 4571254885Sdumbbell#define POWER_SENSOR_I2C 0x02 4572254885Sdumbbell 4573254885Sdumbbelltypedef struct _ATOM_CLK_VOLT_CAPABILITY 4574254885Sdumbbell{ 4575254885Sdumbbell ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 4576254885Sdumbbell ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4577254885Sdumbbell}ATOM_CLK_VOLT_CAPABILITY; 4578254885Sdumbbell 4579254885Sdumbbelltypedef struct _ATOM_AVAILABLE_SCLK_LIST 4580254885Sdumbbell{ 4581254885Sdumbbell ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4582254885Sdumbbell USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 4583254885Sdumbbell USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 4584254885Sdumbbell}ATOM_AVAILABLE_SCLK_LIST; 4585254885Sdumbbell 4586254885Sdumbbell// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 4587254885Sdumbbell#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 4588254885Sdumbbell 4589254885Sdumbbell// this IntegrateSystemInfoTable is used for Liano/Ontario APU 4590254885Sdumbbelltypedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4591254885Sdumbbell{ 4592254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 4593254885Sdumbbell ULONG ulBootUpEngineClock; 4594254885Sdumbbell ULONG ulDentistVCOFreq; 4595254885Sdumbbell ULONG ulBootUpUMAClock; 4596254885Sdumbbell ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4597254885Sdumbbell ULONG ulBootUpReqDisplayVector; 4598254885Sdumbbell ULONG ulOtherDisplayMisc; 4599254885Sdumbbell ULONG ulGPUCapInfo; 4600254885Sdumbbell ULONG ulSB_MMIO_Base_Addr; 4601254885Sdumbbell USHORT usRequestedPWMFreqInHz; 4602254885Sdumbbell UCHAR ucHtcTmpLmt; 4603254885Sdumbbell UCHAR ucHtcHystLmt; 4604254885Sdumbbell ULONG ulMinEngineClock; 4605254885Sdumbbell ULONG ulSystemConfig; 4606254885Sdumbbell ULONG ulCPUCapInfo; 4607254885Sdumbbell USHORT usNBP0Voltage; 4608254885Sdumbbell USHORT usNBP1Voltage; 4609254885Sdumbbell USHORT usBootUpNBVoltage; 4610254885Sdumbbell USHORT usExtDispConnInfoOffset; 4611254885Sdumbbell USHORT usPanelRefreshRateRange; 4612254885Sdumbbell UCHAR ucMemoryType; 4613254885Sdumbbell UCHAR ucUMAChannelNumber; 4614254885Sdumbbell ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4615254885Sdumbbell ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4616254885Sdumbbell ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4617254885Sdumbbell ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4618254885Sdumbbell ULONG ulGMCRestoreResetTime; 4619254885Sdumbbell ULONG ulMinimumNClk; 4620254885Sdumbbell ULONG ulIdleNClk; 4621254885Sdumbbell ULONG ulDDR_DLL_PowerUpTime; 4622254885Sdumbbell ULONG ulDDR_PLL_PowerUpTime; 4623254885Sdumbbell USHORT usPCIEClkSSPercentage; 4624254885Sdumbbell USHORT usPCIEClkSSType; 4625254885Sdumbbell USHORT usLvdsSSPercentage; 4626254885Sdumbbell USHORT usLvdsSSpreadRateIn10Hz; 4627254885Sdumbbell USHORT usHDMISSPercentage; 4628254885Sdumbbell USHORT usHDMISSpreadRateIn10Hz; 4629254885Sdumbbell USHORT usDVISSPercentage; 4630254885Sdumbbell USHORT usDVISSpreadRateIn10Hz; 4631254885Sdumbbell ULONG SclkDpmBoostMargin; 4632254885Sdumbbell ULONG SclkDpmThrottleMargin; 4633254885Sdumbbell USHORT SclkDpmTdpLimitPG; 4634254885Sdumbbell USHORT SclkDpmTdpLimitBoost; 4635254885Sdumbbell ULONG ulBoostEngineCLock; 4636254885Sdumbbell UCHAR ulBoostVid_2bit; 4637254885Sdumbbell UCHAR EnableBoost; 4638254885Sdumbbell USHORT GnbTdpLimit; 4639254885Sdumbbell USHORT usMaxLVDSPclkFreqInSingleLink; 4640254885Sdumbbell UCHAR ucLvdsMisc; 4641254885Sdumbbell UCHAR ucLVDSReserved; 4642254885Sdumbbell ULONG ulReserved3[15]; 4643254885Sdumbbell ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4644254885Sdumbbell}ATOM_INTEGRATED_SYSTEM_INFO_V6; 4645254885Sdumbbell 4646254885Sdumbbell// ulGPUCapInfo 4647254885Sdumbbell#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4648254885Sdumbbell#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 4649254885Sdumbbell 4650254885Sdumbbell//ucLVDSMisc: 4651254885Sdumbbell#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 4652254885Sdumbbell#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 4653254885Sdumbbell#define SYS_INFO_LVDSMISC__888_BPC 0x04 4654254885Sdumbbell#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 4655254885Sdumbbell#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 4656254885Sdumbbell 4657254885Sdumbbell// not used any more 4658254885Sdumbbell#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 4659254885Sdumbbell#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 4660254885Sdumbbell 4661254885Sdumbbell/********************************************************************************************************************** 4662254885Sdumbbell ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4663254885SdumbbellulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4664254885SdumbbellulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4665254885SdumbbellulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4666254885SdumbbellsDISPCLK_Voltage: Report Display clock voltage requirement. 4667254885Sdumbbell 4668254885SdumbbellulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 4669254885Sdumbbell ATOM_DEVICE_CRT1_SUPPORT 0x0001 4670254885Sdumbbell ATOM_DEVICE_CRT2_SUPPORT 0x0010 4671254885Sdumbbell ATOM_DEVICE_DFP1_SUPPORT 0x0008 4672254885Sdumbbell ATOM_DEVICE_DFP6_SUPPORT 0x0040 4673254885Sdumbbell ATOM_DEVICE_DFP2_SUPPORT 0x0080 4674254885Sdumbbell ATOM_DEVICE_DFP3_SUPPORT 0x0200 4675254885Sdumbbell ATOM_DEVICE_DFP4_SUPPORT 0x0400 4676254885Sdumbbell ATOM_DEVICE_DFP5_SUPPORT 0x0800 4677254885Sdumbbell ATOM_DEVICE_LCD1_SUPPORT 0x0002 4678254885SdumbbellulOtherDisplayMisc: Other display related flags, not defined yet. 4679254885SdumbbellulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4680254885Sdumbbell =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4681254885Sdumbbell bit[3]=0: Enable HW AUX mode detection logic 4682254885Sdumbbell =1: Disable HW AUX mode dettion logic 4683254885SdumbbellulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4684254885Sdumbbell 4685254885SdumbbellusRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4686254885Sdumbbell Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4687254885Sdumbbell 4688254885Sdumbbell When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4689254885Sdumbbell 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4690254885Sdumbbell VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4691254885Sdumbbell Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4692254885Sdumbbell and enabling VariBri under the driver environment from PP table is optional. 4693254885Sdumbbell 4694254885Sdumbbell 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4695254885Sdumbbell that BL control from GPU is expected. 4696254885Sdumbbell VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4697254885Sdumbbell Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4698254885Sdumbbell it's per platform 4699254885Sdumbbell and enabling VariBri under the driver environment from PP table is optional. 4700254885Sdumbbell 4701254885SdumbbellucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4702254885Sdumbbell Threshold on value to enter HTC_active state. 4703254885SdumbbellucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4704254885Sdumbbell To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4705254885SdumbbellulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4706254885SdumbbellulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4707254885Sdumbbell =1: PCIE Power Gating Enabled 4708254885Sdumbbell Bit[1]=0: DDR-DLL shut-down feature disabled. 4709254885Sdumbbell 1: DDR-DLL shut-down feature enabled. 4710254885Sdumbbell Bit[2]=0: DDR-PLL Power down feature disabled. 4711254885Sdumbbell 1: DDR-PLL Power down feature enabled. 4712254885SdumbbellulCPUCapInfo: TBD 4713254885SdumbbellusNBP0Voltage: VID for voltage on NB P0 State 4714254885SdumbbellusNBP1Voltage: VID for voltage on NB P1 State 4715254885SdumbbellusBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4716254885SdumbbellusExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4717254885SdumbbellusPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4718254885Sdumbbell to indicate a range. 4719254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4720254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4721254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4722254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4723254885SdumbbellucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4724254885SdumbbellucUMAChannelNumber: System memory channel numbers. 4725254885SdumbbellulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4726254885SdumbbellulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4727254885SdumbbellulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4728298955SpfgsAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high 4729254885SdumbbellulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4730254885SdumbbellulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4731254885SdumbbellulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4732254885SdumbbellulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4733254885SdumbbellulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4734298955SpfgusPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 4735298955SpfgusPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4736254885SdumbbellusLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4737254885SdumbbellusLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4738254885SdumbbellusHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4739254885SdumbbellusHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4740254885SdumbbellusDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4741254885SdumbbellusDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4742254885SdumbbellusMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4743254885SdumbbellucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4744254885Sdumbbell [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4745254885Sdumbbell [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4746254885Sdumbbell [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4747254885Sdumbbell [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4748254885Sdumbbell**********************************************************************************************************************/ 4749254885Sdumbbell 4750254885Sdumbbell// this Table is used for Liano/Ontario APU 4751254885Sdumbbelltypedef struct _ATOM_FUSION_SYSTEM_INFO_V1 4752254885Sdumbbell{ 4753254885Sdumbbell ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 4754254885Sdumbbell ULONG ulPowerplayTable[128]; 4755254885Sdumbbell}ATOM_FUSION_SYSTEM_INFO_V1; 4756254885Sdumbbell/********************************************************************************************************************** 4757254885Sdumbbell ATOM_FUSION_SYSTEM_INFO_V1 Description 4758254885SdumbbellsIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 4759254885SdumbbellulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 4760254885Sdumbbell**********************************************************************************************************************/ 4761254885Sdumbbell 4762254885Sdumbbell// this IntegrateSystemInfoTable is used for Trinity APU 4763254885Sdumbbelltypedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 4764254885Sdumbbell{ 4765254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 4766254885Sdumbbell ULONG ulBootUpEngineClock; 4767254885Sdumbbell ULONG ulDentistVCOFreq; 4768254885Sdumbbell ULONG ulBootUpUMAClock; 4769254885Sdumbbell ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4770254885Sdumbbell ULONG ulBootUpReqDisplayVector; 4771254885Sdumbbell ULONG ulOtherDisplayMisc; 4772254885Sdumbbell ULONG ulGPUCapInfo; 4773254885Sdumbbell ULONG ulSB_MMIO_Base_Addr; 4774254885Sdumbbell USHORT usRequestedPWMFreqInHz; 4775254885Sdumbbell UCHAR ucHtcTmpLmt; 4776254885Sdumbbell UCHAR ucHtcHystLmt; 4777254885Sdumbbell ULONG ulMinEngineClock; 4778254885Sdumbbell ULONG ulSystemConfig; 4779254885Sdumbbell ULONG ulCPUCapInfo; 4780254885Sdumbbell USHORT usNBP0Voltage; 4781254885Sdumbbell USHORT usNBP1Voltage; 4782254885Sdumbbell USHORT usBootUpNBVoltage; 4783254885Sdumbbell USHORT usExtDispConnInfoOffset; 4784254885Sdumbbell USHORT usPanelRefreshRateRange; 4785254885Sdumbbell UCHAR ucMemoryType; 4786254885Sdumbbell UCHAR ucUMAChannelNumber; 4787254885Sdumbbell UCHAR strVBIOSMsg[40]; 4788254885Sdumbbell ULONG ulReserved[20]; 4789254885Sdumbbell ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4790254885Sdumbbell ULONG ulGMCRestoreResetTime; 4791254885Sdumbbell ULONG ulMinimumNClk; 4792254885Sdumbbell ULONG ulIdleNClk; 4793254885Sdumbbell ULONG ulDDR_DLL_PowerUpTime; 4794254885Sdumbbell ULONG ulDDR_PLL_PowerUpTime; 4795254885Sdumbbell USHORT usPCIEClkSSPercentage; 4796254885Sdumbbell USHORT usPCIEClkSSType; 4797254885Sdumbbell USHORT usLvdsSSPercentage; 4798254885Sdumbbell USHORT usLvdsSSpreadRateIn10Hz; 4799254885Sdumbbell USHORT usHDMISSPercentage; 4800254885Sdumbbell USHORT usHDMISSpreadRateIn10Hz; 4801254885Sdumbbell USHORT usDVISSPercentage; 4802254885Sdumbbell USHORT usDVISSpreadRateIn10Hz; 4803254885Sdumbbell ULONG SclkDpmBoostMargin; 4804254885Sdumbbell ULONG SclkDpmThrottleMargin; 4805254885Sdumbbell USHORT SclkDpmTdpLimitPG; 4806254885Sdumbbell USHORT SclkDpmTdpLimitBoost; 4807254885Sdumbbell ULONG ulBoostEngineCLock; 4808254885Sdumbbell UCHAR ulBoostVid_2bit; 4809254885Sdumbbell UCHAR EnableBoost; 4810254885Sdumbbell USHORT GnbTdpLimit; 4811254885Sdumbbell USHORT usMaxLVDSPclkFreqInSingleLink; 4812254885Sdumbbell UCHAR ucLvdsMisc; 4813254885Sdumbbell UCHAR ucLVDSReserved; 4814254885Sdumbbell UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 4815254885Sdumbbell UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 4816254885Sdumbbell UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 4817254885Sdumbbell UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 4818254885Sdumbbell UCHAR ucLVDSOffToOnDelay_in4Ms; 4819254885Sdumbbell UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 4820254885Sdumbbell UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 4821254885Sdumbbell UCHAR ucLVDSReserved1; 4822254885Sdumbbell ULONG ulLCDBitDepthControlVal; 4823254885Sdumbbell ULONG ulNbpStateMemclkFreq[4]; 4824254885Sdumbbell USHORT usNBP2Voltage; 4825254885Sdumbbell USHORT usNBP3Voltage; 4826254885Sdumbbell ULONG ulNbpStateNClkFreq[4]; 4827254885Sdumbbell UCHAR ucNBDPMEnable; 4828254885Sdumbbell UCHAR ucReserved[3]; 4829254885Sdumbbell UCHAR ucDPMState0VclkFid; 4830254885Sdumbbell UCHAR ucDPMState0DclkFid; 4831254885Sdumbbell UCHAR ucDPMState1VclkFid; 4832254885Sdumbbell UCHAR ucDPMState1DclkFid; 4833254885Sdumbbell UCHAR ucDPMState2VclkFid; 4834254885Sdumbbell UCHAR ucDPMState2DclkFid; 4835254885Sdumbbell UCHAR ucDPMState3VclkFid; 4836254885Sdumbbell UCHAR ucDPMState3DclkFid; 4837254885Sdumbbell ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4838254885Sdumbbell}ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 4839254885Sdumbbell 4840254885Sdumbbell// ulOtherDisplayMisc 4841254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 4842254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 4843254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 4844254885Sdumbbell#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 4845254885Sdumbbell 4846254885Sdumbbell// ulGPUCapInfo 4847254885Sdumbbell#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4848254885Sdumbbell#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 4849254885Sdumbbell#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 4850254885Sdumbbell 4851254885Sdumbbell/********************************************************************************************************************** 4852254885Sdumbbell ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 4853254885SdumbbellulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4854254885SdumbbellulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4855254885SdumbbellulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4856254885SdumbbellsDISPCLK_Voltage: Report Display clock voltage requirement. 4857254885Sdumbbell 4858254885SdumbbellulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 4859254885Sdumbbell ATOM_DEVICE_CRT1_SUPPORT 0x0001 4860254885Sdumbbell ATOM_DEVICE_DFP1_SUPPORT 0x0008 4861254885Sdumbbell ATOM_DEVICE_DFP6_SUPPORT 0x0040 4862254885Sdumbbell ATOM_DEVICE_DFP2_SUPPORT 0x0080 4863254885Sdumbbell ATOM_DEVICE_DFP3_SUPPORT 0x0200 4864254885Sdumbbell ATOM_DEVICE_DFP4_SUPPORT 0x0400 4865254885Sdumbbell ATOM_DEVICE_DFP5_SUPPORT 0x0800 4866254885Sdumbbell ATOM_DEVICE_LCD1_SUPPORT 0x0002 4867254885SdumbbellulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 4868254885Sdumbbell =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 4869254885Sdumbbell bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 4870254885Sdumbbell =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 4871254885Sdumbbell bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 4872254885Sdumbbell =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 4873254885Sdumbbell bit[3]=0: VBIOS fast boot is disable 4874254885Sdumbbell =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 4875254885SdumbbellulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4876254885Sdumbbell =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4877254885Sdumbbell bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 4878254885Sdumbbell =1: DP mode use single PLL mode 4879254885Sdumbbell bit[3]=0: Enable AUX HW mode detection logic 4880254885Sdumbbell =1: Disable AUX HW mode detection logic 4881254885Sdumbbell 4882254885SdumbbellulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4883254885Sdumbbell 4884254885SdumbbellusRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4885254885Sdumbbell Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4886254885Sdumbbell 4887254885Sdumbbell When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4888254885Sdumbbell 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4889254885Sdumbbell VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4890254885Sdumbbell Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4891254885Sdumbbell and enabling VariBri under the driver environment from PP table is optional. 4892254885Sdumbbell 4893254885Sdumbbell 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4894254885Sdumbbell that BL control from GPU is expected. 4895254885Sdumbbell VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4896254885Sdumbbell Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4897254885Sdumbbell it's per platform 4898254885Sdumbbell and enabling VariBri under the driver environment from PP table is optional. 4899254885Sdumbbell 4900254885SdumbbellucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4901254885Sdumbbell Threshold on value to enter HTC_active state. 4902254885SdumbbellucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4903254885Sdumbbell To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4904254885SdumbbellulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4905254885SdumbbellulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4906254885Sdumbbell =1: PCIE Power Gating Enabled 4907254885Sdumbbell Bit[1]=0: DDR-DLL shut-down feature disabled. 4908254885Sdumbbell 1: DDR-DLL shut-down feature enabled. 4909254885Sdumbbell Bit[2]=0: DDR-PLL Power down feature disabled. 4910254885Sdumbbell 1: DDR-PLL Power down feature enabled. 4911254885SdumbbellulCPUCapInfo: TBD 4912254885SdumbbellusNBP0Voltage: VID for voltage on NB P0 State 4913254885SdumbbellusNBP1Voltage: VID for voltage on NB P1 State 4914254885SdumbbellusNBP2Voltage: VID for voltage on NB P2 State 4915254885SdumbbellusNBP3Voltage: VID for voltage on NB P3 State 4916254885SdumbbellusBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4917254885SdumbbellusExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4918254885SdumbbellusPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4919254885Sdumbbell to indicate a range. 4920254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4921254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4922254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4923254885Sdumbbell SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4924254885SdumbbellucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4925254885SdumbbellucUMAChannelNumber: System memory channel numbers. 4926254885SdumbbellulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4927254885SdumbbellulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4928254885SdumbbellulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4929298955SpfgsAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high 4930254885SdumbbellulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4931254885SdumbbellulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4932254885SdumbbellulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4933254885SdumbbellulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4934254885SdumbbellulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4935254885SdumbbellusPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 4936254885SdumbbellusPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4937254885SdumbbellusLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4938254885SdumbbellusLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4939254885SdumbbellusHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4940254885SdumbbellusHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4941254885SdumbbellusDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4942254885SdumbbellusDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4943254885SdumbbellusMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4944254885SdumbbellucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4945254885Sdumbbell [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4946254885Sdumbbell [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4947254885Sdumbbell [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4948254885Sdumbbell [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4949254885SdumbbellucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 4950254885Sdumbbell =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 4951254885Sdumbbell This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4952254885SdumbbellucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 4953254885Sdumbbell =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 4954254885Sdumbbell This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4955254885Sdumbbell 4956254885SdumbbellucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 4957254885Sdumbbell =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 4958254885Sdumbbell This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4959254885Sdumbbell 4960254885SdumbbellucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 4961254885Sdumbbell =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 4962254885Sdumbbell This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4963254885Sdumbbell 4964254885SdumbbellucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 4965254885Sdumbbell =0 means to use VBIOS default delay which is 125 ( 500ms ). 4966254885Sdumbbell This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4967254885Sdumbbell 4968254885SdumbbellucLVDSPwrOnVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 4969254885Sdumbbell =0 means to use VBIOS default delay which is 0 ( 0ms ). 4970254885Sdumbbell This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4971254885Sdumbbell 4972254885SdumbbellucLVDSPwrOffBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 4973254885Sdumbbell =0 means to use VBIOS default delay which is 0 ( 0ms ). 4974254885Sdumbbell This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4975254885Sdumbbell 4976254885SdumbbellulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 4977254885Sdumbbell 4978254885Sdumbbell**********************************************************************************************************************/ 4979254885Sdumbbell 4980254885Sdumbbell/**************************************************************************/ 4981254885Sdumbbell// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 4982254885Sdumbbell//Memory SS Info Table 4983254885Sdumbbell//Define Memory Clock SS chip ID 4984254885Sdumbbell#define ICS91719 1 4985254885Sdumbbell#define ICS91720 2 4986254885Sdumbbell 4987254885Sdumbbell//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 4988254885Sdumbbelltypedef struct _ATOM_I2C_DATA_RECORD 4989254885Sdumbbell{ 4990254885Sdumbbell UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 4991254885Sdumbbell UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 4992254885Sdumbbell}ATOM_I2C_DATA_RECORD; 4993254885Sdumbbell 4994254885Sdumbbell 4995254885Sdumbbell//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 4996254885Sdumbbelltypedef struct _ATOM_I2C_DEVICE_SETUP_INFO 4997254885Sdumbbell{ 4998254885Sdumbbell ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 4999254885Sdumbbell UCHAR ucSSChipID; //SS chip being used 5000254885Sdumbbell UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 5001254885Sdumbbell UCHAR ucNumOfI2CDataRecords; //number of data block 5002254885Sdumbbell ATOM_I2C_DATA_RECORD asI2CData[1]; 5003254885Sdumbbell}ATOM_I2C_DEVICE_SETUP_INFO; 5004254885Sdumbbell 5005254885Sdumbbell//========================================================================================== 5006254885Sdumbbelltypedef struct _ATOM_ASIC_MVDD_INFO 5007254885Sdumbbell{ 5008254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5009254885Sdumbbell ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 5010254885Sdumbbell}ATOM_ASIC_MVDD_INFO; 5011254885Sdumbbell 5012254885Sdumbbell//========================================================================================== 5013254885Sdumbbell#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5014254885Sdumbbell 5015254885Sdumbbell//========================================================================================== 5016254885Sdumbbell/**************************************************************************/ 5017254885Sdumbbell 5018254885Sdumbbelltypedef struct _ATOM_ASIC_SS_ASSIGNMENT 5019254885Sdumbbell{ 5020254885Sdumbbell ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5021254885Sdumbbell USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5022254885Sdumbbell USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5023254885Sdumbbell UCHAR ucClockIndication; //Indicate which clock source needs SS 5024254885Sdumbbell UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5025254885Sdumbbell UCHAR ucReserved[2]; 5026254885Sdumbbell}ATOM_ASIC_SS_ASSIGNMENT; 5027254885Sdumbbell 5028254885Sdumbbell//Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 5029254885Sdumbbell//SS is not required or enabled if a match is not found. 5030254885Sdumbbell#define ASIC_INTERNAL_MEMORY_SS 1 5031254885Sdumbbell#define ASIC_INTERNAL_ENGINE_SS 2 5032254885Sdumbbell#define ASIC_INTERNAL_UVD_SS 3 5033254885Sdumbbell#define ASIC_INTERNAL_SS_ON_TMDS 4 5034254885Sdumbbell#define ASIC_INTERNAL_SS_ON_HDMI 5 5035254885Sdumbbell#define ASIC_INTERNAL_SS_ON_LVDS 6 5036254885Sdumbbell#define ASIC_INTERNAL_SS_ON_DP 7 5037254885Sdumbbell#define ASIC_INTERNAL_SS_ON_DCPLL 8 5038254885Sdumbbell#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5039254885Sdumbbell#define ASIC_INTERNAL_VCE_SS 10 5040254885Sdumbbell 5041254885Sdumbbelltypedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5042254885Sdumbbell{ 5043254885Sdumbbell ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5044254885Sdumbbell //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5045254885Sdumbbell USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5046254885Sdumbbell USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5047254885Sdumbbell UCHAR ucClockIndication; //Indicate which clock source needs SS 5048254885Sdumbbell UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5049254885Sdumbbell UCHAR ucReserved[2]; 5050254885Sdumbbell}ATOM_ASIC_SS_ASSIGNMENT_V2; 5051254885Sdumbbell 5052254885Sdumbbell//ucSpreadSpectrumMode 5053254885Sdumbbell//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 5054254885Sdumbbell//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 5055254885Sdumbbell//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 5056254885Sdumbbell//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 5057254885Sdumbbell//#define ATOM_INTERNAL_SS_MASK 0x00000000 5058254885Sdumbbell//#define ATOM_EXTERNAL_SS_MASK 0x00000002 5059254885Sdumbbell 5060254885Sdumbbelltypedef struct _ATOM_ASIC_INTERNAL_SS_INFO 5061254885Sdumbbell{ 5062254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5063254885Sdumbbell ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 5064254885Sdumbbell}ATOM_ASIC_INTERNAL_SS_INFO; 5065254885Sdumbbell 5066254885Sdumbbelltypedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 5067254885Sdumbbell{ 5068254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5069254885Sdumbbell ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 5070254885Sdumbbell}ATOM_ASIC_INTERNAL_SS_INFO_V2; 5071254885Sdumbbell 5072254885Sdumbbelltypedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 5073254885Sdumbbell{ 5074254885Sdumbbell ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5075254885Sdumbbell //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5076254885Sdumbbell USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5077254885Sdumbbell USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5078254885Sdumbbell UCHAR ucClockIndication; //Indicate which clock source needs SS 5079254885Sdumbbell UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5080254885Sdumbbell UCHAR ucReserved[2]; 5081254885Sdumbbell}ATOM_ASIC_SS_ASSIGNMENT_V3; 5082254885Sdumbbell 5083254885Sdumbbelltypedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 5084254885Sdumbbell{ 5085254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5086254885Sdumbbell ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 5087254885Sdumbbell}ATOM_ASIC_INTERNAL_SS_INFO_V3; 5088254885Sdumbbell 5089254885Sdumbbell 5090254885Sdumbbell//==============================Scratch Pad Definition Portion=============================== 5091254885Sdumbbell#define ATOM_DEVICE_CONNECT_INFO_DEF 0 5092254885Sdumbbell#define ATOM_ROM_LOCATION_DEF 1 5093254885Sdumbbell#define ATOM_TV_STANDARD_DEF 2 5094254885Sdumbbell#define ATOM_ACTIVE_INFO_DEF 3 5095254885Sdumbbell#define ATOM_LCD_INFO_DEF 4 5096254885Sdumbbell#define ATOM_DOS_REQ_INFO_DEF 5 5097254885Sdumbbell#define ATOM_ACC_CHANGE_INFO_DEF 6 5098254885Sdumbbell#define ATOM_DOS_MODE_INFO_DEF 7 5099254885Sdumbbell#define ATOM_I2C_CHANNEL_STATUS_DEF 8 5100254885Sdumbbell#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 5101254885Sdumbbell#define ATOM_INTERNAL_TIMER_DEF 10 5102254885Sdumbbell 5103254885Sdumbbell// BIOS_0_SCRATCH Definition 5104254885Sdumbbell#define ATOM_S0_CRT1_MONO 0x00000001L 5105254885Sdumbbell#define ATOM_S0_CRT1_COLOR 0x00000002L 5106254885Sdumbbell#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 5107254885Sdumbbell 5108254885Sdumbbell#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 5109254885Sdumbbell#define ATOM_S0_TV1_SVIDEO_A 0x00000008L 5110254885Sdumbbell#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 5111254885Sdumbbell 5112254885Sdumbbell#define ATOM_S0_CV_A 0x00000010L 5113254885Sdumbbell#define ATOM_S0_CV_DIN_A 0x00000020L 5114254885Sdumbbell#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 5115254885Sdumbbell 5116254885Sdumbbell 5117254885Sdumbbell#define ATOM_S0_CRT2_MONO 0x00000100L 5118254885Sdumbbell#define ATOM_S0_CRT2_COLOR 0x00000200L 5119254885Sdumbbell#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 5120254885Sdumbbell 5121254885Sdumbbell#define ATOM_S0_TV1_COMPOSITE 0x00000400L 5122254885Sdumbbell#define ATOM_S0_TV1_SVIDEO 0x00000800L 5123254885Sdumbbell#define ATOM_S0_TV1_SCART 0x00004000L 5124254885Sdumbbell#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 5125254885Sdumbbell 5126254885Sdumbbell#define ATOM_S0_CV 0x00001000L 5127254885Sdumbbell#define ATOM_S0_CV_DIN 0x00002000L 5128254885Sdumbbell#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 5129254885Sdumbbell 5130254885Sdumbbell#define ATOM_S0_DFP1 0x00010000L 5131254885Sdumbbell#define ATOM_S0_DFP2 0x00020000L 5132254885Sdumbbell#define ATOM_S0_LCD1 0x00040000L 5133254885Sdumbbell#define ATOM_S0_LCD2 0x00080000L 5134254885Sdumbbell#define ATOM_S0_DFP6 0x00100000L 5135254885Sdumbbell#define ATOM_S0_DFP3 0x00200000L 5136254885Sdumbbell#define ATOM_S0_DFP4 0x00400000L 5137254885Sdumbbell#define ATOM_S0_DFP5 0x00800000L 5138254885Sdumbbell 5139254885Sdumbbell#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 5140254885Sdumbbell 5141254885Sdumbbell#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 5142254885Sdumbbell // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 5143254885Sdumbbell 5144254885Sdumbbell#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 5145254885Sdumbbell#define ATOM_S0_THERMAL_STATE_SHIFT 26 5146254885Sdumbbell 5147254885Sdumbbell#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 5148254885Sdumbbell#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 5149254885Sdumbbell 5150254885Sdumbbell#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 5151254885Sdumbbell#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 5152254885Sdumbbell#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 5153254885Sdumbbell#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 5154254885Sdumbbell 5155254885Sdumbbell//Byte aligned definition for BIOS usage 5156254885Sdumbbell#define ATOM_S0_CRT1_MONOb0 0x01 5157254885Sdumbbell#define ATOM_S0_CRT1_COLORb0 0x02 5158254885Sdumbbell#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 5159254885Sdumbbell 5160254885Sdumbbell#define ATOM_S0_TV1_COMPOSITEb0 0x04 5161254885Sdumbbell#define ATOM_S0_TV1_SVIDEOb0 0x08 5162254885Sdumbbell#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 5163254885Sdumbbell 5164254885Sdumbbell#define ATOM_S0_CVb0 0x10 5165254885Sdumbbell#define ATOM_S0_CV_DINb0 0x20 5166254885Sdumbbell#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 5167254885Sdumbbell 5168254885Sdumbbell#define ATOM_S0_CRT2_MONOb1 0x01 5169254885Sdumbbell#define ATOM_S0_CRT2_COLORb1 0x02 5170254885Sdumbbell#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 5171254885Sdumbbell 5172254885Sdumbbell#define ATOM_S0_TV1_COMPOSITEb1 0x04 5173254885Sdumbbell#define ATOM_S0_TV1_SVIDEOb1 0x08 5174254885Sdumbbell#define ATOM_S0_TV1_SCARTb1 0x40 5175254885Sdumbbell#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 5176254885Sdumbbell 5177254885Sdumbbell#define ATOM_S0_CVb1 0x10 5178254885Sdumbbell#define ATOM_S0_CV_DINb1 0x20 5179254885Sdumbbell#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 5180254885Sdumbbell 5181254885Sdumbbell#define ATOM_S0_DFP1b2 0x01 5182254885Sdumbbell#define ATOM_S0_DFP2b2 0x02 5183254885Sdumbbell#define ATOM_S0_LCD1b2 0x04 5184254885Sdumbbell#define ATOM_S0_LCD2b2 0x08 5185254885Sdumbbell#define ATOM_S0_DFP6b2 0x10 5186254885Sdumbbell#define ATOM_S0_DFP3b2 0x20 5187254885Sdumbbell#define ATOM_S0_DFP4b2 0x40 5188254885Sdumbbell#define ATOM_S0_DFP5b2 0x80 5189254885Sdumbbell 5190254885Sdumbbell 5191254885Sdumbbell#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 5192254885Sdumbbell#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 5193254885Sdumbbell 5194254885Sdumbbell#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 5195254885Sdumbbell#define ATOM_S0_LCD1_SHIFT 18 5196254885Sdumbbell 5197254885Sdumbbell// BIOS_1_SCRATCH Definition 5198254885Sdumbbell#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 5199254885Sdumbbell#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 5200254885Sdumbbell 5201254885Sdumbbell// BIOS_2_SCRATCH Definition 5202254885Sdumbbell#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 5203254885Sdumbbell#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 5204254885Sdumbbell#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 5205254885Sdumbbell 5206254885Sdumbbell#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 5207254885Sdumbbell#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 5208254885Sdumbbell#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 5209254885Sdumbbell 5210254885Sdumbbell#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 5211254885Sdumbbell#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 5212254885Sdumbbell 5213254885Sdumbbell#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 5214254885Sdumbbell#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 5215254885Sdumbbell#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 5216254885Sdumbbell#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 5217254885Sdumbbell#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 5218254885Sdumbbell#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 5219254885Sdumbbell 5220254885Sdumbbell 5221254885Sdumbbell//Byte aligned definition for BIOS usage 5222254885Sdumbbell#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 5223254885Sdumbbell#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 5224254885Sdumbbell#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 5225254885Sdumbbell 5226254885Sdumbbell#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 5227254885Sdumbbell#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 5228254885Sdumbbell#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 5229254885Sdumbbell#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 5230254885Sdumbbell#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 5231254885Sdumbbell#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 5232254885Sdumbbell 5233254885Sdumbbell 5234254885Sdumbbell// BIOS_3_SCRATCH Definition 5235254885Sdumbbell#define ATOM_S3_CRT1_ACTIVE 0x00000001L 5236254885Sdumbbell#define ATOM_S3_LCD1_ACTIVE 0x00000002L 5237254885Sdumbbell#define ATOM_S3_TV1_ACTIVE 0x00000004L 5238254885Sdumbbell#define ATOM_S3_DFP1_ACTIVE 0x00000008L 5239254885Sdumbbell#define ATOM_S3_CRT2_ACTIVE 0x00000010L 5240254885Sdumbbell#define ATOM_S3_LCD2_ACTIVE 0x00000020L 5241254885Sdumbbell#define ATOM_S3_DFP6_ACTIVE 0x00000040L 5242254885Sdumbbell#define ATOM_S3_DFP2_ACTIVE 0x00000080L 5243254885Sdumbbell#define ATOM_S3_CV_ACTIVE 0x00000100L 5244254885Sdumbbell#define ATOM_S3_DFP3_ACTIVE 0x00000200L 5245254885Sdumbbell#define ATOM_S3_DFP4_ACTIVE 0x00000400L 5246254885Sdumbbell#define ATOM_S3_DFP5_ACTIVE 0x00000800L 5247254885Sdumbbell 5248254885Sdumbbell#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 5249254885Sdumbbell 5250254885Sdumbbell#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 5251254885Sdumbbell#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 5252254885Sdumbbell 5253254885Sdumbbell#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 5254254885Sdumbbell#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 5255254885Sdumbbell#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 5256254885Sdumbbell#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 5257254885Sdumbbell#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 5258254885Sdumbbell#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 5259254885Sdumbbell#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 5260254885Sdumbbell#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 5261254885Sdumbbell#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 5262254885Sdumbbell#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 5263254885Sdumbbell#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 5264254885Sdumbbell#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 5265254885Sdumbbell 5266254885Sdumbbell#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 5267254885Sdumbbell#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 5268254885Sdumbbell//Below two definitions are not supported in pplib, but in the old powerplay in DAL 5269254885Sdumbbell#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 5270254885Sdumbbell#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 5271254885Sdumbbell 5272254885Sdumbbell//Byte aligned definition for BIOS usage 5273254885Sdumbbell#define ATOM_S3_CRT1_ACTIVEb0 0x01 5274254885Sdumbbell#define ATOM_S3_LCD1_ACTIVEb0 0x02 5275254885Sdumbbell#define ATOM_S3_TV1_ACTIVEb0 0x04 5276254885Sdumbbell#define ATOM_S3_DFP1_ACTIVEb0 0x08 5277254885Sdumbbell#define ATOM_S3_CRT2_ACTIVEb0 0x10 5278254885Sdumbbell#define ATOM_S3_LCD2_ACTIVEb0 0x20 5279254885Sdumbbell#define ATOM_S3_DFP6_ACTIVEb0 0x40 5280254885Sdumbbell#define ATOM_S3_DFP2_ACTIVEb0 0x80 5281254885Sdumbbell#define ATOM_S3_CV_ACTIVEb1 0x01 5282254885Sdumbbell#define ATOM_S3_DFP3_ACTIVEb1 0x02 5283254885Sdumbbell#define ATOM_S3_DFP4_ACTIVEb1 0x04 5284254885Sdumbbell#define ATOM_S3_DFP5_ACTIVEb1 0x08 5285254885Sdumbbell 5286254885Sdumbbell#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 5287254885Sdumbbell 5288254885Sdumbbell#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 5289254885Sdumbbell#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 5290254885Sdumbbell#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 5291254885Sdumbbell#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 5292254885Sdumbbell#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 5293254885Sdumbbell#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 5294254885Sdumbbell#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 5295254885Sdumbbell#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 5296254885Sdumbbell#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 5297254885Sdumbbell#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 5298254885Sdumbbell#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 5299254885Sdumbbell#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 5300254885Sdumbbell 5301254885Sdumbbell#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 5302254885Sdumbbell 5303254885Sdumbbell// BIOS_4_SCRATCH Definition 5304254885Sdumbbell#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 5305254885Sdumbbell#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 5306254885Sdumbbell#define ATOM_S4_LCD1_REFRESH_SHIFT 8 5307254885Sdumbbell 5308254885Sdumbbell//Byte aligned definition for BIOS usage 5309254885Sdumbbell#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 5310254885Sdumbbell#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 5311254885Sdumbbell#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 5312254885Sdumbbell 5313254885Sdumbbell// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 5314254885Sdumbbell#define ATOM_S5_DOS_REQ_CRT1b0 0x01 5315254885Sdumbbell#define ATOM_S5_DOS_REQ_LCD1b0 0x02 5316254885Sdumbbell#define ATOM_S5_DOS_REQ_TV1b0 0x04 5317254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP1b0 0x08 5318254885Sdumbbell#define ATOM_S5_DOS_REQ_CRT2b0 0x10 5319254885Sdumbbell#define ATOM_S5_DOS_REQ_LCD2b0 0x20 5320254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP6b0 0x40 5321254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP2b0 0x80 5322254885Sdumbbell#define ATOM_S5_DOS_REQ_CVb1 0x01 5323254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP3b1 0x02 5324254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP4b1 0x04 5325254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP5b1 0x08 5326254885Sdumbbell 5327254885Sdumbbell#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 5328254885Sdumbbell 5329254885Sdumbbell#define ATOM_S5_DOS_REQ_CRT1 0x0001 5330254885Sdumbbell#define ATOM_S5_DOS_REQ_LCD1 0x0002 5331254885Sdumbbell#define ATOM_S5_DOS_REQ_TV1 0x0004 5332254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP1 0x0008 5333254885Sdumbbell#define ATOM_S5_DOS_REQ_CRT2 0x0010 5334254885Sdumbbell#define ATOM_S5_DOS_REQ_LCD2 0x0020 5335254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP6 0x0040 5336254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP2 0x0080 5337254885Sdumbbell#define ATOM_S5_DOS_REQ_CV 0x0100 5338254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP3 0x0200 5339254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP4 0x0400 5340254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP5 0x0800 5341254885Sdumbbell 5342254885Sdumbbell#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 5343254885Sdumbbell#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 5344254885Sdumbbell#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 5345254885Sdumbbell#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 5346254885Sdumbbell#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 5347254885Sdumbbell (ATOM_S5_DOS_FORCE_CVb3<<8)) 5348254885Sdumbbell 5349254885Sdumbbell// BIOS_6_SCRATCH Definition 5350254885Sdumbbell#define ATOM_S6_DEVICE_CHANGE 0x00000001L 5351254885Sdumbbell#define ATOM_S6_SCALER_CHANGE 0x00000002L 5352254885Sdumbbell#define ATOM_S6_LID_CHANGE 0x00000004L 5353254885Sdumbbell#define ATOM_S6_DOCKING_CHANGE 0x00000008L 5354254885Sdumbbell#define ATOM_S6_ACC_MODE 0x00000010L 5355254885Sdumbbell#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 5356254885Sdumbbell#define ATOM_S6_LID_STATE 0x00000040L 5357254885Sdumbbell#define ATOM_S6_DOCK_STATE 0x00000080L 5358254885Sdumbbell#define ATOM_S6_CRITICAL_STATE 0x00000100L 5359254885Sdumbbell#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 5360254885Sdumbbell#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 5361254885Sdumbbell#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 5362254885Sdumbbell#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 5363254885Sdumbbell#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 5364254885Sdumbbell 5365254885Sdumbbell#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 5366254885Sdumbbell#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 5367254885Sdumbbell 5368254885Sdumbbell#define ATOM_S6_ACC_REQ_CRT1 0x00010000L 5369254885Sdumbbell#define ATOM_S6_ACC_REQ_LCD1 0x00020000L 5370254885Sdumbbell#define ATOM_S6_ACC_REQ_TV1 0x00040000L 5371254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP1 0x00080000L 5372254885Sdumbbell#define ATOM_S6_ACC_REQ_CRT2 0x00100000L 5373254885Sdumbbell#define ATOM_S6_ACC_REQ_LCD2 0x00200000L 5374254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP6 0x00400000L 5375254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP2 0x00800000L 5376254885Sdumbbell#define ATOM_S6_ACC_REQ_CV 0x01000000L 5377254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP3 0x02000000L 5378254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP4 0x04000000L 5379254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP5 0x08000000L 5380254885Sdumbbell 5381254885Sdumbbell#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 5382254885Sdumbbell#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 5383254885Sdumbbell#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 5384254885Sdumbbell#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 5385254885Sdumbbell#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 5386254885Sdumbbell 5387254885Sdumbbell//Byte aligned definition for BIOS usage 5388254885Sdumbbell#define ATOM_S6_DEVICE_CHANGEb0 0x01 5389254885Sdumbbell#define ATOM_S6_SCALER_CHANGEb0 0x02 5390254885Sdumbbell#define ATOM_S6_LID_CHANGEb0 0x04 5391254885Sdumbbell#define ATOM_S6_DOCKING_CHANGEb0 0x08 5392254885Sdumbbell#define ATOM_S6_ACC_MODEb0 0x10 5393254885Sdumbbell#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 5394254885Sdumbbell#define ATOM_S6_LID_STATEb0 0x40 5395254885Sdumbbell#define ATOM_S6_DOCK_STATEb0 0x80 5396254885Sdumbbell#define ATOM_S6_CRITICAL_STATEb1 0x01 5397254885Sdumbbell#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 5398254885Sdumbbell#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 5399254885Sdumbbell#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 5400254885Sdumbbell#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 5401254885Sdumbbell#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 5402254885Sdumbbell 5403254885Sdumbbell#define ATOM_S6_ACC_REQ_CRT1b2 0x01 5404254885Sdumbbell#define ATOM_S6_ACC_REQ_LCD1b2 0x02 5405254885Sdumbbell#define ATOM_S6_ACC_REQ_TV1b2 0x04 5406254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP1b2 0x08 5407254885Sdumbbell#define ATOM_S6_ACC_REQ_CRT2b2 0x10 5408254885Sdumbbell#define ATOM_S6_ACC_REQ_LCD2b2 0x20 5409254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP6b2 0x40 5410254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP2b2 0x80 5411254885Sdumbbell#define ATOM_S6_ACC_REQ_CVb3 0x01 5412254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP3b3 0x02 5413254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP4b3 0x04 5414254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP5b3 0x08 5415254885Sdumbbell 5416254885Sdumbbell#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 5417254885Sdumbbell#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 5418254885Sdumbbell#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 5419254885Sdumbbell#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 5420254885Sdumbbell#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 5421254885Sdumbbell 5422254885Sdumbbell#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 5423254885Sdumbbell#define ATOM_S6_SCALER_CHANGE_SHIFT 1 5424254885Sdumbbell#define ATOM_S6_LID_CHANGE_SHIFT 2 5425254885Sdumbbell#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 5426254885Sdumbbell#define ATOM_S6_ACC_MODE_SHIFT 4 5427254885Sdumbbell#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 5428254885Sdumbbell#define ATOM_S6_LID_STATE_SHIFT 6 5429254885Sdumbbell#define ATOM_S6_DOCK_STATE_SHIFT 7 5430254885Sdumbbell#define ATOM_S6_CRITICAL_STATE_SHIFT 8 5431254885Sdumbbell#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 5432254885Sdumbbell#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 5433254885Sdumbbell#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 5434254885Sdumbbell#define ATOM_S6_REQ_SCALER_SHIFT 12 5435254885Sdumbbell#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 5436254885Sdumbbell#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 5437254885Sdumbbell#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 5438254885Sdumbbell#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 5439254885Sdumbbell#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 5440254885Sdumbbell#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 5441254885Sdumbbell#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 5442254885Sdumbbell 5443254885Sdumbbell// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 5444254885Sdumbbell#define ATOM_S7_DOS_MODE_TYPEb0 0x03 5445254885Sdumbbell#define ATOM_S7_DOS_MODE_VGAb0 0x00 5446254885Sdumbbell#define ATOM_S7_DOS_MODE_VESAb0 0x01 5447254885Sdumbbell#define ATOM_S7_DOS_MODE_EXTb0 0x02 5448254885Sdumbbell#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5449254885Sdumbbell#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5450254885Sdumbbell#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5451254885Sdumbbell#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5452254885Sdumbbell 5453254885Sdumbbell#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 5454254885Sdumbbell 5455254885Sdumbbell// BIOS_8_SCRATCH Definition 5456254885Sdumbbell#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 5457254885Sdumbbell#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 5458254885Sdumbbell 5459254885Sdumbbell#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 5460254885Sdumbbell#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 5461254885Sdumbbell 5462254885Sdumbbell// BIOS_9_SCRATCH Definition 5463254885Sdumbbell#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 5464254885Sdumbbell#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 5465254885Sdumbbell#endif 5466254885Sdumbbell#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 5467254885Sdumbbell#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 5468254885Sdumbbell#endif 5469254885Sdumbbell#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 5470254885Sdumbbell#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 5471254885Sdumbbell#endif 5472254885Sdumbbell#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 5473254885Sdumbbell#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 5474254885Sdumbbell#endif 5475254885Sdumbbell 5476254885Sdumbbell 5477254885Sdumbbell#define ATOM_FLAG_SET 0x20 5478254885Sdumbbell#define ATOM_FLAG_CLEAR 0 5479254885Sdumbbell#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 5480254885Sdumbbell#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 5481254885Sdumbbell#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 5482254885Sdumbbell#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 5483254885Sdumbbell#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 5484254885Sdumbbell 5485254885Sdumbbell#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 5486254885Sdumbbell#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 5487254885Sdumbbell 5488254885Sdumbbell#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 5489254885Sdumbbell#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 5490254885Sdumbbell#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 5491254885Sdumbbell 5492254885Sdumbbell#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 5493254885Sdumbbell#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 5494254885Sdumbbell#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 5495254885Sdumbbell 5496254885Sdumbbell#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 5497254885Sdumbbell#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 5498254885Sdumbbell 5499254885Sdumbbell#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 5500254885Sdumbbell#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 5501254885Sdumbbell 5502254885Sdumbbell#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 5503254885Sdumbbell#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 5504254885Sdumbbell 5505254885Sdumbbell#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5506254885Sdumbbell 5507254885Sdumbbell#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5508254885Sdumbbell 5509254885Sdumbbell#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 5510254885Sdumbbell#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 5511254885Sdumbbell#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 5512254885Sdumbbell#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 5513254885Sdumbbell 5514254885Sdumbbell/****************************************************************************/ 5515254885Sdumbbell//Portion II: Definitinos only used in Driver 5516254885Sdumbbell/****************************************************************************/ 5517254885Sdumbbell 5518254885Sdumbbell// Macros used by driver 5519254885Sdumbbell#ifdef __cplusplus 5520254885Sdumbbell#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 5521254885Sdumbbell 5522254885Sdumbbell#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 5523254885Sdumbbell#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 5524254885Sdumbbell#else // not __cplusplus 5525254885Sdumbbell#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 5526254885Sdumbbell 5527254885Sdumbbell#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 5528254885Sdumbbell#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 5529254885Sdumbbell#endif // __cplusplus 5530254885Sdumbbell 5531254885Sdumbbell#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 5532254885Sdumbbell#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 5533254885Sdumbbell 5534254885Sdumbbell/****************************************************************************/ 5535254885Sdumbbell//Portion III: Definitinos only used in VBIOS 5536254885Sdumbbell/****************************************************************************/ 5537254885Sdumbbell#define ATOM_DAC_SRC 0x80 5538254885Sdumbbell#define ATOM_SRC_DAC1 0 5539254885Sdumbbell#define ATOM_SRC_DAC2 0x80 5540254885Sdumbbell 5541254885Sdumbbelltypedef struct _MEMORY_PLLINIT_PARAMETERS 5542254885Sdumbbell{ 5543254885Sdumbbell ULONG ulTargetMemoryClock; //In 10Khz unit 5544254885Sdumbbell UCHAR ucAction; //not define yet 5545254885Sdumbbell UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 5546254885Sdumbbell UCHAR ucFbDiv; //FB value 5547254885Sdumbbell UCHAR ucPostDiv; //Post div 5548254885Sdumbbell}MEMORY_PLLINIT_PARAMETERS; 5549254885Sdumbbell 5550254885Sdumbbell#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 5551254885Sdumbbell 5552254885Sdumbbell 5553254885Sdumbbell#define GPIO_PIN_WRITE 0x01 5554254885Sdumbbell#define GPIO_PIN_READ 0x00 5555254885Sdumbbell 5556254885Sdumbbelltypedef struct _GPIO_PIN_CONTROL_PARAMETERS 5557254885Sdumbbell{ 5558254885Sdumbbell UCHAR ucGPIO_ID; //return value, read from GPIO pins 5559254885Sdumbbell UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 5560254885Sdumbbell UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 5561254885Sdumbbell UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 5562254885Sdumbbell}GPIO_PIN_CONTROL_PARAMETERS; 5563254885Sdumbbell 5564254885Sdumbbelltypedef struct _ENABLE_SCALER_PARAMETERS 5565254885Sdumbbell{ 5566254885Sdumbbell UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 5567254885Sdumbbell UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 5568254885Sdumbbell UCHAR ucTVStandard; // 5569254885Sdumbbell UCHAR ucPadding[1]; 5570254885Sdumbbell}ENABLE_SCALER_PARAMETERS; 5571254885Sdumbbell#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 5572254885Sdumbbell 5573254885Sdumbbell//ucEnable: 5574254885Sdumbbell#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 5575254885Sdumbbell#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 5576254885Sdumbbell#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 5577254885Sdumbbell#define SCALER_ENABLE_MULTITAP_MODE 3 5578254885Sdumbbell 5579254885Sdumbbelltypedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 5580254885Sdumbbell{ 5581254885Sdumbbell ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 5582254885Sdumbbell UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 5583254885Sdumbbell UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 5584254885Sdumbbell UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 5585254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5586254885Sdumbbell}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 5587254885Sdumbbell 5588254885Sdumbbelltypedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 5589254885Sdumbbell{ 5590254885Sdumbbell ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 5591254885Sdumbbell ENABLE_CRTC_PARAMETERS sReserved; 5592254885Sdumbbell}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 5593254885Sdumbbell 5594254885Sdumbbelltypedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 5595254885Sdumbbell{ 5596254885Sdumbbell USHORT usHight; // Image Hight 5597254885Sdumbbell USHORT usWidth; // Image Width 5598254885Sdumbbell UCHAR ucSurface; // Surface 1 or 2 5599254885Sdumbbell UCHAR ucPadding[3]; 5600254885Sdumbbell}ENABLE_GRAPH_SURFACE_PARAMETERS; 5601254885Sdumbbell 5602254885Sdumbbelltypedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 5603254885Sdumbbell{ 5604254885Sdumbbell USHORT usHight; // Image Hight 5605254885Sdumbbell USHORT usWidth; // Image Width 5606254885Sdumbbell UCHAR ucSurface; // Surface 1 or 2 5607254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5608254885Sdumbbell UCHAR ucPadding[2]; 5609254885Sdumbbell}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 5610254885Sdumbbell 5611254885Sdumbbelltypedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 5612254885Sdumbbell{ 5613254885Sdumbbell USHORT usHight; // Image Hight 5614254885Sdumbbell USHORT usWidth; // Image Width 5615254885Sdumbbell UCHAR ucSurface; // Surface 1 or 2 5616254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5617254885Sdumbbell USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 5618254885Sdumbbell}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 5619254885Sdumbbell 5620254885Sdumbbelltypedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 5621254885Sdumbbell{ 5622254885Sdumbbell USHORT usHight; // Image Hight 5623254885Sdumbbell USHORT usWidth; // Image Width 5624254885Sdumbbell USHORT usGraphPitch; 5625254885Sdumbbell UCHAR ucColorDepth; 5626254885Sdumbbell UCHAR ucPixelFormat; 5627254885Sdumbbell UCHAR ucSurface; // Surface 1 or 2 5628254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5629254885Sdumbbell UCHAR ucModeType; 5630254885Sdumbbell UCHAR ucReserved; 5631254885Sdumbbell}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 5632254885Sdumbbell 5633254885Sdumbbell// ucEnable 5634254885Sdumbbell#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 5635254885Sdumbbell#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 5636254885Sdumbbell 5637254885Sdumbbelltypedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 5638254885Sdumbbell{ 5639254885Sdumbbell ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 5640254885Sdumbbell ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 5641254885Sdumbbell}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 5642254885Sdumbbell 5643254885Sdumbbelltypedef struct _MEMORY_CLEAN_UP_PARAMETERS 5644254885Sdumbbell{ 5645254885Sdumbbell USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address 5646254885Sdumbbell USHORT usMemorySize; //8Kb blocks aligned 5647254885Sdumbbell}MEMORY_CLEAN_UP_PARAMETERS; 5648254885Sdumbbell#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 5649254885Sdumbbell 5650254885Sdumbbelltypedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 5651254885Sdumbbell{ 5652254885Sdumbbell USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 5653254885Sdumbbell USHORT usY_Size; 5654254885Sdumbbell}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 5655254885Sdumbbell 5656254885Sdumbbelltypedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 5657254885Sdumbbell{ 5658254885Sdumbbell union{ 5659254885Sdumbbell USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 5660254885Sdumbbell USHORT usSurface; 5661254885Sdumbbell }; 5662254885Sdumbbell USHORT usY_Size; 5663254885Sdumbbell USHORT usDispXStart; 5664254885Sdumbbell USHORT usDispYStart; 5665254885Sdumbbell}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 5666254885Sdumbbell 5667254885Sdumbbell 5668254885Sdumbbelltypedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 5669254885Sdumbbell{ 5670254885Sdumbbell UCHAR ucLutId; 5671254885Sdumbbell UCHAR ucAction; 5672254885Sdumbbell USHORT usLutStartIndex; 5673254885Sdumbbell USHORT usLutLength; 5674254885Sdumbbell USHORT usLutOffsetInVram; 5675254885Sdumbbell}PALETTE_DATA_CONTROL_PARAMETERS_V3; 5676254885Sdumbbell 5677254885Sdumbbell// ucAction: 5678254885Sdumbbell#define PALETTE_DATA_AUTO_FILL 1 5679254885Sdumbbell#define PALETTE_DATA_READ 2 5680254885Sdumbbell#define PALETTE_DATA_WRITE 3 5681254885Sdumbbell 5682254885Sdumbbell 5683254885Sdumbbelltypedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 5684254885Sdumbbell{ 5685254885Sdumbbell UCHAR ucInterruptId; 5686254885Sdumbbell UCHAR ucServiceId; 5687254885Sdumbbell UCHAR ucStatus; 5688254885Sdumbbell UCHAR ucReserved; 5689254885Sdumbbell}INTERRUPT_SERVICE_PARAMETER_V2; 5690254885Sdumbbell 5691254885Sdumbbell// ucInterruptId 5692254885Sdumbbell#define HDP1_INTERRUPT_ID 1 5693254885Sdumbbell#define HDP2_INTERRUPT_ID 2 5694254885Sdumbbell#define HDP3_INTERRUPT_ID 3 5695254885Sdumbbell#define HDP4_INTERRUPT_ID 4 5696254885Sdumbbell#define HDP5_INTERRUPT_ID 5 5697254885Sdumbbell#define HDP6_INTERRUPT_ID 6 5698254885Sdumbbell#define SW_INTERRUPT_ID 11 5699254885Sdumbbell 5700254885Sdumbbell// ucAction 5701254885Sdumbbell#define INTERRUPT_SERVICE_GEN_SW_INT 1 5702254885Sdumbbell#define INTERRUPT_SERVICE_GET_STATUS 2 5703254885Sdumbbell 5704254885Sdumbbell // ucStatus 5705254885Sdumbbell#define INTERRUPT_STATUS__INT_TRIGGER 1 5706254885Sdumbbell#define INTERRUPT_STATUS__HPD_HIGH 2 5707254885Sdumbbell 5708254885Sdumbbelltypedef struct _INDIRECT_IO_ACCESS 5709254885Sdumbbell{ 5710254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5711254885Sdumbbell UCHAR IOAccessSequence[256]; 5712254885Sdumbbell} INDIRECT_IO_ACCESS; 5713254885Sdumbbell 5714254885Sdumbbell#define INDIRECT_READ 0x00 5715254885Sdumbbell#define INDIRECT_WRITE 0x80 5716254885Sdumbbell 5717254885Sdumbbell#define INDIRECT_IO_MM 0 5718254885Sdumbbell#define INDIRECT_IO_PLL 1 5719254885Sdumbbell#define INDIRECT_IO_MC 2 5720254885Sdumbbell#define INDIRECT_IO_PCIE 3 5721254885Sdumbbell#define INDIRECT_IO_PCIEP 4 5722254885Sdumbbell#define INDIRECT_IO_NBMISC 5 5723254885Sdumbbell 5724254885Sdumbbell#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 5725254885Sdumbbell#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 5726254885Sdumbbell#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 5727254885Sdumbbell#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 5728254885Sdumbbell#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 5729254885Sdumbbell#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 5730254885Sdumbbell#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 5731254885Sdumbbell#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 5732254885Sdumbbell#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 5733254885Sdumbbell#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 5734254885Sdumbbell 5735254885Sdumbbelltypedef struct _ATOM_OEM_INFO 5736254885Sdumbbell{ 5737254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5738254885Sdumbbell ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 5739254885Sdumbbell}ATOM_OEM_INFO; 5740254885Sdumbbell 5741254885Sdumbbelltypedef struct _ATOM_TV_MODE 5742254885Sdumbbell{ 5743254885Sdumbbell UCHAR ucVMode_Num; //Video mode number 5744254885Sdumbbell UCHAR ucTV_Mode_Num; //Internal TV mode number 5745254885Sdumbbell}ATOM_TV_MODE; 5746254885Sdumbbell 5747254885Sdumbbelltypedef struct _ATOM_BIOS_INT_TVSTD_MODE 5748254885Sdumbbell{ 5749254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5750254885Sdumbbell USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 5751254885Sdumbbell USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 5752254885Sdumbbell USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 5753254885Sdumbbell USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5754254885Sdumbbell USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5755254885Sdumbbell}ATOM_BIOS_INT_TVSTD_MODE; 5756254885Sdumbbell 5757254885Sdumbbell 5758254885Sdumbbelltypedef struct _ATOM_TV_MODE_SCALER_PTR 5759254885Sdumbbell{ 5760254885Sdumbbell USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 5761254885Sdumbbell USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 5762254885Sdumbbell UCHAR ucTV_Mode_Num; 5763254885Sdumbbell}ATOM_TV_MODE_SCALER_PTR; 5764254885Sdumbbell 5765254885Sdumbbelltypedef struct _ATOM_STANDARD_VESA_TIMING 5766254885Sdumbbell{ 5767254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5768254885Sdumbbell ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 5769254885Sdumbbell}ATOM_STANDARD_VESA_TIMING; 5770254885Sdumbbell 5771254885Sdumbbell 5772254885Sdumbbelltypedef struct _ATOM_STD_FORMAT 5773254885Sdumbbell{ 5774254885Sdumbbell USHORT usSTD_HDisp; 5775254885Sdumbbell USHORT usSTD_VDisp; 5776254885Sdumbbell USHORT usSTD_RefreshRate; 5777254885Sdumbbell USHORT usReserved; 5778254885Sdumbbell}ATOM_STD_FORMAT; 5779254885Sdumbbell 5780254885Sdumbbelltypedef struct _ATOM_VESA_TO_EXTENDED_MODE 5781254885Sdumbbell{ 5782254885Sdumbbell USHORT usVESA_ModeNumber; 5783254885Sdumbbell USHORT usExtendedModeNumber; 5784254885Sdumbbell}ATOM_VESA_TO_EXTENDED_MODE; 5785254885Sdumbbell 5786254885Sdumbbelltypedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 5787254885Sdumbbell{ 5788254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5789254885Sdumbbell ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 5790254885Sdumbbell}ATOM_VESA_TO_INTENAL_MODE_LUT; 5791254885Sdumbbell 5792254885Sdumbbell/*************** ATOM Memory Related Data Structure ***********************/ 5793254885Sdumbbelltypedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 5794254885Sdumbbell UCHAR ucMemoryType; 5795254885Sdumbbell UCHAR ucMemoryVendor; 5796254885Sdumbbell UCHAR ucAdjMCId; 5797254885Sdumbbell UCHAR ucDynClkId; 5798254885Sdumbbell ULONG ulDllResetClkRange; 5799254885Sdumbbell}ATOM_MEMORY_VENDOR_BLOCK; 5800254885Sdumbbell 5801254885Sdumbbell 5802254885Sdumbbelltypedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 5803254885Sdumbbell#if ATOM_BIG_ENDIAN 5804254885Sdumbbell ULONG ucMemBlkId:8; 5805254885Sdumbbell ULONG ulMemClockRange:24; 5806254885Sdumbbell#else 5807254885Sdumbbell ULONG ulMemClockRange:24; 5808254885Sdumbbell ULONG ucMemBlkId:8; 5809254885Sdumbbell#endif 5810254885Sdumbbell}ATOM_MEMORY_SETTING_ID_CONFIG; 5811254885Sdumbbell 5812254885Sdumbbelltypedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 5813254885Sdumbbell{ 5814254885Sdumbbell ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 5815254885Sdumbbell ULONG ulAccess; 5816254885Sdumbbell}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 5817254885Sdumbbell 5818254885Sdumbbell 5819254885Sdumbbelltypedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 5820254885Sdumbbell ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 5821254885Sdumbbell ULONG aulMemData[1]; 5822254885Sdumbbell}ATOM_MEMORY_SETTING_DATA_BLOCK; 5823254885Sdumbbell 5824254885Sdumbbell 5825254885Sdumbbelltypedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 5826254885Sdumbbell USHORT usRegIndex; // MC register index 5827254885Sdumbbell UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 5828254885Sdumbbell}ATOM_INIT_REG_INDEX_FORMAT; 5829254885Sdumbbell 5830254885Sdumbbell 5831254885Sdumbbelltypedef struct _ATOM_INIT_REG_BLOCK{ 5832254885Sdumbbell USHORT usRegIndexTblSize; //size of asRegIndexBuf 5833254885Sdumbbell USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 5834254885Sdumbbell ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 5835254885Sdumbbell ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 5836254885Sdumbbell}ATOM_INIT_REG_BLOCK; 5837254885Sdumbbell 5838254885Sdumbbell#define END_OF_REG_INDEX_BLOCK 0x0ffff 5839254885Sdumbbell#define END_OF_REG_DATA_BLOCK 0x00000000 5840254885Sdumbbell#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 5841254885Sdumbbell#define CLOCK_RANGE_HIGHEST 0x00ffffff 5842254885Sdumbbell 5843254885Sdumbbell#define VALUE_DWORD SIZEOF ULONG 5844254885Sdumbbell#define VALUE_SAME_AS_ABOVE 0 5845254885Sdumbbell#define VALUE_MASK_DWORD 0x84 5846254885Sdumbbell 5847254885Sdumbbell#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 5848254885Sdumbbell#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 5849254885Sdumbbell#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 5850254885Sdumbbell//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 5851254885Sdumbbell#define ACCESS_PLACEHOLDER 0x80 5852254885Sdumbbell 5853254885Sdumbbelltypedef struct _ATOM_MC_INIT_PARAM_TABLE 5854254885Sdumbbell{ 5855254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 5856254885Sdumbbell USHORT usAdjustARB_SEQDataOffset; 5857254885Sdumbbell USHORT usMCInitMemTypeTblOffset; 5858254885Sdumbbell USHORT usMCInitCommonTblOffset; 5859254885Sdumbbell USHORT usMCInitPowerDownTblOffset; 5860254885Sdumbbell ULONG ulARB_SEQDataBuf[32]; 5861254885Sdumbbell ATOM_INIT_REG_BLOCK asMCInitMemType; 5862254885Sdumbbell ATOM_INIT_REG_BLOCK asMCInitCommon; 5863254885Sdumbbell}ATOM_MC_INIT_PARAM_TABLE; 5864254885Sdumbbell 5865254885Sdumbbell 5866254885Sdumbbell#define _4Mx16 0x2 5867254885Sdumbbell#define _4Mx32 0x3 5868254885Sdumbbell#define _8Mx16 0x12 5869254885Sdumbbell#define _8Mx32 0x13 5870254885Sdumbbell#define _16Mx16 0x22 5871254885Sdumbbell#define _16Mx32 0x23 5872254885Sdumbbell#define _32Mx16 0x32 5873254885Sdumbbell#define _32Mx32 0x33 5874254885Sdumbbell#define _64Mx8 0x41 5875254885Sdumbbell#define _64Mx16 0x42 5876254885Sdumbbell#define _64Mx32 0x43 5877254885Sdumbbell#define _128Mx8 0x51 5878254885Sdumbbell#define _128Mx16 0x52 5879254885Sdumbbell#define _256Mx8 0x61 5880254885Sdumbbell#define _256Mx16 0x62 5881254885Sdumbbell 5882254885Sdumbbell#define SAMSUNG 0x1 5883254885Sdumbbell#define INFINEON 0x2 5884254885Sdumbbell#define ELPIDA 0x3 5885254885Sdumbbell#define ETRON 0x4 5886254885Sdumbbell#define NANYA 0x5 5887254885Sdumbbell#define HYNIX 0x6 5888254885Sdumbbell#define MOSEL 0x7 5889254885Sdumbbell#define WINBOND 0x8 5890254885Sdumbbell#define ESMT 0x9 5891254885Sdumbbell#define MICRON 0xF 5892254885Sdumbbell 5893254885Sdumbbell#define QIMONDA INFINEON 5894254885Sdumbbell#define PROMOS MOSEL 5895254885Sdumbbell#define KRETON INFINEON 5896254885Sdumbbell#define ELIXIR NANYA 5897254885Sdumbbell 5898254885Sdumbbell/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 5899254885Sdumbbell 5900254885Sdumbbell#define UCODE_ROM_START_ADDRESS 0x1b800 5901254885Sdumbbell#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 5902254885Sdumbbell 5903254885Sdumbbell//uCode block header for reference 5904254885Sdumbbell 5905254885Sdumbbelltypedef struct _MCuCodeHeader 5906254885Sdumbbell{ 5907254885Sdumbbell ULONG ulSignature; 5908254885Sdumbbell UCHAR ucRevision; 5909254885Sdumbbell UCHAR ucChecksum; 5910254885Sdumbbell UCHAR ucReserved1; 5911254885Sdumbbell UCHAR ucReserved2; 5912254885Sdumbbell USHORT usParametersLength; 5913254885Sdumbbell USHORT usUCodeLength; 5914254885Sdumbbell USHORT usReserved1; 5915254885Sdumbbell USHORT usReserved2; 5916254885Sdumbbell} MCuCodeHeader; 5917254885Sdumbbell 5918254885Sdumbbell////////////////////////////////////////////////////////////////////////////////// 5919254885Sdumbbell 5920254885Sdumbbell#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 5921254885Sdumbbell 5922254885Sdumbbell#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 5923254885Sdumbbelltypedef struct _ATOM_VRAM_MODULE_V1 5924254885Sdumbbell{ 5925254885Sdumbbell ULONG ulReserved; 5926254885Sdumbbell USHORT usEMRSValue; 5927254885Sdumbbell USHORT usMRSValue; 5928254885Sdumbbell USHORT usReserved; 5929254885Sdumbbell UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5930254885Sdumbbell UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 5931254885Sdumbbell UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 5932254885Sdumbbell UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5933254885Sdumbbell UCHAR ucRow; // Number of Row,in power of 2; 5934254885Sdumbbell UCHAR ucColumn; // Number of Column,in power of 2; 5935254885Sdumbbell UCHAR ucBank; // Nunber of Bank; 5936254885Sdumbbell UCHAR ucRank; // Number of Rank, in power of 2 5937254885Sdumbbell UCHAR ucChannelNum; // Number of channel; 5938254885Sdumbbell UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5939254885Sdumbbell UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5940254885Sdumbbell UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5941254885Sdumbbell UCHAR ucReserved[2]; 5942254885Sdumbbell}ATOM_VRAM_MODULE_V1; 5943254885Sdumbbell 5944254885Sdumbbell 5945254885Sdumbbelltypedef struct _ATOM_VRAM_MODULE_V2 5946254885Sdumbbell{ 5947254885Sdumbbell ULONG ulReserved; 5948254885Sdumbbell ULONG ulFlags; // To enable/disable functionalities based on memory type 5949254885Sdumbbell ULONG ulEngineClock; // Override of default engine clock for particular memory type 5950254885Sdumbbell ULONG ulMemoryClock; // Override of default memory clock for particular memory type 5951254885Sdumbbell USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5952254885Sdumbbell USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5953254885Sdumbbell USHORT usEMRSValue; 5954254885Sdumbbell USHORT usMRSValue; 5955254885Sdumbbell USHORT usReserved; 5956254885Sdumbbell UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5957254885Sdumbbell UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 5958254885Sdumbbell UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 5959254885Sdumbbell UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5960254885Sdumbbell UCHAR ucRow; // Number of Row,in power of 2; 5961254885Sdumbbell UCHAR ucColumn; // Number of Column,in power of 2; 5962254885Sdumbbell UCHAR ucBank; // Nunber of Bank; 5963254885Sdumbbell UCHAR ucRank; // Number of Rank, in power of 2 5964254885Sdumbbell UCHAR ucChannelNum; // Number of channel; 5965254885Sdumbbell UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5966254885Sdumbbell UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5967254885Sdumbbell UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5968254885Sdumbbell UCHAR ucRefreshRateFactor; 5969254885Sdumbbell UCHAR ucReserved[3]; 5970254885Sdumbbell}ATOM_VRAM_MODULE_V2; 5971254885Sdumbbell 5972254885Sdumbbell 5973254885Sdumbbelltypedef struct _ATOM_MEMORY_TIMING_FORMAT 5974254885Sdumbbell{ 5975254885Sdumbbell ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 5976254885Sdumbbell union{ 5977254885Sdumbbell USHORT usMRS; // mode register 5978254885Sdumbbell USHORT usDDR3_MR0; 5979254885Sdumbbell }; 5980254885Sdumbbell union{ 5981254885Sdumbbell USHORT usEMRS; // extended mode register 5982254885Sdumbbell USHORT usDDR3_MR1; 5983254885Sdumbbell }; 5984254885Sdumbbell UCHAR ucCL; // CAS latency 5985254885Sdumbbell UCHAR ucWL; // WRITE Latency 5986254885Sdumbbell UCHAR uctRAS; // tRAS 5987254885Sdumbbell UCHAR uctRC; // tRC 5988254885Sdumbbell UCHAR uctRFC; // tRFC 5989254885Sdumbbell UCHAR uctRCDR; // tRCDR 5990254885Sdumbbell UCHAR uctRCDW; // tRCDW 5991254885Sdumbbell UCHAR uctRP; // tRP 5992254885Sdumbbell UCHAR uctRRD; // tRRD 5993254885Sdumbbell UCHAR uctWR; // tWR 5994254885Sdumbbell UCHAR uctWTR; // tWTR 5995254885Sdumbbell UCHAR uctPDIX; // tPDIX 5996254885Sdumbbell UCHAR uctFAW; // tFAW 5997254885Sdumbbell UCHAR uctAOND; // tAOND 5998254885Sdumbbell union 5999254885Sdumbbell { 6000254885Sdumbbell struct { 6001254885Sdumbbell UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6002254885Sdumbbell UCHAR ucReserved; 6003254885Sdumbbell }; 6004254885Sdumbbell USHORT usDDR3_MR2; 6005254885Sdumbbell }; 6006254885Sdumbbell}ATOM_MEMORY_TIMING_FORMAT; 6007254885Sdumbbell 6008254885Sdumbbell 6009254885Sdumbbelltypedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 6010254885Sdumbbell{ 6011254885Sdumbbell ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6012254885Sdumbbell USHORT usMRS; // mode register 6013254885Sdumbbell USHORT usEMRS; // extended mode register 6014254885Sdumbbell UCHAR ucCL; // CAS latency 6015254885Sdumbbell UCHAR ucWL; // WRITE Latency 6016254885Sdumbbell UCHAR uctRAS; // tRAS 6017254885Sdumbbell UCHAR uctRC; // tRC 6018254885Sdumbbell UCHAR uctRFC; // tRFC 6019254885Sdumbbell UCHAR uctRCDR; // tRCDR 6020254885Sdumbbell UCHAR uctRCDW; // tRCDW 6021254885Sdumbbell UCHAR uctRP; // tRP 6022254885Sdumbbell UCHAR uctRRD; // tRRD 6023254885Sdumbbell UCHAR uctWR; // tWR 6024254885Sdumbbell UCHAR uctWTR; // tWTR 6025254885Sdumbbell UCHAR uctPDIX; // tPDIX 6026254885Sdumbbell UCHAR uctFAW; // tFAW 6027254885Sdumbbell UCHAR uctAOND; // tAOND 6028254885Sdumbbell UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6029254885Sdumbbell////////////////////////////////////GDDR parameters/////////////////////////////////// 6030254885Sdumbbell UCHAR uctCCDL; // 6031254885Sdumbbell UCHAR uctCRCRL; // 6032254885Sdumbbell UCHAR uctCRCWL; // 6033254885Sdumbbell UCHAR uctCKE; // 6034254885Sdumbbell UCHAR uctCKRSE; // 6035254885Sdumbbell UCHAR uctCKRSX; // 6036254885Sdumbbell UCHAR uctFAW32; // 6037254885Sdumbbell UCHAR ucMR5lo; // 6038254885Sdumbbell UCHAR ucMR5hi; // 6039254885Sdumbbell UCHAR ucTerminator; 6040254885Sdumbbell}ATOM_MEMORY_TIMING_FORMAT_V1; 6041254885Sdumbbell 6042254885Sdumbbelltypedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 6043254885Sdumbbell{ 6044254885Sdumbbell ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6045254885Sdumbbell USHORT usMRS; // mode register 6046254885Sdumbbell USHORT usEMRS; // extended mode register 6047254885Sdumbbell UCHAR ucCL; // CAS latency 6048254885Sdumbbell UCHAR ucWL; // WRITE Latency 6049254885Sdumbbell UCHAR uctRAS; // tRAS 6050254885Sdumbbell UCHAR uctRC; // tRC 6051254885Sdumbbell UCHAR uctRFC; // tRFC 6052254885Sdumbbell UCHAR uctRCDR; // tRCDR 6053254885Sdumbbell UCHAR uctRCDW; // tRCDW 6054254885Sdumbbell UCHAR uctRP; // tRP 6055254885Sdumbbell UCHAR uctRRD; // tRRD 6056254885Sdumbbell UCHAR uctWR; // tWR 6057254885Sdumbbell UCHAR uctWTR; // tWTR 6058254885Sdumbbell UCHAR uctPDIX; // tPDIX 6059254885Sdumbbell UCHAR uctFAW; // tFAW 6060254885Sdumbbell UCHAR uctAOND; // tAOND 6061254885Sdumbbell UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6062254885Sdumbbell////////////////////////////////////GDDR parameters/////////////////////////////////// 6063254885Sdumbbell UCHAR uctCCDL; // 6064254885Sdumbbell UCHAR uctCRCRL; // 6065254885Sdumbbell UCHAR uctCRCWL; // 6066254885Sdumbbell UCHAR uctCKE; // 6067254885Sdumbbell UCHAR uctCKRSE; // 6068254885Sdumbbell UCHAR uctCKRSX; // 6069254885Sdumbbell UCHAR uctFAW32; // 6070254885Sdumbbell UCHAR ucMR4lo; // 6071254885Sdumbbell UCHAR ucMR4hi; // 6072254885Sdumbbell UCHAR ucMR5lo; // 6073254885Sdumbbell UCHAR ucMR5hi; // 6074254885Sdumbbell UCHAR ucTerminator; 6075254885Sdumbbell UCHAR ucReserved; 6076254885Sdumbbell}ATOM_MEMORY_TIMING_FORMAT_V2; 6077254885Sdumbbell 6078254885Sdumbbelltypedef struct _ATOM_MEMORY_FORMAT 6079254885Sdumbbell{ 6080254885Sdumbbell ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 6081254885Sdumbbell union{ 6082254885Sdumbbell USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6083254885Sdumbbell USHORT usDDR3_Reserved; // Not used for DDR3 memory 6084254885Sdumbbell }; 6085254885Sdumbbell union{ 6086254885Sdumbbell USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6087254885Sdumbbell USHORT usDDR3_MR3; // Used for DDR3 memory 6088254885Sdumbbell }; 6089254885Sdumbbell UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6090254885Sdumbbell UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6091254885Sdumbbell UCHAR ucRow; // Number of Row,in power of 2; 6092254885Sdumbbell UCHAR ucColumn; // Number of Column,in power of 2; 6093254885Sdumbbell UCHAR ucBank; // Nunber of Bank; 6094254885Sdumbbell UCHAR ucRank; // Number of Rank, in power of 2 6095254885Sdumbbell UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 6096254885Sdumbbell UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 6097254885Sdumbbell UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 6098254885Sdumbbell UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6099254885Sdumbbell UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 6100254885Sdumbbell UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 6101254885Sdumbbell ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 6102254885Sdumbbell}ATOM_MEMORY_FORMAT; 6103254885Sdumbbell 6104254885Sdumbbell 6105254885Sdumbbelltypedef struct _ATOM_VRAM_MODULE_V3 6106254885Sdumbbell{ 6107254885Sdumbbell ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 6108254885Sdumbbell USHORT usSize; // size of ATOM_VRAM_MODULE_V3 6109254885Sdumbbell USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 6110254885Sdumbbell USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 6111254885Sdumbbell UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6112254885Sdumbbell UCHAR ucChannelNum; // board dependent parameter:Number of channel; 6113254885Sdumbbell UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 6114254885Sdumbbell UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 6115254885Sdumbbell UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6116254885Sdumbbell UCHAR ucFlag; // To enable/disable functionalities based on memory type 6117254885Sdumbbell ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 6118254885Sdumbbell}ATOM_VRAM_MODULE_V3; 6119254885Sdumbbell 6120254885Sdumbbell 6121254885Sdumbbell//ATOM_VRAM_MODULE_V3.ucNPL_RT 6122254885Sdumbbell#define NPL_RT_MASK 0x0f 6123254885Sdumbbell#define BATTERY_ODT_MASK 0xc0 6124254885Sdumbbell 6125254885Sdumbbell#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 6126254885Sdumbbell 6127254885Sdumbbelltypedef struct _ATOM_VRAM_MODULE_V4 6128254885Sdumbbell{ 6129254885Sdumbbell ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6130254885Sdumbbell USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6131254885Sdumbbell USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6132254885Sdumbbell // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6133254885Sdumbbell USHORT usReserved; 6134254885Sdumbbell UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6135254885Sdumbbell UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6136254885Sdumbbell UCHAR ucChannelNum; // Number of channels present in this module config 6137254885Sdumbbell UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6138254885Sdumbbell UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6139254885Sdumbbell UCHAR ucFlag; // To enable/disable functionalities based on memory type 6140254885Sdumbbell UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6141254885Sdumbbell UCHAR ucVREFI; // board dependent parameter 6142254885Sdumbbell UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6143254885Sdumbbell UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6144254885Sdumbbell UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6145254885Sdumbbell // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6146254885Sdumbbell UCHAR ucReserved[3]; 6147254885Sdumbbell 6148254885Sdumbbell//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6149254885Sdumbbell union{ 6150254885Sdumbbell USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6151254885Sdumbbell USHORT usDDR3_Reserved; 6152254885Sdumbbell }; 6153254885Sdumbbell union{ 6154254885Sdumbbell USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6155254885Sdumbbell USHORT usDDR3_MR3; // Used for DDR3 memory 6156254885Sdumbbell }; 6157254885Sdumbbell UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6158254885Sdumbbell UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6159254885Sdumbbell UCHAR ucReserved2[2]; 6160254885Sdumbbell ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6161254885Sdumbbell}ATOM_VRAM_MODULE_V4; 6162254885Sdumbbell 6163254885Sdumbbell#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 6164254885Sdumbbell#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 6165254885Sdumbbell#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 6166254885Sdumbbell#define VRAM_MODULE_V4_MISC_BL8 0x4 6167254885Sdumbbell#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 6168254885Sdumbbell 6169254885Sdumbbelltypedef struct _ATOM_VRAM_MODULE_V5 6170254885Sdumbbell{ 6171254885Sdumbbell ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6172254885Sdumbbell USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6173254885Sdumbbell USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6174254885Sdumbbell // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6175254885Sdumbbell USHORT usReserved; 6176254885Sdumbbell UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6177254885Sdumbbell UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6178254885Sdumbbell UCHAR ucChannelNum; // Number of channels present in this module config 6179254885Sdumbbell UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6180254885Sdumbbell UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6181254885Sdumbbell UCHAR ucFlag; // To enable/disable functionalities based on memory type 6182254885Sdumbbell UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6183254885Sdumbbell UCHAR ucVREFI; // board dependent parameter 6184254885Sdumbbell UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6185254885Sdumbbell UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6186254885Sdumbbell UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6187254885Sdumbbell // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6188254885Sdumbbell UCHAR ucReserved[3]; 6189254885Sdumbbell 6190254885Sdumbbell//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6191254885Sdumbbell USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6192254885Sdumbbell USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6193254885Sdumbbell UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6194254885Sdumbbell UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6195254885Sdumbbell UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6196254885Sdumbbell UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6197254885Sdumbbell ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6198254885Sdumbbell}ATOM_VRAM_MODULE_V5; 6199254885Sdumbbell 6200254885Sdumbbelltypedef struct _ATOM_VRAM_MODULE_V6 6201254885Sdumbbell{ 6202254885Sdumbbell ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6203254885Sdumbbell USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6204254885Sdumbbell USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6205254885Sdumbbell // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6206254885Sdumbbell USHORT usReserved; 6207254885Sdumbbell UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6208254885Sdumbbell UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6209254885Sdumbbell UCHAR ucChannelNum; // Number of channels present in this module config 6210254885Sdumbbell UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6211254885Sdumbbell UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6212254885Sdumbbell UCHAR ucFlag; // To enable/disable functionalities based on memory type 6213254885Sdumbbell UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6214254885Sdumbbell UCHAR ucVREFI; // board dependent parameter 6215254885Sdumbbell UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6216254885Sdumbbell UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6217254885Sdumbbell UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6218254885Sdumbbell // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6219254885Sdumbbell UCHAR ucReserved[3]; 6220254885Sdumbbell 6221254885Sdumbbell//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6222254885Sdumbbell USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6223254885Sdumbbell USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6224254885Sdumbbell UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6225254885Sdumbbell UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6226254885Sdumbbell UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6227254885Sdumbbell UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6228254885Sdumbbell ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6229254885Sdumbbell}ATOM_VRAM_MODULE_V6; 6230254885Sdumbbell 6231254885Sdumbbelltypedef struct _ATOM_VRAM_MODULE_V7 6232254885Sdumbbell{ 6233254885Sdumbbell// Design Specific Values 6234254885Sdumbbell ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 6235254885Sdumbbell USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 6236254885Sdumbbell USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6237254885Sdumbbell USHORT usEnableChannels; // bit vector which indicate which channels are enabled 6238254885Sdumbbell UCHAR ucExtMemoryID; // Current memory module ID 6239254885Sdumbbell UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 6240254885Sdumbbell UCHAR ucChannelNum; // Number of mem. channels supported in this module 6241254885Sdumbbell UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 6242254885Sdumbbell UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6243254885Sdumbbell UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. 6244254885Sdumbbell UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 6245254885Sdumbbell UCHAR ucVREFI; // Not used. 6246254885Sdumbbell UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 6247254885Sdumbbell UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6248254885Sdumbbell UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6249254885Sdumbbell USHORT usSEQSettingOffset; 6250254885Sdumbbell UCHAR ucReserved; 6251254885Sdumbbell// Memory Module specific values 6252254885Sdumbbell USHORT usEMRS2Value; // EMRS2/MR2 Value. 6253254885Sdumbbell USHORT usEMRS3Value; // EMRS3/MR3 Value. 6254254885Sdumbbell UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 6255254885Sdumbbell UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6256254885Sdumbbell UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 6257254885Sdumbbell UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6258254885Sdumbbell char strMemPNString[20]; // part number end with '0'. 6259254885Sdumbbell}ATOM_VRAM_MODULE_V7; 6260254885Sdumbbell 6261254885Sdumbbelltypedef struct _ATOM_VRAM_INFO_V2 6262254885Sdumbbell{ 6263254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6264254885Sdumbbell UCHAR ucNumOfVRAMModule; 6265254885Sdumbbell ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6266254885Sdumbbell}ATOM_VRAM_INFO_V2; 6267254885Sdumbbell 6268254885Sdumbbelltypedef struct _ATOM_VRAM_INFO_V3 6269254885Sdumbbell{ 6270254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6271254885Sdumbbell USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6272254885Sdumbbell USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6273254885Sdumbbell USHORT usRerseved; 6274254885Sdumbbell UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 6275254885Sdumbbell UCHAR ucNumOfVRAMModule; 6276254885Sdumbbell ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6277254885Sdumbbell ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6278254885Sdumbbell // ATOM_INIT_REG_BLOCK aMemAdjust; 6279254885Sdumbbell}ATOM_VRAM_INFO_V3; 6280254885Sdumbbell 6281254885Sdumbbell#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 6282254885Sdumbbell 6283254885Sdumbbelltypedef struct _ATOM_VRAM_INFO_V4 6284254885Sdumbbell{ 6285254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6286254885Sdumbbell USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6287254885Sdumbbell USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6288254885Sdumbbell USHORT usRerseved; 6289254885Sdumbbell UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 6290254885Sdumbbell ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 6291254885Sdumbbell UCHAR ucReservde[4]; 6292254885Sdumbbell UCHAR ucNumOfVRAMModule; 6293254885Sdumbbell ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6294254885Sdumbbell ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6295254885Sdumbbell // ATOM_INIT_REG_BLOCK aMemAdjust; 6296254885Sdumbbell}ATOM_VRAM_INFO_V4; 6297254885Sdumbbell 6298254885Sdumbbelltypedef struct _ATOM_VRAM_INFO_HEADER_V2_1 6299254885Sdumbbell{ 6300254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6301254885Sdumbbell USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6302254885Sdumbbell USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6303254885Sdumbbell USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 6304254885Sdumbbell USHORT usReserved[3]; 6305254885Sdumbbell UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 6306254885Sdumbbell UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 6307254885Sdumbbell UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 6308254885Sdumbbell UCHAR ucReserved; 6309254885Sdumbbell ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6310254885Sdumbbell}ATOM_VRAM_INFO_HEADER_V2_1; 6311254885Sdumbbell 6312254885Sdumbbell 6313254885Sdumbbelltypedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 6314254885Sdumbbell{ 6315254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6316254885Sdumbbell UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 6317254885Sdumbbell}ATOM_VRAM_GPIO_DETECTION_INFO; 6318254885Sdumbbell 6319254885Sdumbbell 6320254885Sdumbbelltypedef struct _ATOM_MEMORY_TRAINING_INFO 6321254885Sdumbbell{ 6322254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6323254885Sdumbbell UCHAR ucTrainingLoop; 6324254885Sdumbbell UCHAR ucReserved[3]; 6325254885Sdumbbell ATOM_INIT_REG_BLOCK asMemTrainingSetting; 6326254885Sdumbbell}ATOM_MEMORY_TRAINING_INFO; 6327254885Sdumbbell 6328254885Sdumbbell 6329254885Sdumbbelltypedef struct SW_I2C_CNTL_DATA_PARAMETERS 6330254885Sdumbbell{ 6331254885Sdumbbell UCHAR ucControl; 6332254885Sdumbbell UCHAR ucData; 6333254885Sdumbbell UCHAR ucSatus; 6334254885Sdumbbell UCHAR ucTemp; 6335254885Sdumbbell} SW_I2C_CNTL_DATA_PARAMETERS; 6336254885Sdumbbell 6337254885Sdumbbell#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 6338254885Sdumbbell 6339254885Sdumbbelltypedef struct _SW_I2C_IO_DATA_PARAMETERS 6340254885Sdumbbell{ 6341254885Sdumbbell USHORT GPIO_Info; 6342254885Sdumbbell UCHAR ucAct; 6343254885Sdumbbell UCHAR ucData; 6344254885Sdumbbell } SW_I2C_IO_DATA_PARAMETERS; 6345254885Sdumbbell 6346254885Sdumbbell#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 6347254885Sdumbbell 6348254885Sdumbbell/****************************SW I2C CNTL DEFINITIONS**********************/ 6349254885Sdumbbell#define SW_I2C_IO_RESET 0 6350254885Sdumbbell#define SW_I2C_IO_GET 1 6351254885Sdumbbell#define SW_I2C_IO_DRIVE 2 6352254885Sdumbbell#define SW_I2C_IO_SET 3 6353254885Sdumbbell#define SW_I2C_IO_START 4 6354254885Sdumbbell 6355254885Sdumbbell#define SW_I2C_IO_CLOCK 0 6356254885Sdumbbell#define SW_I2C_IO_DATA 0x80 6357254885Sdumbbell 6358254885Sdumbbell#define SW_I2C_IO_ZERO 0 6359254885Sdumbbell#define SW_I2C_IO_ONE 0x100 6360254885Sdumbbell 6361254885Sdumbbell#define SW_I2C_CNTL_READ 0 6362254885Sdumbbell#define SW_I2C_CNTL_WRITE 1 6363254885Sdumbbell#define SW_I2C_CNTL_START 2 6364254885Sdumbbell#define SW_I2C_CNTL_STOP 3 6365254885Sdumbbell#define SW_I2C_CNTL_OPEN 4 6366254885Sdumbbell#define SW_I2C_CNTL_CLOSE 5 6367254885Sdumbbell#define SW_I2C_CNTL_WRITE1BIT 6 6368254885Sdumbbell 6369254885Sdumbbell//==============================VESA definition Portion=============================== 6370254885Sdumbbell#define VESA_OEM_PRODUCT_REV "01.00" 6371254885Sdumbbell#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 6372254885Sdumbbell#define VESA_MODE_WIN_ATTRIBUTE 7 6373254885Sdumbbell#define VESA_WIN_SIZE 64 6374254885Sdumbbell 6375254885Sdumbbelltypedef struct _PTR_32_BIT_STRUCTURE 6376254885Sdumbbell{ 6377254885Sdumbbell USHORT Offset16; 6378254885Sdumbbell USHORT Segment16; 6379254885Sdumbbell} PTR_32_BIT_STRUCTURE; 6380254885Sdumbbell 6381254885Sdumbbelltypedef union _PTR_32_BIT_UNION 6382254885Sdumbbell{ 6383254885Sdumbbell PTR_32_BIT_STRUCTURE SegmentOffset; 6384254885Sdumbbell ULONG Ptr32_Bit; 6385254885Sdumbbell} PTR_32_BIT_UNION; 6386254885Sdumbbell 6387254885Sdumbbelltypedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 6388254885Sdumbbell{ 6389254885Sdumbbell UCHAR VbeSignature[4]; 6390254885Sdumbbell USHORT VbeVersion; 6391254885Sdumbbell PTR_32_BIT_UNION OemStringPtr; 6392254885Sdumbbell UCHAR Capabilities[4]; 6393254885Sdumbbell PTR_32_BIT_UNION VideoModePtr; 6394254885Sdumbbell USHORT TotalMemory; 6395254885Sdumbbell} VBE_1_2_INFO_BLOCK_UPDATABLE; 6396254885Sdumbbell 6397254885Sdumbbell 6398254885Sdumbbelltypedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 6399254885Sdumbbell{ 6400254885Sdumbbell VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 6401254885Sdumbbell USHORT OemSoftRev; 6402254885Sdumbbell PTR_32_BIT_UNION OemVendorNamePtr; 6403254885Sdumbbell PTR_32_BIT_UNION OemProductNamePtr; 6404254885Sdumbbell PTR_32_BIT_UNION OemProductRevPtr; 6405254885Sdumbbell} VBE_2_0_INFO_BLOCK_UPDATABLE; 6406254885Sdumbbell 6407254885Sdumbbelltypedef union _VBE_VERSION_UNION 6408254885Sdumbbell{ 6409254885Sdumbbell VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 6410254885Sdumbbell VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 6411254885Sdumbbell} VBE_VERSION_UNION; 6412254885Sdumbbell 6413254885Sdumbbelltypedef struct _VBE_INFO_BLOCK 6414254885Sdumbbell{ 6415254885Sdumbbell VBE_VERSION_UNION UpdatableVBE_Info; 6416254885Sdumbbell UCHAR Reserved[222]; 6417254885Sdumbbell UCHAR OemData[256]; 6418254885Sdumbbell} VBE_INFO_BLOCK; 6419254885Sdumbbell 6420254885Sdumbbelltypedef struct _VBE_FP_INFO 6421254885Sdumbbell{ 6422254885Sdumbbell USHORT HSize; 6423254885Sdumbbell USHORT VSize; 6424254885Sdumbbell USHORT FPType; 6425254885Sdumbbell UCHAR RedBPP; 6426254885Sdumbbell UCHAR GreenBPP; 6427254885Sdumbbell UCHAR BlueBPP; 6428254885Sdumbbell UCHAR ReservedBPP; 6429254885Sdumbbell ULONG RsvdOffScrnMemSize; 6430254885Sdumbbell ULONG RsvdOffScrnMEmPtr; 6431254885Sdumbbell UCHAR Reserved[14]; 6432254885Sdumbbell} VBE_FP_INFO; 6433254885Sdumbbell 6434254885Sdumbbelltypedef struct _VESA_MODE_INFO_BLOCK 6435254885Sdumbbell{ 6436254885Sdumbbell// Mandatory information for all VBE revisions 6437254885Sdumbbell USHORT ModeAttributes; // dw ? ; mode attributes 6438254885Sdumbbell UCHAR WinAAttributes; // db ? ; window A attributes 6439254885Sdumbbell UCHAR WinBAttributes; // db ? ; window B attributes 6440254885Sdumbbell USHORT WinGranularity; // dw ? ; window granularity 6441254885Sdumbbell USHORT WinSize; // dw ? ; window size 6442254885Sdumbbell USHORT WinASegment; // dw ? ; window A start segment 6443254885Sdumbbell USHORT WinBSegment; // dw ? ; window B start segment 6444254885Sdumbbell ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 6445254885Sdumbbell USHORT BytesPerScanLine;// dw ? ; bytes per scan line 6446254885Sdumbbell 6447254885Sdumbbell//; Mandatory information for VBE 1.2 and above 6448254885Sdumbbell USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 6449254885Sdumbbell USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 6450254885Sdumbbell UCHAR XCharSize; // db ? ; character cell width in pixels 6451254885Sdumbbell UCHAR YCharSize; // db ? ; character cell height in pixels 6452254885Sdumbbell UCHAR NumberOfPlanes; // db ? ; number of memory planes 6453254885Sdumbbell UCHAR BitsPerPixel; // db ? ; bits per pixel 6454254885Sdumbbell UCHAR NumberOfBanks; // db ? ; number of banks 6455254885Sdumbbell UCHAR MemoryModel; // db ? ; memory model type 6456254885Sdumbbell UCHAR BankSize; // db ? ; bank size in KB 6457254885Sdumbbell UCHAR NumberOfImagePages;// db ? ; number of images 6458254885Sdumbbell UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 6459254885Sdumbbell 6460254885Sdumbbell//; Direct Color fields(required for direct/6 and YUV/7 memory models) 6461254885Sdumbbell UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 6462254885Sdumbbell UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 6463254885Sdumbbell UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 6464254885Sdumbbell UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 6465254885Sdumbbell UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 6466254885Sdumbbell UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 6467254885Sdumbbell UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 6468254885Sdumbbell UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 6469254885Sdumbbell UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 6470254885Sdumbbell 6471254885Sdumbbell//; Mandatory information for VBE 2.0 and above 6472254885Sdumbbell ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 6473254885Sdumbbell ULONG Reserved_1; // dd 0 ; reserved - always set to 0 6474254885Sdumbbell USHORT Reserved_2; // dw 0 ; reserved - always set to 0 6475254885Sdumbbell 6476254885Sdumbbell//; Mandatory information for VBE 3.0 and above 6477254885Sdumbbell USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 6478254885Sdumbbell UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 6479254885Sdumbbell UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 6480254885Sdumbbell UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 6481254885Sdumbbell UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 6482254885Sdumbbell UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 6483254885Sdumbbell UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 6484254885Sdumbbell UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 6485254885Sdumbbell UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 6486254885Sdumbbell UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 6487254885Sdumbbell UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 6488254885Sdumbbell ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 6489254885Sdumbbell UCHAR Reserved; // db 190 dup (0) 6490254885Sdumbbell} VESA_MODE_INFO_BLOCK; 6491254885Sdumbbell 6492254885Sdumbbell// BIOS function CALLS 6493254885Sdumbbell#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 6494254885Sdumbbell#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 6495254885Sdumbbell#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 6496254885Sdumbbell#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 6497254885Sdumbbell#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 6498254885Sdumbbell#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 6499254885Sdumbbell#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 6500254885Sdumbbell#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 6501254885Sdumbbell#define ATOM_BIOS_FUNCTION_STV_STD 0x16 6502254885Sdumbbell#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 6503254885Sdumbbell#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 6504254885Sdumbbell 6505254885Sdumbbell#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 6506254885Sdumbbell#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 6507254885Sdumbbell#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 6508254885Sdumbbell#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 6509254885Sdumbbell#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 6510254885Sdumbbell#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 6511254885Sdumbbell#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 6512254885Sdumbbell 6513254885Sdumbbell#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 6514254885Sdumbbell#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 6515254885Sdumbbell#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 6516254885Sdumbbell#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 6517254885Sdumbbell#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 6518254885Sdumbbell#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 6519254885Sdumbbell#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 6520254885Sdumbbell#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 6521254885Sdumbbell#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 6522254885Sdumbbell#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 6523254885Sdumbbell 6524254885Sdumbbell 6525254885Sdumbbell#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 6526254885Sdumbbell#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 6527254885Sdumbbell#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 6528254885Sdumbbell#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 6529254885Sdumbbell#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 6530254885Sdumbbell#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 6531254885Sdumbbell#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 6532254885Sdumbbell#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 6533254885Sdumbbell 6534254885Sdumbbell#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 6535254885Sdumbbell#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 6536254885Sdumbbell#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 6537254885Sdumbbell 6538254885Sdumbbell// structure used for VBIOS only 6539254885Sdumbbell 6540254885Sdumbbell//DispOutInfoTable 6541254885Sdumbbelltypedef struct _ASIC_TRANSMITTER_INFO 6542254885Sdumbbell{ 6543254885Sdumbbell USHORT usTransmitterObjId; 6544254885Sdumbbell USHORT usSupportDevice; 6545254885Sdumbbell UCHAR ucTransmitterCmdTblId; 6546254885Sdumbbell UCHAR ucConfig; 6547254885Sdumbbell UCHAR ucEncoderID; //available 1st encoder ( default ) 6548254885Sdumbbell UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 6549254885Sdumbbell UCHAR uc2ndEncoderID; 6550254885Sdumbbell UCHAR ucReserved; 6551254885Sdumbbell}ASIC_TRANSMITTER_INFO; 6552254885Sdumbbell 6553254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 6554254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 6555254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 6556254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 6557254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 6558254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 6559254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 6560254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 6561254885Sdumbbell#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 6562254885Sdumbbell 6563254885Sdumbbelltypedef struct _ASIC_ENCODER_INFO 6564254885Sdumbbell{ 6565254885Sdumbbell UCHAR ucEncoderID; 6566254885Sdumbbell UCHAR ucEncoderConfig; 6567254885Sdumbbell USHORT usEncoderCmdTblId; 6568254885Sdumbbell}ASIC_ENCODER_INFO; 6569254885Sdumbbell 6570254885Sdumbbelltypedef struct _ATOM_DISP_OUT_INFO 6571254885Sdumbbell{ 6572254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6573254885Sdumbbell USHORT ptrTransmitterInfo; 6574254885Sdumbbell USHORT ptrEncoderInfo; 6575254885Sdumbbell ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6576254885Sdumbbell ASIC_ENCODER_INFO asEncoderInfo[1]; 6577254885Sdumbbell}ATOM_DISP_OUT_INFO; 6578254885Sdumbbell 6579254885Sdumbbelltypedef struct _ATOM_DISP_OUT_INFO_V2 6580254885Sdumbbell{ 6581254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6582254885Sdumbbell USHORT ptrTransmitterInfo; 6583254885Sdumbbell USHORT ptrEncoderInfo; 6584254885Sdumbbell USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6585254885Sdumbbell ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6586254885Sdumbbell ASIC_ENCODER_INFO asEncoderInfo[1]; 6587254885Sdumbbell}ATOM_DISP_OUT_INFO_V2; 6588254885Sdumbbell 6589254885Sdumbbell 6590254885Sdumbbelltypedef struct _ATOM_DISP_CLOCK_ID { 6591254885Sdumbbell UCHAR ucPpllId; 6592254885Sdumbbell UCHAR ucPpllAttribute; 6593254885Sdumbbell}ATOM_DISP_CLOCK_ID; 6594254885Sdumbbell 6595254885Sdumbbell// ucPpllAttribute 6596254885Sdumbbell#define CLOCK_SOURCE_SHAREABLE 0x01 6597254885Sdumbbell#define CLOCK_SOURCE_DP_MODE 0x02 6598254885Sdumbbell#define CLOCK_SOURCE_NONE_DP_MODE 0x04 6599254885Sdumbbell 6600254885Sdumbbell//DispOutInfoTable 6601254885Sdumbbelltypedef struct _ASIC_TRANSMITTER_INFO_V2 6602254885Sdumbbell{ 6603254885Sdumbbell USHORT usTransmitterObjId; 6604254885Sdumbbell USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 6605254885Sdumbbell UCHAR ucTransmitterCmdTblId; 6606254885Sdumbbell UCHAR ucConfig; 6607254885Sdumbbell UCHAR ucEncoderID; // available 1st encoder ( default ) 6608254885Sdumbbell UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 6609254885Sdumbbell UCHAR uc2ndEncoderID; 6610254885Sdumbbell UCHAR ucReserved; 6611254885Sdumbbell}ASIC_TRANSMITTER_INFO_V2; 6612254885Sdumbbell 6613254885Sdumbbelltypedef struct _ATOM_DISP_OUT_INFO_V3 6614254885Sdumbbell{ 6615254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6616254885Sdumbbell USHORT ptrTransmitterInfo; 6617254885Sdumbbell USHORT ptrEncoderInfo; 6618254885Sdumbbell USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6619254885Sdumbbell USHORT usReserved; 6620254885Sdumbbell UCHAR ucDCERevision; 6621254885Sdumbbell UCHAR ucMaxDispEngineNum; 6622254885Sdumbbell UCHAR ucMaxActiveDispEngineNum; 6623254885Sdumbbell UCHAR ucMaxPPLLNum; 6624254885Sdumbbell UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 6625254885Sdumbbell UCHAR ucReserved[3]; 6626254885Sdumbbell ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 6627254885Sdumbbell}ATOM_DISP_OUT_INFO_V3; 6628254885Sdumbbell 6629254885Sdumbbelltypedef enum CORE_REF_CLK_SOURCE{ 6630254885Sdumbbell CLOCK_SRC_XTALIN=0, 6631254885Sdumbbell CLOCK_SRC_XO_IN=1, 6632254885Sdumbbell CLOCK_SRC_XO_IN2=2, 6633254885Sdumbbell}CORE_REF_CLK_SOURCE; 6634254885Sdumbbell 6635254885Sdumbbell// DispDevicePriorityInfo 6636254885Sdumbbelltypedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 6637254885Sdumbbell{ 6638254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6639254885Sdumbbell USHORT asDevicePriority[16]; 6640254885Sdumbbell}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 6641254885Sdumbbell 6642254885Sdumbbell//ProcessAuxChannelTransactionTable 6643254885Sdumbbelltypedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 6644254885Sdumbbell{ 6645254885Sdumbbell USHORT lpAuxRequest; 6646254885Sdumbbell USHORT lpDataOut; 6647254885Sdumbbell UCHAR ucChannelID; 6648254885Sdumbbell union 6649254885Sdumbbell { 6650254885Sdumbbell UCHAR ucReplyStatus; 6651254885Sdumbbell UCHAR ucDelay; 6652254885Sdumbbell }; 6653254885Sdumbbell UCHAR ucDataOutLen; 6654254885Sdumbbell UCHAR ucReserved; 6655254885Sdumbbell}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 6656254885Sdumbbell 6657254885Sdumbbell//ProcessAuxChannelTransactionTable 6658254885Sdumbbelltypedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 6659254885Sdumbbell{ 6660254885Sdumbbell USHORT lpAuxRequest; 6661254885Sdumbbell USHORT lpDataOut; 6662254885Sdumbbell UCHAR ucChannelID; 6663254885Sdumbbell union 6664254885Sdumbbell { 6665254885Sdumbbell UCHAR ucReplyStatus; 6666254885Sdumbbell UCHAR ucDelay; 6667254885Sdumbbell }; 6668254885Sdumbbell UCHAR ucDataOutLen; 6669254885Sdumbbell UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 6670254885Sdumbbell}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 6671254885Sdumbbell 6672254885Sdumbbell#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 6673254885Sdumbbell 6674254885Sdumbbell//GetSinkType 6675254885Sdumbbell 6676254885Sdumbbelltypedef struct _DP_ENCODER_SERVICE_PARAMETERS 6677254885Sdumbbell{ 6678254885Sdumbbell USHORT ucLinkClock; 6679254885Sdumbbell union 6680254885Sdumbbell { 6681254885Sdumbbell UCHAR ucConfig; // for DP training command 6682254885Sdumbbell UCHAR ucI2cId; // use for GET_SINK_TYPE command 6683254885Sdumbbell }; 6684254885Sdumbbell UCHAR ucAction; 6685254885Sdumbbell UCHAR ucStatus; 6686254885Sdumbbell UCHAR ucLaneNum; 6687254885Sdumbbell UCHAR ucReserved[2]; 6688254885Sdumbbell}DP_ENCODER_SERVICE_PARAMETERS; 6689254885Sdumbbell 6690254885Sdumbbell// ucAction 6691254885Sdumbbell#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 6692254885Sdumbbell/* obselete */ 6693254885Sdumbbell#define ATOM_DP_ACTION_TRAINING_START 0x02 6694254885Sdumbbell#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 6695254885Sdumbbell#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 6696254885Sdumbbell#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 6697254885Sdumbbell#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 6698254885Sdumbbell#define ATOM_DP_ACTION_BLANKING 0x07 6699254885Sdumbbell 6700254885Sdumbbell// ucConfig 6701254885Sdumbbell#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 6702254885Sdumbbell#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 6703254885Sdumbbell#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 6704254885Sdumbbell#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 6705254885Sdumbbell#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 6706254885Sdumbbell#define ATOM_DP_CONFIG_LINK_A 0x00 6707254885Sdumbbell#define ATOM_DP_CONFIG_LINK_B 0x04 6708254885Sdumbbell/* /obselete */ 6709254885Sdumbbell#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 6710254885Sdumbbell 6711254885Sdumbbell 6712254885Sdumbbelltypedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 6713254885Sdumbbell{ 6714254885Sdumbbell USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 6715254885Sdumbbell UCHAR ucAuxId; 6716254885Sdumbbell UCHAR ucAction; 6717254885Sdumbbell UCHAR ucSinkType; // Iput and Output parameters. 6718254885Sdumbbell UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 6719254885Sdumbbell UCHAR ucReserved[2]; 6720254885Sdumbbell}DP_ENCODER_SERVICE_PARAMETERS_V2; 6721254885Sdumbbell 6722254885Sdumbbelltypedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 6723254885Sdumbbell{ 6724254885Sdumbbell DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 6725254885Sdumbbell PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 6726254885Sdumbbell}DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 6727254885Sdumbbell 6728254885Sdumbbell// ucAction 6729254885Sdumbbell#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 6730254885Sdumbbell#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 6731254885Sdumbbell 6732254885Sdumbbell 6733254885Sdumbbell// DP_TRAINING_TABLE 6734254885Sdumbbell#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 6735254885Sdumbbell#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 6736254885Sdumbbell#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 6737254885Sdumbbell#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 6738254885Sdumbbell#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 6739254885Sdumbbell#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 6740254885Sdumbbell#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 6741254885Sdumbbell#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 6742254885Sdumbbell#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 6743254885Sdumbbell#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 6744254885Sdumbbell#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 6745254885Sdumbbell#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 6746254885Sdumbbell#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 6747254885Sdumbbell 6748254885Sdumbbelltypedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6749254885Sdumbbell{ 6750254885Sdumbbell UCHAR ucI2CSpeed; 6751254885Sdumbbell union 6752254885Sdumbbell { 6753254885Sdumbbell UCHAR ucRegIndex; 6754254885Sdumbbell UCHAR ucStatus; 6755254885Sdumbbell }; 6756254885Sdumbbell USHORT lpI2CDataOut; 6757254885Sdumbbell UCHAR ucFlag; 6758254885Sdumbbell UCHAR ucTransBytes; 6759254885Sdumbbell UCHAR ucSlaveAddr; 6760254885Sdumbbell UCHAR ucLineNumber; 6761254885Sdumbbell}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 6762254885Sdumbbell 6763254885Sdumbbell#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6764254885Sdumbbell 6765254885Sdumbbell//ucFlag 6766254885Sdumbbell#define HW_I2C_WRITE 1 6767254885Sdumbbell#define HW_I2C_READ 0 6768254885Sdumbbell#define I2C_2BYTE_ADDR 0x02 6769254885Sdumbbell 6770254885Sdumbbell/****************************************************************************/ 6771254885Sdumbbell// Structures used by HW_Misc_OperationTable 6772254885Sdumbbell/****************************************************************************/ 6773254885Sdumbbelltypedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 6774254885Sdumbbell{ 6775254885Sdumbbell UCHAR ucCmd; // Input: To tell which action to take 6776254885Sdumbbell UCHAR ucReserved[3]; 6777254885Sdumbbell ULONG ulReserved; 6778254885Sdumbbell}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 6779254885Sdumbbell 6780254885Sdumbbelltypedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 6781254885Sdumbbell{ 6782254885Sdumbbell UCHAR ucReturnCode; // Output: Return value base on action was taken 6783254885Sdumbbell UCHAR ucReserved[3]; 6784254885Sdumbbell ULONG ulReserved; 6785254885Sdumbbell}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 6786254885Sdumbbell 6787254885Sdumbbell// Actions code 6788254885Sdumbbell#define ATOM_GET_SDI_SUPPORT 0xF0 6789254885Sdumbbell 6790254885Sdumbbell// Return code 6791254885Sdumbbell#define ATOM_UNKNOWN_CMD 0 6792254885Sdumbbell#define ATOM_FEATURE_NOT_SUPPORTED 1 6793254885Sdumbbell#define ATOM_FEATURE_SUPPORTED 2 6794254885Sdumbbell 6795254885Sdumbbelltypedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 6796254885Sdumbbell{ 6797254885Sdumbbell ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 6798254885Sdumbbell PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 6799254885Sdumbbell}ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 6800254885Sdumbbell 6801254885Sdumbbell/****************************************************************************/ 6802254885Sdumbbell 6803254885Sdumbbelltypedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 6804254885Sdumbbell{ 6805254885Sdumbbell UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 6806254885Sdumbbell UCHAR ucReserved[3]; 6807254885Sdumbbell}SET_HWBLOCK_INSTANCE_PARAMETER_V2; 6808254885Sdumbbell 6809254885Sdumbbell#define HWBLKINST_INSTANCE_MASK 0x07 6810254885Sdumbbell#define HWBLKINST_HWBLK_MASK 0xF0 6811254885Sdumbbell#define HWBLKINST_HWBLK_SHIFT 0x04 6812254885Sdumbbell 6813254885Sdumbbell//ucHWBlock 6814254885Sdumbbell#define SELECT_DISP_ENGINE 0 6815254885Sdumbbell#define SELECT_DISP_PLL 1 6816254885Sdumbbell#define SELECT_DCIO_UNIPHY_LINK0 2 6817254885Sdumbbell#define SELECT_DCIO_UNIPHY_LINK1 3 6818254885Sdumbbell#define SELECT_DCIO_IMPCAL 4 6819254885Sdumbbell#define SELECT_DCIO_DIG 6 6820254885Sdumbbell#define SELECT_CRTC_PIXEL_RATE 7 6821254885Sdumbbell#define SELECT_VGA_BLK 8 6822254885Sdumbbell 6823254885Sdumbbell// DIGTransmitterInfoTable structure used to program UNIPHY settings 6824254885Sdumbbelltypedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 6825254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6826254885Sdumbbell USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 6827254885Sdumbbell USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 6828254885Sdumbbell USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 6829254885Sdumbbell USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 6830254885Sdumbbell USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 6831254885Sdumbbell}DIG_TRANSMITTER_INFO_HEADER_V3_1; 6832254885Sdumbbell 6833254885Sdumbbelltypedef struct _CLOCK_CONDITION_REGESTER_INFO{ 6834254885Sdumbbell USHORT usRegisterIndex; 6835254885Sdumbbell UCHAR ucStartBit; 6836254885Sdumbbell UCHAR ucEndBit; 6837254885Sdumbbell}CLOCK_CONDITION_REGESTER_INFO; 6838254885Sdumbbell 6839254885Sdumbbelltypedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 6840254885Sdumbbell USHORT usMaxClockFreq; 6841254885Sdumbbell UCHAR ucEncodeMode; 6842254885Sdumbbell UCHAR ucPhySel; 6843254885Sdumbbell ULONG ulAnalogSetting[1]; 6844254885Sdumbbell}CLOCK_CONDITION_SETTING_ENTRY; 6845254885Sdumbbell 6846254885Sdumbbelltypedef struct _CLOCK_CONDITION_SETTING_INFO{ 6847254885Sdumbbell USHORT usEntrySize; 6848254885Sdumbbell CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 6849254885Sdumbbell}CLOCK_CONDITION_SETTING_INFO; 6850254885Sdumbbell 6851254885Sdumbbelltypedef struct _PHY_CONDITION_REG_VAL{ 6852254885Sdumbbell ULONG ulCondition; 6853254885Sdumbbell ULONG ulRegVal; 6854254885Sdumbbell}PHY_CONDITION_REG_VAL; 6855254885Sdumbbell 6856254885Sdumbbelltypedef struct _PHY_CONDITION_REG_INFO{ 6857254885Sdumbbell USHORT usRegIndex; 6858254885Sdumbbell USHORT usSize; 6859254885Sdumbbell PHY_CONDITION_REG_VAL asRegVal[1]; 6860254885Sdumbbell}PHY_CONDITION_REG_INFO; 6861254885Sdumbbell 6862254885Sdumbbelltypedef struct _PHY_ANALOG_SETTING_INFO{ 6863254885Sdumbbell UCHAR ucEncodeMode; 6864254885Sdumbbell UCHAR ucPhySel; 6865254885Sdumbbell USHORT usSize; 6866254885Sdumbbell PHY_CONDITION_REG_INFO asAnalogSetting[1]; 6867254885Sdumbbell}PHY_ANALOG_SETTING_INFO; 6868254885Sdumbbell 6869254885Sdumbbell/****************************************************************************/ 6870254885Sdumbbell//Portion VI: Definitinos for vbios MC scratch registers that driver used 6871254885Sdumbbell/****************************************************************************/ 6872254885Sdumbbell 6873254885Sdumbbell#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 6874254885Sdumbbell#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 6875254885Sdumbbell#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 6876254885Sdumbbell#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 6877254885Sdumbbell#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 6878254885Sdumbbell#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 6879254885Sdumbbell#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 6880254885Sdumbbell 6881254885Sdumbbell/****************************************************************************/ 6882254885Sdumbbell//Portion VI: Definitinos being oboselete 6883254885Sdumbbell/****************************************************************************/ 6884254885Sdumbbell 6885254885Sdumbbell//========================================================================================== 6886254885Sdumbbell//Remove the definitions below when driver is ready! 6887254885Sdumbbelltypedef struct _ATOM_DAC_INFO 6888254885Sdumbbell{ 6889254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6890254885Sdumbbell USHORT usMaxFrequency; // in 10kHz unit 6891254885Sdumbbell USHORT usReserved; 6892254885Sdumbbell}ATOM_DAC_INFO; 6893254885Sdumbbell 6894254885Sdumbbell 6895254885Sdumbbelltypedef struct _COMPASSIONATE_DATA 6896254885Sdumbbell{ 6897254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6898254885Sdumbbell 6899254885Sdumbbell //============================== DAC1 portion 6900254885Sdumbbell UCHAR ucDAC1_BG_Adjustment; 6901254885Sdumbbell UCHAR ucDAC1_DAC_Adjustment; 6902254885Sdumbbell USHORT usDAC1_FORCE_Data; 6903254885Sdumbbell //============================== DAC2 portion 6904254885Sdumbbell UCHAR ucDAC2_CRT2_BG_Adjustment; 6905254885Sdumbbell UCHAR ucDAC2_CRT2_DAC_Adjustment; 6906254885Sdumbbell USHORT usDAC2_CRT2_FORCE_Data; 6907254885Sdumbbell USHORT usDAC2_CRT2_MUX_RegisterIndex; 6908254885Sdumbbell UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6909254885Sdumbbell UCHAR ucDAC2_NTSC_BG_Adjustment; 6910254885Sdumbbell UCHAR ucDAC2_NTSC_DAC_Adjustment; 6911254885Sdumbbell USHORT usDAC2_TV1_FORCE_Data; 6912254885Sdumbbell USHORT usDAC2_TV1_MUX_RegisterIndex; 6913254885Sdumbbell UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6914254885Sdumbbell UCHAR ucDAC2_CV_BG_Adjustment; 6915254885Sdumbbell UCHAR ucDAC2_CV_DAC_Adjustment; 6916254885Sdumbbell USHORT usDAC2_CV_FORCE_Data; 6917254885Sdumbbell USHORT usDAC2_CV_MUX_RegisterIndex; 6918254885Sdumbbell UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6919254885Sdumbbell UCHAR ucDAC2_PAL_BG_Adjustment; 6920254885Sdumbbell UCHAR ucDAC2_PAL_DAC_Adjustment; 6921254885Sdumbbell USHORT usDAC2_TV2_FORCE_Data; 6922254885Sdumbbell}COMPASSIONATE_DATA; 6923254885Sdumbbell 6924254885Sdumbbell/****************************Supported Device Info Table Definitions**********************/ 6925254885Sdumbbell// ucConnectInfo: 6926254885Sdumbbell// [7:4] - connector type 6927254885Sdumbbell// = 1 - VGA connector 6928254885Sdumbbell// = 2 - DVI-I 6929254885Sdumbbell// = 3 - DVI-D 6930254885Sdumbbell// = 4 - DVI-A 6931254885Sdumbbell// = 5 - SVIDEO 6932254885Sdumbbell// = 6 - COMPOSITE 6933254885Sdumbbell// = 7 - LVDS 6934254885Sdumbbell// = 8 - DIGITAL LINK 6935254885Sdumbbell// = 9 - SCART 6936254885Sdumbbell// = 0xA - HDMI_type A 6937254885Sdumbbell// = 0xB - HDMI_type B 6938254885Sdumbbell// = 0xE - Special case1 (DVI+DIN) 6939254885Sdumbbell// Others=TBD 6940254885Sdumbbell// [3:0] - DAC Associated 6941254885Sdumbbell// = 0 - no DAC 6942254885Sdumbbell// = 1 - DACA 6943254885Sdumbbell// = 2 - DACB 6944254885Sdumbbell// = 3 - External DAC 6945254885Sdumbbell// Others=TBD 6946254885Sdumbbell// 6947254885Sdumbbell 6948254885Sdumbbelltypedef struct _ATOM_CONNECTOR_INFO 6949254885Sdumbbell{ 6950254885Sdumbbell#if ATOM_BIG_ENDIAN 6951254885Sdumbbell UCHAR bfConnectorType:4; 6952254885Sdumbbell UCHAR bfAssociatedDAC:4; 6953254885Sdumbbell#else 6954254885Sdumbbell UCHAR bfAssociatedDAC:4; 6955254885Sdumbbell UCHAR bfConnectorType:4; 6956254885Sdumbbell#endif 6957254885Sdumbbell}ATOM_CONNECTOR_INFO; 6958254885Sdumbbell 6959254885Sdumbbelltypedef union _ATOM_CONNECTOR_INFO_ACCESS 6960254885Sdumbbell{ 6961254885Sdumbbell ATOM_CONNECTOR_INFO sbfAccess; 6962254885Sdumbbell UCHAR ucAccess; 6963254885Sdumbbell}ATOM_CONNECTOR_INFO_ACCESS; 6964254885Sdumbbell 6965254885Sdumbbelltypedef struct _ATOM_CONNECTOR_INFO_I2C 6966254885Sdumbbell{ 6967254885Sdumbbell ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 6968254885Sdumbbell ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6969254885Sdumbbell}ATOM_CONNECTOR_INFO_I2C; 6970254885Sdumbbell 6971254885Sdumbbell 6972254885Sdumbbelltypedef struct _ATOM_SUPPORTED_DEVICES_INFO 6973254885Sdumbbell{ 6974254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6975254885Sdumbbell USHORT usDeviceSupport; 6976254885Sdumbbell ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 6977254885Sdumbbell}ATOM_SUPPORTED_DEVICES_INFO; 6978254885Sdumbbell 6979254885Sdumbbell#define NO_INT_SRC_MAPPED 0xFF 6980254885Sdumbbell 6981254885Sdumbbelltypedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 6982254885Sdumbbell{ 6983254885Sdumbbell UCHAR ucIntSrcBitmap; 6984254885Sdumbbell}ATOM_CONNECTOR_INC_SRC_BITMAP; 6985254885Sdumbbell 6986254885Sdumbbelltypedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 6987254885Sdumbbell{ 6988254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6989254885Sdumbbell USHORT usDeviceSupport; 6990254885Sdumbbell ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6991254885Sdumbbell ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6992254885Sdumbbell}ATOM_SUPPORTED_DEVICES_INFO_2; 6993254885Sdumbbell 6994254885Sdumbbelltypedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 6995254885Sdumbbell{ 6996254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 6997254885Sdumbbell USHORT usDeviceSupport; 6998254885Sdumbbell ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 6999254885Sdumbbell ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 7000254885Sdumbbell}ATOM_SUPPORTED_DEVICES_INFO_2d1; 7001254885Sdumbbell 7002254885Sdumbbell#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 7003254885Sdumbbell 7004254885Sdumbbell 7005254885Sdumbbell 7006254885Sdumbbelltypedef struct _ATOM_MISC_CONTROL_INFO 7007254885Sdumbbell{ 7008254885Sdumbbell USHORT usFrequency; 7009254885Sdumbbell UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 7010254885Sdumbbell UCHAR ucPLL_DutyCycle; // PLL duty cycle control 7011254885Sdumbbell UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 7012254885Sdumbbell UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 7013254885Sdumbbell}ATOM_MISC_CONTROL_INFO; 7014254885Sdumbbell 7015254885Sdumbbell 7016254885Sdumbbell#define ATOM_MAX_MISC_INFO 4 7017254885Sdumbbell 7018254885Sdumbbelltypedef struct _ATOM_TMDS_INFO 7019254885Sdumbbell{ 7020254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 7021254885Sdumbbell USHORT usMaxFrequency; // in 10Khz 7022254885Sdumbbell ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 7023254885Sdumbbell}ATOM_TMDS_INFO; 7024254885Sdumbbell 7025254885Sdumbbell 7026254885Sdumbbelltypedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 7027254885Sdumbbell{ 7028254885Sdumbbell UCHAR ucTVStandard; //Same as TV standards defined above, 7029254885Sdumbbell UCHAR ucPadding[1]; 7030254885Sdumbbell}ATOM_ENCODER_ANALOG_ATTRIBUTE; 7031254885Sdumbbell 7032254885Sdumbbelltypedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 7033254885Sdumbbell{ 7034254885Sdumbbell UCHAR ucAttribute; //Same as other digital encoder attributes defined above 7035254885Sdumbbell UCHAR ucPadding[1]; 7036254885Sdumbbell}ATOM_ENCODER_DIGITAL_ATTRIBUTE; 7037254885Sdumbbell 7038254885Sdumbbelltypedef union _ATOM_ENCODER_ATTRIBUTE 7039254885Sdumbbell{ 7040254885Sdumbbell ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 7041254885Sdumbbell ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 7042254885Sdumbbell}ATOM_ENCODER_ATTRIBUTE; 7043254885Sdumbbell 7044254885Sdumbbell 7045254885Sdumbbelltypedef struct _DVO_ENCODER_CONTROL_PARAMETERS 7046254885Sdumbbell{ 7047254885Sdumbbell USHORT usPixelClock; 7048254885Sdumbbell USHORT usEncoderID; 7049254885Sdumbbell UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 7050254885Sdumbbell UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 7051254885Sdumbbell ATOM_ENCODER_ATTRIBUTE usDevAttr; 7052254885Sdumbbell}DVO_ENCODER_CONTROL_PARAMETERS; 7053254885Sdumbbell 7054254885Sdumbbelltypedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 7055254885Sdumbbell{ 7056254885Sdumbbell DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 7057254885Sdumbbell WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 7058254885Sdumbbell}DVO_ENCODER_CONTROL_PS_ALLOCATION; 7059254885Sdumbbell 7060254885Sdumbbell 7061254885Sdumbbell#define ATOM_XTMDS_ASIC_SI164_ID 1 7062254885Sdumbbell#define ATOM_XTMDS_ASIC_SI178_ID 2 7063254885Sdumbbell#define ATOM_XTMDS_ASIC_TFP513_ID 3 7064254885Sdumbbell#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 7065254885Sdumbbell#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 7066254885Sdumbbell#define ATOM_XTMDS_MVPU_FPGA 0x00000004 7067254885Sdumbbell 7068254885Sdumbbell 7069254885Sdumbbelltypedef struct _ATOM_XTMDS_INFO 7070254885Sdumbbell{ 7071254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 7072254885Sdumbbell USHORT usSingleLinkMaxFrequency; 7073254885Sdumbbell ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 7074254885Sdumbbell UCHAR ucXtransimitterID; 7075254885Sdumbbell UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 7076254885Sdumbbell UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 7077254885Sdumbbell // due to design. This ID is used to alert driver that the sequence is not "standard"! 7078254885Sdumbbell UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 7079254885Sdumbbell UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 7080254885Sdumbbell}ATOM_XTMDS_INFO; 7081254885Sdumbbell 7082254885Sdumbbelltypedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 7083254885Sdumbbell{ 7084254885Sdumbbell UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 7085254885Sdumbbell UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 7086254885Sdumbbell UCHAR ucPadding[2]; 7087254885Sdumbbell}DFP_DPMS_STATUS_CHANGE_PARAMETERS; 7088254885Sdumbbell 7089254885Sdumbbell/****************************Legacy Power Play Table Definitions **********************/ 7090254885Sdumbbell 7091254885Sdumbbell//Definitions for ulPowerPlayMiscInfo 7092254885Sdumbbell#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 7093254885Sdumbbell#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 7094254885Sdumbbell#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 7095254885Sdumbbell 7096254885Sdumbbell#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 7097254885Sdumbbell#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 7098254885Sdumbbell 7099254885Sdumbbell#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 7100254885Sdumbbell 7101254885Sdumbbell#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 7102254885Sdumbbell#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 7103254885Sdumbbell#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 7104254885Sdumbbell 7105254885Sdumbbell#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 7106254885Sdumbbell#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 7107254885Sdumbbell#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 7108254885Sdumbbell#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 7109254885Sdumbbell#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 7110254885Sdumbbell#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 7111254885Sdumbbell#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 7112254885Sdumbbell 7113254885Sdumbbell#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 7114254885Sdumbbell#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 7115254885Sdumbbell#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 7116254885Sdumbbell#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 7117254885Sdumbbell#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 7118254885Sdumbbell 7119254885Sdumbbell#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 7120254885Sdumbbell#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 7121254885Sdumbbell 7122254885Sdumbbell#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 7123254885Sdumbbell#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 7124254885Sdumbbell#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 7125254885Sdumbbell#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 7126254885Sdumbbell#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 7127254885Sdumbbell#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 7128254885Sdumbbell 7129254885Sdumbbell#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 7130254885Sdumbbell#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 7131254885Sdumbbell#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 7132254885Sdumbbell 7133254885Sdumbbell#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 7134254885Sdumbbell#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 7135254885Sdumbbell#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 7136254885Sdumbbell#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 7137254885Sdumbbell#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 7138254885Sdumbbell#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 7139254885Sdumbbell#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 7140254885Sdumbbell //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 7141254885Sdumbbell#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 7142254885Sdumbbell#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 7143254885Sdumbbell#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 7144254885Sdumbbell 7145254885Sdumbbell//ucTableFormatRevision=1 7146254885Sdumbbell//ucTableContentRevision=1 7147254885Sdumbbelltypedef struct _ATOM_POWERMODE_INFO 7148254885Sdumbbell{ 7149254885Sdumbbell ULONG ulMiscInfo; //The power level should be arranged in ascending order 7150254885Sdumbbell ULONG ulReserved1; // must set to 0 7151254885Sdumbbell ULONG ulReserved2; // must set to 0 7152254885Sdumbbell USHORT usEngineClock; 7153254885Sdumbbell USHORT usMemoryClock; 7154254885Sdumbbell UCHAR ucVoltageDropIndex; // index to GPIO table 7155254885Sdumbbell UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7156254885Sdumbbell UCHAR ucMinTemperature; 7157254885Sdumbbell UCHAR ucMaxTemperature; 7158254885Sdumbbell UCHAR ucNumPciELanes; // number of PCIE lanes 7159254885Sdumbbell}ATOM_POWERMODE_INFO; 7160254885Sdumbbell 7161254885Sdumbbell//ucTableFormatRevision=2 7162254885Sdumbbell//ucTableContentRevision=1 7163254885Sdumbbelltypedef struct _ATOM_POWERMODE_INFO_V2 7164254885Sdumbbell{ 7165254885Sdumbbell ULONG ulMiscInfo; //The power level should be arranged in ascending order 7166254885Sdumbbell ULONG ulMiscInfo2; 7167254885Sdumbbell ULONG ulEngineClock; 7168254885Sdumbbell ULONG ulMemoryClock; 7169254885Sdumbbell UCHAR ucVoltageDropIndex; // index to GPIO table 7170254885Sdumbbell UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7171254885Sdumbbell UCHAR ucMinTemperature; 7172254885Sdumbbell UCHAR ucMaxTemperature; 7173254885Sdumbbell UCHAR ucNumPciELanes; // number of PCIE lanes 7174254885Sdumbbell}ATOM_POWERMODE_INFO_V2; 7175254885Sdumbbell 7176254885Sdumbbell//ucTableFormatRevision=2 7177254885Sdumbbell//ucTableContentRevision=2 7178254885Sdumbbelltypedef struct _ATOM_POWERMODE_INFO_V3 7179254885Sdumbbell{ 7180254885Sdumbbell ULONG ulMiscInfo; //The power level should be arranged in ascending order 7181254885Sdumbbell ULONG ulMiscInfo2; 7182254885Sdumbbell ULONG ulEngineClock; 7183254885Sdumbbell ULONG ulMemoryClock; 7184254885Sdumbbell UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 7185254885Sdumbbell UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7186254885Sdumbbell UCHAR ucMinTemperature; 7187254885Sdumbbell UCHAR ucMaxTemperature; 7188254885Sdumbbell UCHAR ucNumPciELanes; // number of PCIE lanes 7189254885Sdumbbell UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 7190254885Sdumbbell}ATOM_POWERMODE_INFO_V3; 7191254885Sdumbbell 7192254885Sdumbbell 7193254885Sdumbbell#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 7194254885Sdumbbell 7195254885Sdumbbell#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 7196254885Sdumbbell#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 7197254885Sdumbbell 7198254885Sdumbbell#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 7199254885Sdumbbell#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 7200254885Sdumbbell#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 7201254885Sdumbbell#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 7202254885Sdumbbell#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 7203254885Sdumbbell#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 7204254885Sdumbbell#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 7205254885Sdumbbell 7206254885Sdumbbell 7207254885Sdumbbelltypedef struct _ATOM_POWERPLAY_INFO 7208254885Sdumbbell{ 7209254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 7210254885Sdumbbell UCHAR ucOverdriveThermalController; 7211254885Sdumbbell UCHAR ucOverdriveI2cLine; 7212254885Sdumbbell UCHAR ucOverdriveIntBitmap; 7213254885Sdumbbell UCHAR ucOverdriveControllerAddress; 7214254885Sdumbbell UCHAR ucSizeOfPowerModeEntry; 7215254885Sdumbbell UCHAR ucNumOfPowerModeEntries; 7216254885Sdumbbell ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7217254885Sdumbbell}ATOM_POWERPLAY_INFO; 7218254885Sdumbbell 7219254885Sdumbbelltypedef struct _ATOM_POWERPLAY_INFO_V2 7220254885Sdumbbell{ 7221254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 7222254885Sdumbbell UCHAR ucOverdriveThermalController; 7223254885Sdumbbell UCHAR ucOverdriveI2cLine; 7224254885Sdumbbell UCHAR ucOverdriveIntBitmap; 7225254885Sdumbbell UCHAR ucOverdriveControllerAddress; 7226254885Sdumbbell UCHAR ucSizeOfPowerModeEntry; 7227254885Sdumbbell UCHAR ucNumOfPowerModeEntries; 7228254885Sdumbbell ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7229254885Sdumbbell}ATOM_POWERPLAY_INFO_V2; 7230254885Sdumbbell 7231254885Sdumbbelltypedef struct _ATOM_POWERPLAY_INFO_V3 7232254885Sdumbbell{ 7233254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 7234254885Sdumbbell UCHAR ucOverdriveThermalController; 7235254885Sdumbbell UCHAR ucOverdriveI2cLine; 7236254885Sdumbbell UCHAR ucOverdriveIntBitmap; 7237254885Sdumbbell UCHAR ucOverdriveControllerAddress; 7238254885Sdumbbell UCHAR ucSizeOfPowerModeEntry; 7239254885Sdumbbell UCHAR ucNumOfPowerModeEntries; 7240254885Sdumbbell ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7241254885Sdumbbell}ATOM_POWERPLAY_INFO_V3; 7242254885Sdumbbell 7243254885Sdumbbell/* New PPlib */ 7244254885Sdumbbell/**************************************************************************/ 7245254885Sdumbbelltypedef struct _ATOM_PPLIB_THERMALCONTROLLER 7246254885Sdumbbell 7247254885Sdumbbell{ 7248254885Sdumbbell UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 7249254885Sdumbbell UCHAR ucI2cLine; // as interpreted by DAL I2C 7250254885Sdumbbell UCHAR ucI2cAddress; 7251254885Sdumbbell UCHAR ucFanParameters; // Fan Control Parameters. 7252254885Sdumbbell UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 7253254885Sdumbbell UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 7254254885Sdumbbell UCHAR ucReserved; // ---- 7255254885Sdumbbell UCHAR ucFlags; // to be defined 7256254885Sdumbbell} ATOM_PPLIB_THERMALCONTROLLER; 7257254885Sdumbbell 7258254885Sdumbbell#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 7259254885Sdumbbell#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 7260254885Sdumbbell 7261254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_NONE 0 7262254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 7263254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 7264254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 7265254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 7266254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_LM64 5 7267254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 7268254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_RV6xx 7 7269254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_RV770 8 7270254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_ADT7473 9 7271254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 7272254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 7273254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 7274254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 7275254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 7276254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 7277254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_LM96163 17 7278254885Sdumbbell 7279254885Sdumbbell// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 7280254885Sdumbbell// We probably should reserve the bit 0x80 for this use. 7281254885Sdumbbell// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 7282254885Sdumbbell// The driver can pick the correct internal controller based on the ASIC. 7283254885Sdumbbell 7284254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 7285254885Sdumbbell#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 7286254885Sdumbbell 7287254885Sdumbbelltypedef struct _ATOM_PPLIB_STATE 7288254885Sdumbbell{ 7289254885Sdumbbell UCHAR ucNonClockStateIndex; 7290254885Sdumbbell UCHAR ucClockStateIndices[1]; // variable-sized 7291254885Sdumbbell} ATOM_PPLIB_STATE; 7292254885Sdumbbell 7293254885Sdumbbell 7294254885Sdumbbelltypedef struct _ATOM_PPLIB_FANTABLE 7295254885Sdumbbell{ 7296254885Sdumbbell UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 7297254885Sdumbbell UCHAR ucTHyst; // Temperature hysteresis. Integer. 7298254885Sdumbbell USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 7299254885Sdumbbell USHORT usTMed; // The middle temperature where we change slopes. 7300254885Sdumbbell USHORT usTHigh; // The high point above TMed for adjusting the second slope. 7301254885Sdumbbell USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 7302254885Sdumbbell USHORT usPWMMed; // The PWM value (in percent) at TMed. 7303254885Sdumbbell USHORT usPWMHigh; // The PWM value at THigh. 7304254885Sdumbbell} ATOM_PPLIB_FANTABLE; 7305254885Sdumbbell 7306254885Sdumbbelltypedef struct _ATOM_PPLIB_FANTABLE2 7307254885Sdumbbell{ 7308254885Sdumbbell ATOM_PPLIB_FANTABLE basicTable; 7309254885Sdumbbell USHORT usTMax; // The max temperature 7310254885Sdumbbell} ATOM_PPLIB_FANTABLE2; 7311254885Sdumbbell 7312254885Sdumbbelltypedef struct _ATOM_PPLIB_EXTENDEDHEADER 7313254885Sdumbbell{ 7314254885Sdumbbell USHORT usSize; 7315254885Sdumbbell ULONG ulMaxEngineClock; // For Overdrive. 7316254885Sdumbbell ULONG ulMaxMemoryClock; // For Overdrive. 7317254885Sdumbbell // Add extra system parameters here, always adjust size to include all fields. 7318254885Sdumbbell USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table 7319254885Sdumbbell USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table 7320254885Sdumbbell} ATOM_PPLIB_EXTENDEDHEADER; 7321254885Sdumbbell 7322254885Sdumbbell//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 7323254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 7324254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 7325254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 7326254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 7327254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 7328254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 7329254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 7330254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 7331254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 7332254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 7333254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 7334254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 7335254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 7336254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 7337254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 7338254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 7339254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 7340254885Sdumbbell#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 7341254885Sdumbbell 7342254885Sdumbbell 7343254885Sdumbbelltypedef struct _ATOM_PPLIB_POWERPLAYTABLE 7344254885Sdumbbell{ 7345254885Sdumbbell ATOM_COMMON_TABLE_HEADER sHeader; 7346254885Sdumbbell 7347254885Sdumbbell UCHAR ucDataRevision; 7348254885Sdumbbell 7349254885Sdumbbell UCHAR ucNumStates; 7350254885Sdumbbell UCHAR ucStateEntrySize; 7351254885Sdumbbell UCHAR ucClockInfoSize; 7352254885Sdumbbell UCHAR ucNonClockSize; 7353254885Sdumbbell 7354254885Sdumbbell // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 7355254885Sdumbbell USHORT usStateArrayOffset; 7356254885Sdumbbell 7357254885Sdumbbell // offset from start of this table to array of ASIC-specific structures, 7358254885Sdumbbell // currently ATOM_PPLIB_CLOCK_INFO. 7359254885Sdumbbell USHORT usClockInfoArrayOffset; 7360254885Sdumbbell 7361254885Sdumbbell // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 7362254885Sdumbbell USHORT usNonClockInfoArrayOffset; 7363254885Sdumbbell 7364254885Sdumbbell USHORT usBackbiasTime; // in microseconds 7365254885Sdumbbell USHORT usVoltageTime; // in microseconds 7366254885Sdumbbell USHORT usTableSize; //the size of this structure, or the extended structure 7367254885Sdumbbell 7368254885Sdumbbell ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 7369254885Sdumbbell 7370254885Sdumbbell ATOM_PPLIB_THERMALCONTROLLER sThermalController; 7371254885Sdumbbell 7372254885Sdumbbell USHORT usBootClockInfoOffset; 7373254885Sdumbbell USHORT usBootNonClockInfoOffset; 7374254885Sdumbbell 7375254885Sdumbbell} ATOM_PPLIB_POWERPLAYTABLE; 7376254885Sdumbbell 7377254885Sdumbbelltypedef struct _ATOM_PPLIB_POWERPLAYTABLE2 7378254885Sdumbbell{ 7379254885Sdumbbell ATOM_PPLIB_POWERPLAYTABLE basicTable; 7380254885Sdumbbell UCHAR ucNumCustomThermalPolicy; 7381254885Sdumbbell USHORT usCustomThermalPolicyArrayOffset; 7382254885Sdumbbell}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 7383254885Sdumbbell 7384254885Sdumbbelltypedef struct _ATOM_PPLIB_POWERPLAYTABLE3 7385254885Sdumbbell{ 7386254885Sdumbbell ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 7387254885Sdumbbell USHORT usFormatID; // To be used ONLY by PPGen. 7388254885Sdumbbell USHORT usFanTableOffset; 7389254885Sdumbbell USHORT usExtendendedHeaderOffset; 7390254885Sdumbbell} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 7391254885Sdumbbell 7392254885Sdumbbelltypedef struct _ATOM_PPLIB_POWERPLAYTABLE4 7393254885Sdumbbell{ 7394254885Sdumbbell ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 7395254885Sdumbbell ULONG ulGoldenPPID; // PPGen use only 7396254885Sdumbbell ULONG ulGoldenRevision; // PPGen use only 7397254885Sdumbbell USHORT usVddcDependencyOnSCLKOffset; 7398254885Sdumbbell USHORT usVddciDependencyOnMCLKOffset; 7399254885Sdumbbell USHORT usVddcDependencyOnMCLKOffset; 7400254885Sdumbbell USHORT usMaxClockVoltageOnDCOffset; 7401254885Sdumbbell USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table 7402254885Sdumbbell USHORT usReserved; 7403254885Sdumbbell} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 7404254885Sdumbbell 7405254885Sdumbbelltypedef struct _ATOM_PPLIB_POWERPLAYTABLE5 7406254885Sdumbbell{ 7407254885Sdumbbell ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 7408254885Sdumbbell ULONG ulTDPLimit; 7409254885Sdumbbell ULONG ulNearTDPLimit; 7410254885Sdumbbell ULONG ulSQRampingThreshold; 7411254885Sdumbbell USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 7412254885Sdumbbell ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table 7413254885Sdumbbell USHORT usTDPODLimit; 7414254885Sdumbbell USHORT usLoadLineSlope; // in milliOhms * 100 7415254885Sdumbbell} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 7416254885Sdumbbell 7417254885Sdumbbell//// ATOM_PPLIB_NONCLOCK_INFO::usClassification 7418254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 7419254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 7420254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 7421254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 7422254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 7423254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 7424254885Sdumbbell// 2, 4, 6, 7 are reserved 7425254885Sdumbbell 7426254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 7427254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 7428254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 7429254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 7430254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 7431254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 7432254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 7433254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 7434254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 7435254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 7436254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 7437254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 7438254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 7439254885Sdumbbell 7440254885Sdumbbell//// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 7441254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 7442254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 7443254885Sdumbbell#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) 7444254885Sdumbbell 7445254885Sdumbbell//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 7446254885Sdumbbell#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 7447254885Sdumbbell#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 7448254885Sdumbbell 7449254885Sdumbbell// 0 is 2.5Gb/s, 1 is 5Gb/s 7450254885Sdumbbell#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 7451254885Sdumbbell#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 7452254885Sdumbbell 7453254885Sdumbbell// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 7454254885Sdumbbell#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 7455254885Sdumbbell#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 7456254885Sdumbbell 7457254885Sdumbbell// lookup into reduced refresh-rate table 7458254885Sdumbbell#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 7459254885Sdumbbell#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 7460254885Sdumbbell 7461254885Sdumbbell#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 7462254885Sdumbbell#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 7463254885Sdumbbell// 2-15 TBD as needed. 7464254885Sdumbbell 7465254885Sdumbbell#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 7466254885Sdumbbell#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 7467254885Sdumbbell 7468254885Sdumbbell#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 7469254885Sdumbbell 7470254885Sdumbbell#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 7471254885Sdumbbell 7472254885Sdumbbell//memory related flags 7473254885Sdumbbell#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 7474254885Sdumbbell 7475254885Sdumbbell//M3 Arb //2bits, current 3 sets of parameters in total 7476254885Sdumbbell#define ATOM_PPLIB_M3ARB_MASK 0x00060000 7477254885Sdumbbell#define ATOM_PPLIB_M3ARB_SHIFT 17 7478254885Sdumbbell 7479254885Sdumbbell#define ATOM_PPLIB_ENABLE_DRR 0x00080000 7480254885Sdumbbell 7481254885Sdumbbell// remaining 16 bits are reserved 7482254885Sdumbbelltypedef struct _ATOM_PPLIB_THERMAL_STATE 7483254885Sdumbbell{ 7484254885Sdumbbell UCHAR ucMinTemperature; 7485254885Sdumbbell UCHAR ucMaxTemperature; 7486254885Sdumbbell UCHAR ucThermalAction; 7487254885Sdumbbell}ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 7488254885Sdumbbell 7489254885Sdumbbell// Contained in an array starting at the offset 7490254885Sdumbbell// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 7491254885Sdumbbell// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 7492254885Sdumbbell#define ATOM_PPLIB_NONCLOCKINFO_VER1 12 7493254885Sdumbbell#define ATOM_PPLIB_NONCLOCKINFO_VER2 24 7494254885Sdumbbelltypedef struct _ATOM_PPLIB_NONCLOCK_INFO 7495254885Sdumbbell{ 7496254885Sdumbbell USHORT usClassification; 7497254885Sdumbbell UCHAR ucMinTemperature; 7498254885Sdumbbell UCHAR ucMaxTemperature; 7499254885Sdumbbell ULONG ulCapsAndSettings; 7500254885Sdumbbell UCHAR ucRequiredPower; 7501254885Sdumbbell USHORT usClassification2; 7502254885Sdumbbell ULONG ulVCLK; 7503254885Sdumbbell ULONG ulDCLK; 7504254885Sdumbbell UCHAR ucUnused[5]; 7505254885Sdumbbell} ATOM_PPLIB_NONCLOCK_INFO; 7506254885Sdumbbell 7507254885Sdumbbell// Contained in an array starting at the offset 7508254885Sdumbbell// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 7509254885Sdumbbell// referenced from ATOM_PPLIB_STATE::ucClockStateIndices 7510254885Sdumbbelltypedef struct _ATOM_PPLIB_R600_CLOCK_INFO 7511254885Sdumbbell{ 7512254885Sdumbbell USHORT usEngineClockLow; 7513254885Sdumbbell UCHAR ucEngineClockHigh; 7514254885Sdumbbell 7515254885Sdumbbell USHORT usMemoryClockLow; 7516254885Sdumbbell UCHAR ucMemoryClockHigh; 7517254885Sdumbbell 7518254885Sdumbbell USHORT usVDDC; 7519254885Sdumbbell USHORT usUnused1; 7520254885Sdumbbell USHORT usUnused2; 7521254885Sdumbbell 7522254885Sdumbbell ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 7523254885Sdumbbell 7524254885Sdumbbell} ATOM_PPLIB_R600_CLOCK_INFO; 7525254885Sdumbbell 7526254885Sdumbbell// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 7527254885Sdumbbell#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 7528254885Sdumbbell#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 7529254885Sdumbbell#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 7530254885Sdumbbell#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 7531254885Sdumbbell#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 7532254885Sdumbbell#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 7533254885Sdumbbell 7534254885Sdumbbelltypedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 7535254885Sdumbbell{ 7536254885Sdumbbell USHORT usEngineClockLow; 7537254885Sdumbbell UCHAR ucEngineClockHigh; 7538254885Sdumbbell 7539254885Sdumbbell USHORT usMemoryClockLow; 7540254885Sdumbbell UCHAR ucMemoryClockHigh; 7541254885Sdumbbell 7542254885Sdumbbell USHORT usVDDC; 7543254885Sdumbbell USHORT usVDDCI; 7544254885Sdumbbell USHORT usUnused; 7545254885Sdumbbell 7546254885Sdumbbell ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 7547254885Sdumbbell 7548254885Sdumbbell} ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 7549254885Sdumbbell 7550254885Sdumbbelltypedef struct _ATOM_PPLIB_SI_CLOCK_INFO 7551254885Sdumbbell{ 7552254885Sdumbbell USHORT usEngineClockLow; 7553254885Sdumbbell UCHAR ucEngineClockHigh; 7554254885Sdumbbell 7555254885Sdumbbell USHORT usMemoryClockLow; 7556254885Sdumbbell UCHAR ucMemoryClockHigh; 7557254885Sdumbbell 7558254885Sdumbbell USHORT usVDDC; 7559254885Sdumbbell USHORT usVDDCI; 7560254885Sdumbbell UCHAR ucPCIEGen; 7561254885Sdumbbell UCHAR ucUnused1; 7562254885Sdumbbell 7563254885Sdumbbell ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now 7564254885Sdumbbell 7565254885Sdumbbell} ATOM_PPLIB_SI_CLOCK_INFO; 7566254885Sdumbbell 7567254885Sdumbbell 7568254885Sdumbbelltypedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 7569254885Sdumbbell 7570254885Sdumbbell{ 7571254885Sdumbbell USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 7572254885Sdumbbell UCHAR ucLowEngineClockHigh; 7573254885Sdumbbell USHORT usHighEngineClockLow; // High Engine clock in MHz. 7574254885Sdumbbell UCHAR ucHighEngineClockHigh; 7575254885Sdumbbell USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 7576254885Sdumbbell UCHAR ucMemoryClockHigh; // Currentyl unused. 7577254885Sdumbbell UCHAR ucPadding; // For proper alignment and size. 7578254885Sdumbbell USHORT usVDDC; // For the 780, use: None, Low, High, Variable 7579254885Sdumbbell UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 7580254885Sdumbbell UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. 7581254885Sdumbbell USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 7582254885Sdumbbell ULONG ulFlags; 7583254885Sdumbbell} ATOM_PPLIB_RS780_CLOCK_INFO; 7584254885Sdumbbell 7585254885Sdumbbell#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 7586254885Sdumbbell#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 7587254885Sdumbbell#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 7588254885Sdumbbell#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 7589254885Sdumbbell 7590254885Sdumbbell#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 7591254885Sdumbbell#define ATOM_PPLIB_RS780_SPMCLK_LOW 1 7592254885Sdumbbell#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 7593254885Sdumbbell 7594254885Sdumbbell#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 7595254885Sdumbbell#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 7596254885Sdumbbell#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 7597254885Sdumbbell 7598254885Sdumbbelltypedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 7599254885Sdumbbell USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 7600254885Sdumbbell UCHAR ucEngineClockHigh; //clockfrequency >> 16. 7601254885Sdumbbell UCHAR vddcIndex; //2-bit vddc index; 7602254885Sdumbbell USHORT tdpLimit; 7603298955Spfg //please initialize to 0 7604254885Sdumbbell USHORT rsv1; 7605254885Sdumbbell //please initialize to 0s 7606254885Sdumbbell ULONG rsv2[2]; 7607254885Sdumbbell}ATOM_PPLIB_SUMO_CLOCK_INFO; 7608254885Sdumbbell 7609254885Sdumbbell 7610254885Sdumbbell 7611254885Sdumbbelltypedef struct _ATOM_PPLIB_STATE_V2 7612254885Sdumbbell{ 7613254885Sdumbbell //number of valid dpm levels in this state; Driver uses it to calculate the whole 7614254885Sdumbbell //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 7615254885Sdumbbell UCHAR ucNumDPMLevels; 7616254885Sdumbbell 7617254885Sdumbbell //a index to the array of nonClockInfos 7618254885Sdumbbell UCHAR nonClockInfoIndex; 7619254885Sdumbbell /** 7620254885Sdumbbell * Driver will read the first ucNumDPMLevels in this array 7621254885Sdumbbell */ 7622254885Sdumbbell UCHAR clockInfoIndex[1]; 7623254885Sdumbbell} ATOM_PPLIB_STATE_V2; 7624254885Sdumbbell 7625254885Sdumbbelltypedef struct _StateArray{ 7626254885Sdumbbell //how many states we have 7627254885Sdumbbell UCHAR ucNumEntries; 7628254885Sdumbbell 7629254885Sdumbbell ATOM_PPLIB_STATE_V2 states[1]; 7630254885Sdumbbell}StateArray; 7631254885Sdumbbell 7632254885Sdumbbell 7633254885Sdumbbelltypedef struct _ClockInfoArray{ 7634254885Sdumbbell //how many clock levels we have 7635254885Sdumbbell UCHAR ucNumEntries; 7636254885Sdumbbell 7637254885Sdumbbell //sizeof(ATOM_PPLIB_CLOCK_INFO) 7638254885Sdumbbell UCHAR ucEntrySize; 7639254885Sdumbbell 7640254885Sdumbbell UCHAR clockInfo[1]; 7641254885Sdumbbell}ClockInfoArray; 7642254885Sdumbbell 7643254885Sdumbbelltypedef struct _NonClockInfoArray{ 7644254885Sdumbbell 7645254885Sdumbbell //how many non-clock levels we have. normally should be same as number of states 7646254885Sdumbbell UCHAR ucNumEntries; 7647254885Sdumbbell //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 7648254885Sdumbbell UCHAR ucEntrySize; 7649254885Sdumbbell 7650254885Sdumbbell ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 7651254885Sdumbbell}NonClockInfoArray; 7652254885Sdumbbell 7653254885Sdumbbelltypedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 7654254885Sdumbbell{ 7655254885Sdumbbell USHORT usClockLow; 7656254885Sdumbbell UCHAR ucClockHigh; 7657254885Sdumbbell USHORT usVoltage; 7658254885Sdumbbell}ATOM_PPLIB_Clock_Voltage_Dependency_Record; 7659254885Sdumbbell 7660254885Sdumbbelltypedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 7661254885Sdumbbell{ 7662254885Sdumbbell UCHAR ucNumEntries; // Number of entries. 7663254885Sdumbbell ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 7664254885Sdumbbell}ATOM_PPLIB_Clock_Voltage_Dependency_Table; 7665254885Sdumbbell 7666254885Sdumbbelltypedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 7667254885Sdumbbell{ 7668254885Sdumbbell USHORT usSclkLow; 7669254885Sdumbbell UCHAR ucSclkHigh; 7670254885Sdumbbell USHORT usMclkLow; 7671254885Sdumbbell UCHAR ucMclkHigh; 7672254885Sdumbbell USHORT usVddc; 7673254885Sdumbbell USHORT usVddci; 7674254885Sdumbbell}ATOM_PPLIB_Clock_Voltage_Limit_Record; 7675254885Sdumbbell 7676254885Sdumbbelltypedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 7677254885Sdumbbell{ 7678254885Sdumbbell UCHAR ucNumEntries; // Number of entries. 7679254885Sdumbbell ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 7680254885Sdumbbell}ATOM_PPLIB_Clock_Voltage_Limit_Table; 7681254885Sdumbbell 7682254885Sdumbbelltypedef struct _ATOM_PPLIB_CAC_Leakage_Record 7683254885Sdumbbell{ 7684254885Sdumbbell USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations 7685254885Sdumbbell ULONG ulLeakageValue; 7686254885Sdumbbell}ATOM_PPLIB_CAC_Leakage_Record; 7687254885Sdumbbell 7688254885Sdumbbelltypedef struct _ATOM_PPLIB_CAC_Leakage_Table 7689254885Sdumbbell{ 7690254885Sdumbbell UCHAR ucNumEntries; // Number of entries. 7691254885Sdumbbell ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. 7692254885Sdumbbell}ATOM_PPLIB_CAC_Leakage_Table; 7693254885Sdumbbell 7694254885Sdumbbelltypedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 7695254885Sdumbbell{ 7696254885Sdumbbell USHORT usVoltage; 7697254885Sdumbbell USHORT usSclkLow; 7698254885Sdumbbell UCHAR ucSclkHigh; 7699254885Sdumbbell USHORT usMclkLow; 7700254885Sdumbbell UCHAR ucMclkHigh; 7701254885Sdumbbell}ATOM_PPLIB_PhaseSheddingLimits_Record; 7702254885Sdumbbell 7703254885Sdumbbelltypedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table 7704254885Sdumbbell{ 7705254885Sdumbbell UCHAR ucNumEntries; // Number of entries. 7706254885Sdumbbell ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. 7707254885Sdumbbell}ATOM_PPLIB_PhaseSheddingLimits_Table; 7708254885Sdumbbell 7709254885Sdumbbelltypedef struct _VCEClockInfo{ 7710254885Sdumbbell USHORT usEVClkLow; 7711254885Sdumbbell UCHAR ucEVClkHigh; 7712254885Sdumbbell USHORT usECClkLow; 7713254885Sdumbbell UCHAR ucECClkHigh; 7714254885Sdumbbell}VCEClockInfo; 7715254885Sdumbbell 7716254885Sdumbbelltypedef struct _VCEClockInfoArray{ 7717254885Sdumbbell UCHAR ucNumEntries; 7718254885Sdumbbell VCEClockInfo entries[1]; 7719254885Sdumbbell}VCEClockInfoArray; 7720254885Sdumbbell 7721254885Sdumbbelltypedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 7722254885Sdumbbell{ 7723254885Sdumbbell USHORT usVoltage; 7724254885Sdumbbell UCHAR ucVCEClockInfoIndex; 7725254885Sdumbbell}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; 7726254885Sdumbbell 7727254885Sdumbbelltypedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table 7728254885Sdumbbell{ 7729254885Sdumbbell UCHAR numEntries; 7730254885Sdumbbell ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; 7731254885Sdumbbell}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; 7732254885Sdumbbell 7733254885Sdumbbelltypedef struct _ATOM_PPLIB_VCE_State_Record 7734254885Sdumbbell{ 7735254885Sdumbbell UCHAR ucVCEClockInfoIndex; 7736254885Sdumbbell UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 7737254885Sdumbbell}ATOM_PPLIB_VCE_State_Record; 7738254885Sdumbbell 7739254885Sdumbbelltypedef struct _ATOM_PPLIB_VCE_State_Table 7740254885Sdumbbell{ 7741254885Sdumbbell UCHAR numEntries; 7742254885Sdumbbell ATOM_PPLIB_VCE_State_Record entries[1]; 7743254885Sdumbbell}ATOM_PPLIB_VCE_State_Table; 7744254885Sdumbbell 7745254885Sdumbbell 7746254885Sdumbbelltypedef struct _ATOM_PPLIB_VCE_Table 7747254885Sdumbbell{ 7748254885Sdumbbell UCHAR revid; 7749254885Sdumbbell// VCEClockInfoArray array; 7750254885Sdumbbell// ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; 7751254885Sdumbbell// ATOM_PPLIB_VCE_State_Table states; 7752254885Sdumbbell}ATOM_PPLIB_VCE_Table; 7753254885Sdumbbell 7754254885Sdumbbell 7755254885Sdumbbelltypedef struct _UVDClockInfo{ 7756254885Sdumbbell USHORT usVClkLow; 7757254885Sdumbbell UCHAR ucVClkHigh; 7758254885Sdumbbell USHORT usDClkLow; 7759254885Sdumbbell UCHAR ucDClkHigh; 7760254885Sdumbbell}UVDClockInfo; 7761254885Sdumbbell 7762254885Sdumbbelltypedef struct _UVDClockInfoArray{ 7763254885Sdumbbell UCHAR ucNumEntries; 7764254885Sdumbbell UVDClockInfo entries[1]; 7765254885Sdumbbell}UVDClockInfoArray; 7766254885Sdumbbell 7767254885Sdumbbelltypedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 7768254885Sdumbbell{ 7769254885Sdumbbell USHORT usVoltage; 7770254885Sdumbbell UCHAR ucUVDClockInfoIndex; 7771254885Sdumbbell}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; 7772254885Sdumbbell 7773254885Sdumbbelltypedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table 7774254885Sdumbbell{ 7775254885Sdumbbell UCHAR numEntries; 7776254885Sdumbbell ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; 7777254885Sdumbbell}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; 7778254885Sdumbbell 7779254885Sdumbbelltypedef struct _ATOM_PPLIB_UVD_State_Record 7780254885Sdumbbell{ 7781254885Sdumbbell UCHAR ucUVDClockInfoIndex; 7782254885Sdumbbell UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 7783254885Sdumbbell}ATOM_PPLIB_UVD_State_Record; 7784254885Sdumbbell 7785254885Sdumbbelltypedef struct _ATOM_PPLIB_UVD_State_Table 7786254885Sdumbbell{ 7787254885Sdumbbell UCHAR numEntries; 7788254885Sdumbbell ATOM_PPLIB_UVD_State_Record entries[1]; 7789254885Sdumbbell}ATOM_PPLIB_UVD_State_Table; 7790254885Sdumbbell 7791254885Sdumbbell 7792254885Sdumbbelltypedef struct _ATOM_PPLIB_UVD_Table 7793254885Sdumbbell{ 7794254885Sdumbbell UCHAR revid; 7795254885Sdumbbell// UVDClockInfoArray array; 7796254885Sdumbbell// ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; 7797254885Sdumbbell// ATOM_PPLIB_UVD_State_Table states; 7798254885Sdumbbell}ATOM_PPLIB_UVD_Table; 7799254885Sdumbbell 7800254885Sdumbbell/**************************************************************************/ 7801254885Sdumbbell 7802254885Sdumbbell 7803254885Sdumbbell// Following definitions are for compatibility issue in different SW components. 7804254885Sdumbbell#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 7805254885Sdumbbell#define Object_Info Object_Header 7806254885Sdumbbell#define AdjustARB_SEQ MC_InitParameter 7807254885Sdumbbell#define VRAM_GPIO_DetectionInfo VoltageObjectInfo 7808254885Sdumbbell#define ASIC_VDDCI_Info ASIC_ProfilingInfo 7809254885Sdumbbell#define ASIC_MVDDQ_Info MemoryTrainingInfo 7810254885Sdumbbell#define SS_Info PPLL_SS_Info 7811254885Sdumbbell#define ASIC_MVDDC_Info ASIC_InternalSS_Info 7812254885Sdumbbell#define DispDevicePriorityInfo SaveRestoreInfo 7813254885Sdumbbell#define DispOutInfo TV_VideoMode 7814254885Sdumbbell 7815254885Sdumbbell 7816254885Sdumbbell#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 7817254885Sdumbbell#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 7818254885Sdumbbell 7819254885Sdumbbell//New device naming, remove them when both DAL/VBIOS is ready 7820254885Sdumbbell#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7821254885Sdumbbell#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 7822254885Sdumbbell 7823254885Sdumbbell#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7824254885Sdumbbell#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 7825254885Sdumbbell 7826254885Sdumbbell#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 7827254885Sdumbbell#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 7828254885Sdumbbell 7829254885Sdumbbell#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 7830254885Sdumbbell#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 7831254885Sdumbbell 7832254885Sdumbbell#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 7833254885Sdumbbell#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 7834254885Sdumbbell 7835254885Sdumbbell#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 7836254885Sdumbbell#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 7837254885Sdumbbell 7838254885Sdumbbell#define ATOM_S0_DFP1I ATOM_S0_DFP1 7839254885Sdumbbell#define ATOM_S0_DFP1X ATOM_S0_DFP2 7840254885Sdumbbell 7841254885Sdumbbell#define ATOM_S0_DFP2I 0x00200000L 7842254885Sdumbbell#define ATOM_S0_DFP2Ib2 0x20 7843254885Sdumbbell 7844254885Sdumbbell#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 7845254885Sdumbbell#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 7846254885Sdumbbell 7847254885Sdumbbell#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 7848254885Sdumbbell#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 7849254885Sdumbbell 7850254885Sdumbbell#define ATOM_S3_DFP2I_ACTIVEb1 0x02 7851254885Sdumbbell 7852254885Sdumbbell#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 7853254885Sdumbbell#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 7854254885Sdumbbell 7855254885Sdumbbell#define ATOM_S3_DFP2I_ACTIVE 0x00000200L 7856254885Sdumbbell 7857254885Sdumbbell#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 7858254885Sdumbbell#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 7859254885Sdumbbell#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 7860254885Sdumbbell 7861254885Sdumbbell#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 7862254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 7863254885Sdumbbell 7864254885Sdumbbell#define ATOM_S5_DOS_REQ_DFP2I 0x0200 7865254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 7866254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 7867254885Sdumbbell 7868254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 7869254885Sdumbbell#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 7870254885Sdumbbell 7871254885Sdumbbell#define TMDS1XEncoderControl DVOEncoderControl 7872254885Sdumbbell#define DFP1XOutputControl DVOOutputControl 7873254885Sdumbbell 7874254885Sdumbbell#define ExternalDFPOutputControl DFP1XOutputControl 7875254885Sdumbbell#define EnableExternalTMDS_Encoder TMDS1XEncoderControl 7876254885Sdumbbell 7877254885Sdumbbell#define DFP1IOutputControl TMDSAOutputControl 7878254885Sdumbbell#define DFP2IOutputControl LVTMAOutputControl 7879254885Sdumbbell 7880254885Sdumbbell#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7881254885Sdumbbell#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7882254885Sdumbbell 7883254885Sdumbbell#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7884254885Sdumbbell#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7885254885Sdumbbell 7886254885Sdumbbell#define ucDac1Standard ucDacStandard 7887254885Sdumbbell#define ucDac2Standard ucDacStandard 7888254885Sdumbbell 7889254885Sdumbbell#define TMDS1EncoderControl TMDSAEncoderControl 7890254885Sdumbbell#define TMDS2EncoderControl LVTMAEncoderControl 7891254885Sdumbbell 7892254885Sdumbbell#define DFP1OutputControl TMDSAOutputControl 7893254885Sdumbbell#define DFP2OutputControl LVTMAOutputControl 7894254885Sdumbbell#define CRT1OutputControl DAC1OutputControl 7895254885Sdumbbell#define CRT2OutputControl DAC2OutputControl 7896254885Sdumbbell 7897254885Sdumbbell//These two lines will be removed for sure in a few days, will follow up with Michael V. 7898254885Sdumbbell#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 7899254885Sdumbbell#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 7900254885Sdumbbell 7901254885Sdumbbell//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7902254885Sdumbbell//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7903254885Sdumbbell//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7904254885Sdumbbell//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7905254885Sdumbbell//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7906254885Sdumbbell 7907254885Sdumbbell#define ATOM_S6_ACC_REQ_TV2 0x00400000L 7908254885Sdumbbell#define ATOM_DEVICE_TV2_INDEX 0x00000006 7909254885Sdumbbell#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 7910254885Sdumbbell#define ATOM_S0_TV2 0x00100000L 7911254885Sdumbbell#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 7912254885Sdumbbell#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 7913254885Sdumbbell 7914254885Sdumbbell// 7915254885Sdumbbell#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7916254885Sdumbbell#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 7917254885Sdumbbell#define ATOM_S2_TV1_DPMS_STATE 0x00040000L 7918254885Sdumbbell#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 7919254885Sdumbbell#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 7920254885Sdumbbell#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 7921254885Sdumbbell#define ATOM_S2_TV2_DPMS_STATE 0x00400000L 7922254885Sdumbbell#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 7923254885Sdumbbell#define ATOM_S2_CV_DPMS_STATE 0x01000000L 7924254885Sdumbbell#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 7925254885Sdumbbell#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 7926254885Sdumbbell#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 7927254885Sdumbbell 7928254885Sdumbbell#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 7929254885Sdumbbell#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 7930254885Sdumbbell#define ATOM_S2_TV1_DPMS_STATEb2 0x04 7931254885Sdumbbell#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 7932254885Sdumbbell#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 7933254885Sdumbbell#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 7934254885Sdumbbell#define ATOM_S2_TV2_DPMS_STATEb2 0x40 7935254885Sdumbbell#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 7936254885Sdumbbell#define ATOM_S2_CV_DPMS_STATEb3 0x01 7937254885Sdumbbell#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 7938254885Sdumbbell#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 7939254885Sdumbbell#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 7940254885Sdumbbell 7941254885Sdumbbell#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 7942254885Sdumbbell#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 7943254885Sdumbbell#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 7944254885Sdumbbell 7945254885Sdumbbell/*********************************************************************************/ 7946254885Sdumbbell 7947254885Sdumbbell#pragma pack() // BIOS data must use byte aligment 7948254885Sdumbbell 7949254885Sdumbbell// 7950254885Sdumbbell// AMD ACPI Table 7951254885Sdumbbell// 7952254885Sdumbbell#pragma pack(1) 7953254885Sdumbbell 7954254885Sdumbbelltypedef struct { 7955254885Sdumbbell ULONG Signature; 7956254885Sdumbbell ULONG TableLength; //Length 7957254885Sdumbbell UCHAR Revision; 7958254885Sdumbbell UCHAR Checksum; 7959254885Sdumbbell UCHAR OemId[6]; 7960254885Sdumbbell UCHAR OemTableId[8]; //UINT64 OemTableId; 7961254885Sdumbbell ULONG OemRevision; 7962254885Sdumbbell ULONG CreatorId; 7963254885Sdumbbell ULONG CreatorRevision; 7964254885Sdumbbell} AMD_ACPI_DESCRIPTION_HEADER; 7965254885Sdumbbell/* 7966254885Sdumbbell//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 7967254885Sdumbbelltypedef struct { 7968254885Sdumbbell UINT32 Signature; //0x0 7969254885Sdumbbell UINT32 Length; //0x4 7970254885Sdumbbell UINT8 Revision; //0x8 7971254885Sdumbbell UINT8 Checksum; //0x9 7972254885Sdumbbell UINT8 OemId[6]; //0xA 7973254885Sdumbbell UINT64 OemTableId; //0x10 7974254885Sdumbbell UINT32 OemRevision; //0x18 7975254885Sdumbbell UINT32 CreatorId; //0x1C 7976254885Sdumbbell UINT32 CreatorRevision; //0x20 7977254885Sdumbbell}EFI_ACPI_DESCRIPTION_HEADER; 7978254885Sdumbbell*/ 7979254885Sdumbbelltypedef struct { 7980254885Sdumbbell AMD_ACPI_DESCRIPTION_HEADER SHeader; 7981254885Sdumbbell UCHAR TableUUID[16]; //0x24 7982298955Spfg ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure. 7983298955Spfg ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure. 7984254885Sdumbbell ULONG Reserved[4]; //0x3C 7985254885Sdumbbell}UEFI_ACPI_VFCT; 7986254885Sdumbbell 7987254885Sdumbbelltypedef struct { 7988254885Sdumbbell ULONG PCIBus; //0x4C 7989254885Sdumbbell ULONG PCIDevice; //0x50 7990254885Sdumbbell ULONG PCIFunction; //0x54 7991254885Sdumbbell USHORT VendorID; //0x58 7992254885Sdumbbell USHORT DeviceID; //0x5A 7993254885Sdumbbell USHORT SSVID; //0x5C 7994254885Sdumbbell USHORT SSID; //0x5E 7995254885Sdumbbell ULONG Revision; //0x60 7996254885Sdumbbell ULONG ImageLength; //0x64 7997254885Sdumbbell}VFCT_IMAGE_HEADER; 7998254885Sdumbbell 7999254885Sdumbbell 8000254885Sdumbbelltypedef struct { 8001254885Sdumbbell VFCT_IMAGE_HEADER VbiosHeader; 8002254885Sdumbbell UCHAR VbiosContent[1]; 8003254885Sdumbbell}GOP_VBIOS_CONTENT; 8004254885Sdumbbell 8005254885Sdumbbelltypedef struct { 8006254885Sdumbbell VFCT_IMAGE_HEADER Lib1Header; 8007254885Sdumbbell UCHAR Lib1Content[1]; 8008254885Sdumbbell}GOP_LIB1_CONTENT; 8009254885Sdumbbell 8010254885Sdumbbell#pragma pack() 8011254885Sdumbbell 8012254885Sdumbbell 8013254885Sdumbbell#endif /* _ATOMBIOS_H */ 8014