intel_sdvo_regs.h revision 235783
1235783Skib/* 2235783Skib * Copyright �� 2006-2007 Intel Corporation 3235783Skib * 4235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 5235783Skib * copy of this software and associated documentation files (the "Software"), 6235783Skib * to deal in the Software without restriction, including without limitation 7235783Skib * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8235783Skib * and/or sell copies of the Software, and to permit persons to whom the 9235783Skib * Software is furnished to do so, subject to the following conditions: 10235783Skib * 11235783Skib * The above copyright notice and this permission notice (including the next 12235783Skib * paragraph) shall be included in all copies or substantial portions of the 13235783Skib * Software. 14235783Skib * 15235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16235783Skib * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17235783Skib * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18235783Skib * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19235783Skib * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20235783Skib * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21235783Skib * DEALINGS IN THE SOFTWARE. 22235783Skib * 23235783Skib * Authors: 24235783Skib * Eric Anholt <eric@anholt.net> 25235783Skib * 26235783Skib * $FreeBSD: head/sys/dev/drm2/i915/intel_sdvo_regs.h 235783 2012-05-22 11:07:44Z kib $ 27235783Skib */ 28235783Skib 29235783Skib/** 30235783Skib * @file SDVO command definitions and structures. 31235783Skib */ 32235783Skib 33235783Skib#define SDVO_OUTPUT_FIRST (0) 34235783Skib#define SDVO_OUTPUT_TMDS0 (1 << 0) 35235783Skib#define SDVO_OUTPUT_RGB0 (1 << 1) 36235783Skib#define SDVO_OUTPUT_CVBS0 (1 << 2) 37235783Skib#define SDVO_OUTPUT_SVID0 (1 << 3) 38235783Skib#define SDVO_OUTPUT_YPRPB0 (1 << 4) 39235783Skib#define SDVO_OUTPUT_SCART0 (1 << 5) 40235783Skib#define SDVO_OUTPUT_LVDS0 (1 << 6) 41235783Skib#define SDVO_OUTPUT_TMDS1 (1 << 8) 42235783Skib#define SDVO_OUTPUT_RGB1 (1 << 9) 43235783Skib#define SDVO_OUTPUT_CVBS1 (1 << 10) 44235783Skib#define SDVO_OUTPUT_SVID1 (1 << 11) 45235783Skib#define SDVO_OUTPUT_YPRPB1 (1 << 12) 46235783Skib#define SDVO_OUTPUT_SCART1 (1 << 13) 47235783Skib#define SDVO_OUTPUT_LVDS1 (1 << 14) 48235783Skib#define SDVO_OUTPUT_LAST (14) 49235783Skib 50235783Skibstruct intel_sdvo_caps { 51235783Skib u8 vendor_id; 52235783Skib u8 device_id; 53235783Skib u8 device_rev_id; 54235783Skib u8 sdvo_version_major; 55235783Skib u8 sdvo_version_minor; 56235783Skib unsigned int sdvo_inputs_mask:2; 57235783Skib unsigned int smooth_scaling:1; 58235783Skib unsigned int sharp_scaling:1; 59235783Skib unsigned int up_scaling:1; 60235783Skib unsigned int down_scaling:1; 61235783Skib unsigned int stall_support:1; 62235783Skib unsigned int pad:1; 63235783Skib u16 output_flags; 64235783Skib} __attribute__((packed)); 65235783Skib 66235783Skib/** This matches the EDID DTD structure, more or less */ 67235783Skibstruct intel_sdvo_dtd { 68235783Skib struct { 69235783Skib u16 clock; /**< pixel clock, in 10kHz units */ 70235783Skib u8 h_active; /**< lower 8 bits (pixels) */ 71235783Skib u8 h_blank; /**< lower 8 bits (pixels) */ 72235783Skib u8 h_high; /**< upper 4 bits each h_active, h_blank */ 73235783Skib u8 v_active; /**< lower 8 bits (lines) */ 74235783Skib u8 v_blank; /**< lower 8 bits (lines) */ 75235783Skib u8 v_high; /**< upper 4 bits each v_active, v_blank */ 76235783Skib } part1; 77235783Skib 78235783Skib struct { 79235783Skib u8 h_sync_off; /**< lower 8 bits, from hblank start */ 80235783Skib u8 h_sync_width; /**< lower 8 bits (pixels) */ 81235783Skib /** lower 4 bits each vsync offset, vsync width */ 82235783Skib u8 v_sync_off_width; 83235783Skib /** 84235783Skib * 2 high bits of hsync offset, 2 high bits of hsync width, 85235783Skib * bits 4-5 of vsync offset, and 2 high bits of vsync width. 86235783Skib */ 87235783Skib u8 sync_off_width_high; 88235783Skib u8 dtd_flags; 89235783Skib u8 sdvo_flags; 90235783Skib /** bits 6-7 of vsync offset at bits 6-7 */ 91235783Skib u8 v_sync_off_high; 92235783Skib u8 reserved; 93235783Skib } part2; 94235783Skib} __attribute__((packed)); 95235783Skib 96235783Skibstruct intel_sdvo_pixel_clock_range { 97235783Skib u16 min; /**< pixel clock, in 10kHz units */ 98235783Skib u16 max; /**< pixel clock, in 10kHz units */ 99235783Skib} __attribute__((packed)); 100235783Skib 101235783Skibstruct intel_sdvo_preferred_input_timing_args { 102235783Skib u16 clock; 103235783Skib u16 width; 104235783Skib u16 height; 105235783Skib u8 interlace:1; 106235783Skib u8 scaled:1; 107235783Skib u8 pad:6; 108235783Skib} __attribute__((packed)); 109235783Skib 110235783Skib/* I2C registers for SDVO */ 111235783Skib#define SDVO_I2C_ARG_0 0x07 112235783Skib#define SDVO_I2C_ARG_1 0x06 113235783Skib#define SDVO_I2C_ARG_2 0x05 114235783Skib#define SDVO_I2C_ARG_3 0x04 115235783Skib#define SDVO_I2C_ARG_4 0x03 116235783Skib#define SDVO_I2C_ARG_5 0x02 117235783Skib#define SDVO_I2C_ARG_6 0x01 118235783Skib#define SDVO_I2C_ARG_7 0x00 119235783Skib#define SDVO_I2C_OPCODE 0x08 120235783Skib#define SDVO_I2C_CMD_STATUS 0x09 121235783Skib#define SDVO_I2C_RETURN_0 0x0a 122235783Skib#define SDVO_I2C_RETURN_1 0x0b 123235783Skib#define SDVO_I2C_RETURN_2 0x0c 124235783Skib#define SDVO_I2C_RETURN_3 0x0d 125235783Skib#define SDVO_I2C_RETURN_4 0x0e 126235783Skib#define SDVO_I2C_RETURN_5 0x0f 127235783Skib#define SDVO_I2C_RETURN_6 0x10 128235783Skib#define SDVO_I2C_RETURN_7 0x11 129235783Skib#define SDVO_I2C_VENDOR_BEGIN 0x20 130235783Skib 131235783Skib/* Status results */ 132235783Skib#define SDVO_CMD_STATUS_POWER_ON 0x0 133235783Skib#define SDVO_CMD_STATUS_SUCCESS 0x1 134235783Skib#define SDVO_CMD_STATUS_NOTSUPP 0x2 135235783Skib#define SDVO_CMD_STATUS_INVALID_ARG 0x3 136235783Skib#define SDVO_CMD_STATUS_PENDING 0x4 137235783Skib#define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5 138235783Skib#define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6 139235783Skib 140235783Skib/* SDVO commands, argument/result registers */ 141235783Skib 142235783Skib#define SDVO_CMD_RESET 0x01 143235783Skib 144235783Skib/** Returns a struct intel_sdvo_caps */ 145235783Skib#define SDVO_CMD_GET_DEVICE_CAPS 0x02 146235783Skib 147235783Skib#define SDVO_CMD_GET_FIRMWARE_REV 0x86 148235783Skib# define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0 149235783Skib# define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1 150235783Skib# define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2 151235783Skib 152235783Skib/** 153235783Skib * Reports which inputs are trained (managed to sync). 154235783Skib * 155235783Skib * Devices must have trained within 2 vsyncs of a mode change. 156235783Skib */ 157235783Skib#define SDVO_CMD_GET_TRAINED_INPUTS 0x03 158235783Skibstruct intel_sdvo_get_trained_inputs_response { 159235783Skib unsigned int input0_trained:1; 160235783Skib unsigned int input1_trained:1; 161235783Skib unsigned int pad:6; 162235783Skib} __attribute__((packed)); 163235783Skib 164235783Skib/** Returns a struct intel_sdvo_output_flags of active outputs. */ 165235783Skib#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 166235783Skib 167235783Skib/** 168235783Skib * Sets the current set of active outputs. 169235783Skib * 170235783Skib * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP 171235783Skib * on multi-output devices. 172235783Skib */ 173235783Skib#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 174235783Skib 175235783Skib/** 176235783Skib * Returns the current mapping of SDVO inputs to outputs on the device. 177235783Skib * 178235783Skib * Returns two struct intel_sdvo_output_flags structures. 179235783Skib */ 180235783Skib#define SDVO_CMD_GET_IN_OUT_MAP 0x06 181235783Skibstruct intel_sdvo_in_out_map { 182235783Skib u16 in0, in1; 183235783Skib}; 184235783Skib 185235783Skib/** 186235783Skib * Sets the current mapping of SDVO inputs to outputs on the device. 187235783Skib * 188235783Skib * Takes two struct i380_sdvo_output_flags structures. 189235783Skib */ 190235783Skib#define SDVO_CMD_SET_IN_OUT_MAP 0x07 191235783Skib 192235783Skib/** 193235783Skib * Returns a struct intel_sdvo_output_flags of attached displays. 194235783Skib */ 195235783Skib#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b 196235783Skib 197235783Skib/** 198235783Skib * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. 199235783Skib */ 200235783Skib#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c 201235783Skib 202235783Skib/** 203235783Skib * Takes a struct intel_sdvo_output_flags. 204235783Skib */ 205235783Skib#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d 206235783Skib 207235783Skib/** 208235783Skib * Returns a struct intel_sdvo_output_flags of displays with hot plug 209235783Skib * interrupts enabled. 210235783Skib */ 211235783Skib#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e 212235783Skib 213235783Skib#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 214235783Skibstruct intel_sdvo_get_interrupt_event_source_response { 215235783Skib u16 interrupt_status; 216235783Skib unsigned int ambient_light_interrupt:1; 217235783Skib unsigned int hdmi_audio_encrypt_change:1; 218235783Skib unsigned int pad:6; 219235783Skib} __attribute__((packed)); 220235783Skib 221235783Skib/** 222235783Skib * Selects which input is affected by future input commands. 223235783Skib * 224235783Skib * Commands affected include SET_INPUT_TIMINGS_PART[12], 225235783Skib * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], 226235783Skib * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. 227235783Skib */ 228235783Skib#define SDVO_CMD_SET_TARGET_INPUT 0x10 229235783Skibstruct intel_sdvo_set_target_input_args { 230235783Skib unsigned int target_1:1; 231235783Skib unsigned int pad:7; 232235783Skib} __attribute__((packed)); 233235783Skib 234235783Skib/** 235235783Skib * Takes a struct intel_sdvo_output_flags of which outputs are targeted by 236235783Skib * future output commands. 237235783Skib * 238235783Skib * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 239235783Skib * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. 240235783Skib */ 241235783Skib#define SDVO_CMD_SET_TARGET_OUTPUT 0x11 242235783Skib 243235783Skib#define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12 244235783Skib#define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13 245235783Skib#define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14 246235783Skib#define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15 247235783Skib#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16 248235783Skib#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17 249235783Skib#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18 250235783Skib#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19 251235783Skib/* Part 1 */ 252235783Skib# define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0 253235783Skib# define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1 254235783Skib# define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2 255235783Skib# define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3 256235783Skib# define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4 257235783Skib# define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5 258235783Skib# define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6 259235783Skib# define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7 260235783Skib/* Part 2 */ 261235783Skib# define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0 262235783Skib# define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1 263235783Skib# define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2 264235783Skib# define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3 265235783Skib# define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4 266235783Skib# define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7) 267235783Skib# define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5) 268235783Skib# define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3) 269235783Skib# define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1) 270235783Skib# define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5 271235783Skib# define SDVO_DTD_SDVO_FLAG_STALL (1 << 7) 272235783Skib# define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6) 273235783Skib# define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6) 274235783Skib# define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4) 275235783Skib# define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4) 276235783Skib# define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4) 277235783Skib# define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4) 278235783Skib# define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6 279235783Skib 280235783Skib/** 281235783Skib * Generates a DTD based on the given width, height, and flags. 282235783Skib * 283235783Skib * This will be supported by any device supporting scaling or interlaced 284235783Skib * modes. 285235783Skib */ 286235783Skib#define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a 287235783Skib# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0 288235783Skib# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1 289235783Skib# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2 290235783Skib# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3 291235783Skib# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4 292235783Skib# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5 293235783Skib# define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6 294235783Skib# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0) 295235783Skib# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1) 296235783Skib 297235783Skib#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b 298235783Skib#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c 299235783Skib 300235783Skib/** Returns a struct intel_sdvo_pixel_clock_range */ 301235783Skib#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d 302235783Skib/** Returns a struct intel_sdvo_pixel_clock_range */ 303235783Skib#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e 304235783Skib 305235783Skib/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 306235783Skib#define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f 307235783Skib 308235783Skib/** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 309235783Skib#define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20 310235783Skib/** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 311235783Skib#define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21 312235783Skib# define SDVO_CLOCK_RATE_MULT_1X (1 << 0) 313235783Skib# define SDVO_CLOCK_RATE_MULT_2X (1 << 1) 314235783Skib# define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 315235783Skib 316235783Skib#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 317235783Skib/** 6 bytes of bit flags for TV formats shared by all TV format functions */ 318235783Skibstruct intel_sdvo_tv_format { 319235783Skib unsigned int ntsc_m:1; 320235783Skib unsigned int ntsc_j:1; 321235783Skib unsigned int ntsc_443:1; 322235783Skib unsigned int pal_b:1; 323235783Skib unsigned int pal_d:1; 324235783Skib unsigned int pal_g:1; 325235783Skib unsigned int pal_h:1; 326235783Skib unsigned int pal_i:1; 327235783Skib 328235783Skib unsigned int pal_m:1; 329235783Skib unsigned int pal_n:1; 330235783Skib unsigned int pal_nc:1; 331235783Skib unsigned int pal_60:1; 332235783Skib unsigned int secam_b:1; 333235783Skib unsigned int secam_d:1; 334235783Skib unsigned int secam_g:1; 335235783Skib unsigned int secam_k:1; 336235783Skib 337235783Skib unsigned int secam_k1:1; 338235783Skib unsigned int secam_l:1; 339235783Skib unsigned int secam_60:1; 340235783Skib unsigned int hdtv_std_smpte_240m_1080i_59:1; 341235783Skib unsigned int hdtv_std_smpte_240m_1080i_60:1; 342235783Skib unsigned int hdtv_std_smpte_260m_1080i_59:1; 343235783Skib unsigned int hdtv_std_smpte_260m_1080i_60:1; 344235783Skib unsigned int hdtv_std_smpte_274m_1080i_50:1; 345235783Skib 346235783Skib unsigned int hdtv_std_smpte_274m_1080i_59:1; 347235783Skib unsigned int hdtv_std_smpte_274m_1080i_60:1; 348235783Skib unsigned int hdtv_std_smpte_274m_1080p_23:1; 349235783Skib unsigned int hdtv_std_smpte_274m_1080p_24:1; 350235783Skib unsigned int hdtv_std_smpte_274m_1080p_25:1; 351235783Skib unsigned int hdtv_std_smpte_274m_1080p_29:1; 352235783Skib unsigned int hdtv_std_smpte_274m_1080p_30:1; 353235783Skib unsigned int hdtv_std_smpte_274m_1080p_50:1; 354235783Skib 355235783Skib unsigned int hdtv_std_smpte_274m_1080p_59:1; 356235783Skib unsigned int hdtv_std_smpte_274m_1080p_60:1; 357235783Skib unsigned int hdtv_std_smpte_295m_1080i_50:1; 358235783Skib unsigned int hdtv_std_smpte_295m_1080p_50:1; 359235783Skib unsigned int hdtv_std_smpte_296m_720p_59:1; 360235783Skib unsigned int hdtv_std_smpte_296m_720p_60:1; 361235783Skib unsigned int hdtv_std_smpte_296m_720p_50:1; 362235783Skib unsigned int hdtv_std_smpte_293m_480p_59:1; 363235783Skib 364235783Skib unsigned int hdtv_std_smpte_170m_480i_59:1; 365235783Skib unsigned int hdtv_std_iturbt601_576i_50:1; 366235783Skib unsigned int hdtv_std_iturbt601_576p_50:1; 367235783Skib unsigned int hdtv_std_eia_7702a_480i_60:1; 368235783Skib unsigned int hdtv_std_eia_7702a_480p_60:1; 369235783Skib unsigned int pad:3; 370235783Skib} __attribute__((packed)); 371235783Skib 372235783Skib#define SDVO_CMD_GET_TV_FORMAT 0x28 373235783Skib 374235783Skib#define SDVO_CMD_SET_TV_FORMAT 0x29 375235783Skib 376235783Skib/** Returns the resolutiosn that can be used with the given TV format */ 377235783Skib#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83 378235783Skibstruct intel_sdvo_sdtv_resolution_request { 379235783Skib unsigned int ntsc_m:1; 380235783Skib unsigned int ntsc_j:1; 381235783Skib unsigned int ntsc_443:1; 382235783Skib unsigned int pal_b:1; 383235783Skib unsigned int pal_d:1; 384235783Skib unsigned int pal_g:1; 385235783Skib unsigned int pal_h:1; 386235783Skib unsigned int pal_i:1; 387235783Skib 388235783Skib unsigned int pal_m:1; 389235783Skib unsigned int pal_n:1; 390235783Skib unsigned int pal_nc:1; 391235783Skib unsigned int pal_60:1; 392235783Skib unsigned int secam_b:1; 393235783Skib unsigned int secam_d:1; 394235783Skib unsigned int secam_g:1; 395235783Skib unsigned int secam_k:1; 396235783Skib 397235783Skib unsigned int secam_k1:1; 398235783Skib unsigned int secam_l:1; 399235783Skib unsigned int secam_60:1; 400235783Skib unsigned int pad:5; 401235783Skib} __attribute__((packed)); 402235783Skib 403235783Skibstruct intel_sdvo_sdtv_resolution_reply { 404235783Skib unsigned int res_320x200:1; 405235783Skib unsigned int res_320x240:1; 406235783Skib unsigned int res_400x300:1; 407235783Skib unsigned int res_640x350:1; 408235783Skib unsigned int res_640x400:1; 409235783Skib unsigned int res_640x480:1; 410235783Skib unsigned int res_704x480:1; 411235783Skib unsigned int res_704x576:1; 412235783Skib 413235783Skib unsigned int res_720x350:1; 414235783Skib unsigned int res_720x400:1; 415235783Skib unsigned int res_720x480:1; 416235783Skib unsigned int res_720x540:1; 417235783Skib unsigned int res_720x576:1; 418235783Skib unsigned int res_768x576:1; 419235783Skib unsigned int res_800x600:1; 420235783Skib unsigned int res_832x624:1; 421235783Skib 422235783Skib unsigned int res_920x766:1; 423235783Skib unsigned int res_1024x768:1; 424235783Skib unsigned int res_1280x1024:1; 425235783Skib unsigned int pad:5; 426235783Skib} __attribute__((packed)); 427235783Skib 428235783Skib/* Get supported resolution with squire pixel aspect ratio that can be 429235783Skib scaled for the requested HDTV format */ 430235783Skib#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85 431235783Skib 432235783Skibstruct intel_sdvo_hdtv_resolution_request { 433235783Skib unsigned int hdtv_std_smpte_240m_1080i_59:1; 434235783Skib unsigned int hdtv_std_smpte_240m_1080i_60:1; 435235783Skib unsigned int hdtv_std_smpte_260m_1080i_59:1; 436235783Skib unsigned int hdtv_std_smpte_260m_1080i_60:1; 437235783Skib unsigned int hdtv_std_smpte_274m_1080i_50:1; 438235783Skib unsigned int hdtv_std_smpte_274m_1080i_59:1; 439235783Skib unsigned int hdtv_std_smpte_274m_1080i_60:1; 440235783Skib unsigned int hdtv_std_smpte_274m_1080p_23:1; 441235783Skib 442235783Skib unsigned int hdtv_std_smpte_274m_1080p_24:1; 443235783Skib unsigned int hdtv_std_smpte_274m_1080p_25:1; 444235783Skib unsigned int hdtv_std_smpte_274m_1080p_29:1; 445235783Skib unsigned int hdtv_std_smpte_274m_1080p_30:1; 446235783Skib unsigned int hdtv_std_smpte_274m_1080p_50:1; 447235783Skib unsigned int hdtv_std_smpte_274m_1080p_59:1; 448235783Skib unsigned int hdtv_std_smpte_274m_1080p_60:1; 449235783Skib unsigned int hdtv_std_smpte_295m_1080i_50:1; 450235783Skib 451235783Skib unsigned int hdtv_std_smpte_295m_1080p_50:1; 452235783Skib unsigned int hdtv_std_smpte_296m_720p_59:1; 453235783Skib unsigned int hdtv_std_smpte_296m_720p_60:1; 454235783Skib unsigned int hdtv_std_smpte_296m_720p_50:1; 455235783Skib unsigned int hdtv_std_smpte_293m_480p_59:1; 456235783Skib unsigned int hdtv_std_smpte_170m_480i_59:1; 457235783Skib unsigned int hdtv_std_iturbt601_576i_50:1; 458235783Skib unsigned int hdtv_std_iturbt601_576p_50:1; 459235783Skib 460235783Skib unsigned int hdtv_std_eia_7702a_480i_60:1; 461235783Skib unsigned int hdtv_std_eia_7702a_480p_60:1; 462235783Skib unsigned int pad:6; 463235783Skib} __attribute__((packed)); 464235783Skib 465235783Skibstruct intel_sdvo_hdtv_resolution_reply { 466235783Skib unsigned int res_640x480:1; 467235783Skib unsigned int res_800x600:1; 468235783Skib unsigned int res_1024x768:1; 469235783Skib unsigned int res_1280x960:1; 470235783Skib unsigned int res_1400x1050:1; 471235783Skib unsigned int res_1600x1200:1; 472235783Skib unsigned int res_1920x1440:1; 473235783Skib unsigned int res_2048x1536:1; 474235783Skib 475235783Skib unsigned int res_2560x1920:1; 476235783Skib unsigned int res_3200x2400:1; 477235783Skib unsigned int res_3840x2880:1; 478235783Skib unsigned int pad1:5; 479235783Skib 480235783Skib unsigned int res_848x480:1; 481235783Skib unsigned int res_1064x600:1; 482235783Skib unsigned int res_1280x720:1; 483235783Skib unsigned int res_1360x768:1; 484235783Skib unsigned int res_1704x960:1; 485235783Skib unsigned int res_1864x1050:1; 486235783Skib unsigned int res_1920x1080:1; 487235783Skib unsigned int res_2128x1200:1; 488235783Skib 489235783Skib unsigned int res_2560x1400:1; 490235783Skib unsigned int res_2728x1536:1; 491235783Skib unsigned int res_3408x1920:1; 492235783Skib unsigned int res_4264x2400:1; 493235783Skib unsigned int res_5120x2880:1; 494235783Skib unsigned int pad2:3; 495235783Skib 496235783Skib unsigned int res_768x480:1; 497235783Skib unsigned int res_960x600:1; 498235783Skib unsigned int res_1152x720:1; 499235783Skib unsigned int res_1124x768:1; 500235783Skib unsigned int res_1536x960:1; 501235783Skib unsigned int res_1680x1050:1; 502235783Skib unsigned int res_1728x1080:1; 503235783Skib unsigned int res_1920x1200:1; 504235783Skib 505235783Skib unsigned int res_2304x1440:1; 506235783Skib unsigned int res_2456x1536:1; 507235783Skib unsigned int res_3072x1920:1; 508235783Skib unsigned int res_3840x2400:1; 509235783Skib unsigned int res_4608x2880:1; 510235783Skib unsigned int pad3:3; 511235783Skib 512235783Skib unsigned int res_1280x1024:1; 513235783Skib unsigned int pad4:7; 514235783Skib 515235783Skib unsigned int res_1280x768:1; 516235783Skib unsigned int pad5:7; 517235783Skib} __attribute__((packed)); 518235783Skib 519235783Skib/* Get supported power state returns info for encoder and monitor, rely on 520235783Skib last SetTargetInput and SetTargetOutput calls */ 521235783Skib#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a 522235783Skib/* Get power state returns info for encoder and monitor, rely on last 523235783Skib SetTargetInput and SetTargetOutput calls */ 524235783Skib#define SDVO_CMD_GET_POWER_STATE 0x2b 525235783Skib#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b 526235783Skib#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c 527235783Skib# define SDVO_ENCODER_STATE_ON (1 << 0) 528235783Skib# define SDVO_ENCODER_STATE_STANDBY (1 << 1) 529235783Skib# define SDVO_ENCODER_STATE_SUSPEND (1 << 2) 530235783Skib# define SDVO_ENCODER_STATE_OFF (1 << 3) 531235783Skib# define SDVO_MONITOR_STATE_ON (1 << 4) 532235783Skib# define SDVO_MONITOR_STATE_STANDBY (1 << 5) 533235783Skib# define SDVO_MONITOR_STATE_SUSPEND (1 << 6) 534235783Skib# define SDVO_MONITOR_STATE_OFF (1 << 7) 535235783Skib 536235783Skib#define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d 537235783Skib#define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e 538235783Skib#define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f 539235783Skib/** 540235783Skib * The panel power sequencing parameters are in units of milliseconds. 541235783Skib * The high fields are bits 8:9 of the 10-bit values. 542235783Skib */ 543235783Skibstruct sdvo_panel_power_sequencing { 544235783Skib u8 t0; 545235783Skib u8 t1; 546235783Skib u8 t2; 547235783Skib u8 t3; 548235783Skib u8 t4; 549235783Skib 550235783Skib unsigned int t0_high:2; 551235783Skib unsigned int t1_high:2; 552235783Skib unsigned int t2_high:2; 553235783Skib unsigned int t3_high:2; 554235783Skib 555235783Skib unsigned int t4_high:2; 556235783Skib unsigned int pad:6; 557235783Skib} __attribute__((packed)); 558235783Skib 559235783Skib#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30 560235783Skibstruct sdvo_max_backlight_reply { 561235783Skib u8 max_value; 562235783Skib u8 default_value; 563235783Skib} __attribute__((packed)); 564235783Skib 565235783Skib#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31 566235783Skib#define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32 567235783Skib 568235783Skib#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33 569235783Skibstruct sdvo_get_ambient_light_reply { 570235783Skib u16 trip_low; 571235783Skib u16 trip_high; 572235783Skib u16 value; 573235783Skib} __attribute__((packed)); 574235783Skib#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34 575235783Skibstruct sdvo_set_ambient_light_reply { 576235783Skib u16 trip_low; 577235783Skib u16 trip_high; 578235783Skib unsigned int enable:1; 579235783Skib unsigned int pad:7; 580235783Skib} __attribute__((packed)); 581235783Skib 582235783Skib/* Set display power state */ 583235783Skib#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d 584235783Skib# define SDVO_DISPLAY_STATE_ON (1 << 0) 585235783Skib# define SDVO_DISPLAY_STATE_STANDBY (1 << 1) 586235783Skib# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2) 587235783Skib# define SDVO_DISPLAY_STATE_OFF (1 << 3) 588235783Skib 589235783Skib#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84 590235783Skibstruct intel_sdvo_enhancements_reply { 591235783Skib unsigned int flicker_filter:1; 592235783Skib unsigned int flicker_filter_adaptive:1; 593235783Skib unsigned int flicker_filter_2d:1; 594235783Skib unsigned int saturation:1; 595235783Skib unsigned int hue:1; 596235783Skib unsigned int brightness:1; 597235783Skib unsigned int contrast:1; 598235783Skib unsigned int overscan_h:1; 599235783Skib 600235783Skib unsigned int overscan_v:1; 601235783Skib unsigned int hpos:1; 602235783Skib unsigned int vpos:1; 603235783Skib unsigned int sharpness:1; 604235783Skib unsigned int dot_crawl:1; 605235783Skib unsigned int dither:1; 606235783Skib unsigned int tv_chroma_filter:1; 607235783Skib unsigned int tv_luma_filter:1; 608235783Skib} __attribute__((packed)); 609235783Skib 610235783Skib/* Picture enhancement limits below are dependent on the current TV format, 611235783Skib * and thus need to be queried and set after it. 612235783Skib */ 613235783Skib#define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d 614235783Skib#define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b 615235783Skib#define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52 616235783Skib#define SDVO_CMD_GET_MAX_SATURATION 0x55 617235783Skib#define SDVO_CMD_GET_MAX_HUE 0x58 618235783Skib#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b 619235783Skib#define SDVO_CMD_GET_MAX_CONTRAST 0x5e 620235783Skib#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61 621235783Skib#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64 622235783Skib#define SDVO_CMD_GET_MAX_HPOS 0x67 623235783Skib#define SDVO_CMD_GET_MAX_VPOS 0x6a 624235783Skib#define SDVO_CMD_GET_MAX_SHARPNESS 0x6d 625235783Skib#define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74 626235783Skib#define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77 627235783Skibstruct intel_sdvo_enhancement_limits_reply { 628235783Skib u16 max_value; 629235783Skib u16 default_value; 630235783Skib} __attribute__((packed)); 631235783Skib 632235783Skib#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f 633235783Skib#define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80 634235783Skib# define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0) 635235783Skib# define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0) 636235783Skib# define SDVO_LVDS_CONNECTOR_SPWG (0 << 2) 637235783Skib# define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2) 638235783Skib# define SDVO_LVDS_SINGLE_CHANNEL (0 << 4) 639235783Skib# define SDVO_LVDS_DUAL_CHANNEL (1 << 4) 640235783Skib 641235783Skib#define SDVO_CMD_GET_FLICKER_FILTER 0x4e 642235783Skib#define SDVO_CMD_SET_FLICKER_FILTER 0x4f 643235783Skib#define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50 644235783Skib#define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51 645235783Skib#define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53 646235783Skib#define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54 647235783Skib#define SDVO_CMD_GET_SATURATION 0x56 648235783Skib#define SDVO_CMD_SET_SATURATION 0x57 649235783Skib#define SDVO_CMD_GET_HUE 0x59 650235783Skib#define SDVO_CMD_SET_HUE 0x5a 651235783Skib#define SDVO_CMD_GET_BRIGHTNESS 0x5c 652235783Skib#define SDVO_CMD_SET_BRIGHTNESS 0x5d 653235783Skib#define SDVO_CMD_GET_CONTRAST 0x5f 654235783Skib#define SDVO_CMD_SET_CONTRAST 0x60 655235783Skib#define SDVO_CMD_GET_OVERSCAN_H 0x62 656235783Skib#define SDVO_CMD_SET_OVERSCAN_H 0x63 657235783Skib#define SDVO_CMD_GET_OVERSCAN_V 0x65 658235783Skib#define SDVO_CMD_SET_OVERSCAN_V 0x66 659235783Skib#define SDVO_CMD_GET_HPOS 0x68 660235783Skib#define SDVO_CMD_SET_HPOS 0x69 661235783Skib#define SDVO_CMD_GET_VPOS 0x6b 662235783Skib#define SDVO_CMD_SET_VPOS 0x6c 663235783Skib#define SDVO_CMD_GET_SHARPNESS 0x6e 664235783Skib#define SDVO_CMD_SET_SHARPNESS 0x6f 665235783Skib#define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75 666235783Skib#define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76 667235783Skib#define SDVO_CMD_GET_TV_LUMA_FILTER 0x78 668235783Skib#define SDVO_CMD_SET_TV_LUMA_FILTER 0x79 669235783Skibstruct intel_sdvo_enhancements_arg { 670235783Skib u16 value; 671235783Skib} __attribute__((packed)); 672235783Skib 673235783Skib#define SDVO_CMD_GET_DOT_CRAWL 0x70 674235783Skib#define SDVO_CMD_SET_DOT_CRAWL 0x71 675235783Skib# define SDVO_DOT_CRAWL_ON (1 << 0) 676235783Skib# define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1) 677235783Skib 678235783Skib#define SDVO_CMD_GET_DITHER 0x72 679235783Skib#define SDVO_CMD_SET_DITHER 0x73 680235783Skib# define SDVO_DITHER_ON (1 << 0) 681235783Skib# define SDVO_DITHER_DEFAULT_ON (1 << 1) 682235783Skib 683235783Skib#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a 684235783Skib# define SDVO_CONTROL_BUS_PROM (1 << 0) 685235783Skib# define SDVO_CONTROL_BUS_DDC1 (1 << 1) 686235783Skib# define SDVO_CONTROL_BUS_DDC2 (1 << 2) 687235783Skib# define SDVO_CONTROL_BUS_DDC3 (1 << 3) 688235783Skib 689235783Skib/* HDMI op codes */ 690235783Skib#define SDVO_CMD_GET_SUPP_ENCODE 0x9d 691235783Skib#define SDVO_CMD_GET_ENCODE 0x9e 692235783Skib#define SDVO_CMD_SET_ENCODE 0x9f 693235783Skib #define SDVO_ENCODE_DVI 0x0 694235783Skib #define SDVO_ENCODE_HDMI 0x1 695235783Skib#define SDVO_CMD_SET_PIXEL_REPLI 0x8b 696235783Skib#define SDVO_CMD_GET_PIXEL_REPLI 0x8c 697235783Skib#define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d 698235783Skib#define SDVO_CMD_SET_COLORIMETRY 0x8e 699235783Skib #define SDVO_COLORIMETRY_RGB256 0x0 700235783Skib #define SDVO_COLORIMETRY_RGB220 0x1 701235783Skib #define SDVO_COLORIMETRY_YCrCb422 0x3 702235783Skib #define SDVO_COLORIMETRY_YCrCb444 0x4 703235783Skib#define SDVO_CMD_GET_COLORIMETRY 0x8f 704235783Skib#define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90 705235783Skib#define SDVO_CMD_SET_AUDIO_STAT 0x91 706235783Skib#define SDVO_CMD_GET_AUDIO_STAT 0x92 707235783Skib#define SDVO_CMD_SET_HBUF_INDEX 0x93 708235783Skib#define SDVO_CMD_GET_HBUF_INDEX 0x94 709235783Skib#define SDVO_CMD_GET_HBUF_INFO 0x95 710235783Skib#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96 711235783Skib#define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97 712235783Skib#define SDVO_CMD_SET_HBUF_DATA 0x98 713235783Skib#define SDVO_CMD_GET_HBUF_DATA 0x99 714235783Skib#define SDVO_CMD_SET_HBUF_TXRATE 0x9a 715235783Skib#define SDVO_CMD_GET_HBUF_TXRATE 0x9b 716235783Skib #define SDVO_HBUF_TX_DISABLED (0 << 6) 717235783Skib #define SDVO_HBUF_TX_ONCE (2 << 6) 718235783Skib #define SDVO_HBUF_TX_VSYNC (3 << 6) 719235783Skib#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c 720235783Skib#define SDVO_NEED_TO_STALL (1 << 7) 721235783Skib 722235783Skibstruct intel_sdvo_encode { 723235783Skib u8 dvi_rev; 724235783Skib u8 hdmi_rev; 725235783Skib} __attribute__ ((packed)); 726