i915_gem.c revision 296548
1/* 2 * Copyright �� 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * Copyright (c) 2011 The FreeBSD Foundation 27 * All rights reserved. 28 * 29 * This software was developed by Konstantin Belousov under sponsorship from 30 * the FreeBSD Foundation. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54#include <sys/cdefs.h> 55__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 296548 2016-03-08 20:33:02Z dumbbell $"); 56 57#include <dev/drm2/drmP.h> 58#include <dev/drm2/i915/i915_drm.h> 59#include <dev/drm2/i915/i915_drv.h> 60#include <dev/drm2/i915/intel_drv.h> 61 62#include <sys/resourcevar.h> 63#include <sys/sched.h> 64#include <sys/sf_buf.h> 65 66#include <vm/vm.h> 67#include <vm/vm_pageout.h> 68 69#include <machine/md_var.h> 70 71static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); 72static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); 73static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, 74 unsigned alignment, 75 bool map_and_fenceable, 76 bool nonblocking); 77static int i915_gem_phys_pwrite(struct drm_device *dev, 78 struct drm_i915_gem_object *obj, 79 struct drm_i915_gem_pwrite *args, 80 struct drm_file *file); 81 82static void i915_gem_write_fence(struct drm_device *dev, int reg, 83 struct drm_i915_gem_object *obj); 84static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, 85 struct drm_i915_fence_reg *fence, 86 bool enable); 87 88static void i915_gem_inactive_shrink(void *); 89static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); 90static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); 91static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); 92 93static int i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj, 94 off_t start, off_t end); 95 96static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex, 97 bool *fresh); 98 99MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem"); 100long i915_gem_wired_pages_cnt; 101 102static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) 103{ 104 if (obj->tiling_mode) 105 i915_gem_release_mmap(obj); 106 107 /* As we do not have an associated fence register, we will force 108 * a tiling change if we ever need to acquire one. 109 */ 110 obj->fence_dirty = false; 111 obj->fence_reg = I915_FENCE_REG_NONE; 112} 113 114/* some bookkeeping */ 115static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, 116 size_t size) 117{ 118 dev_priv->mm.object_count++; 119 dev_priv->mm.object_memory += size; 120} 121 122static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, 123 size_t size) 124{ 125 dev_priv->mm.object_count--; 126 dev_priv->mm.object_memory -= size; 127} 128 129static int 130i915_gem_wait_for_error(struct drm_device *dev) 131{ 132 struct drm_i915_private *dev_priv = dev->dev_private; 133 struct completion *x = &dev_priv->error_completion; 134 int ret; 135 136 if (!atomic_read(&dev_priv->mm.wedged)) 137 return 0; 138 139 /* 140 * Only wait 10 seconds for the gpu reset to complete to avoid hanging 141 * userspace. If it takes that long something really bad is going on and 142 * we should simply try to bail out and fail as gracefully as possible. 143 */ 144 ret = wait_for_completion_interruptible_timeout(x, 10*HZ); 145 if (ret == 0) { 146 DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); 147 return -EIO; 148 } else if (ret < 0) { 149 return ret; 150 } 151 152 if (atomic_read(&dev_priv->mm.wedged)) { 153 /* GPU is hung, bump the completion count to account for 154 * the token we just consumed so that we never hit zero and 155 * end up waiting upon a subsequent completion event that 156 * will never happen. 157 */ 158 mtx_lock(&x->lock); 159 x->done++; 160 mtx_unlock(&x->lock); 161 } 162 return 0; 163} 164 165int i915_mutex_lock_interruptible(struct drm_device *dev) 166{ 167 int ret; 168 169 ret = i915_gem_wait_for_error(dev); 170 if (ret) 171 return ret; 172 173 /* 174 * interruptible shall it be. might indeed be if dev_lock is 175 * changed to sx 176 */ 177 ret = sx_xlock_sig(&dev->dev_struct_lock); 178 if (ret) 179 return -EINTR; 180 181 WARN_ON(i915_verify_lists(dev)); 182 return 0; 183} 184 185static inline bool 186i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) 187{ 188 return obj->gtt_space && !obj->active; 189} 190 191int 192i915_gem_init_ioctl(struct drm_device *dev, void *data, 193 struct drm_file *file) 194{ 195 struct drm_i915_gem_init *args = data; 196 197 if (drm_core_check_feature(dev, DRIVER_MODESET)) 198 return -ENODEV; 199 200 if (args->gtt_start >= args->gtt_end || 201 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) 202 return -EINVAL; 203 204 /* GEM with user mode setting was never supported on ilk and later. */ 205 if (INTEL_INFO(dev)->gen >= 5) 206 return -ENODEV; 207 208 /* 209 * XXXKIB. The second-time initialization should be guarded 210 * against. 211 */ 212 DRM_LOCK(dev); 213 i915_gem_init_global_gtt(dev, args->gtt_start, 214 args->gtt_end, args->gtt_end); 215 DRM_UNLOCK(dev); 216 217 return 0; 218} 219 220int 221i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 222 struct drm_file *file) 223{ 224 struct drm_i915_private *dev_priv = dev->dev_private; 225 struct drm_i915_gem_get_aperture *args = data; 226 struct drm_i915_gem_object *obj; 227 size_t pinned; 228 229 pinned = 0; 230 DRM_LOCK(dev); 231 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) 232 if (obj->pin_count) 233 pinned += obj->gtt_space->size; 234 DRM_UNLOCK(dev); 235 236 args->aper_size = dev_priv->mm.gtt_total; 237 args->aper_available_size = args->aper_size - pinned; 238 239 return 0; 240} 241 242static int 243i915_gem_create(struct drm_file *file, 244 struct drm_device *dev, 245 uint64_t size, 246 uint32_t *handle_p) 247{ 248 struct drm_i915_gem_object *obj; 249 int ret; 250 u32 handle; 251 252 size = roundup(size, PAGE_SIZE); 253 if (size == 0) 254 return -EINVAL; 255 256 /* Allocate the new object */ 257 obj = i915_gem_alloc_object(dev, size); 258 if (obj == NULL) 259 return -ENOMEM; 260 261 ret = drm_gem_handle_create(file, &obj->base, &handle); 262 if (ret) { 263 drm_gem_object_release(&obj->base); 264 i915_gem_info_remove_obj(dev->dev_private, obj->base.size); 265 free(obj, DRM_I915_GEM); 266 return ret; 267 } 268 269 /* drop reference from allocate - handle holds it now */ 270 drm_gem_object_unreference(&obj->base); 271 CTR2(KTR_DRM, "object_create %p %x", obj, size); 272 273 *handle_p = handle; 274 return 0; 275} 276 277int 278i915_gem_dumb_create(struct drm_file *file, 279 struct drm_device *dev, 280 struct drm_mode_create_dumb *args) 281{ 282 /* have to work out size/pitch and return them */ 283 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64); 284 args->size = args->pitch * args->height; 285 return i915_gem_create(file, dev, 286 args->size, &args->handle); 287} 288 289int i915_gem_dumb_destroy(struct drm_file *file, 290 struct drm_device *dev, 291 uint32_t handle) 292{ 293 return drm_gem_handle_delete(file, handle); 294} 295 296/** 297 * Creates a new mm object and returns a handle to it. 298 */ 299int 300i915_gem_create_ioctl(struct drm_device *dev, void *data, 301 struct drm_file *file) 302{ 303 struct drm_i915_gem_create *args = data; 304 305 return i915_gem_create(file, dev, 306 args->size, &args->handle); 307} 308 309static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 310{ 311 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 312 313 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 314 obj->tiling_mode != I915_TILING_NONE; 315} 316 317static inline int 318__copy_to_user_swizzled(char __user *cpu_vaddr, 319 const char *gpu_vaddr, int gpu_offset, 320 int length) 321{ 322 int ret, cpu_offset = 0; 323 324 while (length > 0) { 325 int cacheline_end = roundup2(gpu_offset + 1, 64); 326 int this_length = min(cacheline_end - gpu_offset, length); 327 int swizzled_gpu_offset = gpu_offset ^ 64; 328 329 ret = __copy_to_user(cpu_vaddr + cpu_offset, 330 gpu_vaddr + swizzled_gpu_offset, 331 this_length); 332 if (ret) 333 return ret + length; 334 335 cpu_offset += this_length; 336 gpu_offset += this_length; 337 length -= this_length; 338 } 339 340 return 0; 341} 342 343static inline int 344__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, 345 const char __user *cpu_vaddr, 346 int length) 347{ 348 int ret, cpu_offset = 0; 349 350 while (length > 0) { 351 int cacheline_end = roundup2(gpu_offset + 1, 64); 352 int this_length = min(cacheline_end - gpu_offset, length); 353 int swizzled_gpu_offset = gpu_offset ^ 64; 354 355 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, 356 cpu_vaddr + cpu_offset, 357 this_length); 358 if (ret) 359 return ret + length; 360 361 cpu_offset += this_length; 362 gpu_offset += this_length; 363 length -= this_length; 364 } 365 366 return 0; 367} 368 369/* Per-page copy function for the shmem pread fastpath. 370 * Flushes invalid cachelines before reading the target if 371 * needs_clflush is set. */ 372static int 373shmem_pread_fast(vm_page_t page, int shmem_page_offset, int page_length, 374 char __user *user_data, 375 bool page_do_bit17_swizzling, bool needs_clflush) 376{ 377 char *vaddr; 378 struct sf_buf *sf; 379 int ret; 380 381 if (unlikely(page_do_bit17_swizzling)) 382 return -EINVAL; 383 384 sched_pin(); 385 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE); 386 if (sf == NULL) { 387 sched_unpin(); 388 return (-EFAULT); 389 } 390 vaddr = (char *)sf_buf_kva(sf); 391 if (needs_clflush) 392 drm_clflush_virt_range(vaddr + shmem_page_offset, 393 page_length); 394 ret = __copy_to_user_inatomic(user_data, 395 vaddr + shmem_page_offset, 396 page_length); 397 sf_buf_free(sf); 398 sched_unpin(); 399 400 return ret ? -EFAULT : 0; 401} 402 403static void 404shmem_clflush_swizzled_range(char *addr, unsigned long length, 405 bool swizzled) 406{ 407 if (unlikely(swizzled)) { 408 unsigned long start = (unsigned long) addr; 409 unsigned long end = (unsigned long) addr + length; 410 411 /* For swizzling simply ensure that we always flush both 412 * channels. Lame, but simple and it works. Swizzled 413 * pwrite/pread is far from a hotpath - current userspace 414 * doesn't use it at all. */ 415 start = round_down(start, 128); 416 end = round_up(end, 128); 417 418 drm_clflush_virt_range((void *)start, end - start); 419 } else { 420 drm_clflush_virt_range(addr, length); 421 } 422 423} 424 425/* Only difference to the fast-path function is that this can handle bit17 426 * and uses non-atomic copy and kmap functions. */ 427static int 428shmem_pread_slow(vm_page_t page, int shmem_page_offset, int page_length, 429 char __user *user_data, 430 bool page_do_bit17_swizzling, bool needs_clflush) 431{ 432 char *vaddr; 433 struct sf_buf *sf; 434 int ret; 435 436 sf = sf_buf_alloc(page, 0); 437 vaddr = (char *)sf_buf_kva(sf); 438 if (needs_clflush) 439 shmem_clflush_swizzled_range(vaddr + shmem_page_offset, 440 page_length, 441 page_do_bit17_swizzling); 442 443 if (page_do_bit17_swizzling) 444 ret = __copy_to_user_swizzled(user_data, 445 vaddr, shmem_page_offset, 446 page_length); 447 else 448 ret = __copy_to_user(user_data, 449 vaddr + shmem_page_offset, 450 page_length); 451 sf_buf_free(sf); 452 453 return ret ? - EFAULT : 0; 454} 455 456static int 457i915_gem_shmem_pread(struct drm_device *dev, 458 struct drm_i915_gem_object *obj, 459 struct drm_i915_gem_pread *args, 460 struct drm_file *file) 461{ 462 char __user *user_data; 463 ssize_t remain; 464 off_t offset; 465 int shmem_page_offset, page_length, ret = 0; 466 int obj_do_bit17_swizzling, page_do_bit17_swizzling; 467 int hit_slowpath = 0; 468 int prefaulted = 0; 469 int needs_clflush = 0; 470 471 user_data = to_user_ptr(args->data_ptr); 472 remain = args->size; 473 474 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); 475 476 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { 477 /* If we're not in the cpu read domain, set ourself into the gtt 478 * read domain and manually flush cachelines (if required). This 479 * optimizes for the case when the gpu will dirty the data 480 * anyway again before the next pread happens. */ 481 if (obj->cache_level == I915_CACHE_NONE) 482 needs_clflush = 1; 483 if (obj->gtt_space) { 484 ret = i915_gem_object_set_to_gtt_domain(obj, false); 485 if (ret) 486 return ret; 487 } 488 } 489 490 ret = i915_gem_object_get_pages(obj); 491 if (ret) 492 return ret; 493 494 i915_gem_object_pin_pages(obj); 495 496 offset = args->offset; 497 498 VM_OBJECT_WLOCK(obj->base.vm_obj); 499 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj, 500 OFF_TO_IDX(offset));; page = vm_page_next(page)) { 501 VM_OBJECT_WUNLOCK(obj->base.vm_obj); 502 503 if (remain <= 0) 504 break; 505 506 /* Operation in this page 507 * 508 * shmem_page_offset = offset within page in shmem file 509 * page_length = bytes to copy for this page 510 */ 511 shmem_page_offset = offset_in_page(offset); 512 page_length = remain; 513 if ((shmem_page_offset + page_length) > PAGE_SIZE) 514 page_length = PAGE_SIZE - shmem_page_offset; 515 516 page_do_bit17_swizzling = obj_do_bit17_swizzling && 517 (page_to_phys(page) & (1 << 17)) != 0; 518 519 ret = shmem_pread_fast(page, shmem_page_offset, page_length, 520 user_data, page_do_bit17_swizzling, 521 needs_clflush); 522 if (ret == 0) 523 goto next_page; 524 525 hit_slowpath = 1; 526 DRM_UNLOCK(dev); 527 528 if (!prefaulted) { 529 ret = fault_in_multipages_writeable(user_data, remain); 530 /* Userspace is tricking us, but we've already clobbered 531 * its pages with the prefault and promised to write the 532 * data up to the first fault. Hence ignore any errors 533 * and just continue. */ 534 (void)ret; 535 prefaulted = 1; 536 } 537 538 ret = shmem_pread_slow(page, shmem_page_offset, page_length, 539 user_data, page_do_bit17_swizzling, 540 needs_clflush); 541 542 DRM_LOCK(dev); 543 544next_page: 545 vm_page_reference(page); 546 547 if (ret) 548 goto out; 549 550 remain -= page_length; 551 user_data += page_length; 552 offset += page_length; 553 VM_OBJECT_WLOCK(obj->base.vm_obj); 554 } 555 556out: 557 i915_gem_object_unpin_pages(obj); 558 559 if (hit_slowpath) { 560 /* Fixup: Kill any reinstated backing storage pages */ 561 if (obj->madv == __I915_MADV_PURGED) 562 i915_gem_object_truncate(obj); 563 } 564 565 return ret; 566} 567 568/** 569 * Reads data from the object referenced by handle. 570 * 571 * On error, the contents of *data are undefined. 572 */ 573int 574i915_gem_pread_ioctl(struct drm_device *dev, void *data, 575 struct drm_file *file) 576{ 577 struct drm_i915_gem_pread *args = data; 578 struct drm_i915_gem_object *obj; 579 int ret = 0; 580 581 if (args->size == 0) 582 return 0; 583 584 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_WRITE)) 585 return -EFAULT; 586 587 ret = i915_mutex_lock_interruptible(dev); 588 if (ret) 589 return ret; 590 591 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 592 if (&obj->base == NULL) { 593 ret = -ENOENT; 594 goto unlock; 595 } 596 597 /* Bounds check source. */ 598 if (args->offset > obj->base.size || 599 args->size > obj->base.size - args->offset) { 600 ret = -EINVAL; 601 goto out; 602 } 603 604#ifdef FREEBSD_WIP 605 /* prime objects have no backing filp to GEM pread/pwrite 606 * pages from. 607 */ 608 if (!obj->base.filp) { 609 ret = -EINVAL; 610 goto out; 611 } 612#endif /* FREEBSD_WIP */ 613 614 CTR3(KTR_DRM, "pread %p %jx %jx", obj, args->offset, args->size); 615 616 ret = i915_gem_shmem_pread(dev, obj, args, file); 617 618out: 619 drm_gem_object_unreference(&obj->base); 620unlock: 621 DRM_UNLOCK(dev); 622 return ret; 623} 624 625/* This is the fast write path which cannot handle 626 * page faults in the source data 627 */ 628 629static inline int 630fast_user_write(vm_paddr_t mapping_addr, 631 off_t page_base, int page_offset, 632 char __user *user_data, 633 int length) 634{ 635 void __iomem *vaddr_atomic; 636 void *vaddr; 637 unsigned long unwritten; 638 639 vaddr_atomic = pmap_mapdev_attr(mapping_addr + page_base, 640 length, PAT_WRITE_COMBINING); 641 /* We can use the cpu mem copy function because this is X86. */ 642 vaddr = (char __force*)vaddr_atomic + page_offset; 643 unwritten = __copy_from_user_inatomic_nocache(vaddr, 644 user_data, length); 645 pmap_unmapdev((vm_offset_t)vaddr_atomic, length); 646 return unwritten; 647} 648 649/** 650 * This is the fast pwrite path, where we copy the data directly from the 651 * user into the GTT, uncached. 652 */ 653static int 654i915_gem_gtt_pwrite_fast(struct drm_device *dev, 655 struct drm_i915_gem_object *obj, 656 struct drm_i915_gem_pwrite *args, 657 struct drm_file *file) 658{ 659 drm_i915_private_t *dev_priv = dev->dev_private; 660 ssize_t remain; 661 off_t offset, page_base; 662 char __user *user_data; 663 int page_offset, page_length, ret; 664 665 ret = i915_gem_object_pin(obj, 0, true, true); 666 if (ret) 667 goto out; 668 669 ret = i915_gem_object_set_to_gtt_domain(obj, true); 670 if (ret) 671 goto out_unpin; 672 673 ret = i915_gem_object_put_fence(obj); 674 if (ret) 675 goto out_unpin; 676 677 user_data = to_user_ptr(args->data_ptr); 678 remain = args->size; 679 680 offset = obj->gtt_offset + args->offset; 681 682 while (remain > 0) { 683 /* Operation in this page 684 * 685 * page_base = page offset within aperture 686 * page_offset = offset within page 687 * page_length = bytes to copy for this page 688 */ 689 page_base = offset & ~PAGE_MASK; 690 page_offset = offset_in_page(offset); 691 page_length = remain; 692 if ((page_offset + remain) > PAGE_SIZE) 693 page_length = PAGE_SIZE - page_offset; 694 695 /* If we get a fault while copying data, then (presumably) our 696 * source page isn't available. Return the error and we'll 697 * retry in the slow path. 698 */ 699 if (fast_user_write(dev_priv->mm.gtt_base_addr, page_base, 700 page_offset, user_data, page_length)) { 701 ret = -EFAULT; 702 goto out_unpin; 703 } 704 705 remain -= page_length; 706 user_data += page_length; 707 offset += page_length; 708 } 709 710out_unpin: 711 i915_gem_object_unpin(obj); 712out: 713 return ret; 714} 715 716/* Per-page copy function for the shmem pwrite fastpath. 717 * Flushes invalid cachelines before writing to the target if 718 * needs_clflush_before is set and flushes out any written cachelines after 719 * writing if needs_clflush is set. */ 720static int 721shmem_pwrite_fast(vm_page_t page, int shmem_page_offset, int page_length, 722 char __user *user_data, 723 bool page_do_bit17_swizzling, 724 bool needs_clflush_before, 725 bool needs_clflush_after) 726{ 727 char *vaddr; 728 struct sf_buf *sf; 729 int ret; 730 731 if (unlikely(page_do_bit17_swizzling)) 732 return -EINVAL; 733 734 sched_pin(); 735 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE); 736 if (sf == NULL) { 737 sched_unpin(); 738 return (-EFAULT); 739 } 740 vaddr = (char *)sf_buf_kva(sf); 741 if (needs_clflush_before) 742 drm_clflush_virt_range(vaddr + shmem_page_offset, 743 page_length); 744 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, 745 user_data, 746 page_length); 747 if (needs_clflush_after) 748 drm_clflush_virt_range(vaddr + shmem_page_offset, 749 page_length); 750 sf_buf_free(sf); 751 sched_unpin(); 752 753 return ret ? -EFAULT : 0; 754} 755 756/* Only difference to the fast-path function is that this can handle bit17 757 * and uses non-atomic copy and kmap functions. */ 758static int 759shmem_pwrite_slow(vm_page_t page, int shmem_page_offset, int page_length, 760 char __user *user_data, 761 bool page_do_bit17_swizzling, 762 bool needs_clflush_before, 763 bool needs_clflush_after) 764{ 765 char *vaddr; 766 struct sf_buf *sf; 767 int ret; 768 769 sf = sf_buf_alloc(page, 0); 770 vaddr = (char *)sf_buf_kva(sf); 771 if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) 772 shmem_clflush_swizzled_range(vaddr + shmem_page_offset, 773 page_length, 774 page_do_bit17_swizzling); 775 if (page_do_bit17_swizzling) 776 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, 777 user_data, 778 page_length); 779 else 780 ret = __copy_from_user(vaddr + shmem_page_offset, 781 user_data, 782 page_length); 783 if (needs_clflush_after) 784 shmem_clflush_swizzled_range(vaddr + shmem_page_offset, 785 page_length, 786 page_do_bit17_swizzling); 787 sf_buf_free(sf); 788 789 return ret ? -EFAULT : 0; 790} 791 792static int 793i915_gem_shmem_pwrite(struct drm_device *dev, 794 struct drm_i915_gem_object *obj, 795 struct drm_i915_gem_pwrite *args, 796 struct drm_file *file) 797{ 798 ssize_t remain; 799 off_t offset; 800 char __user *user_data; 801 int shmem_page_offset, page_length, ret = 0; 802 int obj_do_bit17_swizzling, page_do_bit17_swizzling; 803 int hit_slowpath = 0; 804 int needs_clflush_after = 0; 805 int needs_clflush_before = 0; 806 807 user_data = to_user_ptr(args->data_ptr); 808 remain = args->size; 809 810 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); 811 812 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { 813 /* If we're not in the cpu write domain, set ourself into the gtt 814 * write domain and manually flush cachelines (if required). This 815 * optimizes for the case when the gpu will use the data 816 * right away and we therefore have to clflush anyway. */ 817 if (obj->cache_level == I915_CACHE_NONE) 818 needs_clflush_after = 1; 819 if (obj->gtt_space) { 820 ret = i915_gem_object_set_to_gtt_domain(obj, true); 821 if (ret) 822 return ret; 823 } 824 } 825 /* Same trick applies for invalidate partially written cachelines before 826 * writing. */ 827 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) 828 && obj->cache_level == I915_CACHE_NONE) 829 needs_clflush_before = 1; 830 831 ret = i915_gem_object_get_pages(obj); 832 if (ret) 833 return ret; 834 835 i915_gem_object_pin_pages(obj); 836 837 offset = args->offset; 838 obj->dirty = 1; 839 840 VM_OBJECT_WLOCK(obj->base.vm_obj); 841 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj, 842 OFF_TO_IDX(offset));; page = vm_page_next(page)) { 843 VM_OBJECT_WUNLOCK(obj->base.vm_obj); 844 int partial_cacheline_write; 845 846 if (remain <= 0) 847 break; 848 849 /* Operation in this page 850 * 851 * shmem_page_offset = offset within page in shmem file 852 * page_length = bytes to copy for this page 853 */ 854 shmem_page_offset = offset_in_page(offset); 855 856 page_length = remain; 857 if ((shmem_page_offset + page_length) > PAGE_SIZE) 858 page_length = PAGE_SIZE - shmem_page_offset; 859 860 /* If we don't overwrite a cacheline completely we need to be 861 * careful to have up-to-date data by first clflushing. Don't 862 * overcomplicate things and flush the entire patch. */ 863 partial_cacheline_write = needs_clflush_before && 864 ((shmem_page_offset | page_length) 865 & (cpu_clflush_line_size - 1)); 866 867 page_do_bit17_swizzling = obj_do_bit17_swizzling && 868 (page_to_phys(page) & (1 << 17)) != 0; 869 870 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, 871 user_data, page_do_bit17_swizzling, 872 partial_cacheline_write, 873 needs_clflush_after); 874 if (ret == 0) 875 goto next_page; 876 877 hit_slowpath = 1; 878 DRM_UNLOCK(dev); 879 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, 880 user_data, page_do_bit17_swizzling, 881 partial_cacheline_write, 882 needs_clflush_after); 883 884 DRM_LOCK(dev); 885 886next_page: 887 vm_page_dirty(page); 888 vm_page_reference(page); 889 890 if (ret) 891 goto out; 892 893 remain -= page_length; 894 user_data += page_length; 895 offset += page_length; 896 VM_OBJECT_WLOCK(obj->base.vm_obj); 897 } 898 899out: 900 i915_gem_object_unpin_pages(obj); 901 902 if (hit_slowpath) { 903 /* Fixup: Kill any reinstated backing storage pages */ 904 if (obj->madv == __I915_MADV_PURGED) 905 i915_gem_object_truncate(obj); 906 /* and flush dirty cachelines in case the object isn't in the cpu write 907 * domain anymore. */ 908 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { 909 i915_gem_clflush_object(obj); 910 i915_gem_chipset_flush(dev); 911 } 912 } 913 914 if (needs_clflush_after) 915 i915_gem_chipset_flush(dev); 916 917 return ret; 918} 919 920/** 921 * Writes data to the object referenced by handle. 922 * 923 * On error, the contents of the buffer that were to be modified are undefined. 924 */ 925int 926i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 927 struct drm_file *file) 928{ 929 struct drm_i915_gem_pwrite *args = data; 930 struct drm_i915_gem_object *obj; 931 int ret; 932 933 if (args->size == 0) 934 return 0; 935 936 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_READ)) 937 return -EFAULT; 938 939 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), 940 args->size); 941 if (ret) 942 return -EFAULT; 943 944 ret = i915_mutex_lock_interruptible(dev); 945 if (ret) 946 return ret; 947 948 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 949 if (&obj->base == NULL) { 950 ret = -ENOENT; 951 goto unlock; 952 } 953 954 /* Bounds check destination. */ 955 if (args->offset > obj->base.size || 956 args->size > obj->base.size - args->offset) { 957 ret = -EINVAL; 958 goto out; 959 } 960 961#ifdef FREEBSD_WIP 962 /* prime objects have no backing filp to GEM pread/pwrite 963 * pages from. 964 */ 965 if (!obj->base.filp) { 966 ret = -EINVAL; 967 goto out; 968 } 969#endif /* FREEBSD_WIP */ 970 971 CTR3(KTR_DRM, "pwrite %p %jx %jx", obj, args->offset, args->size); 972 973 ret = -EFAULT; 974 /* We can only do the GTT pwrite on untiled buffers, as otherwise 975 * it would end up going through the fenced access, and we'll get 976 * different detiling behavior between reading and writing. 977 * pread/pwrite currently are reading and writing from the CPU 978 * perspective, requiring manual detiling by the client. 979 */ 980 if (obj->phys_obj) { 981 ret = i915_gem_phys_pwrite(dev, obj, args, file); 982 goto out; 983 } 984 985 if (obj->cache_level == I915_CACHE_NONE && 986 obj->tiling_mode == I915_TILING_NONE && 987 obj->base.write_domain != I915_GEM_DOMAIN_CPU) { 988 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); 989 /* Note that the gtt paths might fail with non-page-backed user 990 * pointers (e.g. gtt mappings when moving data between 991 * textures). Fallback to the shmem path in that case. */ 992 } 993 994 if (ret == -EFAULT || ret == -ENOSPC) 995 ret = i915_gem_shmem_pwrite(dev, obj, args, file); 996 997out: 998 drm_gem_object_unreference(&obj->base); 999unlock: 1000 DRM_UNLOCK(dev); 1001 return ret; 1002} 1003 1004int 1005i915_gem_check_wedge(struct drm_i915_private *dev_priv, 1006 bool interruptible) 1007{ 1008 if (atomic_read(&dev_priv->mm.wedged)) { 1009 struct completion *x = &dev_priv->error_completion; 1010 bool recovery_complete; 1011 1012 /* Give the error handler a chance to run. */ 1013 mtx_lock(&x->lock); 1014 recovery_complete = x->done > 0; 1015 mtx_unlock(&x->lock); 1016 1017 /* Non-interruptible callers can't handle -EAGAIN, hence return 1018 * -EIO unconditionally for these. */ 1019 if (!interruptible) 1020 return -EIO; 1021 1022 /* Recovery complete, but still wedged means reset failure. */ 1023 if (recovery_complete) 1024 return -EIO; 1025 1026 return -EAGAIN; 1027 } 1028 1029 return 0; 1030} 1031 1032/* 1033 * Compare seqno against outstanding lazy request. Emit a request if they are 1034 * equal. 1035 */ 1036static int 1037i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) 1038{ 1039 int ret; 1040 1041 DRM_LOCK_ASSERT(ring->dev); 1042 1043 ret = 0; 1044 if (seqno == ring->outstanding_lazy_request) 1045 ret = i915_add_request(ring, NULL, NULL); 1046 1047 return ret; 1048} 1049 1050/** 1051 * __wait_seqno - wait until execution of seqno has finished 1052 * @ring: the ring expected to report seqno 1053 * @seqno: duh! 1054 * @interruptible: do an interruptible wait (normally yes) 1055 * @timeout: in - how long to wait (NULL forever); out - how much time remaining 1056 * 1057 * Returns 0 if the seqno was found within the alloted time. Else returns the 1058 * errno with remaining time filled in timeout argument. 1059 */ 1060static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 1061 bool interruptible, struct timespec *timeout) 1062{ 1063 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1064 struct timespec before, now, wait_time={1,0}; 1065 sbintime_t timeout_sbt; 1066 long end; 1067 bool wait_forever = true; 1068 int ret, flags; 1069 1070 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) 1071 return 0; 1072 1073 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno); 1074 1075 if (timeout != NULL) { 1076 wait_time = *timeout; 1077 wait_forever = false; 1078 } 1079 1080 timeout_sbt = tstosbt(wait_time); 1081 1082 if (WARN_ON(!ring->irq_get(ring))) 1083 return -ENODEV; 1084 1085 /* Record current time in case interrupted by signal, or wedged * */ 1086 getrawmonotonic(&before); 1087 1088#define EXIT_COND \ 1089 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ 1090 atomic_read(&dev_priv->mm.wedged)) 1091 flags = interruptible ? PCATCH : 0; 1092 mtx_lock(&dev_priv->irq_lock); 1093 do { 1094 if (EXIT_COND) { 1095 end = 1; 1096 } else { 1097 ret = -msleep_sbt(&ring->irq_queue, &dev_priv->irq_lock, flags, 1098 "915gwr", timeout_sbt, 0, 0); 1099 1100 /* 1101 * NOTE Linux<->FreeBSD: Convert msleep_sbt() return 1102 * value to something close to wait_event*_timeout() 1103 * functions used on Linux. 1104 * 1105 * >0 -> condition is true (end = time remaining) 1106 * =0 -> sleep timed out 1107 * <0 -> error (interrupted) 1108 * 1109 * We fake the remaining time by returning 1. We 1110 * compute a proper value later. 1111 */ 1112 if (EXIT_COND) 1113 /* We fake a remaining time of 1 tick. */ 1114 end = 1; 1115 else if (ret == -EINTR || ret == -ERESTART) 1116 /* Interrupted. */ 1117 end = -ERESTARTSYS; 1118 else 1119 /* Timeout. */ 1120 end = 0; 1121 } 1122 1123 ret = i915_gem_check_wedge(dev_priv, interruptible); 1124 if (ret) 1125 end = ret; 1126 } while (end == 0 && wait_forever); 1127 mtx_unlock(&dev_priv->irq_lock); 1128 1129 getrawmonotonic(&now); 1130 1131 ring->irq_put(ring); 1132 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno, end); 1133#undef EXIT_COND 1134 1135 if (timeout) { 1136 timespecsub(&now, &before); 1137 timespecsub(timeout, &now); 1138 } 1139 1140 switch (end) { 1141 case -EIO: 1142 case -EAGAIN: /* Wedged */ 1143 case -ERESTARTSYS: /* Signal */ 1144 case -ETIMEDOUT: /* Timeout */ 1145 return (int)end; 1146 case 0: /* Timeout */ 1147 return -ETIMEDOUT; 1148 default: /* Completed */ 1149 WARN_ON(end < 0); /* We're not aware of other errors */ 1150 return 0; 1151 } 1152} 1153 1154/** 1155 * Waits for a sequence number to be signaled, and cleans up the 1156 * request and object lists appropriately for that event. 1157 */ 1158int 1159i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) 1160{ 1161 struct drm_device *dev = ring->dev; 1162 struct drm_i915_private *dev_priv = dev->dev_private; 1163 bool interruptible = dev_priv->mm.interruptible; 1164 int ret; 1165 1166 DRM_LOCK_ASSERT(dev); 1167 BUG_ON(seqno == 0); 1168 1169 ret = i915_gem_check_wedge(dev_priv, interruptible); 1170 if (ret) 1171 return ret; 1172 1173 ret = i915_gem_check_olr(ring, seqno); 1174 if (ret) 1175 return ret; 1176 1177 return __wait_seqno(ring, seqno, interruptible, NULL); 1178} 1179 1180/** 1181 * Ensures that all rendering to the object has completed and the object is 1182 * safe to unbind from the GTT or access from the CPU. 1183 */ 1184static __must_check int 1185i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 1186 bool readonly) 1187{ 1188 struct intel_ring_buffer *ring = obj->ring; 1189 u32 seqno; 1190 int ret; 1191 1192 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; 1193 if (seqno == 0) 1194 return 0; 1195 1196 ret = i915_wait_seqno(ring, seqno); 1197 if (ret) 1198 return ret; 1199 1200 i915_gem_retire_requests_ring(ring); 1201 1202 /* Manually manage the write flush as we may have not yet 1203 * retired the buffer. 1204 */ 1205 if (obj->last_write_seqno && 1206 i915_seqno_passed(seqno, obj->last_write_seqno)) { 1207 obj->last_write_seqno = 0; 1208 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; 1209 } 1210 1211 return 0; 1212} 1213 1214/* A nonblocking variant of the above wait. This is a highly dangerous routine 1215 * as the object state may change during this call. 1216 */ 1217static __must_check int 1218i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, 1219 bool readonly) 1220{ 1221 struct drm_device *dev = obj->base.dev; 1222 struct drm_i915_private *dev_priv = dev->dev_private; 1223 struct intel_ring_buffer *ring = obj->ring; 1224 u32 seqno; 1225 int ret; 1226 1227 DRM_LOCK_ASSERT(dev); 1228 BUG_ON(!dev_priv->mm.interruptible); 1229 1230 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; 1231 if (seqno == 0) 1232 return 0; 1233 1234 ret = i915_gem_check_wedge(dev_priv, true); 1235 if (ret) 1236 return ret; 1237 1238 ret = i915_gem_check_olr(ring, seqno); 1239 if (ret) 1240 return ret; 1241 1242 DRM_UNLOCK(dev); 1243 ret = __wait_seqno(ring, seqno, true, NULL); 1244 DRM_LOCK(dev); 1245 1246 i915_gem_retire_requests_ring(ring); 1247 1248 /* Manually manage the write flush as we may have not yet 1249 * retired the buffer. 1250 */ 1251 if (ret == 0 && 1252 obj->last_write_seqno && 1253 i915_seqno_passed(seqno, obj->last_write_seqno)) { 1254 obj->last_write_seqno = 0; 1255 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; 1256 } 1257 1258 return ret; 1259} 1260 1261/** 1262 * Called when user space prepares to use an object with the CPU, either 1263 * through the mmap ioctl's mapping or a GTT mapping. 1264 */ 1265int 1266i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1267 struct drm_file *file) 1268{ 1269 struct drm_i915_gem_set_domain *args = data; 1270 struct drm_i915_gem_object *obj; 1271 uint32_t read_domains = args->read_domains; 1272 uint32_t write_domain = args->write_domain; 1273 int ret; 1274 1275 /* Only handle setting domains to types used by the CPU. */ 1276 if (write_domain & I915_GEM_GPU_DOMAINS) 1277 return -EINVAL; 1278 1279 if (read_domains & I915_GEM_GPU_DOMAINS) 1280 return -EINVAL; 1281 1282 /* Having something in the write domain implies it's in the read 1283 * domain, and only that read domain. Enforce that in the request. 1284 */ 1285 if (write_domain != 0 && read_domains != write_domain) 1286 return -EINVAL; 1287 1288 ret = i915_mutex_lock_interruptible(dev); 1289 if (ret) 1290 return ret; 1291 1292 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 1293 if (&obj->base == NULL) { 1294 ret = -ENOENT; 1295 goto unlock; 1296 } 1297 1298 /* Try to flush the object off the GPU without holding the lock. 1299 * We will repeat the flush holding the lock in the normal manner 1300 * to catch cases where we are gazumped. 1301 */ 1302 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); 1303 if (ret) 1304 goto unref; 1305 1306 if (read_domains & I915_GEM_DOMAIN_GTT) { 1307 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); 1308 1309 /* Silently promote "you're not bound, there was nothing to do" 1310 * to success, since the client was just asking us to 1311 * make sure everything was done. 1312 */ 1313 if (ret == -EINVAL) 1314 ret = 0; 1315 } else { 1316 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); 1317 } 1318 1319unref: 1320 drm_gem_object_unreference(&obj->base); 1321unlock: 1322 DRM_UNLOCK(dev); 1323 return ret; 1324} 1325 1326/** 1327 * Called when user space has done writes to this buffer 1328 */ 1329int 1330i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1331 struct drm_file *file) 1332{ 1333 struct drm_i915_gem_sw_finish *args = data; 1334 struct drm_i915_gem_object *obj; 1335 int ret = 0; 1336 1337 ret = i915_mutex_lock_interruptible(dev); 1338 if (ret) 1339 return ret; 1340 1341 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 1342 if (&obj->base == NULL) { 1343 ret = -ENOENT; 1344 goto unlock; 1345 } 1346 1347 /* Pinned buffers may be scanout, so flush the cache */ 1348 if (obj->pin_count) 1349 i915_gem_object_flush_cpu_write_domain(obj); 1350 1351 drm_gem_object_unreference(&obj->base); 1352unlock: 1353 DRM_UNLOCK(dev); 1354 return ret; 1355} 1356 1357/** 1358 * Maps the contents of an object, returning the address it is mapped 1359 * into. 1360 * 1361 * While the mapping holds a reference on the contents of the object, it doesn't 1362 * imply a ref on the object itself. 1363 */ 1364int 1365i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1366 struct drm_file *file) 1367{ 1368 struct drm_i915_gem_mmap *args = data; 1369 struct drm_gem_object *obj; 1370 struct proc *p; 1371 vm_map_t map; 1372 vm_offset_t addr; 1373 vm_size_t size; 1374 int error, rv; 1375 1376 obj = drm_gem_object_lookup(dev, file, args->handle); 1377 if (obj == NULL) 1378 return -ENOENT; 1379 1380#ifdef FREEBSD_WIP 1381 /* prime objects have no backing filp to GEM mmap 1382 * pages from. 1383 */ 1384 if (!obj->filp) { 1385 drm_gem_object_unreference_unlocked(obj); 1386 return -EINVAL; 1387 } 1388#endif /* FREEBSD_WIP */ 1389 1390 error = 0; 1391 if (args->size == 0) 1392 goto out; 1393 p = curproc; 1394 map = &p->p_vmspace->vm_map; 1395 size = round_page(args->size); 1396 PROC_LOCK(p); 1397 if (map->size + size > lim_cur_proc(p, RLIMIT_VMEM)) { 1398 PROC_UNLOCK(p); 1399 error = -ENOMEM; 1400 goto out; 1401 } 1402 PROC_UNLOCK(p); 1403 1404 addr = 0; 1405 vm_object_reference(obj->vm_obj); 1406 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size, 0, 1407 VMFS_OPTIMAL_SPACE, VM_PROT_READ | VM_PROT_WRITE, 1408 VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE); 1409 if (rv != KERN_SUCCESS) { 1410 vm_object_deallocate(obj->vm_obj); 1411 error = -vm_mmap_to_errno(rv); 1412 } else { 1413 args->addr_ptr = (uint64_t)addr; 1414 } 1415out: 1416 drm_gem_object_unreference_unlocked(obj); 1417 return (error); 1418} 1419 1420static int 1421i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot, 1422 vm_ooffset_t foff, struct ucred *cred, u_short *color) 1423{ 1424 1425 /* 1426 * NOTE Linux<->FreeBSD: drm_gem_mmap_single() takes care of 1427 * calling drm_gem_object_reference(). That's why we don't 1428 * do this here. i915_gem_pager_dtor(), below, will call 1429 * drm_gem_object_unreference(). 1430 * 1431 * On Linux, drm_gem_vm_open() references the object because 1432 * it's called the mapping is copied. drm_gem_vm_open() is not 1433 * called when the mapping is created. So the possible sequences 1434 * are: 1435 * 1. drm_gem_mmap(): ref++ 1436 * 2. drm_gem_vm_close(): ref-- 1437 * 1438 * 1. drm_gem_mmap(): ref++ 1439 * 2. drm_gem_vm_open(): ref++ (for the copied vma) 1440 * 3. drm_gem_vm_close(): ref-- (for the copied vma) 1441 * 4. drm_gem_vm_close(): ref-- (for the initial vma) 1442 * 1443 * On FreeBSD, i915_gem_pager_ctor() is called once during the 1444 * creation of the mapping. No callback is called when the 1445 * mapping is shared during a fork(). i915_gem_pager_dtor() is 1446 * called when the last reference to the mapping is dropped. So 1447 * the only sequence is: 1448 * 1. drm_gem_mmap_single(): ref++ 1449 * 2. i915_gem_pager_ctor(): <noop> 1450 * 3. i915_gem_pager_dtor(): ref-- 1451 */ 1452 1453 *color = 0; /* XXXKIB */ 1454 return (0); 1455} 1456 1457/** 1458 * i915_gem_fault - fault a page into the GTT 1459 * vma: VMA in question 1460 * vmf: fault info 1461 * 1462 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped 1463 * from userspace. The fault handler takes care of binding the object to 1464 * the GTT (if needed), allocating and programming a fence register (again, 1465 * only if needed based on whether the old reg is still valid or the object 1466 * is tiled) and inserting a new PTE into the faulting process. 1467 * 1468 * Note that the faulting process may involve evicting existing objects 1469 * from the GTT and/or fence registers to make room. So performance may 1470 * suffer if the GTT working set is large or there are few fence registers 1471 * left. 1472 */ 1473 1474int i915_intr_pf; 1475 1476static int 1477i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, 1478 vm_page_t *mres) 1479{ 1480 struct drm_gem_object *gem_obj = vm_obj->handle; 1481 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 1482 struct drm_device *dev = obj->base.dev; 1483 drm_i915_private_t *dev_priv = dev->dev_private; 1484 vm_page_t page, oldpage; 1485 int ret = 0; 1486#ifdef FREEBSD_WIP 1487 bool write = (prot & VM_PROT_WRITE) != 0; 1488#else 1489 bool write = true; 1490#endif /* FREEBSD_WIP */ 1491 bool pinned; 1492 1493 vm_object_pip_add(vm_obj, 1); 1494 1495 /* 1496 * Remove the placeholder page inserted by vm_fault() from the 1497 * object before dropping the object lock. If 1498 * i915_gem_release_mmap() is active in parallel on this gem 1499 * object, then it owns the drm device sx and might find the 1500 * placeholder already. Then, since the page is busy, 1501 * i915_gem_release_mmap() sleeps waiting for the busy state 1502 * of the page cleared. We will be unable to acquire drm 1503 * device lock until i915_gem_release_mmap() is able to make a 1504 * progress. 1505 */ 1506 if (*mres != NULL) { 1507 oldpage = *mres; 1508 vm_page_lock(oldpage); 1509 vm_page_remove(oldpage); 1510 vm_page_unlock(oldpage); 1511 *mres = NULL; 1512 } else 1513 oldpage = NULL; 1514 VM_OBJECT_WUNLOCK(vm_obj); 1515retry: 1516 ret = 0; 1517 pinned = 0; 1518 page = NULL; 1519 1520 if (i915_intr_pf) { 1521 ret = i915_mutex_lock_interruptible(dev); 1522 if (ret != 0) 1523 goto out; 1524 } else 1525 DRM_LOCK(dev); 1526 1527 /* 1528 * Since the object lock was dropped, other thread might have 1529 * faulted on the same GTT address and instantiated the 1530 * mapping for the page. Recheck. 1531 */ 1532 VM_OBJECT_WLOCK(vm_obj); 1533 page = vm_page_lookup(vm_obj, OFF_TO_IDX(offset)); 1534 if (page != NULL) { 1535 if (vm_page_busied(page)) { 1536 DRM_UNLOCK(dev); 1537 vm_page_lock(page); 1538 VM_OBJECT_WUNLOCK(vm_obj); 1539 vm_page_busy_sleep(page, "915pee"); 1540 goto retry; 1541 } 1542 goto have_page; 1543 } else 1544 VM_OBJECT_WUNLOCK(vm_obj); 1545 1546 /* Now bind it into the GTT if needed */ 1547 ret = i915_gem_object_pin(obj, 0, true, false); 1548 if (ret) 1549 goto unlock; 1550 pinned = 1; 1551 1552 ret = i915_gem_object_set_to_gtt_domain(obj, write); 1553 if (ret) 1554 goto unpin; 1555 1556 ret = i915_gem_object_get_fence(obj); 1557 if (ret) 1558 goto unpin; 1559 1560 obj->fault_mappable = true; 1561 1562 VM_OBJECT_WLOCK(vm_obj); 1563 page = PHYS_TO_VM_PAGE(dev_priv->mm.gtt_base_addr + obj->gtt_offset + offset); 1564 KASSERT((page->flags & PG_FICTITIOUS) != 0, 1565 ("physical address %#jx not fictitious", 1566 (uintmax_t)(dev_priv->mm.gtt_base_addr + obj->gtt_offset + offset))); 1567 if (page == NULL) { 1568 VM_OBJECT_WUNLOCK(vm_obj); 1569 ret = -EFAULT; 1570 goto unpin; 1571 } 1572 KASSERT((page->flags & PG_FICTITIOUS) != 0, 1573 ("not fictitious %p", page)); 1574 KASSERT(page->wire_count == 1, ("wire_count not 1 %p", page)); 1575 1576 if (vm_page_busied(page)) { 1577 i915_gem_object_unpin(obj); 1578 DRM_UNLOCK(dev); 1579 vm_page_lock(page); 1580 VM_OBJECT_WUNLOCK(vm_obj); 1581 vm_page_busy_sleep(page, "915pbs"); 1582 goto retry; 1583 } 1584 if (vm_page_insert(page, vm_obj, OFF_TO_IDX(offset))) { 1585 i915_gem_object_unpin(obj); 1586 DRM_UNLOCK(dev); 1587 VM_OBJECT_WUNLOCK(vm_obj); 1588 VM_WAIT; 1589 goto retry; 1590 } 1591 page->valid = VM_PAGE_BITS_ALL; 1592have_page: 1593 *mres = page; 1594 vm_page_xbusy(page); 1595 1596 CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot, 1597 page->phys_addr); 1598 if (pinned) { 1599 /* 1600 * We may have not pinned the object if the page was 1601 * found by the call to vm_page_lookup() 1602 */ 1603 i915_gem_object_unpin(obj); 1604 } 1605 DRM_UNLOCK(dev); 1606 if (oldpage != NULL) { 1607 vm_page_lock(oldpage); 1608 vm_page_free(oldpage); 1609 vm_page_unlock(oldpage); 1610 } 1611 vm_object_pip_wakeup(vm_obj); 1612 return (VM_PAGER_OK); 1613 1614unpin: 1615 i915_gem_object_unpin(obj); 1616unlock: 1617 DRM_UNLOCK(dev); 1618out: 1619 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return")); 1620 CTR4(KTR_DRM, "fault_fail %p %jx %x err %d", gem_obj, offset, prot, 1621 -ret); 1622 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) { 1623 kern_yield(PRI_USER); 1624 goto retry; 1625 } 1626 VM_OBJECT_WLOCK(vm_obj); 1627 vm_object_pip_wakeup(vm_obj); 1628 return (VM_PAGER_ERROR); 1629} 1630 1631static void 1632i915_gem_pager_dtor(void *handle) 1633{ 1634 struct drm_gem_object *obj = handle; 1635 struct drm_device *dev = obj->dev; 1636 1637 DRM_LOCK(dev); 1638 drm_gem_object_unreference(obj); 1639 DRM_UNLOCK(dev); 1640} 1641 1642struct cdev_pager_ops i915_gem_pager_ops = { 1643 .cdev_pg_fault = i915_gem_pager_fault, 1644 .cdev_pg_ctor = i915_gem_pager_ctor, 1645 .cdev_pg_dtor = i915_gem_pager_dtor 1646}; 1647 1648/** 1649 * i915_gem_release_mmap - remove physical page mappings 1650 * @obj: obj in question 1651 * 1652 * Preserve the reservation of the mmapping with the DRM core code, but 1653 * relinquish ownership of the pages back to the system. 1654 * 1655 * It is vital that we remove the page mapping if we have mapped a tiled 1656 * object through the GTT and then lose the fence register due to 1657 * resource pressure. Similarly if the object has been moved out of the 1658 * aperture, than pages mapped into userspace must be revoked. Removing the 1659 * mapping will then trigger a page fault on the next user access, allowing 1660 * fixup by i915_gem_fault(). 1661 */ 1662void 1663i915_gem_release_mmap(struct drm_i915_gem_object *obj) 1664{ 1665 vm_object_t devobj; 1666 vm_page_t page; 1667 int i, page_count; 1668 1669 if (!obj->fault_mappable) 1670 return; 1671 1672 CTR3(KTR_DRM, "release_mmap %p %x %x", obj, obj->gtt_offset, 1673 OFF_TO_IDX(obj->base.size)); 1674 devobj = cdev_pager_lookup(obj); 1675 if (devobj != NULL) { 1676 page_count = OFF_TO_IDX(obj->base.size); 1677 1678 VM_OBJECT_WLOCK(devobj); 1679retry: 1680 for (i = 0; i < page_count; i++) { 1681 page = vm_page_lookup(devobj, i); 1682 if (page == NULL) 1683 continue; 1684 if (vm_page_sleep_if_busy(page, "915unm")) 1685 goto retry; 1686 cdev_pager_free_page(devobj, page); 1687 } 1688 VM_OBJECT_WUNLOCK(devobj); 1689 vm_object_deallocate(devobj); 1690 } 1691 1692 obj->fault_mappable = false; 1693} 1694 1695static uint32_t 1696i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) 1697{ 1698 uint32_t gtt_size; 1699 1700 if (INTEL_INFO(dev)->gen >= 4 || 1701 tiling_mode == I915_TILING_NONE) 1702 return size; 1703 1704 /* Previous chips need a power-of-two fence region when tiling */ 1705 if (INTEL_INFO(dev)->gen == 3) 1706 gtt_size = 1024*1024; 1707 else 1708 gtt_size = 512*1024; 1709 1710 while (gtt_size < size) 1711 gtt_size <<= 1; 1712 1713 return gtt_size; 1714} 1715 1716/** 1717 * i915_gem_get_gtt_alignment - return required GTT alignment for an object 1718 * @obj: object to check 1719 * 1720 * Return the required GTT alignment for an object, taking into account 1721 * potential fence register mapping. 1722 */ 1723static uint32_t 1724i915_gem_get_gtt_alignment(struct drm_device *dev, 1725 uint32_t size, 1726 int tiling_mode) 1727{ 1728 /* 1729 * Minimum alignment is 4k (GTT page size), but might be greater 1730 * if a fence register is needed for the object. 1731 */ 1732 if (INTEL_INFO(dev)->gen >= 4 || 1733 tiling_mode == I915_TILING_NONE) 1734 return 4096; 1735 1736 /* 1737 * Previous chips need to be aligned to the size of the smallest 1738 * fence register that can contain the object. 1739 */ 1740 return i915_gem_get_gtt_size(dev, size, tiling_mode); 1741} 1742 1743/** 1744 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an 1745 * unfenced object 1746 * @dev: the device 1747 * @size: size of the object 1748 * @tiling_mode: tiling mode of the object 1749 * 1750 * Return the required GTT alignment for an object, only taking into account 1751 * unfenced tiled surface requirements. 1752 */ 1753uint32_t 1754i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1755 uint32_t size, 1756 int tiling_mode) 1757{ 1758 /* 1759 * Minimum alignment is 4k (GTT page size) for sane hw. 1760 */ 1761 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || 1762 tiling_mode == I915_TILING_NONE) 1763 return 4096; 1764 1765 /* Previous hardware however needs to be aligned to a power-of-two 1766 * tile height. The simplest method for determining this is to reuse 1767 * the power-of-tile object size. 1768 */ 1769 return i915_gem_get_gtt_size(dev, size, tiling_mode); 1770} 1771 1772static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) 1773{ 1774 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1775 int ret; 1776 1777 if (obj->base.on_map) 1778 return 0; 1779 1780 dev_priv->mm.shrinker_no_lock_stealing = true; 1781 1782 ret = drm_gem_create_mmap_offset(&obj->base); 1783 if (ret != -ENOSPC) 1784 goto out; 1785 1786 /* Badly fragmented mmap space? The only way we can recover 1787 * space is by destroying unwanted objects. We can't randomly release 1788 * mmap_offsets as userspace expects them to be persistent for the 1789 * lifetime of the objects. The closest we can is to release the 1790 * offsets on purgeable objects by truncating it and marking it purged, 1791 * which prevents userspace from ever using that object again. 1792 */ 1793 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); 1794 ret = drm_gem_create_mmap_offset(&obj->base); 1795 if (ret != -ENOSPC) 1796 goto out; 1797 1798 i915_gem_shrink_all(dev_priv); 1799 ret = drm_gem_create_mmap_offset(&obj->base); 1800out: 1801 dev_priv->mm.shrinker_no_lock_stealing = false; 1802 1803 return ret; 1804} 1805 1806static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) 1807{ 1808 if (!obj->base.on_map) 1809 return; 1810 1811 drm_gem_free_mmap_offset(&obj->base); 1812} 1813 1814int 1815i915_gem_mmap_gtt(struct drm_file *file, 1816 struct drm_device *dev, 1817 uint32_t handle, 1818 uint64_t *offset) 1819{ 1820 struct drm_i915_private *dev_priv = dev->dev_private; 1821 struct drm_i915_gem_object *obj; 1822 int ret; 1823 1824 ret = i915_mutex_lock_interruptible(dev); 1825 if (ret) 1826 return ret; 1827 1828 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); 1829 if (&obj->base == NULL) { 1830 ret = -ENOENT; 1831 goto unlock; 1832 } 1833 1834 if (obj->base.size > dev_priv->mm.gtt_mappable_end) { 1835 ret = -E2BIG; 1836 goto out; 1837 } 1838 1839 if (obj->madv != I915_MADV_WILLNEED) { 1840 DRM_ERROR("Attempting to mmap a purgeable buffer\n"); 1841 ret = -EINVAL; 1842 goto out; 1843 } 1844 1845 ret = i915_gem_object_create_mmap_offset(obj); 1846 if (ret) 1847 goto out; 1848 1849 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) | 1850 DRM_GEM_MAPPING_KEY; 1851 1852out: 1853 drm_gem_object_unreference(&obj->base); 1854unlock: 1855 DRM_UNLOCK(dev); 1856 return ret; 1857} 1858 1859/** 1860 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing 1861 * @dev: DRM device 1862 * @data: GTT mapping ioctl data 1863 * @file: GEM object info 1864 * 1865 * Simply returns the fake offset to userspace so it can mmap it. 1866 * The mmap call will end up in drm_gem_mmap(), which will set things 1867 * up so we can get faults in the handler above. 1868 * 1869 * The fault handler will take care of binding the object into the GTT 1870 * (since it may have been evicted to make room for something), allocating 1871 * a fence register, and mapping the appropriate aperture address into 1872 * userspace. 1873 */ 1874int 1875i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1876 struct drm_file *file) 1877{ 1878 struct drm_i915_gem_mmap_gtt *args = data; 1879 1880 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); 1881} 1882 1883/* Immediately discard the backing storage */ 1884static void 1885i915_gem_object_truncate(struct drm_i915_gem_object *obj) 1886{ 1887 vm_object_t vm_obj; 1888 1889 vm_obj = obj->base.vm_obj; 1890 VM_OBJECT_WLOCK(vm_obj); 1891 vm_object_page_remove(vm_obj, 0, 0, false); 1892 VM_OBJECT_WUNLOCK(vm_obj); 1893 i915_gem_object_free_mmap_offset(obj); 1894 1895 obj->madv = __I915_MADV_PURGED; 1896} 1897 1898static inline int 1899i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) 1900{ 1901 return obj->madv == I915_MADV_DONTNEED; 1902} 1903 1904static void 1905i915_gem_object_put_pages_range_locked(struct drm_i915_gem_object *obj, 1906 vm_pindex_t si, vm_pindex_t ei) 1907{ 1908 vm_object_t vm_obj; 1909 vm_page_t page; 1910 vm_pindex_t i; 1911 1912 vm_obj = obj->base.vm_obj; 1913 VM_OBJECT_ASSERT_LOCKED(vm_obj); 1914 for (i = si, page = vm_page_lookup(vm_obj, i); i < ei; 1915 page = vm_page_next(page), i++) { 1916 KASSERT(page->pindex == i, ("pindex %jx %jx", 1917 (uintmax_t)page->pindex, (uintmax_t)i)); 1918 vm_page_lock(page); 1919 vm_page_unwire(page, PQ_INACTIVE); 1920 if (page->wire_count == 0) 1921 atomic_add_long(&i915_gem_wired_pages_cnt, -1); 1922 vm_page_unlock(page); 1923 } 1924} 1925 1926#define GEM_PARANOID_CHECK_GTT 0 1927#if GEM_PARANOID_CHECK_GTT 1928static void 1929i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma, 1930 int page_count) 1931{ 1932 struct drm_i915_private *dev_priv; 1933 vm_paddr_t pa; 1934 unsigned long start, end; 1935 u_int i; 1936 int j; 1937 1938 dev_priv = dev->dev_private; 1939 start = OFF_TO_IDX(dev_priv->mm.gtt_start); 1940 end = OFF_TO_IDX(dev_priv->mm.gtt_end); 1941 for (i = start; i < end; i++) { 1942 pa = intel_gtt_read_pte_paddr(i); 1943 for (j = 0; j < page_count; j++) { 1944 if (pa == VM_PAGE_TO_PHYS(ma[j])) { 1945 panic("Page %p in GTT pte index %d pte %x", 1946 ma[i], i, intel_gtt_read_pte(i)); 1947 } 1948 } 1949 } 1950} 1951#endif 1952 1953static void 1954i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) 1955{ 1956 int page_count = obj->base.size / PAGE_SIZE; 1957 int ret, i; 1958 1959 BUG_ON(obj->madv == __I915_MADV_PURGED); 1960 1961 ret = i915_gem_object_set_to_cpu_domain(obj, true); 1962 if (ret) { 1963 /* In the event of a disaster, abandon all caches and 1964 * hope for the best. 1965 */ 1966 WARN_ON(ret != -EIO); 1967 i915_gem_clflush_object(obj); 1968 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; 1969 } 1970 1971 if (i915_gem_object_needs_bit17_swizzle(obj)) 1972 i915_gem_object_save_bit_17_swizzle(obj); 1973 1974 if (obj->madv == I915_MADV_DONTNEED) 1975 obj->dirty = 0; 1976 1977 VM_OBJECT_WLOCK(obj->base.vm_obj); 1978#if GEM_PARANOID_CHECK_GTT 1979 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count); 1980#endif 1981 for (i = 0; i < page_count; i++) { 1982 vm_page_t page = obj->pages[i]; 1983 1984 if (obj->dirty) 1985 vm_page_dirty(page); 1986 1987 if (obj->madv == I915_MADV_WILLNEED) 1988 vm_page_reference(page); 1989 1990 vm_page_lock(page); 1991 vm_page_unwire(obj->pages[i], PQ_ACTIVE); 1992 vm_page_unlock(page); 1993 atomic_add_long(&i915_gem_wired_pages_cnt, -1); 1994 } 1995 VM_OBJECT_WUNLOCK(obj->base.vm_obj); 1996 obj->dirty = 0; 1997 1998 free(obj->pages, DRM_I915_GEM); 1999 obj->pages = NULL; 2000} 2001 2002static int 2003i915_gem_object_put_pages(struct drm_i915_gem_object *obj) 2004{ 2005 const struct drm_i915_gem_object_ops *ops = obj->ops; 2006 2007 if (obj->pages == NULL) 2008 return 0; 2009 2010 BUG_ON(obj->gtt_space); 2011 2012 if (obj->pages_pin_count) 2013 return -EBUSY; 2014 2015 /* ->put_pages might need to allocate memory for the bit17 swizzle 2016 * array, hence protect them from being reaped by removing them from gtt 2017 * lists early. */ 2018 list_del(&obj->gtt_list); 2019 2020 ops->put_pages(obj); 2021 obj->pages = NULL; 2022 2023 if (i915_gem_object_is_purgeable(obj)) 2024 i915_gem_object_truncate(obj); 2025 2026 return 0; 2027} 2028 2029static long 2030__i915_gem_shrink(struct drm_i915_private *dev_priv, long target, 2031 bool purgeable_only) 2032{ 2033 struct drm_i915_gem_object *obj, *next; 2034 long count = 0; 2035 2036 list_for_each_entry_safe(obj, next, 2037 &dev_priv->mm.unbound_list, 2038 gtt_list) { 2039 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && 2040 i915_gem_object_put_pages(obj) == 0) { 2041 count += obj->base.size >> PAGE_SHIFT; 2042 if (target != -1 && count >= target) 2043 return count; 2044 } 2045 } 2046 2047 list_for_each_entry_safe(obj, next, 2048 &dev_priv->mm.inactive_list, 2049 mm_list) { 2050 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && 2051 i915_gem_object_unbind(obj) == 0 && 2052 i915_gem_object_put_pages(obj) == 0) { 2053 count += obj->base.size >> PAGE_SHIFT; 2054 if (target != -1 && count >= target) 2055 return count; 2056 } 2057 } 2058 2059 return count; 2060} 2061 2062static long 2063i915_gem_purge(struct drm_i915_private *dev_priv, long target) 2064{ 2065 return __i915_gem_shrink(dev_priv, target, true); 2066} 2067 2068static void 2069i915_gem_shrink_all(struct drm_i915_private *dev_priv) 2070{ 2071 struct drm_i915_gem_object *obj, *next; 2072 2073 i915_gem_evict_everything(dev_priv->dev); 2074 2075 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) 2076 i915_gem_object_put_pages(obj); 2077} 2078 2079static int 2080i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj, 2081 off_t start, off_t end) 2082{ 2083 vm_object_t vm_obj; 2084 vm_page_t page; 2085 vm_pindex_t si, ei, i; 2086 bool need_swizzle, fresh; 2087 2088 need_swizzle = i915_gem_object_needs_bit17_swizzle(obj) != 0; 2089 vm_obj = obj->base.vm_obj; 2090 si = OFF_TO_IDX(trunc_page(start)); 2091 ei = OFF_TO_IDX(round_page(end)); 2092 VM_OBJECT_WLOCK(vm_obj); 2093 for (i = si; i < ei; i++) { 2094 page = i915_gem_wire_page(vm_obj, i, &fresh); 2095 if (page == NULL) 2096 goto failed; 2097 if (need_swizzle && fresh) 2098 i915_gem_object_do_bit_17_swizzle_page(obj, page); 2099 } 2100 VM_OBJECT_WUNLOCK(vm_obj); 2101 return (0); 2102failed: 2103 i915_gem_object_put_pages_range_locked(obj, si, i); 2104 VM_OBJECT_WUNLOCK(vm_obj); 2105 return (-EIO); 2106} 2107 2108static int 2109i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) 2110{ 2111 vm_object_t vm_obj; 2112 vm_page_t page; 2113 vm_pindex_t i, page_count; 2114 int res; 2115 2116 /* Assert that the object is not currently in any GPU domain. As it 2117 * wasn't in the GTT, there shouldn't be any way it could have been in 2118 * a GPU cache 2119 */ 2120 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); 2121 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); 2122 KASSERT(obj->pages == NULL, ("Obj already has pages")); 2123 2124 page_count = OFF_TO_IDX(obj->base.size); 2125 obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM, 2126 M_WAITOK); 2127 res = i915_gem_object_get_pages_range(obj, 0, obj->base.size); 2128 if (res != 0) { 2129 free(obj->pages, DRM_I915_GEM); 2130 obj->pages = NULL; 2131 return (res); 2132 } 2133 vm_obj = obj->base.vm_obj; 2134 VM_OBJECT_WLOCK(vm_obj); 2135 for (i = 0, page = vm_page_lookup(vm_obj, 0); i < page_count; 2136 i++, page = vm_page_next(page)) { 2137 KASSERT(page->pindex == i, ("pindex %jx %jx", 2138 (uintmax_t)page->pindex, (uintmax_t)i)); 2139 obj->pages[i] = page; 2140 } 2141 VM_OBJECT_WUNLOCK(vm_obj); 2142 return (0); 2143} 2144 2145/* Ensure that the associated pages are gathered from the backing storage 2146 * and pinned into our object. i915_gem_object_get_pages() may be called 2147 * multiple times before they are released by a single call to 2148 * i915_gem_object_put_pages() - once the pages are no longer referenced 2149 * either as a result of memory pressure (reaping pages under the shrinker) 2150 * or as the object is itself released. 2151 */ 2152int 2153i915_gem_object_get_pages(struct drm_i915_gem_object *obj) 2154{ 2155 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2156 const struct drm_i915_gem_object_ops *ops = obj->ops; 2157 int ret; 2158 2159 if (obj->pages) 2160 return 0; 2161 2162 BUG_ON(obj->pages_pin_count); 2163 2164 ret = ops->get_pages(obj); 2165 if (ret) 2166 return ret; 2167 2168 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); 2169 return 0; 2170} 2171 2172void 2173i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 2174 struct intel_ring_buffer *ring) 2175{ 2176 struct drm_device *dev = obj->base.dev; 2177 struct drm_i915_private *dev_priv = dev->dev_private; 2178 u32 seqno = intel_ring_get_seqno(ring); 2179 2180 BUG_ON(ring == NULL); 2181 obj->ring = ring; 2182 2183 /* Add a reference if we're newly entering the active list. */ 2184 if (!obj->active) { 2185 drm_gem_object_reference(&obj->base); 2186 obj->active = 1; 2187 } 2188 2189 /* Move from whatever list we were on to the tail of execution. */ 2190 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); 2191 list_move_tail(&obj->ring_list, &ring->active_list); 2192 2193 obj->last_read_seqno = seqno; 2194 2195 if (obj->fenced_gpu_access) { 2196 obj->last_fenced_seqno = seqno; 2197 2198 /* Bump MRU to take account of the delayed flush */ 2199 if (obj->fence_reg != I915_FENCE_REG_NONE) { 2200 struct drm_i915_fence_reg *reg; 2201 2202 reg = &dev_priv->fence_regs[obj->fence_reg]; 2203 list_move_tail(®->lru_list, 2204 &dev_priv->mm.fence_list); 2205 } 2206 } 2207} 2208 2209static void 2210i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) 2211{ 2212 struct drm_device *dev = obj->base.dev; 2213 struct drm_i915_private *dev_priv = dev->dev_private; 2214 2215 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); 2216 BUG_ON(!obj->active); 2217 2218 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); 2219 2220 list_del_init(&obj->ring_list); 2221 obj->ring = NULL; 2222 2223 obj->last_read_seqno = 0; 2224 obj->last_write_seqno = 0; 2225 obj->base.write_domain = 0; 2226 2227 obj->last_fenced_seqno = 0; 2228 obj->fenced_gpu_access = false; 2229 2230 obj->active = 0; 2231 drm_gem_object_unreference(&obj->base); 2232 2233 WARN_ON(i915_verify_lists(dev)); 2234} 2235 2236static int 2237i915_gem_handle_seqno_wrap(struct drm_device *dev) 2238{ 2239 struct drm_i915_private *dev_priv = dev->dev_private; 2240 struct intel_ring_buffer *ring; 2241 int ret, i, j; 2242 2243 /* The hardware uses various monotonic 32-bit counters, if we 2244 * detect that they will wraparound we need to idle the GPU 2245 * and reset those counters. 2246 */ 2247 ret = 0; 2248 for_each_ring(ring, dev_priv, i) { 2249 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) 2250 ret |= ring->sync_seqno[j] != 0; 2251 } 2252 if (ret == 0) 2253 return ret; 2254 2255 ret = i915_gpu_idle(dev); 2256 if (ret) 2257 return ret; 2258 2259 i915_gem_retire_requests(dev); 2260 for_each_ring(ring, dev_priv, i) { 2261 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) 2262 ring->sync_seqno[j] = 0; 2263 } 2264 2265 return 0; 2266} 2267 2268int 2269i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) 2270{ 2271 struct drm_i915_private *dev_priv = dev->dev_private; 2272 2273 /* reserve 0 for non-seqno */ 2274 if (dev_priv->next_seqno == 0) { 2275 int ret = i915_gem_handle_seqno_wrap(dev); 2276 if (ret) 2277 return ret; 2278 2279 dev_priv->next_seqno = 1; 2280 } 2281 2282 *seqno = dev_priv->next_seqno++; 2283 return 0; 2284} 2285 2286int 2287i915_add_request(struct intel_ring_buffer *ring, 2288 struct drm_file *file, 2289 u32 *out_seqno) 2290{ 2291 drm_i915_private_t *dev_priv = ring->dev->dev_private; 2292 struct drm_i915_gem_request *request; 2293 u32 request_ring_position; 2294 int was_empty; 2295 int ret; 2296 2297 /* 2298 * Emit any outstanding flushes - execbuf can fail to emit the flush 2299 * after having emitted the batchbuffer command. Hence we need to fix 2300 * things up similar to emitting the lazy request. The difference here 2301 * is that the flush _must_ happen before the next request, no matter 2302 * what. 2303 */ 2304 ret = intel_ring_flush_all_caches(ring); 2305 if (ret) 2306 return ret; 2307 2308 request = malloc(sizeof(*request), DRM_I915_GEM, M_NOWAIT); 2309 if (request == NULL) 2310 return -ENOMEM; 2311 2312 2313 /* Record the position of the start of the request so that 2314 * should we detect the updated seqno part-way through the 2315 * GPU processing the request, we never over-estimate the 2316 * position of the head. 2317 */ 2318 request_ring_position = intel_ring_get_tail(ring); 2319 2320 ret = ring->add_request(ring); 2321 if (ret) { 2322 free(request, DRM_I915_GEM); 2323 return ret; 2324 } 2325 2326 request->seqno = intel_ring_get_seqno(ring); 2327 request->ring = ring; 2328 request->tail = request_ring_position; 2329 request->emitted_jiffies = jiffies; 2330 was_empty = list_empty(&ring->request_list); 2331 list_add_tail(&request->list, &ring->request_list); 2332 request->file_priv = NULL; 2333 2334 if (file) { 2335 struct drm_i915_file_private *file_priv = file->driver_priv; 2336 2337 mtx_lock(&file_priv->mm.lock); 2338 request->file_priv = file_priv; 2339 list_add_tail(&request->client_list, 2340 &file_priv->mm.request_list); 2341 mtx_unlock(&file_priv->mm.lock); 2342 } 2343 2344 CTR2(KTR_DRM, "request_add %s %d", ring->name, request->seqno); 2345 ring->outstanding_lazy_request = 0; 2346 2347 if (!dev_priv->mm.suspended) { 2348 if (i915_enable_hangcheck) { 2349 callout_schedule(&dev_priv->hangcheck_timer, 2350 DRM_I915_HANGCHECK_PERIOD); 2351 } 2352 if (was_empty) { 2353 taskqueue_enqueue_timeout(dev_priv->wq, 2354 &dev_priv->mm.retire_work, hz); 2355 intel_mark_busy(dev_priv->dev); 2356 } 2357 } 2358 2359 if (out_seqno) 2360 *out_seqno = request->seqno; 2361 return 0; 2362} 2363 2364static inline void 2365i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) 2366{ 2367 struct drm_i915_file_private *file_priv = request->file_priv; 2368 2369 if (!file_priv) 2370 return; 2371 2372 mtx_lock(&file_priv->mm.lock); 2373 if (request->file_priv) { 2374 list_del(&request->client_list); 2375 request->file_priv = NULL; 2376 } 2377 mtx_unlock(&file_priv->mm.lock); 2378} 2379 2380static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, 2381 struct intel_ring_buffer *ring) 2382{ 2383 if (ring->dev != NULL) 2384 DRM_LOCK_ASSERT(ring->dev); 2385 2386 while (!list_empty(&ring->request_list)) { 2387 struct drm_i915_gem_request *request; 2388 2389 request = list_first_entry(&ring->request_list, 2390 struct drm_i915_gem_request, 2391 list); 2392 2393 list_del(&request->list); 2394 i915_gem_request_remove_from_client(request); 2395 free(request, DRM_I915_GEM); 2396 } 2397 2398 while (!list_empty(&ring->active_list)) { 2399 struct drm_i915_gem_object *obj; 2400 2401 obj = list_first_entry(&ring->active_list, 2402 struct drm_i915_gem_object, 2403 ring_list); 2404 2405 i915_gem_object_move_to_inactive(obj); 2406 } 2407} 2408 2409static void i915_gem_reset_fences(struct drm_device *dev) 2410{ 2411 struct drm_i915_private *dev_priv = dev->dev_private; 2412 int i; 2413 2414 for (i = 0; i < dev_priv->num_fence_regs; i++) { 2415 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; 2416 2417 i915_gem_write_fence(dev, i, NULL); 2418 2419 if (reg->obj) 2420 i915_gem_object_fence_lost(reg->obj); 2421 2422 reg->pin_count = 0; 2423 reg->obj = NULL; 2424 INIT_LIST_HEAD(®->lru_list); 2425 } 2426 2427 INIT_LIST_HEAD(&dev_priv->mm.fence_list); 2428} 2429 2430void i915_gem_reset(struct drm_device *dev) 2431{ 2432 struct drm_i915_private *dev_priv = dev->dev_private; 2433 struct drm_i915_gem_object *obj; 2434 struct intel_ring_buffer *ring; 2435 int i; 2436 2437 for_each_ring(ring, dev_priv, i) 2438 i915_gem_reset_ring_lists(dev_priv, ring); 2439 2440 /* Move everything out of the GPU domains to ensure we do any 2441 * necessary invalidation upon reuse. 2442 */ 2443 list_for_each_entry(obj, 2444 &dev_priv->mm.inactive_list, 2445 mm_list) 2446 { 2447 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; 2448 } 2449 2450 /* The fence registers are invalidated so clear them out */ 2451 i915_gem_reset_fences(dev); 2452} 2453 2454/** 2455 * This function clears the request list as sequence numbers are passed. 2456 */ 2457void 2458i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) 2459{ 2460 uint32_t seqno; 2461 2462 if (list_empty(&ring->request_list)) 2463 return; 2464 2465 WARN_ON(i915_verify_lists(ring->dev)); 2466 2467 seqno = ring->get_seqno(ring, true); 2468 CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno); 2469 2470 while (!list_empty(&ring->request_list)) { 2471 struct drm_i915_gem_request *request; 2472 2473 request = list_first_entry(&ring->request_list, 2474 struct drm_i915_gem_request, 2475 list); 2476 2477 if (!i915_seqno_passed(seqno, request->seqno)) 2478 break; 2479 2480 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d", 2481 ring->name, seqno); 2482 /* We know the GPU must have read the request to have 2483 * sent us the seqno + interrupt, so use the position 2484 * of tail of the request to update the last known position 2485 * of the GPU head. 2486 */ 2487 ring->last_retired_head = request->tail; 2488 2489 list_del(&request->list); 2490 i915_gem_request_remove_from_client(request); 2491 free(request, DRM_I915_GEM); 2492 } 2493 2494 /* Move any buffers on the active list that are no longer referenced 2495 * by the ringbuffer to the flushing/inactive lists as appropriate. 2496 */ 2497 while (!list_empty(&ring->active_list)) { 2498 struct drm_i915_gem_object *obj; 2499 2500 obj = list_first_entry(&ring->active_list, 2501 struct drm_i915_gem_object, 2502 ring_list); 2503 2504 if (!i915_seqno_passed(seqno, obj->last_read_seqno)) 2505 break; 2506 2507 i915_gem_object_move_to_inactive(obj); 2508 } 2509 2510 if (unlikely(ring->trace_irq_seqno && 2511 i915_seqno_passed(seqno, ring->trace_irq_seqno))) { 2512 ring->irq_put(ring); 2513 ring->trace_irq_seqno = 0; 2514 } 2515 2516 WARN_ON(i915_verify_lists(ring->dev)); 2517} 2518 2519void 2520i915_gem_retire_requests(struct drm_device *dev) 2521{ 2522 drm_i915_private_t *dev_priv = dev->dev_private; 2523 struct intel_ring_buffer *ring; 2524 int i; 2525 2526 for_each_ring(ring, dev_priv, i) 2527 i915_gem_retire_requests_ring(ring); 2528} 2529 2530static void 2531i915_gem_retire_work_handler(void *arg, int pending) 2532{ 2533 drm_i915_private_t *dev_priv; 2534 struct drm_device *dev; 2535 struct intel_ring_buffer *ring; 2536 bool idle; 2537 int i; 2538 2539 dev_priv = arg; 2540 dev = dev_priv->dev; 2541 2542 /* Come back later if the device is busy... */ 2543 if (!sx_try_xlock(&dev->dev_struct_lock)) { 2544 taskqueue_enqueue_timeout(dev_priv->wq, 2545 &dev_priv->mm.retire_work, hz); 2546 return; 2547 } 2548 2549 CTR0(KTR_DRM, "retire_task"); 2550 2551 i915_gem_retire_requests(dev); 2552 2553 /* Send a periodic flush down the ring so we don't hold onto GEM 2554 * objects indefinitely. 2555 */ 2556 idle = true; 2557 for_each_ring(ring, dev_priv, i) { 2558 if (ring->gpu_caches_dirty) 2559 i915_add_request(ring, NULL, NULL); 2560 2561 idle &= list_empty(&ring->request_list); 2562 } 2563 2564 if (!dev_priv->mm.suspended && !idle) 2565 taskqueue_enqueue_timeout(dev_priv->wq, 2566 &dev_priv->mm.retire_work, hz); 2567 if (idle) 2568 intel_mark_idle(dev); 2569 2570 DRM_UNLOCK(dev); 2571} 2572 2573/** 2574 * Ensures that an object will eventually get non-busy by flushing any required 2575 * write domains, emitting any outstanding lazy request and retiring and 2576 * completed requests. 2577 */ 2578static int 2579i915_gem_object_flush_active(struct drm_i915_gem_object *obj) 2580{ 2581 int ret; 2582 2583 if (obj->active) { 2584 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); 2585 if (ret) 2586 return ret; 2587 2588 i915_gem_retire_requests_ring(obj->ring); 2589 } 2590 2591 return 0; 2592} 2593 2594/** 2595 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT 2596 * @DRM_IOCTL_ARGS: standard ioctl arguments 2597 * 2598 * Returns 0 if successful, else an error is returned with the remaining time in 2599 * the timeout parameter. 2600 * -ETIME: object is still busy after timeout 2601 * -ERESTARTSYS: signal interrupted the wait 2602 * -ENONENT: object doesn't exist 2603 * Also possible, but rare: 2604 * -EAGAIN: GPU wedged 2605 * -ENOMEM: damn 2606 * -ENODEV: Internal IRQ fail 2607 * -E?: The add request failed 2608 * 2609 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any 2610 * non-zero timeout parameter the wait ioctl will wait for the given number of 2611 * nanoseconds on an object becoming unbusy. Since the wait itself does so 2612 * without holding struct_mutex the object may become re-busied before this 2613 * function completes. A similar but shorter * race condition exists in the busy 2614 * ioctl 2615 */ 2616int 2617i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 2618{ 2619 struct drm_i915_gem_wait *args = data; 2620 struct drm_i915_gem_object *obj; 2621 struct intel_ring_buffer *ring = NULL; 2622 struct timespec timeout_stack, *timeout = NULL; 2623 u32 seqno = 0; 2624 int ret = 0; 2625 2626 if (args->timeout_ns >= 0) { 2627 timeout_stack.tv_sec = args->timeout_ns / 1000000; 2628 timeout_stack.tv_nsec = args->timeout_ns % 1000000; 2629 timeout = &timeout_stack; 2630 } 2631 2632 ret = i915_mutex_lock_interruptible(dev); 2633 if (ret) 2634 return ret; 2635 2636 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); 2637 if (&obj->base == NULL) { 2638 DRM_UNLOCK(dev); 2639 return -ENOENT; 2640 } 2641 2642 /* Need to make sure the object gets inactive eventually. */ 2643 ret = i915_gem_object_flush_active(obj); 2644 if (ret) 2645 goto out; 2646 2647 if (obj->active) { 2648 seqno = obj->last_read_seqno; 2649 ring = obj->ring; 2650 } 2651 2652 if (seqno == 0) 2653 goto out; 2654 2655 /* Do this after OLR check to make sure we make forward progress polling 2656 * on this IOCTL with a 0 timeout (like busy ioctl) 2657 */ 2658 if (!args->timeout_ns) { 2659 ret = -ETIMEDOUT; 2660 goto out; 2661 } 2662 2663 drm_gem_object_unreference(&obj->base); 2664 DRM_UNLOCK(dev); 2665 2666 ret = __wait_seqno(ring, seqno, true, timeout); 2667 if (timeout) { 2668 args->timeout_ns = timeout->tv_sec * 1000000 + timeout->tv_nsec; 2669 } 2670 return ret; 2671 2672out: 2673 drm_gem_object_unreference(&obj->base); 2674 DRM_UNLOCK(dev); 2675 return ret; 2676} 2677 2678/** 2679 * i915_gem_object_sync - sync an object to a ring. 2680 * 2681 * @obj: object which may be in use on another ring. 2682 * @to: ring we wish to use the object on. May be NULL. 2683 * 2684 * This code is meant to abstract object synchronization with the GPU. 2685 * Calling with NULL implies synchronizing the object with the CPU 2686 * rather than a particular GPU ring. 2687 * 2688 * Returns 0 if successful, else propagates up the lower layer error. 2689 */ 2690int 2691i915_gem_object_sync(struct drm_i915_gem_object *obj, 2692 struct intel_ring_buffer *to) 2693{ 2694 struct intel_ring_buffer *from = obj->ring; 2695 u32 seqno; 2696 int ret, idx; 2697 2698 if (from == NULL || to == from) 2699 return 0; 2700 2701 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) 2702 return i915_gem_object_wait_rendering(obj, false); 2703 2704 idx = intel_ring_sync_index(from, to); 2705 2706 seqno = obj->last_read_seqno; 2707 if (seqno <= from->sync_seqno[idx]) 2708 return 0; 2709 2710 ret = i915_gem_check_olr(obj->ring, seqno); 2711 if (ret) 2712 return ret; 2713 2714 ret = to->sync_to(to, from, seqno); 2715 if (!ret) 2716 /* We use last_read_seqno because sync_to() 2717 * might have just caused seqno wrap under 2718 * the radar. 2719 */ 2720 from->sync_seqno[idx] = obj->last_read_seqno; 2721 2722 return ret; 2723} 2724 2725static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) 2726{ 2727 u32 old_write_domain, old_read_domains; 2728 2729 /* Act a barrier for all accesses through the GTT */ 2730 mb(); 2731 2732 /* Force a pagefault for domain tracking on next user access */ 2733 i915_gem_release_mmap(obj); 2734 2735 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) 2736 return; 2737 2738 old_read_domains = obj->base.read_domains; 2739 old_write_domain = obj->base.write_domain; 2740 2741 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; 2742 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; 2743 2744 CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x", 2745 obj, old_read_domains, old_write_domain); 2746} 2747 2748/** 2749 * Unbinds an object from the GTT aperture. 2750 */ 2751int 2752i915_gem_object_unbind(struct drm_i915_gem_object *obj) 2753{ 2754 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 2755 int ret = 0; 2756 2757 if (obj->gtt_space == NULL) 2758 return 0; 2759 2760 if (obj->pin_count) 2761 return -EBUSY; 2762 2763 BUG_ON(obj->pages == NULL); 2764 2765 ret = i915_gem_object_finish_gpu(obj); 2766 if (ret) 2767 return ret; 2768 /* Continue on if we fail due to EIO, the GPU is hung so we 2769 * should be safe and we need to cleanup or else we might 2770 * cause memory corruption through use-after-free. 2771 */ 2772 2773 i915_gem_object_finish_gtt(obj); 2774 2775 /* release the fence reg _after_ flushing */ 2776 ret = i915_gem_object_put_fence(obj); 2777 if (ret) 2778 return ret; 2779 2780 if (obj->has_global_gtt_mapping) 2781 i915_gem_gtt_unbind_object(obj); 2782 if (obj->has_aliasing_ppgtt_mapping) { 2783 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); 2784 obj->has_aliasing_ppgtt_mapping = 0; 2785 } 2786 i915_gem_gtt_finish_object(obj); 2787 2788 list_del(&obj->mm_list); 2789 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); 2790 /* Avoid an unnecessary call to unbind on rebind. */ 2791 obj->map_and_fenceable = true; 2792 2793 drm_mm_put_block(obj->gtt_space); 2794 obj->gtt_space = NULL; 2795 obj->gtt_offset = 0; 2796 2797 return 0; 2798} 2799 2800int i915_gpu_idle(struct drm_device *dev) 2801{ 2802 drm_i915_private_t *dev_priv = dev->dev_private; 2803 struct intel_ring_buffer *ring; 2804 int ret, i; 2805 2806 /* Flush everything onto the inactive list. */ 2807 for_each_ring(ring, dev_priv, i) { 2808 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); 2809 if (ret) 2810 return ret; 2811 2812 ret = intel_ring_idle(ring); 2813 if (ret) 2814 return ret; 2815 } 2816 2817 return 0; 2818} 2819 2820static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, 2821 struct drm_i915_gem_object *obj) 2822{ 2823 drm_i915_private_t *dev_priv = dev->dev_private; 2824 uint64_t val; 2825 2826 if (obj) { 2827 u32 size = obj->gtt_space->size; 2828 2829 val = (uint64_t)((obj->gtt_offset + size - 4096) & 2830 0xfffff000) << 32; 2831 val |= obj->gtt_offset & 0xfffff000; 2832 val |= (uint64_t)((obj->stride / 128) - 1) << 2833 SANDYBRIDGE_FENCE_PITCH_SHIFT; 2834 2835 if (obj->tiling_mode == I915_TILING_Y) 2836 val |= 1 << I965_FENCE_TILING_Y_SHIFT; 2837 val |= I965_FENCE_REG_VALID; 2838 } else 2839 val = 0; 2840 2841 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); 2842 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); 2843} 2844 2845static void i965_write_fence_reg(struct drm_device *dev, int reg, 2846 struct drm_i915_gem_object *obj) 2847{ 2848 drm_i915_private_t *dev_priv = dev->dev_private; 2849 uint64_t val; 2850 2851 if (obj) { 2852 u32 size = obj->gtt_space->size; 2853 2854 val = (uint64_t)((obj->gtt_offset + size - 4096) & 2855 0xfffff000) << 32; 2856 val |= obj->gtt_offset & 0xfffff000; 2857 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; 2858 if (obj->tiling_mode == I915_TILING_Y) 2859 val |= 1 << I965_FENCE_TILING_Y_SHIFT; 2860 val |= I965_FENCE_REG_VALID; 2861 } else 2862 val = 0; 2863 2864 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); 2865 POSTING_READ(FENCE_REG_965_0 + reg * 8); 2866} 2867 2868static void i915_write_fence_reg(struct drm_device *dev, int reg, 2869 struct drm_i915_gem_object *obj) 2870{ 2871 drm_i915_private_t *dev_priv = dev->dev_private; 2872 u32 val; 2873 2874 if (obj) { 2875 u32 size = obj->gtt_space->size; 2876 int pitch_val; 2877 int tile_width; 2878 2879 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || 2880 (size & -size) != size || 2881 (obj->gtt_offset & (size - 1)), 2882 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", 2883 obj->gtt_offset, obj->map_and_fenceable, size); 2884 2885 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) 2886 tile_width = 128; 2887 else 2888 tile_width = 512; 2889 2890 /* Note: pitch better be a power of two tile widths */ 2891 pitch_val = obj->stride / tile_width; 2892 pitch_val = ffs(pitch_val) - 1; 2893 2894 val = obj->gtt_offset; 2895 if (obj->tiling_mode == I915_TILING_Y) 2896 val |= 1 << I830_FENCE_TILING_Y_SHIFT; 2897 val |= I915_FENCE_SIZE_BITS(size); 2898 val |= pitch_val << I830_FENCE_PITCH_SHIFT; 2899 val |= I830_FENCE_REG_VALID; 2900 } else 2901 val = 0; 2902 2903 if (reg < 8) 2904 reg = FENCE_REG_830_0 + reg * 4; 2905 else 2906 reg = FENCE_REG_945_8 + (reg - 8) * 4; 2907 2908 I915_WRITE(reg, val); 2909 POSTING_READ(reg); 2910} 2911 2912static void i830_write_fence_reg(struct drm_device *dev, int reg, 2913 struct drm_i915_gem_object *obj) 2914{ 2915 drm_i915_private_t *dev_priv = dev->dev_private; 2916 uint32_t val; 2917 2918 if (obj) { 2919 u32 size = obj->gtt_space->size; 2920 uint32_t pitch_val; 2921 2922 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || 2923 (size & -size) != size || 2924 (obj->gtt_offset & (size - 1)), 2925 "object 0x%08x not 512K or pot-size 0x%08x aligned\n", 2926 obj->gtt_offset, size); 2927 2928 pitch_val = obj->stride / 128; 2929 pitch_val = ffs(pitch_val) - 1; 2930 2931 val = obj->gtt_offset; 2932 if (obj->tiling_mode == I915_TILING_Y) 2933 val |= 1 << I830_FENCE_TILING_Y_SHIFT; 2934 val |= I830_FENCE_SIZE_BITS(size); 2935 val |= pitch_val << I830_FENCE_PITCH_SHIFT; 2936 val |= I830_FENCE_REG_VALID; 2937 } else 2938 val = 0; 2939 2940 I915_WRITE(FENCE_REG_830_0 + reg * 4, val); 2941 POSTING_READ(FENCE_REG_830_0 + reg * 4); 2942} 2943 2944static void i915_gem_write_fence(struct drm_device *dev, int reg, 2945 struct drm_i915_gem_object *obj) 2946{ 2947 switch (INTEL_INFO(dev)->gen) { 2948 case 7: 2949 case 6: sandybridge_write_fence_reg(dev, reg, obj); break; 2950 case 5: 2951 case 4: i965_write_fence_reg(dev, reg, obj); break; 2952 case 3: i915_write_fence_reg(dev, reg, obj); break; 2953 case 2: i830_write_fence_reg(dev, reg, obj); break; 2954 default: break; 2955 } 2956} 2957 2958static inline int fence_number(struct drm_i915_private *dev_priv, 2959 struct drm_i915_fence_reg *fence) 2960{ 2961 return fence - dev_priv->fence_regs; 2962} 2963 2964static void i915_gem_write_fence__ipi(void *data) 2965{ 2966 wbinvd(); 2967} 2968 2969static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, 2970 struct drm_i915_fence_reg *fence, 2971 bool enable) 2972{ 2973 struct drm_device *dev = obj->base.dev; 2974 struct drm_i915_private *dev_priv = dev->dev_private; 2975 int fence_reg = fence_number(dev_priv, fence); 2976 2977 /* In order to fully serialize access to the fenced region and 2978 * the update to the fence register we need to take extreme 2979 * measures on SNB+. In theory, the write to the fence register 2980 * flushes all memory transactions before, and coupled with the 2981 * mb() placed around the register write we serialise all memory 2982 * operations with respect to the changes in the tiler. Yet, on 2983 * SNB+ we need to take a step further and emit an explicit wbinvd() 2984 * on each processor in order to manually flush all memory 2985 * transactions before updating the fence register. 2986 */ 2987 if (HAS_LLC(obj->base.dev)) 2988 on_each_cpu(i915_gem_write_fence__ipi, NULL, 1); 2989 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL); 2990 2991 if (enable) { 2992 obj->fence_reg = fence_reg; 2993 fence->obj = obj; 2994 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); 2995 } else { 2996 obj->fence_reg = I915_FENCE_REG_NONE; 2997 fence->obj = NULL; 2998 list_del_init(&fence->lru_list); 2999 } 3000} 3001 3002static int 3003i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) 3004{ 3005 if (obj->last_fenced_seqno) { 3006 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); 3007 if (ret) 3008 return ret; 3009 3010 obj->last_fenced_seqno = 0; 3011 } 3012 3013 /* Ensure that all CPU reads are completed before installing a fence 3014 * and all writes before removing the fence. 3015 */ 3016 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) 3017 mb(); 3018 3019 obj->fenced_gpu_access = false; 3020 return 0; 3021} 3022 3023int 3024i915_gem_object_put_fence(struct drm_i915_gem_object *obj) 3025{ 3026 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 3027 int ret; 3028 3029 ret = i915_gem_object_flush_fence(obj); 3030 if (ret) 3031 return ret; 3032 3033 if (obj->fence_reg == I915_FENCE_REG_NONE) 3034 return 0; 3035 3036 i915_gem_object_update_fence(obj, 3037 &dev_priv->fence_regs[obj->fence_reg], 3038 false); 3039 i915_gem_object_fence_lost(obj); 3040 3041 return 0; 3042} 3043 3044static struct drm_i915_fence_reg * 3045i915_find_fence_reg(struct drm_device *dev) 3046{ 3047 struct drm_i915_private *dev_priv = dev->dev_private; 3048 struct drm_i915_fence_reg *reg, *avail; 3049 int i; 3050 3051 /* First try to find a free reg */ 3052 avail = NULL; 3053 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { 3054 reg = &dev_priv->fence_regs[i]; 3055 if (!reg->obj) 3056 return reg; 3057 3058 if (!reg->pin_count) 3059 avail = reg; 3060 } 3061 3062 if (avail == NULL) 3063 return NULL; 3064 3065 /* None available, try to steal one or wait for a user to finish */ 3066 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { 3067 if (reg->pin_count) 3068 continue; 3069 3070 return reg; 3071 } 3072 3073 return NULL; 3074} 3075 3076/** 3077 * i915_gem_object_get_fence - set up fencing for an object 3078 * @obj: object to map through a fence reg 3079 * 3080 * When mapping objects through the GTT, userspace wants to be able to write 3081 * to them without having to worry about swizzling if the object is tiled. 3082 * This function walks the fence regs looking for a free one for @obj, 3083 * stealing one if it can't find any. 3084 * 3085 * It then sets up the reg based on the object's properties: address, pitch 3086 * and tiling format. 3087 * 3088 * For an untiled surface, this removes any existing fence. 3089 */ 3090int 3091i915_gem_object_get_fence(struct drm_i915_gem_object *obj) 3092{ 3093 struct drm_device *dev = obj->base.dev; 3094 struct drm_i915_private *dev_priv = dev->dev_private; 3095 bool enable = obj->tiling_mode != I915_TILING_NONE; 3096 struct drm_i915_fence_reg *reg; 3097 int ret; 3098 3099 /* Have we updated the tiling parameters upon the object and so 3100 * will need to serialise the write to the associated fence register? 3101 */ 3102 if (obj->fence_dirty) { 3103 ret = i915_gem_object_flush_fence(obj); 3104 if (ret) 3105 return ret; 3106 } 3107 3108 /* Just update our place in the LRU if our fence is getting reused. */ 3109 if (obj->fence_reg != I915_FENCE_REG_NONE) { 3110 reg = &dev_priv->fence_regs[obj->fence_reg]; 3111 if (!obj->fence_dirty) { 3112 list_move_tail(®->lru_list, 3113 &dev_priv->mm.fence_list); 3114 return 0; 3115 } 3116 } else if (enable) { 3117 reg = i915_find_fence_reg(dev); 3118 if (reg == NULL) 3119 return -EDEADLK; 3120 3121 if (reg->obj) { 3122 struct drm_i915_gem_object *old = reg->obj; 3123 3124 ret = i915_gem_object_flush_fence(old); 3125 if (ret) 3126 return ret; 3127 3128 i915_gem_object_fence_lost(old); 3129 } 3130 } else 3131 return 0; 3132 3133 i915_gem_object_update_fence(obj, reg, enable); 3134 obj->fence_dirty = false; 3135 3136 return 0; 3137} 3138 3139static bool i915_gem_valid_gtt_space(struct drm_device *dev, 3140 struct drm_mm_node *gtt_space, 3141 unsigned long cache_level) 3142{ 3143 struct drm_mm_node *other; 3144 3145 /* On non-LLC machines we have to be careful when putting differing 3146 * types of snoopable memory together to avoid the prefetcher 3147 * crossing memory domains and dieing. 3148 */ 3149 if (HAS_LLC(dev)) 3150 return true; 3151 3152 if (gtt_space == NULL) 3153 return true; 3154 3155 if (list_empty(>t_space->node_list)) 3156 return true; 3157 3158 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); 3159 if (other->allocated && !other->hole_follows && other->color != cache_level) 3160 return false; 3161 3162 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); 3163 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) 3164 return false; 3165 3166 return true; 3167} 3168 3169static void i915_gem_verify_gtt(struct drm_device *dev) 3170{ 3171#if WATCH_GTT 3172 struct drm_i915_private *dev_priv = dev->dev_private; 3173 struct drm_i915_gem_object *obj; 3174 int err = 0; 3175 3176 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { 3177 if (obj->gtt_space == NULL) { 3178 DRM_ERROR("object found on GTT list with no space reserved\n"); 3179 err++; 3180 continue; 3181 } 3182 3183 if (obj->cache_level != obj->gtt_space->color) { 3184 DRM_ERROR("object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", 3185 obj->gtt_space->start, 3186 obj->gtt_space->start + obj->gtt_space->size, 3187 obj->cache_level, 3188 obj->gtt_space->color); 3189 err++; 3190 continue; 3191 } 3192 3193 if (!i915_gem_valid_gtt_space(dev, 3194 obj->gtt_space, 3195 obj->cache_level)) { 3196 DRM_ERROR("invalid GTT space found at [%08lx, %08lx] - color=%x\n", 3197 obj->gtt_space->start, 3198 obj->gtt_space->start + obj->gtt_space->size, 3199 obj->cache_level); 3200 err++; 3201 continue; 3202 } 3203 } 3204 3205 WARN_ON(err); 3206#endif 3207} 3208 3209/** 3210 * Finds free space in the GTT aperture and binds the object there. 3211 */ 3212static int 3213i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, 3214 unsigned alignment, 3215 bool map_and_fenceable, 3216 bool nonblocking) 3217{ 3218 struct drm_device *dev = obj->base.dev; 3219 drm_i915_private_t *dev_priv = dev->dev_private; 3220 struct drm_mm_node *node; 3221 u32 size, fence_size, fence_alignment, unfenced_alignment; 3222 bool mappable, fenceable; 3223 int ret; 3224 3225 if (obj->madv != I915_MADV_WILLNEED) { 3226 DRM_ERROR("Attempting to bind a purgeable object\n"); 3227 return -EINVAL; 3228 } 3229 3230 fence_size = i915_gem_get_gtt_size(dev, 3231 obj->base.size, 3232 obj->tiling_mode); 3233 fence_alignment = i915_gem_get_gtt_alignment(dev, 3234 obj->base.size, 3235 obj->tiling_mode); 3236 unfenced_alignment = 3237 i915_gem_get_unfenced_gtt_alignment(dev, 3238 obj->base.size, 3239 obj->tiling_mode); 3240 3241 if (alignment == 0) 3242 alignment = map_and_fenceable ? fence_alignment : 3243 unfenced_alignment; 3244 if (map_and_fenceable && alignment & (fence_alignment - 1)) { 3245 DRM_ERROR("Invalid object alignment requested %u\n", alignment); 3246 return -EINVAL; 3247 } 3248 3249 size = map_and_fenceable ? fence_size : obj->base.size; 3250 3251 /* If the object is bigger than the entire aperture, reject it early 3252 * before evicting everything in a vain attempt to find space. 3253 */ 3254 if (obj->base.size > 3255 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { 3256 DRM_ERROR("Attempting to bind an object larger than the aperture\n"); 3257 return -E2BIG; 3258 } 3259 3260 ret = i915_gem_object_get_pages(obj); 3261 if (ret) 3262 return ret; 3263 3264 i915_gem_object_pin_pages(obj); 3265 3266 node = malloc(sizeof(*node), DRM_I915_GEM, M_NOWAIT | M_ZERO); 3267 if (node == NULL) { 3268 i915_gem_object_unpin_pages(obj); 3269 return -ENOMEM; 3270 } 3271 3272 search_free: 3273 if (map_and_fenceable) 3274 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, 3275 size, alignment, obj->cache_level, 3276 0, dev_priv->mm.gtt_mappable_end); 3277 else 3278 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, 3279 size, alignment, obj->cache_level); 3280 if (ret) { 3281 ret = i915_gem_evict_something(dev, size, alignment, 3282 obj->cache_level, 3283 map_and_fenceable, 3284 nonblocking); 3285 if (ret == 0) 3286 goto search_free; 3287 3288 i915_gem_object_unpin_pages(obj); 3289 free(node, DRM_I915_GEM); 3290 return ret; 3291 } 3292 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { 3293 i915_gem_object_unpin_pages(obj); 3294 drm_mm_put_block(node); 3295 return -EINVAL; 3296 } 3297 3298 ret = i915_gem_gtt_prepare_object(obj); 3299 if (ret) { 3300 i915_gem_object_unpin_pages(obj); 3301 drm_mm_put_block(node); 3302 return ret; 3303 } 3304 3305 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); 3306 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); 3307 3308 obj->gtt_space = node; 3309 obj->gtt_offset = node->start; 3310 3311 fenceable = 3312 node->size == fence_size && 3313 (node->start & (fence_alignment - 1)) == 0; 3314 3315 mappable = 3316 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; 3317 3318 obj->map_and_fenceable = mappable && fenceable; 3319 3320 i915_gem_object_unpin_pages(obj); 3321 CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset, 3322 obj->base.size, map_and_fenceable); 3323 i915_gem_verify_gtt(dev); 3324 return 0; 3325} 3326 3327void 3328i915_gem_clflush_object(struct drm_i915_gem_object *obj) 3329{ 3330 /* If we don't have a page list set up, then we're not pinned 3331 * to GPU, and we can ignore the cache flush because it'll happen 3332 * again at bind time. 3333 */ 3334 if (obj->pages == NULL) 3335 return; 3336 3337 /* If the GPU is snooping the contents of the CPU cache, 3338 * we do not need to manually clear the CPU cache lines. However, 3339 * the caches are only snooped when the render cache is 3340 * flushed/invalidated. As we always have to emit invalidations 3341 * and flushes when moving into and out of the RENDER domain, correct 3342 * snooping behaviour occurs naturally as the result of our domain 3343 * tracking. 3344 */ 3345 if (obj->cache_level != I915_CACHE_NONE) 3346 return; 3347 3348 CTR1(KTR_DRM, "object_clflush %p", obj); 3349 3350 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); 3351} 3352 3353/** Flushes the GTT write domain for the object if it's dirty. */ 3354static void 3355i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) 3356{ 3357 uint32_t old_write_domain; 3358 3359 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) 3360 return; 3361 3362 /* No actual flushing is required for the GTT write domain. Writes 3363 * to it immediately go to main memory as far as we know, so there's 3364 * no chipset flush. It also doesn't land in render cache. 3365 * 3366 * However, we do have to enforce the order so that all writes through 3367 * the GTT land before any writes to the device, such as updates to 3368 * the GATT itself. 3369 */ 3370 wmb(); 3371 3372 old_write_domain = obj->base.write_domain; 3373 obj->base.write_domain = 0; 3374 3375 CTR3(KTR_DRM, "object_change_domain flush gtt_write %p %x %x", obj, 3376 obj->base.read_domains, old_write_domain); 3377} 3378 3379/** Flushes the CPU write domain for the object if it's dirty. */ 3380static void 3381i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) 3382{ 3383 uint32_t old_write_domain; 3384 3385 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) 3386 return; 3387 3388 i915_gem_clflush_object(obj); 3389 i915_gem_chipset_flush(obj->base.dev); 3390 old_write_domain = obj->base.write_domain; 3391 obj->base.write_domain = 0; 3392 3393 CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj, 3394 obj->base.read_domains, old_write_domain); 3395} 3396 3397/** 3398 * Moves a single object to the GTT read, and possibly write domain. 3399 * 3400 * This function returns when the move is complete, including waiting on 3401 * flushes to occur. 3402 */ 3403int 3404i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 3405{ 3406 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 3407 uint32_t old_write_domain, old_read_domains; 3408 int ret; 3409 3410 /* Not valid to be called on unbound objects. */ 3411 if (obj->gtt_space == NULL) 3412 return -EINVAL; 3413 3414 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) 3415 return 0; 3416 3417 ret = i915_gem_object_wait_rendering(obj, !write); 3418 if (ret) 3419 return ret; 3420 3421 i915_gem_object_flush_cpu_write_domain(obj); 3422 3423 old_write_domain = obj->base.write_domain; 3424 old_read_domains = obj->base.read_domains; 3425 3426 /* It should now be out of any other write domains, and we can update 3427 * the domain values for our changes. 3428 */ 3429 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); 3430 obj->base.read_domains |= I915_GEM_DOMAIN_GTT; 3431 if (write) { 3432 obj->base.read_domains = I915_GEM_DOMAIN_GTT; 3433 obj->base.write_domain = I915_GEM_DOMAIN_GTT; 3434 obj->dirty = 1; 3435 } 3436 3437 CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj, 3438 old_read_domains, old_write_domain); 3439 3440 /* And bump the LRU for this access */ 3441 if (i915_gem_object_is_inactive(obj)) 3442 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); 3443 3444 return 0; 3445} 3446 3447int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 3448 enum i915_cache_level cache_level) 3449{ 3450 struct drm_device *dev = obj->base.dev; 3451 drm_i915_private_t *dev_priv = dev->dev_private; 3452 int ret; 3453 3454 if (obj->cache_level == cache_level) 3455 return 0; 3456 3457 if (obj->pin_count) { 3458 DRM_DEBUG("can not change the cache level of pinned objects\n"); 3459 return -EBUSY; 3460 } 3461 3462 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { 3463 ret = i915_gem_object_unbind(obj); 3464 if (ret) 3465 return ret; 3466 } 3467 3468 if (obj->gtt_space) { 3469 ret = i915_gem_object_finish_gpu(obj); 3470 if (ret) 3471 return ret; 3472 3473 i915_gem_object_finish_gtt(obj); 3474 3475 /* Before SandyBridge, you could not use tiling or fence 3476 * registers with snooped memory, so relinquish any fences 3477 * currently pointing to our region in the aperture. 3478 */ 3479 if (INTEL_INFO(dev)->gen < 6) { 3480 ret = i915_gem_object_put_fence(obj); 3481 if (ret) 3482 return ret; 3483 } 3484 3485 if (obj->has_global_gtt_mapping) 3486 i915_gem_gtt_bind_object(obj, cache_level); 3487 if (obj->has_aliasing_ppgtt_mapping) 3488 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, 3489 obj, cache_level); 3490 3491 obj->gtt_space->color = cache_level; 3492 } 3493 3494 if (cache_level == I915_CACHE_NONE) { 3495 u32 old_read_domains, old_write_domain; 3496 3497 /* If we're coming from LLC cached, then we haven't 3498 * actually been tracking whether the data is in the 3499 * CPU cache or not, since we only allow one bit set 3500 * in obj->write_domain and have been skipping the clflushes. 3501 * Just set it to the CPU cache for now. 3502 */ 3503 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); 3504 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); 3505 3506 old_read_domains = obj->base.read_domains; 3507 old_write_domain = obj->base.write_domain; 3508 3509 obj->base.read_domains = I915_GEM_DOMAIN_CPU; 3510 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 3511 3512 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x", 3513 obj, old_read_domains, old_write_domain); 3514 } 3515 3516 obj->cache_level = cache_level; 3517 i915_gem_verify_gtt(dev); 3518 return 0; 3519} 3520 3521int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 3522 struct drm_file *file) 3523{ 3524 struct drm_i915_gem_caching *args = data; 3525 struct drm_i915_gem_object *obj; 3526 int ret; 3527 3528 ret = i915_mutex_lock_interruptible(dev); 3529 if (ret) 3530 return ret; 3531 3532 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3533 if (&obj->base == NULL) { 3534 ret = -ENOENT; 3535 goto unlock; 3536 } 3537 3538 args->caching = obj->cache_level != I915_CACHE_NONE; 3539 3540 drm_gem_object_unreference(&obj->base); 3541unlock: 3542 DRM_UNLOCK(dev); 3543 return ret; 3544} 3545 3546int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 3547 struct drm_file *file) 3548{ 3549 struct drm_i915_gem_caching *args = data; 3550 struct drm_i915_gem_object *obj; 3551 enum i915_cache_level level; 3552 int ret; 3553 3554 switch (args->caching) { 3555 case I915_CACHING_NONE: 3556 level = I915_CACHE_NONE; 3557 break; 3558 case I915_CACHING_CACHED: 3559 level = I915_CACHE_LLC; 3560 break; 3561 default: 3562 return -EINVAL; 3563 } 3564 3565 ret = i915_mutex_lock_interruptible(dev); 3566 if (ret) 3567 return ret; 3568 3569 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3570 if (&obj->base == NULL) { 3571 ret = -ENOENT; 3572 goto unlock; 3573 } 3574 3575 ret = i915_gem_object_set_cache_level(obj, level); 3576 3577 drm_gem_object_unreference(&obj->base); 3578unlock: 3579 DRM_UNLOCK(dev); 3580 return ret; 3581} 3582 3583static bool is_pin_display(struct drm_i915_gem_object *obj) 3584{ 3585 /* There are 3 sources that pin objects: 3586 * 1. The display engine (scanouts, sprites, cursors); 3587 * 2. Reservations for execbuffer; 3588 * 3. The user. 3589 * 3590 * We can ignore reservations as we hold the struct_mutex and 3591 * are only called outside of the reservation path. The user 3592 * can only increment pin_count once, and so if after 3593 * subtracting the potential reference by the user, any pin_count 3594 * remains, it must be due to another use by the display engine. 3595 */ 3596 return obj->pin_count - !!obj->user_pin_count; 3597} 3598 3599/* 3600 * Prepare buffer for display plane (scanout, cursors, etc). 3601 * Can be called from an uninterruptible phase (modesetting) and allows 3602 * any flushes to be pipelined (for pageflips). 3603 */ 3604int 3605i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 3606 u32 alignment, 3607 struct intel_ring_buffer *pipelined) 3608{ 3609 u32 old_read_domains, old_write_domain; 3610 int ret; 3611 3612 if (pipelined != obj->ring) { 3613 ret = i915_gem_object_sync(obj, pipelined); 3614 if (ret) 3615 return ret; 3616 } 3617 3618 /* Mark the pin_display early so that we account for the 3619 * display coherency whilst setting up the cache domains. 3620 */ 3621 obj->pin_display = true; 3622 3623 /* The display engine is not coherent with the LLC cache on gen6. As 3624 * a result, we make sure that the pinning that is about to occur is 3625 * done with uncached PTEs. This is lowest common denominator for all 3626 * chipsets. 3627 * 3628 * However for gen6+, we could do better by using the GFDT bit instead 3629 * of uncaching, which would allow us to flush all the LLC-cached data 3630 * with that bit in the PTE to main memory with just one PIPE_CONTROL. 3631 */ 3632 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); 3633 if (ret) 3634 goto err_unpin_display; 3635 3636 /* As the user may map the buffer once pinned in the display plane 3637 * (e.g. libkms for the bootup splash), we have to ensure that we 3638 * always use map_and_fenceable for all scanout buffers. 3639 */ 3640 ret = i915_gem_object_pin(obj, alignment, true, false); 3641 if (ret) 3642 goto err_unpin_display; 3643 3644 i915_gem_object_flush_cpu_write_domain(obj); 3645 3646 old_write_domain = obj->base.write_domain; 3647 old_read_domains = obj->base.read_domains; 3648 3649 /* It should now be out of any other write domains, and we can update 3650 * the domain values for our changes. 3651 */ 3652 obj->base.write_domain = 0; 3653 obj->base.read_domains |= I915_GEM_DOMAIN_GTT; 3654 3655 CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x", 3656 obj, old_read_domains, old_write_domain); 3657 3658 return 0; 3659 3660err_unpin_display: 3661 obj->pin_display = is_pin_display(obj); 3662 return ret; 3663} 3664 3665void 3666i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) 3667{ 3668 i915_gem_object_unpin(obj); 3669 obj->pin_display = is_pin_display(obj); 3670} 3671 3672int 3673i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) 3674{ 3675 int ret; 3676 3677 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) 3678 return 0; 3679 3680 ret = i915_gem_object_wait_rendering(obj, false); 3681 if (ret) 3682 return ret; 3683 3684 /* Ensure that we invalidate the GPU's caches and TLBs. */ 3685 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; 3686 return 0; 3687} 3688 3689/** 3690 * Moves a single object to the CPU read, and possibly write domain. 3691 * 3692 * This function returns when the move is complete, including waiting on 3693 * flushes to occur. 3694 */ 3695int 3696i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) 3697{ 3698 uint32_t old_write_domain, old_read_domains; 3699 int ret; 3700 3701 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) 3702 return 0; 3703 3704 ret = i915_gem_object_wait_rendering(obj, !write); 3705 if (ret) 3706 return ret; 3707 3708 i915_gem_object_flush_gtt_write_domain(obj); 3709 3710 old_write_domain = obj->base.write_domain; 3711 old_read_domains = obj->base.read_domains; 3712 3713 /* Flush the CPU cache if it's still invalid. */ 3714 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { 3715 i915_gem_clflush_object(obj); 3716 3717 obj->base.read_domains |= I915_GEM_DOMAIN_CPU; 3718 } 3719 3720 /* It should now be out of any other write domains, and we can update 3721 * the domain values for our changes. 3722 */ 3723 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); 3724 3725 /* If we're writing through the CPU, then the GPU read domains will 3726 * need to be invalidated at next use. 3727 */ 3728 if (write) { 3729 obj->base.read_domains = I915_GEM_DOMAIN_CPU; 3730 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 3731 } 3732 3733 CTR3(KTR_DRM, "object_change_domain set_to_cpu %p %x %x", obj, 3734 old_read_domains, old_write_domain); 3735 3736 return 0; 3737} 3738 3739/* Throttle our rendering by waiting until the ring has completed our requests 3740 * emitted over 20 msec ago. 3741 * 3742 * Note that if we were to use the current jiffies each time around the loop, 3743 * we wouldn't escape the function with any frames outstanding if the time to 3744 * render a frame was over 20ms. 3745 * 3746 * This should get us reasonable parallelism between CPU and GPU but also 3747 * relatively low latency when blocking on a particular request to finish. 3748 */ 3749static int 3750i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) 3751{ 3752 struct drm_i915_private *dev_priv = dev->dev_private; 3753 struct drm_i915_file_private *file_priv = file->driver_priv; 3754 unsigned long recent_enough = jiffies - msecs_to_jiffies(20); 3755 struct drm_i915_gem_request *request; 3756 struct intel_ring_buffer *ring = NULL; 3757 u32 seqno = 0; 3758 int ret; 3759 3760 if (atomic_read(&dev_priv->mm.wedged)) 3761 return -EIO; 3762 3763 mtx_lock(&file_priv->mm.lock); 3764 list_for_each_entry(request, &file_priv->mm.request_list, client_list) { 3765 if (time_after_eq(request->emitted_jiffies, recent_enough)) 3766 break; 3767 3768 ring = request->ring; 3769 seqno = request->seqno; 3770 } 3771 mtx_unlock(&file_priv->mm.lock); 3772 3773 if (seqno == 0) 3774 return 0; 3775 3776 ret = __wait_seqno(ring, seqno, true, NULL); 3777 if (ret == 0) 3778 taskqueue_enqueue_timeout(dev_priv->wq, 3779 &dev_priv->mm.retire_work, 0); 3780 3781 return ret; 3782} 3783 3784int 3785i915_gem_object_pin(struct drm_i915_gem_object *obj, 3786 uint32_t alignment, 3787 bool map_and_fenceable, 3788 bool nonblocking) 3789{ 3790 int ret; 3791 3792 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) 3793 return -EBUSY; 3794 3795 if (obj->gtt_space != NULL) { 3796 if ((alignment && obj->gtt_offset & (alignment - 1)) || 3797 (map_and_fenceable && !obj->map_and_fenceable)) { 3798 WARN(obj->pin_count, 3799 "bo is already pinned with incorrect alignment:" 3800 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," 3801 " obj->map_and_fenceable=%d\n", 3802 obj->gtt_offset, alignment, 3803 map_and_fenceable, 3804 obj->map_and_fenceable); 3805 ret = i915_gem_object_unbind(obj); 3806 if (ret) 3807 return ret; 3808 } 3809 } 3810 3811 if (obj->gtt_space == NULL) { 3812 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 3813 3814 ret = i915_gem_object_bind_to_gtt(obj, alignment, 3815 map_and_fenceable, 3816 nonblocking); 3817 if (ret) 3818 return ret; 3819 3820 if (!dev_priv->mm.aliasing_ppgtt) 3821 i915_gem_gtt_bind_object(obj, obj->cache_level); 3822 } 3823 3824 if (!obj->has_global_gtt_mapping && map_and_fenceable) 3825 i915_gem_gtt_bind_object(obj, obj->cache_level); 3826 3827 obj->pin_count++; 3828 obj->pin_mappable |= map_and_fenceable; 3829 3830 return 0; 3831} 3832 3833void 3834i915_gem_object_unpin(struct drm_i915_gem_object *obj) 3835{ 3836 BUG_ON(obj->pin_count == 0); 3837 BUG_ON(obj->gtt_space == NULL); 3838 3839 if (--obj->pin_count == 0) 3840 obj->pin_mappable = false; 3841} 3842 3843int 3844i915_gem_pin_ioctl(struct drm_device *dev, void *data, 3845 struct drm_file *file) 3846{ 3847 struct drm_i915_gem_pin *args = data; 3848 struct drm_i915_gem_object *obj; 3849 int ret; 3850 3851 ret = i915_mutex_lock_interruptible(dev); 3852 if (ret) 3853 return ret; 3854 3855 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3856 if (&obj->base == NULL) { 3857 ret = -ENOENT; 3858 goto unlock; 3859 } 3860 3861 if (obj->madv != I915_MADV_WILLNEED) { 3862 DRM_ERROR("Attempting to pin a purgeable buffer\n"); 3863 ret = -EINVAL; 3864 goto out; 3865 } 3866 3867 if (obj->pin_filp != NULL && obj->pin_filp != file) { 3868 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", 3869 args->handle); 3870 ret = -EINVAL; 3871 goto out; 3872 } 3873 3874 if (obj->user_pin_count == 0) { 3875 ret = i915_gem_object_pin(obj, args->alignment, true, false); 3876 if (ret) 3877 goto out; 3878 } 3879 3880 obj->user_pin_count++; 3881 obj->pin_filp = file; 3882 3883 /* XXX - flush the CPU caches for pinned objects 3884 * as the X server doesn't manage domains yet 3885 */ 3886 i915_gem_object_flush_cpu_write_domain(obj); 3887 args->offset = obj->gtt_offset; 3888out: 3889 drm_gem_object_unreference(&obj->base); 3890unlock: 3891 DRM_UNLOCK(dev); 3892 return ret; 3893} 3894 3895int 3896i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 3897 struct drm_file *file) 3898{ 3899 struct drm_i915_gem_pin *args = data; 3900 struct drm_i915_gem_object *obj; 3901 int ret; 3902 3903 ret = i915_mutex_lock_interruptible(dev); 3904 if (ret) 3905 return ret; 3906 3907 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3908 if (&obj->base == NULL) { 3909 ret = -ENOENT; 3910 goto unlock; 3911 } 3912 3913 if (obj->pin_filp != file) { 3914 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", 3915 args->handle); 3916 ret = -EINVAL; 3917 goto out; 3918 } 3919 obj->user_pin_count--; 3920 if (obj->user_pin_count == 0) { 3921 obj->pin_filp = NULL; 3922 i915_gem_object_unpin(obj); 3923 } 3924 3925out: 3926 drm_gem_object_unreference(&obj->base); 3927unlock: 3928 DRM_UNLOCK(dev); 3929 return ret; 3930} 3931 3932int 3933i915_gem_busy_ioctl(struct drm_device *dev, void *data, 3934 struct drm_file *file) 3935{ 3936 struct drm_i915_gem_busy *args = data; 3937 struct drm_i915_gem_object *obj; 3938 int ret; 3939 3940 ret = i915_mutex_lock_interruptible(dev); 3941 if (ret) 3942 return ret; 3943 3944 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3945 if (&obj->base == NULL) { 3946 ret = -ENOENT; 3947 goto unlock; 3948 } 3949 3950 /* Count all active objects as busy, even if they are currently not used 3951 * by the gpu. Users of this interface expect objects to eventually 3952 * become non-busy without any further actions, therefore emit any 3953 * necessary flushes here. 3954 */ 3955 ret = i915_gem_object_flush_active(obj); 3956 3957 args->busy = obj->active; 3958 if (obj->ring) { 3959 BUILD_BUG_ON(I915_NUM_RINGS > 16); 3960 args->busy |= intel_ring_flag(obj->ring) << 16; 3961 } 3962 3963 drm_gem_object_unreference(&obj->base); 3964unlock: 3965 DRM_UNLOCK(dev); 3966 return ret; 3967} 3968 3969int 3970i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 3971 struct drm_file *file_priv) 3972{ 3973 return i915_gem_ring_throttle(dev, file_priv); 3974} 3975 3976int 3977i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 3978 struct drm_file *file_priv) 3979{ 3980 struct drm_i915_gem_madvise *args = data; 3981 struct drm_i915_gem_object *obj; 3982 int ret; 3983 3984 switch (args->madv) { 3985 case I915_MADV_DONTNEED: 3986 case I915_MADV_WILLNEED: 3987 break; 3988 default: 3989 return -EINVAL; 3990 } 3991 3992 ret = i915_mutex_lock_interruptible(dev); 3993 if (ret) 3994 return ret; 3995 3996 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); 3997 if (&obj->base == NULL) { 3998 ret = -ENOENT; 3999 goto unlock; 4000 } 4001 4002 if (obj->pin_count) { 4003 ret = -EINVAL; 4004 goto out; 4005 } 4006 4007 if (obj->madv != __I915_MADV_PURGED) 4008 obj->madv = args->madv; 4009 4010 /* if the object is no longer attached, discard its backing storage */ 4011 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) 4012 i915_gem_object_truncate(obj); 4013 4014 args->retained = obj->madv != __I915_MADV_PURGED; 4015 4016out: 4017 drm_gem_object_unreference(&obj->base); 4018unlock: 4019 DRM_UNLOCK(dev); 4020 return ret; 4021} 4022 4023void i915_gem_object_init(struct drm_i915_gem_object *obj, 4024 const struct drm_i915_gem_object_ops *ops) 4025{ 4026 INIT_LIST_HEAD(&obj->mm_list); 4027 INIT_LIST_HEAD(&obj->gtt_list); 4028 INIT_LIST_HEAD(&obj->ring_list); 4029 INIT_LIST_HEAD(&obj->exec_list); 4030 4031 obj->ops = ops; 4032 4033 obj->fence_reg = I915_FENCE_REG_NONE; 4034 obj->madv = I915_MADV_WILLNEED; 4035 /* Avoid an unnecessary call to unbind on the first bind. */ 4036 obj->map_and_fenceable = true; 4037 4038 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); 4039} 4040 4041static const struct drm_i915_gem_object_ops i915_gem_object_ops = { 4042 .get_pages = i915_gem_object_get_pages_gtt, 4043 .put_pages = i915_gem_object_put_pages_gtt, 4044}; 4045 4046struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 4047 size_t size) 4048{ 4049 struct drm_i915_gem_object *obj; 4050 4051 obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO); 4052 if (obj == NULL) 4053 return NULL; 4054 4055 if (drm_gem_object_init(dev, &obj->base, size) != 0) { 4056 free(obj, DRM_I915_GEM); 4057 return NULL; 4058 } 4059 4060#ifdef FREEBSD_WIP 4061 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; 4062 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { 4063 /* 965gm cannot relocate objects above 4GiB. */ 4064 mask &= ~__GFP_HIGHMEM; 4065 mask |= __GFP_DMA32; 4066 } 4067 4068 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; 4069 mapping_set_gfp_mask(mapping, mask); 4070#endif /* FREEBSD_WIP */ 4071 4072 i915_gem_object_init(obj, &i915_gem_object_ops); 4073 4074 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 4075 obj->base.read_domains = I915_GEM_DOMAIN_CPU; 4076 4077 if (HAS_LLC(dev)) { 4078 /* On some devices, we can have the GPU use the LLC (the CPU 4079 * cache) for about a 10% performance improvement 4080 * compared to uncached. Graphics requests other than 4081 * display scanout are coherent with the CPU in 4082 * accessing this cache. This means in this mode we 4083 * don't need to clflush on the CPU side, and on the 4084 * GPU side we only need to flush internal caches to 4085 * get data visible to the CPU. 4086 * 4087 * However, we maintain the display planes as UC, and so 4088 * need to rebind when first used as such. 4089 */ 4090 obj->cache_level = I915_CACHE_LLC; 4091 } else 4092 obj->cache_level = I915_CACHE_NONE; 4093 4094 return obj; 4095} 4096 4097int i915_gem_init_object(struct drm_gem_object *obj) 4098{ 4099 printf("i915_gem_init_object called\n"); 4100 4101 return 0; 4102} 4103 4104void i915_gem_free_object(struct drm_gem_object *gem_obj) 4105{ 4106 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 4107 struct drm_device *dev = obj->base.dev; 4108 drm_i915_private_t *dev_priv = dev->dev_private; 4109 4110 CTR1(KTR_DRM, "object_destroy_tail %p", obj); 4111 4112 if (obj->phys_obj) 4113 i915_gem_detach_phys_object(dev, obj); 4114 4115 obj->pin_count = 0; 4116 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { 4117 bool was_interruptible; 4118 4119 was_interruptible = dev_priv->mm.interruptible; 4120 dev_priv->mm.interruptible = false; 4121 4122 WARN_ON(i915_gem_object_unbind(obj)); 4123 4124 dev_priv->mm.interruptible = was_interruptible; 4125 } 4126 4127 obj->pages_pin_count = 0; 4128 i915_gem_object_put_pages(obj); 4129 i915_gem_object_free_mmap_offset(obj); 4130 4131 BUG_ON(obj->pages); 4132 4133#ifdef FREEBSD_WIP 4134 if (obj->base.import_attach) 4135 drm_prime_gem_destroy(&obj->base, NULL); 4136#endif /* FREEBSD_WIP */ 4137 4138 drm_gem_object_release(&obj->base); 4139 i915_gem_info_remove_obj(dev_priv, obj->base.size); 4140 4141 free(obj->bit_17, DRM_I915_GEM); 4142 free(obj, DRM_I915_GEM); 4143} 4144 4145int 4146i915_gem_idle(struct drm_device *dev) 4147{ 4148 drm_i915_private_t *dev_priv = dev->dev_private; 4149 int ret; 4150 4151 DRM_LOCK(dev); 4152 4153 if (dev_priv->mm.suspended) { 4154 DRM_UNLOCK(dev); 4155 return 0; 4156 } 4157 4158 ret = i915_gpu_idle(dev); 4159 if (ret) { 4160 DRM_UNLOCK(dev); 4161 return ret; 4162 } 4163 i915_gem_retire_requests(dev); 4164 4165 /* Under UMS, be paranoid and evict. */ 4166 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 4167 i915_gem_evict_everything(dev); 4168 4169 i915_gem_reset_fences(dev); 4170 4171 /* Hack! Don't let anybody do execbuf while we don't control the chip. 4172 * We need to replace this with a semaphore, or something. 4173 * And not confound mm.suspended! 4174 */ 4175 dev_priv->mm.suspended = 1; 4176 callout_stop(&dev_priv->hangcheck_timer); 4177 4178 i915_kernel_lost_context(dev); 4179 i915_gem_cleanup_ringbuffer(dev); 4180 4181 DRM_UNLOCK(dev); 4182 4183 /* Cancel the retire work handler, which should be idle now. */ 4184 taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->mm.retire_work, NULL); 4185 4186 return 0; 4187} 4188 4189void i915_gem_l3_remap(struct drm_device *dev) 4190{ 4191 drm_i915_private_t *dev_priv = dev->dev_private; 4192 u32 misccpctl; 4193 int i; 4194 4195 if (!HAS_L3_GPU_CACHE(dev)) 4196 return; 4197 4198 if (!dev_priv->l3_parity.remap_info) 4199 return; 4200 4201 misccpctl = I915_READ(GEN7_MISCCPCTL); 4202 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 4203 POSTING_READ(GEN7_MISCCPCTL); 4204 4205 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { 4206 u32 remap = I915_READ(GEN7_L3LOG_BASE + i); 4207 if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) 4208 DRM_DEBUG("0x%x was already programmed to %x\n", 4209 GEN7_L3LOG_BASE + i, remap); 4210 if (remap && !dev_priv->l3_parity.remap_info[i/4]) 4211 DRM_DEBUG_DRIVER("Clearing remapped register\n"); 4212 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); 4213 } 4214 4215 /* Make sure all the writes land before disabling dop clock gating */ 4216 POSTING_READ(GEN7_L3LOG_BASE); 4217 4218 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 4219} 4220 4221void i915_gem_init_swizzling(struct drm_device *dev) 4222{ 4223 drm_i915_private_t *dev_priv = dev->dev_private; 4224 4225 if (INTEL_INFO(dev)->gen < 5 || 4226 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) 4227 return; 4228 4229 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | 4230 DISP_TILE_SURFACE_SWIZZLING); 4231 4232 if (IS_GEN5(dev)) 4233 return; 4234 4235 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); 4236 if (IS_GEN6(dev)) 4237 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); 4238 else 4239 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); 4240} 4241 4242static bool 4243intel_enable_blt(struct drm_device *dev) 4244{ 4245 if (!HAS_BLT(dev)) 4246 return false; 4247 4248 /* The blitter was dysfunctional on early prototypes */ 4249 if (IS_GEN6(dev) && pci_get_revid(dev->dev) < 8) { 4250 DRM_INFO("BLT not supported on this pre-production hardware;" 4251 " graphics performance will be degraded.\n"); 4252 return false; 4253 } 4254 4255 return true; 4256} 4257 4258int 4259i915_gem_init_hw(struct drm_device *dev) 4260{ 4261 drm_i915_private_t *dev_priv = dev->dev_private; 4262 int ret; 4263 4264#ifdef FREEBSD_WIP 4265 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) 4266 return -EIO; 4267#endif /* FREEBSD_WIP */ 4268 4269 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) 4270 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); 4271 4272 i915_gem_l3_remap(dev); 4273 4274 i915_gem_init_swizzling(dev); 4275 4276 ret = intel_init_render_ring_buffer(dev); 4277 if (ret) 4278 return ret; 4279 4280 if (HAS_BSD(dev)) { 4281 ret = intel_init_bsd_ring_buffer(dev); 4282 if (ret) 4283 goto cleanup_render_ring; 4284 } 4285 4286 if (intel_enable_blt(dev)) { 4287 ret = intel_init_blt_ring_buffer(dev); 4288 if (ret) 4289 goto cleanup_bsd_ring; 4290 } 4291 4292 dev_priv->next_seqno = 1; 4293 4294 /* 4295 * XXX: There was some w/a described somewhere suggesting loading 4296 * contexts before PPGTT. 4297 */ 4298 i915_gem_context_init(dev); 4299 i915_gem_init_ppgtt(dev); 4300 4301 return 0; 4302 4303cleanup_bsd_ring: 4304 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); 4305cleanup_render_ring: 4306 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); 4307 return ret; 4308} 4309 4310static bool 4311intel_enable_ppgtt(struct drm_device *dev) 4312{ 4313 if (i915_enable_ppgtt >= 0) 4314 return i915_enable_ppgtt; 4315 4316#ifdef CONFIG_INTEL_IOMMU 4317 /* Disable ppgtt on SNB if VT-d is on. */ 4318 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 4319 return false; 4320#endif 4321 4322 return true; 4323} 4324 4325int i915_gem_init(struct drm_device *dev) 4326{ 4327 struct drm_i915_private *dev_priv = dev->dev_private; 4328 unsigned long gtt_size, mappable_size; 4329 int ret; 4330 4331 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; 4332 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; 4333 4334 DRM_LOCK(dev); 4335 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { 4336 /* PPGTT pdes are stolen from global gtt ptes, so shrink the 4337 * aperture accordingly when using aliasing ppgtt. */ 4338 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; 4339 4340 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); 4341 4342 ret = i915_gem_init_aliasing_ppgtt(dev); 4343 if (ret) { 4344 DRM_UNLOCK(dev); 4345 return ret; 4346 } 4347 } else { 4348 /* Let GEM Manage all of the aperture. 4349 * 4350 * However, leave one page at the end still bound to the scratch 4351 * page. There are a number of places where the hardware 4352 * apparently prefetches past the end of the object, and we've 4353 * seen multiple hangs with the GPU head pointer stuck in a 4354 * batchbuffer bound at the last page of the aperture. One page 4355 * should be enough to keep any prefetching inside of the 4356 * aperture. 4357 */ 4358 i915_gem_init_global_gtt(dev, 0, mappable_size, 4359 gtt_size); 4360 } 4361 4362 ret = i915_gem_init_hw(dev); 4363 DRM_UNLOCK(dev); 4364 if (ret) { 4365 i915_gem_cleanup_aliasing_ppgtt(dev); 4366 return ret; 4367 } 4368 4369 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ 4370 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 4371 dev_priv->dri1.allow_batchbuffer = 1; 4372 return 0; 4373} 4374 4375void 4376i915_gem_cleanup_ringbuffer(struct drm_device *dev) 4377{ 4378 drm_i915_private_t *dev_priv = dev->dev_private; 4379 struct intel_ring_buffer *ring; 4380 int i; 4381 4382 for_each_ring(ring, dev_priv, i) 4383 intel_cleanup_ring_buffer(ring); 4384} 4385 4386int 4387i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 4388 struct drm_file *file_priv) 4389{ 4390 drm_i915_private_t *dev_priv = dev->dev_private; 4391 int ret; 4392 4393 if (drm_core_check_feature(dev, DRIVER_MODESET)) 4394 return 0; 4395 4396 if (atomic_read(&dev_priv->mm.wedged)) { 4397 DRM_ERROR("Reenabling wedged hardware, good luck\n"); 4398 atomic_set(&dev_priv->mm.wedged, 0); 4399 } 4400 4401 DRM_LOCK(dev); 4402 dev_priv->mm.suspended = 0; 4403 4404 ret = i915_gem_init_hw(dev); 4405 if (ret != 0) { 4406 DRM_UNLOCK(dev); 4407 return ret; 4408 } 4409 4410 BUG_ON(!list_empty(&dev_priv->mm.active_list)); 4411 DRM_UNLOCK(dev); 4412 4413 ret = drm_irq_install(dev); 4414 if (ret) 4415 goto cleanup_ringbuffer; 4416 4417 return 0; 4418 4419cleanup_ringbuffer: 4420 DRM_LOCK(dev); 4421 i915_gem_cleanup_ringbuffer(dev); 4422 dev_priv->mm.suspended = 1; 4423 DRM_UNLOCK(dev); 4424 4425 return ret; 4426} 4427 4428int 4429i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 4430 struct drm_file *file_priv) 4431{ 4432 if (drm_core_check_feature(dev, DRIVER_MODESET)) 4433 return 0; 4434 4435 drm_irq_uninstall(dev); 4436 return i915_gem_idle(dev); 4437} 4438 4439void 4440i915_gem_lastclose(struct drm_device *dev) 4441{ 4442 int ret; 4443 4444 if (drm_core_check_feature(dev, DRIVER_MODESET)) 4445 return; 4446 4447 ret = i915_gem_idle(dev); 4448 if (ret) 4449 DRM_ERROR("failed to idle hardware: %d\n", ret); 4450} 4451 4452static void 4453init_ring_lists(struct intel_ring_buffer *ring) 4454{ 4455 INIT_LIST_HEAD(&ring->active_list); 4456 INIT_LIST_HEAD(&ring->request_list); 4457} 4458 4459void 4460i915_gem_load(struct drm_device *dev) 4461{ 4462 int i; 4463 drm_i915_private_t *dev_priv = dev->dev_private; 4464 4465 INIT_LIST_HEAD(&dev_priv->mm.active_list); 4466 INIT_LIST_HEAD(&dev_priv->mm.inactive_list); 4467 INIT_LIST_HEAD(&dev_priv->mm.unbound_list); 4468 INIT_LIST_HEAD(&dev_priv->mm.bound_list); 4469 INIT_LIST_HEAD(&dev_priv->mm.fence_list); 4470 for (i = 0; i < I915_NUM_RINGS; i++) 4471 init_ring_lists(&dev_priv->ring[i]); 4472 for (i = 0; i < I915_MAX_NUM_FENCES; i++) 4473 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); 4474 TIMEOUT_TASK_INIT(dev_priv->wq, &dev_priv->mm.retire_work, 0, 4475 i915_gem_retire_work_handler, dev_priv); 4476 init_completion(&dev_priv->error_completion); 4477 4478 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 4479 if (IS_GEN3(dev)) { 4480 I915_WRITE(MI_ARB_STATE, 4481 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 4482 } 4483 4484 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; 4485 4486 /* Old X drivers will take 0-2 for front, back, depth buffers */ 4487 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 4488 dev_priv->fence_reg_start = 3; 4489 4490 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 4491 dev_priv->num_fence_regs = 16; 4492 else 4493 dev_priv->num_fence_regs = 8; 4494 4495 /* Initialize fence registers to zero */ 4496 i915_gem_reset_fences(dev); 4497 4498 i915_gem_detect_bit_6_swizzle(dev); 4499 DRM_INIT_WAITQUEUE(&dev_priv->pending_flip_queue); 4500 4501 dev_priv->mm.interruptible = true; 4502 4503 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem, 4504 i915_gem_inactive_shrink, dev, EVENTHANDLER_PRI_ANY); 4505} 4506 4507/* 4508 * Create a physically contiguous memory object for this object 4509 * e.g. for cursor + overlay regs 4510 */ 4511static int i915_gem_init_phys_object(struct drm_device *dev, 4512 int id, int size, int align) 4513{ 4514 drm_i915_private_t *dev_priv = dev->dev_private; 4515 struct drm_i915_gem_phys_object *phys_obj; 4516 int ret; 4517 4518 if (dev_priv->mm.phys_objs[id - 1] || !size) 4519 return 0; 4520 4521 phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object), 4522 DRM_I915_GEM, M_WAITOK | M_ZERO); 4523 if (!phys_obj) 4524 return -ENOMEM; 4525 4526 phys_obj->id = id; 4527 4528 phys_obj->handle = drm_pci_alloc(dev, size, align, BUS_SPACE_MAXADDR); 4529 if (!phys_obj->handle) { 4530 ret = -ENOMEM; 4531 goto kfree_obj; 4532 } 4533#ifdef CONFIG_X86 4534 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr, 4535 size / PAGE_SIZE, PAT_WRITE_COMBINING); 4536#endif 4537 4538 dev_priv->mm.phys_objs[id - 1] = phys_obj; 4539 4540 return 0; 4541kfree_obj: 4542 free(phys_obj, DRM_I915_GEM); 4543 return ret; 4544} 4545 4546static void i915_gem_free_phys_object(struct drm_device *dev, int id) 4547{ 4548 drm_i915_private_t *dev_priv = dev->dev_private; 4549 struct drm_i915_gem_phys_object *phys_obj; 4550 4551 if (!dev_priv->mm.phys_objs[id - 1]) 4552 return; 4553 4554 phys_obj = dev_priv->mm.phys_objs[id - 1]; 4555 if (phys_obj->cur_obj) { 4556 i915_gem_detach_phys_object(dev, phys_obj->cur_obj); 4557 } 4558 4559#ifdef FREEBSD_WIP 4560#ifdef CONFIG_X86 4561 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); 4562#endif 4563#endif /* FREEBSD_WIP */ 4564 4565 drm_pci_free(dev, phys_obj->handle); 4566 free(phys_obj, DRM_I915_GEM); 4567 dev_priv->mm.phys_objs[id - 1] = NULL; 4568} 4569 4570void i915_gem_free_all_phys_object(struct drm_device *dev) 4571{ 4572 int i; 4573 4574 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) 4575 i915_gem_free_phys_object(dev, i); 4576} 4577 4578void i915_gem_detach_phys_object(struct drm_device *dev, 4579 struct drm_i915_gem_object *obj) 4580{ 4581 struct sf_buf *sf; 4582 char *vaddr; 4583 char *dst; 4584 int i; 4585 int page_count; 4586 4587 if (!obj->phys_obj) 4588 return; 4589 vaddr = obj->phys_obj->handle->vaddr; 4590 4591 page_count = obj->base.size / PAGE_SIZE; 4592 VM_OBJECT_WLOCK(obj->base.vm_obj); 4593 for (i = 0; i < page_count; i++) { 4594 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL); 4595 if (page == NULL) 4596 continue; /* XXX */ 4597 4598 VM_OBJECT_WUNLOCK(obj->base.vm_obj); 4599 sf = sf_buf_alloc(page, 0); 4600 if (sf != NULL) { 4601 dst = (char *)sf_buf_kva(sf); 4602 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE); 4603 sf_buf_free(sf); 4604 } 4605 drm_clflush_pages(&page, 1); 4606 4607 VM_OBJECT_WLOCK(obj->base.vm_obj); 4608 vm_page_reference(page); 4609 vm_page_lock(page); 4610 vm_page_dirty(page); 4611 vm_page_unwire(page, PQ_INACTIVE); 4612 vm_page_unlock(page); 4613 atomic_add_long(&i915_gem_wired_pages_cnt, -1); 4614 } 4615 VM_OBJECT_WUNLOCK(obj->base.vm_obj); 4616 i915_gem_chipset_flush(dev); 4617 4618 obj->phys_obj->cur_obj = NULL; 4619 obj->phys_obj = NULL; 4620} 4621 4622int 4623i915_gem_attach_phys_object(struct drm_device *dev, 4624 struct drm_i915_gem_object *obj, 4625 int id, 4626 int align) 4627{ 4628 drm_i915_private_t *dev_priv = dev->dev_private; 4629 struct sf_buf *sf; 4630 char *dst, *src; 4631 int ret = 0; 4632 int page_count; 4633 int i; 4634 4635 if (id > I915_MAX_PHYS_OBJECT) 4636 return -EINVAL; 4637 4638 if (obj->phys_obj) { 4639 if (obj->phys_obj->id == id) 4640 return 0; 4641 i915_gem_detach_phys_object(dev, obj); 4642 } 4643 4644 /* create a new object */ 4645 if (!dev_priv->mm.phys_objs[id - 1]) { 4646 ret = i915_gem_init_phys_object(dev, id, 4647 obj->base.size, align); 4648 if (ret) { 4649 DRM_ERROR("failed to init phys object %d size: %zu\n", 4650 id, obj->base.size); 4651 return ret; 4652 } 4653 } 4654 4655 /* bind to the object */ 4656 obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; 4657 obj->phys_obj->cur_obj = obj; 4658 4659 page_count = obj->base.size / PAGE_SIZE; 4660 4661 VM_OBJECT_WLOCK(obj->base.vm_obj); 4662 for (i = 0; i < page_count; i++) { 4663 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL); 4664 if (page == NULL) { 4665 ret = -EIO; 4666 break; 4667 } 4668 VM_OBJECT_WUNLOCK(obj->base.vm_obj); 4669 sf = sf_buf_alloc(page, 0); 4670 src = (char *)sf_buf_kva(sf); 4671 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i); 4672 memcpy(dst, src, PAGE_SIZE); 4673 sf_buf_free(sf); 4674 4675 VM_OBJECT_WLOCK(obj->base.vm_obj); 4676 4677 vm_page_reference(page); 4678 vm_page_lock(page); 4679 vm_page_unwire(page, PQ_INACTIVE); 4680 vm_page_unlock(page); 4681 atomic_add_long(&i915_gem_wired_pages_cnt, -1); 4682 } 4683 VM_OBJECT_WUNLOCK(obj->base.vm_obj); 4684 4685 return ret; 4686} 4687 4688static int 4689i915_gem_phys_pwrite(struct drm_device *dev, 4690 struct drm_i915_gem_object *obj, 4691 struct drm_i915_gem_pwrite *args, 4692 struct drm_file *file_priv) 4693{ 4694 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset; 4695 char __user *user_data = to_user_ptr(args->data_ptr); 4696 4697 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { 4698 unsigned long unwritten; 4699 4700 /* The physical object once assigned is fixed for the lifetime 4701 * of the obj, so we can safely drop the lock and continue 4702 * to access vaddr. 4703 */ 4704 DRM_UNLOCK(dev); 4705 unwritten = copy_from_user(vaddr, user_data, args->size); 4706 DRM_LOCK(dev); 4707 if (unwritten) 4708 return -EFAULT; 4709 } 4710 4711 i915_gem_chipset_flush(dev); 4712 return 0; 4713} 4714 4715void i915_gem_release(struct drm_device *dev, struct drm_file *file) 4716{ 4717 struct drm_i915_file_private *file_priv = file->driver_priv; 4718 4719 /* Clean up our request list when the client is going away, so that 4720 * later retire_requests won't dereference our soon-to-be-gone 4721 * file_priv. 4722 */ 4723 mtx_lock(&file_priv->mm.lock); 4724 while (!list_empty(&file_priv->mm.request_list)) { 4725 struct drm_i915_gem_request *request; 4726 4727 request = list_first_entry(&file_priv->mm.request_list, 4728 struct drm_i915_gem_request, 4729 client_list); 4730 list_del(&request->client_list); 4731 request->file_priv = NULL; 4732 } 4733 mtx_unlock(&file_priv->mm.lock); 4734} 4735 4736static void 4737i915_gem_inactive_shrink(void *arg) 4738{ 4739 struct drm_device *dev = arg; 4740 struct drm_i915_private *dev_priv = dev->dev_private; 4741 int pass1, pass2; 4742 4743 if (!sx_try_xlock(&dev->dev_struct_lock)) { 4744 return; 4745 } 4746 4747 CTR0(KTR_DRM, "gem_lowmem"); 4748 4749 pass1 = i915_gem_purge(dev_priv, -1); 4750 pass2 = __i915_gem_shrink(dev_priv, -1, false); 4751 4752 if (pass2 <= pass1 / 100) 4753 i915_gem_shrink_all(dev_priv); 4754 4755 DRM_UNLOCK(dev); 4756} 4757 4758static vm_page_t 4759i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex, bool *fresh) 4760{ 4761 vm_page_t page; 4762 int rv; 4763 4764 VM_OBJECT_ASSERT_WLOCKED(object); 4765 page = vm_page_grab(object, pindex, VM_ALLOC_NORMAL); 4766 if (page->valid != VM_PAGE_BITS_ALL) { 4767 if (vm_pager_has_page(object, pindex, NULL, NULL)) { 4768 rv = vm_pager_get_pages(object, &page, 1, NULL, NULL); 4769 if (rv != VM_PAGER_OK) { 4770 vm_page_lock(page); 4771 vm_page_free(page); 4772 vm_page_unlock(page); 4773 return (NULL); 4774 } 4775 if (fresh != NULL) 4776 *fresh = true; 4777 } else { 4778 pmap_zero_page(page); 4779 page->valid = VM_PAGE_BITS_ALL; 4780 page->dirty = 0; 4781 if (fresh != NULL) 4782 *fresh = false; 4783 } 4784 } else if (fresh != NULL) { 4785 *fresh = false; 4786 } 4787 vm_page_lock(page); 4788 vm_page_wire(page); 4789 vm_page_unlock(page); 4790 vm_page_xunbusy(page); 4791 atomic_add_long(&i915_gem_wired_pages_cnt, 1); 4792 return (page); 4793} 4794