i915_drv.h revision 287177
1235783Skib/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2235783Skib */ 3235783Skib/* 4235783Skib * 5235783Skib * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6235783Skib * All Rights Reserved. 7235783Skib * 8235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 9235783Skib * copy of this software and associated documentation files (the 10235783Skib * "Software"), to deal in the Software without restriction, including 11235783Skib * without limitation the rights to use, copy, modify, merge, publish, 12235783Skib * distribute, sub license, and/or sell copies of the Software, and to 13235783Skib * permit persons to whom the Software is furnished to do so, subject to 14235783Skib * the following conditions: 15235783Skib * 16235783Skib * The above copyright notice and this permission notice (including the 17235783Skib * next paragraph) shall be included in all copies or substantial portions 18235783Skib * of the Software. 19235783Skib * 20235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21235783Skib * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22235783Skib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23235783Skib * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24235783Skib * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25235783Skib * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26235783Skib * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27235783Skib * 28235783Skib */ 29235783Skib 30235783Skib#include <sys/cdefs.h> 31235783Skib__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.h 287177 2015-08-26 22:19:53Z bapt $"); 32235783Skib 33235783Skib#ifndef _I915_DRV_H_ 34235783Skib#define _I915_DRV_H_ 35235783Skib 36235783Skib#include <dev/agp/agp_i810.h> 37235783Skib#include <dev/drm2/drm_mm.h> 38235783Skib#include <dev/drm2/i915/i915_reg.h> 39235783Skib#include <dev/drm2/i915/intel_ringbuffer.h> 40235783Skib#include <dev/drm2/i915/intel_bios.h> 41235783Skib 42235783Skib/* General customization: 43235783Skib */ 44235783Skib 45235783Skib#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46235783Skib 47235783Skib#define DRIVER_NAME "i915" 48235783Skib#define DRIVER_DESC "Intel Graphics" 49235783Skib#define DRIVER_DATE "20080730" 50235783Skib 51235783SkibMALLOC_DECLARE(DRM_I915_GEM); 52235783Skib 53235783Skibenum pipe { 54235783Skib PIPE_A = 0, 55235783Skib PIPE_B, 56235783Skib PIPE_C, 57235783Skib I915_MAX_PIPES 58235783Skib}; 59235783Skib#define pipe_name(p) ((p) + 'A') 60235783Skib#define I915_NUM_PIPE 2 61235783Skib 62235783Skibenum plane { 63235783Skib PLANE_A = 0, 64235783Skib PLANE_B, 65235783Skib PLANE_C, 66235783Skib}; 67235783Skib#define plane_name(p) ((p) + 'A') 68235783Skib 69277487Skibenum port { 70277487Skib PORT_A = 0, 71277487Skib PORT_B, 72277487Skib PORT_C, 73277487Skib PORT_D, 74277487Skib PORT_E, 75277487Skib I915_MAX_PORTS 76277487Skib}; 77277487Skib#define port_name(p) ((p) + 'A') 78235783Skib 79277487Skib#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 80277487Skib 81277487Skib 82235783Skib#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 83235783Skib 84277487Skibstruct intel_pch_pll { 85277487Skib int refcount; /* count of number of CRTCs sharing this PLL */ 86277487Skib int active; /* count of number of active CRTCs (i.e. DPMS on) */ 87277487Skib bool on; /* is the PLL actually active? Disabled during modeset */ 88277487Skib int pll_reg; 89277487Skib int fp0_reg; 90277487Skib int fp1_reg; 91277487Skib}; 92277487Skib#define I915_NUM_PLLS 2 93277487Skib 94235783Skib/* Interface history: 95235783Skib * 96235783Skib * 1.1: Original. 97235783Skib * 1.2: Add Power Management 98235783Skib * 1.3: Add vblank support 99235783Skib * 1.4: Fix cmdbuffer path, add heap destroy 100235783Skib * 1.5: Add vblank pipe configuration 101235783Skib * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 102235783Skib * - Support vertical blank on secondary display pipe 103235783Skib */ 104235783Skib#define DRIVER_MAJOR 1 105235783Skib#define DRIVER_MINOR 6 106235783Skib#define DRIVER_PATCHLEVEL 0 107235783Skib 108235783Skib#define WATCH_COHERENCY 0 109235783Skib#define WATCH_BUF 0 110235783Skib#define WATCH_EXEC 0 111235783Skib#define WATCH_LRU 0 112235783Skib#define WATCH_RELOC 0 113235783Skib#define WATCH_INACTIVE 0 114235783Skib#define WATCH_PWRITE 0 115235783Skib 116235783Skib#define I915_GEM_PHYS_CURSOR_0 1 117235783Skib#define I915_GEM_PHYS_CURSOR_1 2 118235783Skib#define I915_GEM_PHYS_OVERLAY_REGS 3 119235783Skib#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 120235783Skib 121235783Skibstruct drm_i915_gem_phys_object { 122235783Skib int id; 123235783Skib drm_dma_handle_t *handle; 124235783Skib struct drm_i915_gem_object *cur_obj; 125235783Skib}; 126235783Skib 127235783Skibstruct drm_i915_private; 128235783Skib 129235783Skibstruct drm_i915_display_funcs { 130235783Skib void (*dpms)(struct drm_crtc *crtc, int mode); 131235783Skib bool (*fbc_enabled)(struct drm_device *dev); 132235783Skib void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 133235783Skib void (*disable_fbc)(struct drm_device *dev); 134235783Skib int (*get_display_clock_speed)(struct drm_device *dev); 135235783Skib int (*get_fifo_size)(struct drm_device *dev, int plane); 136235783Skib void (*update_wm)(struct drm_device *dev); 137235783Skib void (*update_sprite_wm)(struct drm_device *dev, int pipe, 138235783Skib uint32_t sprite_width, int pixel_size); 139277487Skib void (*sanitize_pm)(struct drm_device *dev); 140277487Skib void (*update_linetime_wm)(struct drm_device *dev, int pipe, 141277487Skib struct drm_display_mode *mode); 142235783Skib int (*crtc_mode_set)(struct drm_crtc *crtc, 143235783Skib struct drm_display_mode *mode, 144235783Skib struct drm_display_mode *adjusted_mode, 145235783Skib int x, int y, 146235783Skib struct drm_framebuffer *old_fb); 147277487Skib void (*off)(struct drm_crtc *crtc); 148235783Skib void (*write_eld)(struct drm_connector *connector, 149235783Skib struct drm_crtc *crtc); 150235783Skib void (*fdi_link_train)(struct drm_crtc *crtc); 151235783Skib void (*init_clock_gating)(struct drm_device *dev); 152235783Skib void (*init_pch_clock_gating)(struct drm_device *dev); 153235783Skib int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 154235783Skib struct drm_framebuffer *fb, 155235783Skib struct drm_i915_gem_object *obj); 156235783Skib void (*force_wake_get)(struct drm_i915_private *dev_priv); 157235783Skib void (*force_wake_put)(struct drm_i915_private *dev_priv); 158235783Skib int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 159235783Skib int x, int y); 160235783Skib /* clock updates for mode set */ 161235783Skib /* cursor updates */ 162235783Skib /* render clock increase/decrease */ 163235783Skib /* display clock increase/decrease */ 164235783Skib /* pll clock increase/decrease */ 165235783Skib}; 166235783Skib 167235783Skibstruct intel_device_info { 168235783Skib u8 gen; 169278146Skib u8 not_supported:1; 170235783Skib u8 is_mobile:1; 171235783Skib u8 is_i85x:1; 172235783Skib u8 is_i915g:1; 173235783Skib u8 is_i945gm:1; 174235783Skib u8 is_g33:1; 175235783Skib u8 need_gfx_hws:1; 176235783Skib u8 is_g4x:1; 177235783Skib u8 is_pineview:1; 178235783Skib u8 is_broadwater:1; 179235783Skib u8 is_crestline:1; 180235783Skib u8 is_ivybridge:1; 181277487Skib u8 is_valleyview:1; 182277487Skib u8 has_pch_split:1; 183277487Skib u8 is_haswell:1; 184235783Skib u8 has_fbc:1; 185235783Skib u8 has_pipe_cxsr:1; 186235783Skib u8 has_hotplug:1; 187235783Skib u8 cursor_needs_physical:1; 188235783Skib u8 has_overlay:1; 189235783Skib u8 overlay_needs_physical:1; 190235783Skib u8 supports_tv:1; 191235783Skib u8 has_bsd_ring:1; 192235783Skib u8 has_blt_ring:1; 193235783Skib u8 has_llc:1; 194235783Skib}; 195235783Skib 196235783Skib#define I915_PPGTT_PD_ENTRIES 512 197235783Skib#define I915_PPGTT_PT_ENTRIES 1024 198235783Skibstruct i915_hw_ppgtt { 199235783Skib unsigned num_pd_entries; 200235783Skib vm_page_t *pt_pages; 201235783Skib uint32_t pd_offset; 202235783Skib vm_paddr_t *pt_dma_addr; 203235783Skib vm_paddr_t scratch_page_dma_addr; 204235783Skib}; 205235783Skib 206271705Sdumbbell 207271705Sdumbbell/* This must match up with the value previously used for execbuf2.rsvd1. */ 208271705Sdumbbell#define DEFAULT_CONTEXT_ID 0 209271705Sdumbbellstruct i915_hw_context { 210271705Sdumbbell uint32_t id; 211271705Sdumbbell bool is_initialized; 212271705Sdumbbell struct drm_i915_file_private *file_priv; 213271705Sdumbbell struct intel_ring_buffer *ring; 214271705Sdumbbell struct drm_i915_gem_object *obj; 215271705Sdumbbell}; 216271705Sdumbbell 217235783Skibenum no_fbc_reason { 218235783Skib FBC_NO_OUTPUT, /* no outputs enabled to compress */ 219235783Skib FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 220235783Skib FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 221235783Skib FBC_MODE_TOO_LARGE, /* mode too large for compression */ 222235783Skib FBC_BAD_PLANE, /* fbc not supported on plane */ 223235783Skib FBC_NOT_TILED, /* buffer not tiled */ 224235783Skib FBC_MULTIPLE_PIPES, /* more than one pipe active */ 225235783Skib FBC_MODULE_PARAM, 226235783Skib}; 227235783Skib 228235783Skibstruct mem_block { 229235783Skib struct mem_block *next; 230235783Skib struct mem_block *prev; 231235783Skib int start; 232235783Skib int size; 233235783Skib struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 234235783Skib}; 235235783Skib 236235783Skibstruct opregion_header; 237235783Skibstruct opregion_acpi; 238235783Skibstruct opregion_swsci; 239235783Skibstruct opregion_asle; 240235783Skib 241235783Skibstruct intel_opregion { 242235783Skib struct opregion_header *header; 243235783Skib struct opregion_acpi *acpi; 244235783Skib struct opregion_swsci *swsci; 245235783Skib struct opregion_asle *asle; 246235783Skib void *vbt; 247235783Skib u32 *lid_state; 248235783Skib}; 249235783Skib#define OPREGION_SIZE (8*1024) 250235783Skib 251280183Sdumbbellstruct drm_i915_master_private { 252280183Sdumbbell drm_local_map_t *sarea; 253280183Sdumbbell struct _drm_i915_sarea *sarea_priv; 254280183Sdumbbell}; 255235783Skib#define I915_FENCE_REG_NONE -1 256235783Skib#define I915_MAX_NUM_FENCES 16 257235783Skib/* 16 fences + sign bit for FENCE_REG_NONE */ 258235783Skib#define I915_MAX_NUM_FENCE_BITS 5 259235783Skib 260235783Skibstruct drm_i915_fence_reg { 261235783Skib struct list_head lru_list; 262235783Skib struct drm_i915_gem_object *obj; 263235783Skib int pin_count; 264235783Skib}; 265235783Skib 266235783Skibstruct sdvo_device_mapping { 267235783Skib u8 initialized; 268235783Skib u8 dvo_port; 269235783Skib u8 slave_addr; 270235783Skib u8 dvo_wiring; 271235783Skib u8 i2c_pin; 272235783Skib u8 ddc_pin; 273235783Skib}; 274235783Skib 275235783Skibenum intel_pch { 276235783Skib PCH_IBX, /* Ibexpeak PCH */ 277235783Skib PCH_CPT, /* Cougarpoint PCH */ 278277487Skib PCH_LPT, /* Lynxpoint PCH */ 279235783Skib}; 280235783Skib 281235783Skib#define QUIRK_PIPEA_FORCE (1<<0) 282235783Skib#define QUIRK_LVDS_SSC_DISABLE (1<<1) 283277487Skib#define QUIRK_INVERT_BRIGHTNESS (1<<2) 284235783Skib 285235783Skibstruct intel_fbdev; 286235783Skibstruct intel_fbc_work; 287235783Skib 288235783Skibtypedef struct drm_i915_private { 289235783Skib struct drm_device *dev; 290235783Skib 291277487Skib device_t gmbus_bridge[GMBUS_NUM_PORTS + 1]; 292277487Skib device_t bbbus_bridge[GMBUS_NUM_PORTS + 1]; 293277487Skib device_t gmbus[GMBUS_NUM_PORTS + 1]; 294277487Skib device_t bbbus[GMBUS_NUM_PORTS + 1]; 295235783Skib /** gmbus_sx protects against concurrent usage of the single hw gmbus 296235783Skib * controller on different i2c buses. */ 297235783Skib struct sx gmbus_sx; 298277487Skib uint32_t gpio_mmio_base; 299235783Skib 300235783Skib int relative_constants_mode; 301235783Skib 302235783Skib drm_local_map_t *mmio_map; 303235783Skib 304235783Skib /** gt_fifo_count and the subsequent register write are synchronized 305235783Skib * with dev->struct_mutex. */ 306235783Skib unsigned gt_fifo_count; 307235783Skib /** forcewake_count is protected by gt_lock */ 308235783Skib unsigned forcewake_count; 309235783Skib /** gt_lock is also taken in irq contexts. */ 310235783Skib struct mtx gt_lock; 311235783Skib 312235783Skib /* drm_i915_ring_buffer_t ring; */ 313235783Skib struct intel_ring_buffer rings[I915_NUM_RINGS]; 314235783Skib uint32_t next_seqno; 315235783Skib 316235783Skib drm_dma_handle_t *status_page_dmah; 317235783Skib void *hw_status_page; 318235783Skib dma_addr_t dma_status_page; 319235783Skib uint32_t counter; 320235783Skib unsigned int status_gfx_addr; 321235783Skib struct drm_gem_object *hws_obj; 322235783Skib 323235783Skib struct drm_i915_gem_object *pwrctx; 324235783Skib struct drm_i915_gem_object *renderctx; 325235783Skib 326235783Skib unsigned int cpp; 327235783Skib int back_offset; 328235783Skib int front_offset; 329235783Skib int current_page; 330235783Skib int page_flipping; 331235783Skib 332235783Skib atomic_t irq_received; 333235783Skib u32 trace_irq_seqno; 334235783Skib 335235783Skib /** Cached value of IER to avoid reads in updating the bitfield */ 336235783Skib u32 pipestat[2]; 337235783Skib u32 irq_mask; 338235783Skib u32 gt_irq_mask; 339235783Skib u32 pch_irq_mask; 340235783Skib struct mtx irq_lock; 341235783Skib 342277487Skib struct mtx dpio_lock; 343277487Skib 344235783Skib u32 hotplug_supported_mask; 345235783Skib 346235783Skib unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 347235783Skib int num_pipe; 348277487Skib int num_pch_pll; 349235783Skib 350235783Skib /* For hangcheck timer */ 351235783Skib#define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 352235783Skib int hangcheck_count; 353277487Skib uint32_t last_acthd[I915_NUM_RINGS]; 354235783Skib uint32_t last_instdone; 355235783Skib uint32_t last_instdone1; 356235783Skib 357277487Skib unsigned int stop_rings; 358277487Skib 359235783Skib struct intel_opregion opregion; 360235783Skib 361235783Skib 362235783Skib /* overlay */ 363235783Skib struct intel_overlay *overlay; 364235783Skib bool sprite_scaling_enabled; 365235783Skib 366235783Skib /* LVDS info */ 367235783Skib int backlight_level; /* restore backlight to this value */ 368235783Skib bool backlight_enabled; 369235783Skib struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 370235783Skib struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 371235783Skib 372235783Skib /* Feature bits from the VBIOS */ 373235783Skib unsigned int int_tv_support:1; 374235783Skib unsigned int lvds_dither:1; 375235783Skib unsigned int lvds_vbt:1; 376235783Skib unsigned int int_crt_support:1; 377235783Skib unsigned int lvds_use_ssc:1; 378235783Skib unsigned int display_clock_mode:1; 379235783Skib int lvds_ssc_freq; 380277487Skib unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 381277487Skib unsigned int lvds_val; /* used for checking LVDS channel mode */ 382235783Skib struct { 383235783Skib int rate; 384235783Skib int lanes; 385235783Skib int preemphasis; 386235783Skib int vswing; 387235783Skib 388235783Skib bool initialized; 389235783Skib bool support; 390235783Skib int bpp; 391235783Skib struct edp_power_seq pps; 392235783Skib } edp; 393235783Skib bool no_aux_handshake; 394235783Skib 395235783Skib int crt_ddc_pin; 396235783Skib struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 397235783Skib int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 398235783Skib int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 399235783Skib 400235783Skib /* PCH chipset type */ 401235783Skib enum intel_pch pch_type; 402235783Skib 403235783Skib /* Display functions */ 404235783Skib struct drm_i915_display_funcs display; 405235783Skib 406235783Skib unsigned long quirks; 407235783Skib 408235783Skib /* Register state */ 409235783Skib bool modeset_on_lid; 410235783Skib u8 saveLBB; 411235783Skib u32 saveDSPACNTR; 412235783Skib u32 saveDSPBCNTR; 413235783Skib u32 saveDSPARB; 414235783Skib u32 saveHWS; 415235783Skib u32 savePIPEACONF; 416235783Skib u32 savePIPEBCONF; 417235783Skib u32 savePIPEASRC; 418235783Skib u32 savePIPEBSRC; 419235783Skib u32 saveFPA0; 420235783Skib u32 saveFPA1; 421235783Skib u32 saveDPLL_A; 422235783Skib u32 saveDPLL_A_MD; 423235783Skib u32 saveHTOTAL_A; 424235783Skib u32 saveHBLANK_A; 425235783Skib u32 saveHSYNC_A; 426235783Skib u32 saveVTOTAL_A; 427235783Skib u32 saveVBLANK_A; 428235783Skib u32 saveVSYNC_A; 429235783Skib u32 saveBCLRPAT_A; 430235783Skib u32 saveTRANSACONF; 431235783Skib u32 saveTRANS_HTOTAL_A; 432235783Skib u32 saveTRANS_HBLANK_A; 433235783Skib u32 saveTRANS_HSYNC_A; 434235783Skib u32 saveTRANS_VTOTAL_A; 435235783Skib u32 saveTRANS_VBLANK_A; 436235783Skib u32 saveTRANS_VSYNC_A; 437235783Skib u32 savePIPEASTAT; 438235783Skib u32 saveDSPASTRIDE; 439235783Skib u32 saveDSPASIZE; 440235783Skib u32 saveDSPAPOS; 441235783Skib u32 saveDSPAADDR; 442235783Skib u32 saveDSPASURF; 443235783Skib u32 saveDSPATILEOFF; 444235783Skib u32 savePFIT_PGM_RATIOS; 445235783Skib u32 saveBLC_HIST_CTL; 446235783Skib u32 saveBLC_PWM_CTL; 447235783Skib u32 saveBLC_PWM_CTL2; 448235783Skib u32 saveBLC_CPU_PWM_CTL; 449235783Skib u32 saveBLC_CPU_PWM_CTL2; 450235783Skib u32 saveFPB0; 451235783Skib u32 saveFPB1; 452235783Skib u32 saveDPLL_B; 453235783Skib u32 saveDPLL_B_MD; 454235783Skib u32 saveHTOTAL_B; 455235783Skib u32 saveHBLANK_B; 456235783Skib u32 saveHSYNC_B; 457235783Skib u32 saveVTOTAL_B; 458235783Skib u32 saveVBLANK_B; 459235783Skib u32 saveVSYNC_B; 460235783Skib u32 saveBCLRPAT_B; 461235783Skib u32 saveTRANSBCONF; 462235783Skib u32 saveTRANS_HTOTAL_B; 463235783Skib u32 saveTRANS_HBLANK_B; 464235783Skib u32 saveTRANS_HSYNC_B; 465235783Skib u32 saveTRANS_VTOTAL_B; 466235783Skib u32 saveTRANS_VBLANK_B; 467235783Skib u32 saveTRANS_VSYNC_B; 468235783Skib u32 savePIPEBSTAT; 469235783Skib u32 saveDSPBSTRIDE; 470235783Skib u32 saveDSPBSIZE; 471235783Skib u32 saveDSPBPOS; 472235783Skib u32 saveDSPBADDR; 473235783Skib u32 saveDSPBSURF; 474235783Skib u32 saveDSPBTILEOFF; 475235783Skib u32 saveVGA0; 476235783Skib u32 saveVGA1; 477235783Skib u32 saveVGA_PD; 478235783Skib u32 saveVGACNTRL; 479235783Skib u32 saveADPA; 480235783Skib u32 saveLVDS; 481235783Skib u32 savePP_ON_DELAYS; 482235783Skib u32 savePP_OFF_DELAYS; 483235783Skib u32 saveDVOA; 484235783Skib u32 saveDVOB; 485235783Skib u32 saveDVOC; 486235783Skib u32 savePP_ON; 487235783Skib u32 savePP_OFF; 488235783Skib u32 savePP_CONTROL; 489235783Skib u32 savePP_DIVISOR; 490235783Skib u32 savePFIT_CONTROL; 491235783Skib u32 save_palette_a[256]; 492235783Skib u32 save_palette_b[256]; 493235783Skib u32 saveDPFC_CB_BASE; 494235783Skib u32 saveFBC_CFB_BASE; 495235783Skib u32 saveFBC_LL_BASE; 496235783Skib u32 saveFBC_CONTROL; 497235783Skib u32 saveFBC_CONTROL2; 498235783Skib u32 saveIER; 499235783Skib u32 saveIIR; 500235783Skib u32 saveIMR; 501235783Skib u32 saveDEIER; 502235783Skib u32 saveDEIMR; 503235783Skib u32 saveGTIER; 504235783Skib u32 saveGTIMR; 505235783Skib u32 saveFDI_RXA_IMR; 506235783Skib u32 saveFDI_RXB_IMR; 507235783Skib u32 saveCACHE_MODE_0; 508235783Skib u32 saveMI_ARB_STATE; 509235783Skib u32 saveSWF0[16]; 510235783Skib u32 saveSWF1[16]; 511235783Skib u32 saveSWF2[3]; 512235783Skib u8 saveMSR; 513235783Skib u8 saveSR[8]; 514235783Skib u8 saveGR[25]; 515235783Skib u8 saveAR_INDEX; 516235783Skib u8 saveAR[21]; 517235783Skib u8 saveDACMASK; 518235783Skib u8 saveCR[37]; 519235783Skib uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 520235783Skib u32 saveCURACNTR; 521235783Skib u32 saveCURAPOS; 522235783Skib u32 saveCURABASE; 523235783Skib u32 saveCURBCNTR; 524235783Skib u32 saveCURBPOS; 525235783Skib u32 saveCURBBASE; 526235783Skib u32 saveCURSIZE; 527235783Skib u32 saveDP_B; 528235783Skib u32 saveDP_C; 529235783Skib u32 saveDP_D; 530235783Skib u32 savePIPEA_GMCH_DATA_M; 531235783Skib u32 savePIPEB_GMCH_DATA_M; 532235783Skib u32 savePIPEA_GMCH_DATA_N; 533235783Skib u32 savePIPEB_GMCH_DATA_N; 534235783Skib u32 savePIPEA_DP_LINK_M; 535235783Skib u32 savePIPEB_DP_LINK_M; 536235783Skib u32 savePIPEA_DP_LINK_N; 537235783Skib u32 savePIPEB_DP_LINK_N; 538235783Skib u32 saveFDI_RXA_CTL; 539235783Skib u32 saveFDI_TXA_CTL; 540235783Skib u32 saveFDI_RXB_CTL; 541235783Skib u32 saveFDI_TXB_CTL; 542235783Skib u32 savePFA_CTL_1; 543235783Skib u32 savePFB_CTL_1; 544235783Skib u32 savePFA_WIN_SZ; 545235783Skib u32 savePFB_WIN_SZ; 546235783Skib u32 savePFA_WIN_POS; 547235783Skib u32 savePFB_WIN_POS; 548235783Skib u32 savePCH_DREF_CONTROL; 549235783Skib u32 saveDISP_ARB_CTL; 550235783Skib u32 savePIPEA_DATA_M1; 551235783Skib u32 savePIPEA_DATA_N1; 552235783Skib u32 savePIPEA_LINK_M1; 553235783Skib u32 savePIPEA_LINK_N1; 554235783Skib u32 savePIPEB_DATA_M1; 555235783Skib u32 savePIPEB_DATA_N1; 556235783Skib u32 savePIPEB_LINK_M1; 557235783Skib u32 savePIPEB_LINK_N1; 558235783Skib u32 saveMCHBAR_RENDER_STANDBY; 559235783Skib u32 savePCH_PORT_HOTPLUG; 560235783Skib 561235783Skib struct { 562235783Skib /** Memory allocator for GTT stolen memory */ 563235783Skib struct drm_mm stolen; 564235783Skib /** Memory allocator for GTT */ 565235783Skib struct drm_mm gtt_space; 566235783Skib /** List of all objects in gtt_space. Used to restore gtt 567235783Skib * mappings on resume */ 568235783Skib struct list_head gtt_list; 569235783Skib 570235783Skib /** Usable portion of the GTT for GEM */ 571235783Skib unsigned long gtt_start; 572235783Skib unsigned long gtt_mappable_end; 573235783Skib unsigned long gtt_end; 574235783Skib 575235783Skib /** PPGTT used for aliasing the PPGTT with the GTT */ 576235783Skib struct i915_hw_ppgtt *aliasing_ppgtt; 577235783Skib 578235783Skib /** 579235783Skib * List of objects currently involved in rendering from the 580235783Skib * ringbuffer. 581235783Skib * 582235783Skib * Includes buffers having the contents of their GPU caches 583235783Skib * flushed, not necessarily primitives. last_rendering_seqno 584235783Skib * represents when the rendering involved will be completed. 585235783Skib * 586235783Skib * A reference is held on the buffer while on this list. 587235783Skib */ 588235783Skib struct list_head active_list; 589235783Skib 590235783Skib /** 591235783Skib * List of objects which are not in the ringbuffer but which 592235783Skib * still have a write_domain which needs to be flushed before 593235783Skib * unbinding. 594235783Skib * 595235783Skib * A reference is held on the buffer while on this list. 596235783Skib */ 597235783Skib struct list_head flushing_list; 598235783Skib 599235783Skib /** 600235783Skib * LRU list of objects which are not in the ringbuffer and 601235783Skib * are ready to unbind, but are still in the GTT. 602235783Skib * 603235783Skib * last_rendering_seqno is 0 while an object is in this list. 604235783Skib * 605235783Skib * A reference is not held on the buffer while on this list, 606235783Skib * as merely being GTT-bound shouldn't prevent its being 607235783Skib * freed, and we'll pull it off the list in the free path. 608235783Skib */ 609235783Skib struct list_head inactive_list; 610235783Skib 611235783Skib /** LRU list of objects with fence regs on them. */ 612235783Skib struct list_head fence_list; 613235783Skib 614235783Skib /** 615235783Skib * We leave the user IRQ off as much as possible, 616235783Skib * but this means that requests will finish and never 617235783Skib * be retired once the system goes idle. Set a timer to 618235783Skib * fire periodically while the ring is running. When it 619235783Skib * fires, go retire requests. 620235783Skib */ 621235783Skib struct timeout_task retire_task; 622235783Skib 623235783Skib /** 624235783Skib * Are we in a non-interruptible section of code like 625235783Skib * modesetting? 626235783Skib */ 627235783Skib bool interruptible; 628235783Skib 629235783Skib uint32_t next_gem_seqno; 630235783Skib 631235783Skib /** 632235783Skib * Waiting sequence number, if any 633235783Skib */ 634235783Skib uint32_t waiting_gem_seqno; 635235783Skib 636235783Skib /** 637235783Skib * Last seq seen at irq time 638235783Skib */ 639235783Skib uint32_t irq_gem_seqno; 640235783Skib 641235783Skib /** 642235783Skib * Flag if the X Server, and thus DRM, is not currently in 643235783Skib * control of the device. 644235783Skib * 645235783Skib * This is set between LeaveVT and EnterVT. It needs to be 646235783Skib * replaced with a semaphore. It also needs to be 647235783Skib * transitioned away from for kernel modesetting. 648235783Skib */ 649235783Skib int suspended; 650235783Skib 651235783Skib /** 652235783Skib * Flag if the hardware appears to be wedged. 653235783Skib * 654235783Skib * This is set when attempts to idle the device timeout. 655235783Skib * It prevents command submission from occuring and makes 656235783Skib * every pending request fail 657235783Skib */ 658235783Skib int wedged; 659235783Skib 660235783Skib /** Bit 6 swizzling required for X tiling */ 661235783Skib uint32_t bit_6_swizzle_x; 662235783Skib /** Bit 6 swizzling required for Y tiling */ 663235783Skib uint32_t bit_6_swizzle_y; 664235783Skib 665235783Skib /* storage for physical objects */ 666235783Skib struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 667235783Skib 668235783Skib /* accounting, useful for userland debugging */ 669235783Skib size_t gtt_total; 670235783Skib size_t mappable_gtt_total; 671235783Skib size_t object_memory; 672235783Skib u32 object_count; 673235783Skib 674235783Skib struct intel_gtt gtt; 675235783Skib eventhandler_tag i915_lowmem; 676235783Skib } mm; 677235783Skib 678235783Skib const struct intel_device_info *info; 679235783Skib 680277487Skib /* Old dri1 support infrastructure, beware the dragons ya fools entering 681277487Skib * here! */ 682277487Skib struct { 683277487Skib unsigned allow_batchbuffer : 1; 684277487Skib u32 *gfx_hws_cpu_addr; 685277487Skib } dri1; 686277487Skib 687277487Skib /* Kernel Modesetting */ 688277487Skib 689235783Skib struct sdvo_device_mapping sdvo_mappings[2]; 690235783Skib /* indicate whether the LVDS_BORDER should be enabled or not */ 691235783Skib unsigned int lvds_border_bits; 692235783Skib /* Panel fitter placement and size for Ironlake+ */ 693235783Skib u32 pch_pf_pos, pch_pf_size; 694235783Skib 695235783Skib struct drm_crtc *plane_to_crtc_mapping[3]; 696235783Skib struct drm_crtc *pipe_to_crtc_mapping[3]; 697235783Skib /* wait_queue_head_t pending_flip_queue; XXXKIB */ 698235783Skib 699277487Skib struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 700277487Skib 701235783Skib /* Reclocking support */ 702235783Skib bool render_reclock_avail; 703235783Skib bool lvds_downclock_avail; 704235783Skib /* indicates the reduced downclock for LVDS*/ 705235783Skib int lvds_downclock; 706235783Skib struct task idle_task; 707235783Skib struct callout idle_callout; 708235783Skib bool busy; 709235783Skib u16 orig_clock; 710235783Skib int child_dev_num; 711235783Skib struct child_device_config *child_dev; 712235783Skib struct drm_connector *int_lvds_connector; 713235783Skib struct drm_connector *int_edp_connector; 714235783Skib 715235783Skib device_t bridge_dev; 716235783Skib bool mchbar_need_disable; 717235783Skib int mch_res_rid; 718235783Skib struct resource *mch_res; 719235783Skib 720235783Skib struct mtx rps_lock; 721235783Skib u32 pm_iir; 722235783Skib struct task rps_task; 723235783Skib 724235783Skib u8 cur_delay; 725235783Skib u8 min_delay; 726235783Skib u8 max_delay; 727235783Skib u8 fmax; 728235783Skib u8 fstart; 729235783Skib 730235783Skib u64 last_count1; 731235783Skib unsigned long last_time1; 732235783Skib unsigned long chipset_power; 733235783Skib u64 last_count2; 734235783Skib struct timespec last_time2; 735235783Skib unsigned long gfx_power; 736235783Skib int c_m; 737235783Skib int r_t; 738235783Skib u8 corr; 739235783Skib struct mtx *mchdev_lock; 740235783Skib 741235783Skib enum no_fbc_reason no_fbc_reason; 742235783Skib 743277487Skib struct drm_mm_node *compressed_fb; 744277487Skib struct drm_mm_node *compressed_llb; 745271705Sdumbbell 746235783Skib unsigned long cfb_size; 747235783Skib unsigned int cfb_fb; 748235783Skib int cfb_plane; 749235783Skib int cfb_y; 750235783Skib struct intel_fbc_work *fbc_work; 751235783Skib 752235783Skib unsigned int fsb_freq, mem_freq, is_ddr3; 753235783Skib 754235783Skib struct taskqueue *tq; 755235783Skib struct task error_task; 756235783Skib struct task hotplug_task; 757235783Skib int error_completion; 758235783Skib struct mtx error_completion_lock; 759277487Skib /* Protected by dev->error_lock. */ 760235783Skib struct drm_i915_error_state *first_error; 761235783Skib struct mtx error_lock; 762235783Skib struct callout hangcheck_timer; 763235783Skib 764235783Skib unsigned long last_gpu_reset; 765235783Skib 766235783Skib struct intel_fbdev *fbdev; 767235783Skib 768235783Skib struct drm_property *broadcast_rgb_property; 769235783Skib struct drm_property *force_audio_property; 770271705Sdumbbell 771271705Sdumbbell bool hw_contexts_disabled; 772271705Sdumbbell uint32_t hw_context_size; 773235783Skib} drm_i915_private_t; 774235783Skib 775271705Sdumbbell/* Iterate over initialised rings */ 776271705Sdumbbell#define for_each_ring(ring__, dev_priv__, i__) \ 777271705Sdumbbell for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 778271705Sdumbbell if (((ring__) = &(dev_priv__)->rings[(i__)]), intel_ring_initialized((ring__))) 779271705Sdumbbell 780235783Skibenum hdmi_force_audio { 781235783Skib HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 782235783Skib HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 783235783Skib HDMI_AUDIO_AUTO, /* trust EDID */ 784235783Skib HDMI_AUDIO_ON, /* force turn on HDMI audio */ 785235783Skib}; 786235783Skib 787235783Skibenum i915_cache_level { 788235783Skib I915_CACHE_NONE, 789235783Skib I915_CACHE_LLC, 790235783Skib I915_CACHE_LLC_MLC, /* gen6+ */ 791235783Skib}; 792235783Skib 793235783Skibenum intel_chip_family { 794235783Skib CHIP_I8XX = 0x01, 795235783Skib CHIP_I9XX = 0x02, 796235783Skib CHIP_I915 = 0x04, 797235783Skib CHIP_I965 = 0x08, 798235783Skib}; 799235783Skib 800235783Skib/** driver private structure attached to each drm_gem_object */ 801235783Skibstruct drm_i915_gem_object { 802235783Skib struct drm_gem_object base; 803235783Skib 804235783Skib /** Current space allocated to this object in the GTT, if any. */ 805235783Skib struct drm_mm_node *gtt_space; 806235783Skib struct list_head gtt_list; 807235783Skib /** This object's place on the active/flushing/inactive lists */ 808235783Skib struct list_head ring_list; 809235783Skib struct list_head mm_list; 810235783Skib /** This object's place on GPU write list */ 811235783Skib struct list_head gpu_write_list; 812235783Skib /** This object's place in the batchbuffer or on the eviction list */ 813235783Skib struct list_head exec_list; 814235783Skib 815235783Skib /** 816235783Skib * This is set if the object is on the active or flushing lists 817235783Skib * (has pending rendering), and is not set if it's on inactive (ready 818235783Skib * to be unbound). 819235783Skib */ 820235783Skib unsigned int active:1; 821235783Skib 822235783Skib /** 823235783Skib * This is set if the object has been written to since last bound 824235783Skib * to the GTT 825235783Skib */ 826235783Skib unsigned int dirty:1; 827235783Skib 828235783Skib /** 829235783Skib * This is set if the object has been written to since the last 830235783Skib * GPU flush. 831235783Skib */ 832235783Skib unsigned int pending_gpu_write:1; 833235783Skib 834235783Skib /** 835235783Skib * Fence register bits (if any) for this object. Will be set 836235783Skib * as needed when mapped into the GTT. 837235783Skib * Protected by dev->struct_mutex. 838235783Skib */ 839235783Skib signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 840235783Skib 841235783Skib /** 842235783Skib * Advice: are the backing pages purgeable? 843235783Skib */ 844235783Skib unsigned int madv:2; 845235783Skib 846235783Skib /** 847235783Skib * Current tiling mode for the object. 848235783Skib */ 849235783Skib unsigned int tiling_mode:2; 850277487Skib /** 851277487Skib * Whether the tiling parameters for the currently associated fence 852277487Skib * register have changed. Note that for the purposes of tracking 853277487Skib * tiling changes we also treat the unfenced register, the register 854277487Skib * slot that the object occupies whilst it executes a fenced 855277487Skib * command (such as BLT on gen2/3), as a "fence". 856277487Skib */ 857277487Skib unsigned int fence_dirty:1; 858235783Skib 859235783Skib /** How many users have pinned this object in GTT space. The following 860235783Skib * users can each hold at most one reference: pwrite/pread, pin_ioctl 861235783Skib * (via user_pin_count), execbuffer (objects are not allowed multiple 862235783Skib * times for the same batchbuffer), and the framebuffer code. When 863235783Skib * switching/pageflipping, the framebuffer code has at most two buffers 864235783Skib * pinned per crtc. 865235783Skib * 866235783Skib * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 867235783Skib * bits with absolutely no headroom. So use 4 bits. */ 868235783Skib unsigned int pin_count:4; 869235783Skib#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 870235783Skib 871235783Skib /** 872235783Skib * Is the object at the current location in the gtt mappable and 873235783Skib * fenceable? Used to avoid costly recalculations. 874235783Skib */ 875235783Skib unsigned int map_and_fenceable:1; 876235783Skib 877235783Skib /** 878235783Skib * Whether the current gtt mapping needs to be mappable (and isn't just 879235783Skib * mappable by accident). Track pin and fault separate for a more 880235783Skib * accurate mappable working set. 881235783Skib */ 882235783Skib unsigned int fault_mappable:1; 883235783Skib unsigned int pin_mappable:1; 884277487Skib unsigned int pin_display:1; 885235783Skib 886235783Skib /* 887235783Skib * Is the GPU currently using a fence to access this buffer, 888235783Skib */ 889235783Skib unsigned int pending_fenced_gpu_access:1; 890235783Skib unsigned int fenced_gpu_access:1; 891235783Skib 892235783Skib unsigned int cache_level:2; 893235783Skib 894235783Skib unsigned int has_aliasing_ppgtt_mapping:1; 895271705Sdumbbell unsigned int has_global_gtt_mapping:1; 896235783Skib 897235783Skib vm_page_t *pages; 898277487Skib int pages_pin_count; 899235783Skib 900235783Skib /** 901235783Skib * DMAR support 902235783Skib */ 903235783Skib struct sglist *sg_list; 904235783Skib 905235783Skib /** 906235783Skib * Used for performing relocations during execbuffer insertion. 907235783Skib */ 908235783Skib LIST_ENTRY(drm_i915_gem_object) exec_node; 909235783Skib unsigned long exec_handle; 910235783Skib struct drm_i915_gem_exec_object2 *exec_entry; 911235783Skib 912235783Skib /** 913235783Skib * Current offset of the object in GTT space. 914235783Skib * 915235783Skib * This is the same as gtt_space->start 916235783Skib */ 917235783Skib uint32_t gtt_offset; 918235783Skib 919277487Skib struct intel_ring_buffer *ring; 920277487Skib 921235783Skib /** Breadcrumb of last rendering to the buffer. */ 922235783Skib uint32_t last_rendering_seqno; 923235783Skib /** Breadcrumb of last fenced GPU access to the buffer. */ 924235783Skib uint32_t last_fenced_seqno; 925235783Skib 926235783Skib /** Current tiling stride for the object, if it's tiled. */ 927235783Skib uint32_t stride; 928235783Skib 929235783Skib /** Record of address bit 17 of each page at last unbind. */ 930235783Skib unsigned long *bit_17; 931235783Skib 932235783Skib /** User space pin count and filp owning the pin */ 933235783Skib uint32_t user_pin_count; 934235783Skib struct drm_file *pin_filp; 935235783Skib 936235783Skib /** for phy allocated objects */ 937235783Skib struct drm_i915_gem_phys_object *phys_obj; 938235783Skib 939235783Skib /** 940235783Skib * Number of crtcs where this object is currently the fb, but 941235783Skib * will be page flipped away on the next vblank. When it 942235783Skib * reaches 0, dev_priv->pending_flip_queue will be woken up. 943235783Skib */ 944235783Skib int pending_flip; 945235783Skib}; 946235783Skib 947240539Sed#define to_intel_bo(x) __containerof(x, struct drm_i915_gem_object, base) 948235783Skib 949235783Skib/** 950235783Skib * Request queue structure. 951235783Skib * 952235783Skib * The request queue allows us to note sequence numbers that have been emitted 953235783Skib * and may be associated with active buffers to be retired. 954235783Skib * 955235783Skib * By keeping this list, we can avoid having to do questionable 956235783Skib * sequence-number comparisons on buffer last_rendering_seqnos, and associate 957235783Skib * an emission time with seqnos for tracking how far ahead of the GPU we are. 958235783Skib */ 959235783Skibstruct drm_i915_gem_request { 960235783Skib /** On Which ring this request was generated */ 961235783Skib struct intel_ring_buffer *ring; 962235783Skib 963235783Skib /** GEM sequence number associated with this request. */ 964235783Skib uint32_t seqno; 965235783Skib 966235783Skib /** Postion in the ringbuffer of the end of the request */ 967235783Skib u32 tail; 968235783Skib 969235783Skib /** Time at which this request was emitted, in jiffies. */ 970235783Skib unsigned long emitted_jiffies; 971235783Skib 972235783Skib /** global list entry for this request */ 973235783Skib struct list_head list; 974235783Skib 975235783Skib struct drm_i915_file_private *file_priv; 976235783Skib /** file_priv list entry for this request */ 977235783Skib struct list_head client_list; 978235783Skib}; 979235783Skib 980235783Skibstruct drm_i915_file_private { 981235783Skib struct { 982235783Skib struct list_head request_list; 983235783Skib struct mtx lck; 984235783Skib } mm; 985271705Sdumbbell struct drm_gem_names context_idr; 986235783Skib}; 987235783Skib 988235783Skibstruct drm_i915_error_state { 989277487Skib u_int ref; 990235783Skib u32 eir; 991235783Skib u32 pgtbl_er; 992277487Skib u32 ier; 993277487Skib bool waiting[I915_NUM_RINGS]; 994235783Skib u32 pipestat[I915_MAX_PIPES]; 995235783Skib u32 tail[I915_NUM_RINGS]; 996235783Skib u32 head[I915_NUM_RINGS]; 997235783Skib u32 ipeir[I915_NUM_RINGS]; 998235783Skib u32 ipehr[I915_NUM_RINGS]; 999235783Skib u32 instdone[I915_NUM_RINGS]; 1000235783Skib u32 acthd[I915_NUM_RINGS]; 1001235783Skib u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 1002235783Skib /* our own tracking of ring head and tail */ 1003235783Skib u32 cpu_ring_head[I915_NUM_RINGS]; 1004235783Skib u32 cpu_ring_tail[I915_NUM_RINGS]; 1005235783Skib u32 error; /* gen6+ */ 1006235783Skib u32 instpm[I915_NUM_RINGS]; 1007235783Skib u32 instps[I915_NUM_RINGS]; 1008235783Skib u32 instdone1; 1009235783Skib u32 seqno[I915_NUM_RINGS]; 1010235783Skib u64 bbaddr; 1011235783Skib u32 fault_reg[I915_NUM_RINGS]; 1012235783Skib u32 done_reg; 1013235783Skib u32 faddr[I915_NUM_RINGS]; 1014235783Skib u64 fence[I915_MAX_NUM_FENCES]; 1015235783Skib struct timeval time; 1016235783Skib struct drm_i915_error_ring { 1017235783Skib struct drm_i915_error_object { 1018235783Skib int page_count; 1019235783Skib u32 gtt_offset; 1020235783Skib u32 *pages[0]; 1021235783Skib } *ringbuffer, *batchbuffer; 1022235783Skib struct drm_i915_error_request { 1023235783Skib long jiffies; 1024235783Skib u32 seqno; 1025235783Skib u32 tail; 1026235783Skib } *requests; 1027235783Skib int num_requests; 1028235783Skib } ring[I915_NUM_RINGS]; 1029235783Skib struct drm_i915_error_buffer { 1030235783Skib u32 size; 1031235783Skib u32 name; 1032235783Skib u32 seqno; 1033235783Skib u32 gtt_offset; 1034235783Skib u32 read_domains; 1035235783Skib u32 write_domain; 1036235783Skib s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 1037235783Skib s32 pinned:2; 1038235783Skib u32 tiling:2; 1039235783Skib u32 dirty:1; 1040235783Skib u32 purgeable:1; 1041235783Skib s32 ring:4; 1042235783Skib u32 cache_level:2; 1043235783Skib } *active_bo, *pinned_bo; 1044235783Skib u32 active_bo_count, pinned_bo_count; 1045235783Skib struct intel_overlay_error_state *overlay; 1046235783Skib struct intel_display_error_state *display; 1047235783Skib}; 1048235783Skib 1049235783Skib/** 1050235783Skib * RC6 is a special power stage which allows the GPU to enter an very 1051235783Skib * low-voltage mode when idle, using down to 0V while at this stage. This 1052235783Skib * stage is entered automatically when the GPU is idle when RC6 support is 1053235783Skib * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1054235783Skib * 1055235783Skib * There are different RC6 modes available in Intel GPU, which differentiate 1056235783Skib * among each other with the latency required to enter and leave RC6 and 1057235783Skib * voltage consumed by the GPU in different states. 1058235783Skib * 1059235783Skib * The combination of the following flags define which states GPU is allowed 1060235783Skib * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1061235783Skib * RC6pp is deepest RC6. Their support by hardware varies according to the 1062235783Skib * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1063235783Skib * which brings the most power savings; deeper states save more power, but 1064235783Skib * require higher latency to switch to and wake up. 1065235783Skib */ 1066235783Skib#define INTEL_RC6_ENABLE (1<<0) 1067235783Skib#define INTEL_RC6p_ENABLE (1<<1) 1068235783Skib#define INTEL_RC6pp_ENABLE (1<<2) 1069235783Skib 1070235783Skibextern int intel_iommu_enabled; 1071235783Skibextern struct drm_ioctl_desc i915_ioctls[]; 1072280183Sdumbbellextern struct drm_driver i915_driver_info; 1073235783Skibextern struct cdev_pager_ops i915_gem_pager_ops; 1074235783Skibextern unsigned int i915_fbpercrtc; 1075235783Skibextern int i915_panel_ignore_lid; 1076277487Skibextern int i915_panel_invert_brightness; 1077235783Skibextern unsigned int i915_powersave; 1078277487Skibextern int i915_prefault_disable; 1079235783Skibextern int i915_semaphores; 1080235783Skibextern unsigned int i915_lvds_downclock; 1081277487Skibextern int i915_lvds_channel_mode; 1082235783Skibextern int i915_panel_use_ssc; 1083235783Skibextern int i915_vbt_sdvo_panel_type; 1084235783Skibextern int i915_enable_rc6; 1085235783Skibextern int i915_enable_fbc; 1086235783Skibextern int i915_enable_ppgtt; 1087235783Skibextern int i915_enable_hangcheck; 1088235783Skib 1089235783Skibconst struct intel_device_info *i915_get_device_id(int device); 1090235783Skib 1091277487Skibint i915_reset(struct drm_device *dev); 1092271705Sdumbbellextern int intel_gpu_reset(struct drm_device *dev); 1093235783Skib 1094235783Skib/* i915_debug.c */ 1095235783Skibint i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1096235783Skib struct sysctl_oid *top); 1097235783Skibvoid i915_sysctl_cleanup(struct drm_device *dev); 1098235783Skib 1099280183Sdumbbellextern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1100280183Sdumbbellextern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1101280183Sdumbbell 1102235783Skib /* i915_dma.c */ 1103239375Skibint i915_batchbuffer(struct drm_device *dev, void *data, 1104239375Skib struct drm_file *file_priv); 1105239375Skibint i915_cmdbuffer(struct drm_device *dev, void *data, 1106239375Skib struct drm_file *file_priv); 1107239375Skibint i915_getparam(struct drm_device *dev, void *data, 1108239375Skib struct drm_file *file_priv); 1109277487Skibvoid i915_update_dri1_breadcrumb(struct drm_device *dev); 1110235783Skibextern void i915_kernel_lost_context(struct drm_device * dev); 1111235783Skibextern int i915_driver_load(struct drm_device *, unsigned long flags); 1112235783Skibextern int i915_driver_unload(struct drm_device *); 1113235783Skibextern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1114235783Skibextern void i915_driver_lastclose(struct drm_device * dev); 1115235783Skibextern void i915_driver_preclose(struct drm_device *dev, 1116235783Skib struct drm_file *file_priv); 1117235783Skibextern void i915_driver_postclose(struct drm_device *dev, 1118235783Skib struct drm_file *file_priv); 1119235783Skibextern int i915_driver_device_is_agp(struct drm_device * dev); 1120235783Skibextern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1121235783Skib unsigned long arg); 1122235783Skibextern int i915_emit_box(struct drm_device *dev, 1123287177Sbapt struct drm_clip_rect *box, 1124287177Sbapt int DR1, int DR4); 1125235783Skibunsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1126235783Skibunsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1127235783Skibvoid i915_update_gfx_val(struct drm_i915_private *dev_priv); 1128235783Skibunsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1129235783Skibunsigned long i915_read_mch_val(void); 1130235783Skibbool i915_gpu_raise(void); 1131235783Skibbool i915_gpu_lower(void); 1132235783Skibbool i915_gpu_busy(void); 1133235783Skibbool i915_gpu_turbo_disable(void); 1134235783Skib 1135235783Skib/* i915_irq.c */ 1136235783Skibextern int i915_irq_emit(struct drm_device *dev, void *data, 1137235783Skib struct drm_file *file_priv); 1138235783Skibextern void intel_irq_init(struct drm_device *dev); 1139235783Skib 1140235783Skibvoid intel_enable_asle(struct drm_device *dev); 1141235783Skibvoid i915_hangcheck_elapsed(void *context); 1142235783Skibvoid i915_handle_error(struct drm_device *dev, bool wedged); 1143277487Skibvoid i915_error_state_free(struct drm_i915_error_state *error); 1144235783Skib 1145235783Skibvoid i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1146235783Skibvoid i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1147235783Skib 1148235783Skibvoid i915_destroy_error_state(struct drm_device *dev); 1149235783Skib 1150235783Skib/* i915_gem.c */ 1151235783Skibint i915_gem_init_ioctl(struct drm_device *dev, void *data, 1152235783Skib struct drm_file *file_priv); 1153235783Skibint i915_gem_create_ioctl(struct drm_device *dev, void *data, 1154235783Skib struct drm_file *file_priv); 1155235783Skibint i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1156235783Skib struct drm_file *file_priv); 1157235783Skibint i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1158235783Skib struct drm_file *file_priv); 1159235783Skibint i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1160235783Skib struct drm_file *file_priv); 1161235783Skibint i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1162235783Skib struct drm_file *file_priv); 1163235783Skibint i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1164235783Skib struct drm_file *file_priv); 1165235783Skibint i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1166235783Skib struct drm_file *file_priv); 1167235783Skibint i915_gem_execbuffer(struct drm_device *dev, void *data, 1168235783Skib struct drm_file *file_priv); 1169235783Skibint i915_gem_execbuffer2(struct drm_device *dev, void *data, 1170235783Skib struct drm_file *file_priv); 1171235783Skibint i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1172235783Skib struct drm_file *file_priv); 1173235783Skibint i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1174235783Skib struct drm_file *file_priv); 1175235783Skibint i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1176235783Skib struct drm_file *file_priv); 1177235783Skibint i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1178235783Skib struct drm_file *file_priv); 1179235783Skibint i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1180235783Skib struct drm_file *file_priv); 1181235783Skibint i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1182235783Skib struct drm_file *file_priv); 1183235783Skibint i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1184235783Skib struct drm_file *file_priv); 1185235783Skibint i915_gem_set_tiling(struct drm_device *dev, void *data, 1186235783Skib struct drm_file *file_priv); 1187235783Skibint i915_gem_get_tiling(struct drm_device *dev, void *data, 1188235783Skib struct drm_file *file_priv); 1189235783Skibint i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1190235783Skib struct drm_file *file_priv); 1191235783Skibvoid i915_gem_load(struct drm_device *dev); 1192235783Skibvoid i915_gem_unload(struct drm_device *dev); 1193235783Skibint i915_gem_init_object(struct drm_gem_object *obj); 1194235783Skibvoid i915_gem_free_object(struct drm_gem_object *obj); 1195235783Skibint i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1196235783Skib bool map_and_fenceable); 1197235783Skibvoid i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1198235783Skibint i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1199235783Skibvoid i915_gem_lastclose(struct drm_device *dev); 1200235783Skibuint32_t i915_get_gem_seqno(struct drm_device *dev); 1201235783Skib 1202277487Skibstatic inline bool 1203235783Skibi915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1204235783Skib{ 1205235783Skib if (obj->fence_reg != I915_FENCE_REG_NONE) { 1206235783Skib struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1207235783Skib dev_priv->fence_regs[obj->fence_reg].pin_count++; 1208277487Skib return true; 1209277487Skib } else 1210277487Skib return false; 1211235783Skib} 1212235783Skib 1213235783Skibstatic inline void 1214235783Skibi915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1215235783Skib{ 1216235783Skib if (obj->fence_reg != I915_FENCE_REG_NONE) { 1217235783Skib struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1218235783Skib dev_priv->fence_regs[obj->fence_reg].pin_count--; 1219235783Skib } 1220235783Skib} 1221235783Skib 1222235783Skibvoid i915_gem_retire_requests(struct drm_device *dev); 1223235783Skibvoid i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1224235783Skibvoid i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1225235783Skibstruct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1226235783Skib size_t size); 1227235783Skibuint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1228235783Skib uint32_t size, int tiling_mode); 1229235783Skibint i915_mutex_lock_interruptible(struct drm_device *dev); 1230235783Skibint i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1231235783Skib bool write); 1232277487Skibint i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, 1233277487Skib bool write); 1234235783Skibint i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1235235783Skib u32 alignment, struct intel_ring_buffer *pipelined); 1236277487Skibvoid i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 1237235783Skibint i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1238235783Skibint i915_gem_flush_ring(struct intel_ring_buffer *ring, 1239235783Skib uint32_t invalidate_domains, uint32_t flush_domains); 1240235783Skibvoid i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1241277487Skibint i915_gem_object_sync(struct drm_i915_gem_object *obj, 1242277487Skib struct intel_ring_buffer *to); 1243235783Skibint i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1244235783Skibint i915_gem_idle(struct drm_device *dev); 1245277487Skibint i915_gem_init(struct drm_device *dev); 1246235783Skibint i915_gem_init_hw(struct drm_device *dev); 1247235783Skibvoid i915_gem_init_swizzling(struct drm_device *dev); 1248235783Skibvoid i915_gem_init_ppgtt(struct drm_device *dev); 1249235783Skibvoid i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1250277487Skibint i915_gpu_idle(struct drm_device *dev); 1251235783Skibvoid i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1252235783Skib struct intel_ring_buffer *ring, uint32_t seqno); 1253235783Skibint i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1254235783Skib struct drm_i915_gem_request *request); 1255277487Skibint i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1256235783Skibvoid i915_gem_reset(struct drm_device *dev); 1257277487Skibint i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno); 1258235783Skibint i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1259235783Skibint i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1260235783Skib uint64_t *phys); 1261235783Skibvoid i915_gem_release(struct drm_device *dev, struct drm_file *file); 1262235783Skibint i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1263235783Skib enum i915_cache_level cache_level); 1264235783Skib 1265271705Sdumbbell/* i915_gem_context.c */ 1266271705Sdumbbellvoid i915_gem_context_init(struct drm_device *dev); 1267271705Sdumbbellvoid i915_gem_context_fini(struct drm_device *dev); 1268271705Sdumbbellvoid i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1269271705Sdumbbellint i915_switch_context(struct intel_ring_buffer *ring, 1270271705Sdumbbell struct drm_file *file, int to_id); 1271271705Sdumbbellint i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1272271705Sdumbbell struct drm_file *file); 1273271705Sdumbbellint i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1274271705Sdumbbell struct drm_file *file); 1275271705Sdumbbell 1276235783Skibvoid i915_gem_free_all_phys_object(struct drm_device *dev); 1277235783Skibvoid i915_gem_detach_phys_object(struct drm_device *dev, 1278235783Skib struct drm_i915_gem_object *obj); 1279235783Skibint i915_gem_attach_phys_object(struct drm_device *dev, 1280235783Skib struct drm_i915_gem_object *obj, int id, int align); 1281235783Skib 1282235783Skibint i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1283235783Skib struct drm_mode_create_dumb *args); 1284235783Skibint i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1285235783Skib uint32_t handle, uint64_t *offset); 1286235783Skibint i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1287235783Skib uint32_t handle); 1288235783Skib 1289235783Skib/* i915_gem_tiling.c */ 1290235783Skibvoid i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1291235783Skibvoid i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1292235783Skibvoid i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1293277487Skibvoid i915_gem_object_do_bit_17_swizzle_page(struct drm_i915_gem_object *obj, 1294277487Skib struct vm_page *m); 1295235783Skib 1296235783Skib/* i915_gem_evict.c */ 1297235783Skibint i915_gem_evict_something(struct drm_device *dev, int min_size, 1298235783Skib unsigned alignment, bool mappable); 1299235783Skibint i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1300235783Skib 1301277487Skib/* i915_gem_stolen.c */ 1302277487Skibint i915_gem_init_stolen(struct drm_device *dev); 1303277487Skibvoid i915_gem_cleanup_stolen(struct drm_device *dev); 1304277487Skib 1305235783Skib/* i915_suspend.c */ 1306235783Skibextern int i915_save_state(struct drm_device *dev); 1307235783Skibextern int i915_restore_state(struct drm_device *dev); 1308235783Skib 1309235783Skib/* intel_iic.c */ 1310235783Skibextern int intel_setup_gmbus(struct drm_device *dev); 1311235783Skibextern void intel_teardown_gmbus(struct drm_device *dev); 1312235783Skibextern void intel_gmbus_set_speed(device_t idev, int speed); 1313235783Skibextern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1314235783Skibextern void intel_iic_reset(struct drm_device *dev); 1315277487Skibstatic inline bool intel_gmbus_is_port_valid(unsigned port) 1316277487Skib{ 1317277487Skib return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1318277487Skib} 1319277487Skibextern device_t intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 1320277487Skib unsigned port); 1321235783Skib 1322235783Skib/* intel_opregion.c */ 1323235783Skibint intel_opregion_setup(struct drm_device *dev); 1324270516Sadrianextern void intel_opregion_init(struct drm_device *dev); 1325235783Skibextern void intel_opregion_fini(struct drm_device *dev); 1326270516Sadrianextern void intel_opregion_asle_intr(struct drm_device *dev); 1327270516Sadrianextern void intel_opregion_gse_intr(struct drm_device *dev); 1328270516Sadrianextern void intel_opregion_enable_asle(struct drm_device *dev); 1329235783Skib 1330235783Skib/* i915_gem_gtt.c */ 1331235783Skibint i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1332235783Skibvoid i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1333235783Skibvoid i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1334235783Skib struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1335235783Skibvoid i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1336235783Skib struct drm_i915_gem_object *obj); 1337235783Skib 1338235783Skibvoid i915_gem_restore_gtt_mappings(struct drm_device *dev); 1339277487Skibint i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1340277487Skibvoid i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1341277487Skib enum i915_cache_level cache_level); 1342235783Skibvoid i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1343277487Skibvoid i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1344277487Skibint i915_gem_init_global_gtt(struct drm_device *dev, unsigned long start, 1345277487Skib unsigned long mappable_end, unsigned long end); 1346235783Skib 1347235783Skib/* modesetting */ 1348277487Skibextern void intel_modeset_init_hw(struct drm_device *dev); 1349235783Skibextern void intel_modeset_init(struct drm_device *dev); 1350235783Skibextern void intel_modeset_gem_init(struct drm_device *dev); 1351235783Skibextern void intel_modeset_cleanup(struct drm_device *dev); 1352235783Skibextern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1353235783Skibextern void intel_disable_fbc(struct drm_device *dev); 1354235783Skibextern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1355235783Skibextern void ironlake_init_pch_refclk(struct drm_device *dev); 1356235783Skibextern void ironlake_enable_rc6(struct drm_device *dev); 1357235783Skibextern void gen6_set_rps(struct drm_device *dev, u8 val); 1358235783Skibextern void intel_detect_pch(struct drm_device *dev); 1359235783Skibextern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1360277487Skib/* IPS */ 1361277487Skibextern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 1362277487Skibextern void intel_gpu_ips_teardown(void); 1363235783Skib 1364277487Skibextern bool i915_semaphore_is_enabled(struct drm_device *dev); 1365235783Skibextern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1366235783Skibextern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1367235783Skibextern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1368235783Skibextern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1369235783Skib 1370277487Skibextern void vlv_force_wake_get(struct drm_i915_private *dev_priv); 1371277487Skibextern void vlv_force_wake_put(struct drm_i915_private *dev_priv); 1372277487Skib 1373235783Skibextern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1374235783Skib struct drm_device *dev); 1375235783Skibextern void intel_overlay_print_error_state(struct sbuf *m, 1376235783Skib struct intel_overlay_error_state *error); 1377235783Skibextern struct intel_display_error_state *intel_display_capture_error_state( 1378235783Skib struct drm_device *dev); 1379235783Skibextern void intel_display_print_error_state(struct sbuf *m, 1380235783Skib struct drm_device *dev, struct intel_display_error_state *error); 1381235783Skib 1382235783Skibstatic inline void 1383235783Skibtrace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1384235783Skib{ 1385235783Skib 1386235783Skib CTR4(KTR_DRM_REG, "[%x/%d] %c %x", reg, sz, rw ? "w" : "r", val); 1387235783Skib} 1388235783Skib 1389235783Skib/* On SNB platform, before reading ring registers forcewake bit 1390235783Skib * must be set to prevent GT core from power down and stale values being 1391235783Skib * returned. 1392235783Skib */ 1393235783Skibvoid gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1394235783Skibvoid gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1395235783Skibint __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1396235783Skib 1397235783Skib#define __i915_read(x, y) \ 1398235783Skib u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1399235783Skib 1400235783Skib__i915_read(8, 8) 1401235783Skib__i915_read(16, 16) 1402235783Skib__i915_read(32, 32) 1403235783Skib__i915_read(64, 64) 1404235783Skib#undef __i915_read 1405235783Skib 1406235783Skib#define __i915_write(x, y) \ 1407235783Skib void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1408235783Skib 1409235783Skib__i915_write(8, 8) 1410235783Skib__i915_write(16, 16) 1411235783Skib__i915_write(32, 32) 1412235783Skib__i915_write(64, 64) 1413235783Skib#undef __i915_write 1414235783Skib 1415235783Skib#define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1416235783Skib#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1417235783Skib 1418235783Skib#define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1419235783Skib#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1420235783Skib#define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1421235783Skib#define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1422235783Skib 1423235783Skib#define I915_READ(reg) i915_read32(dev_priv, (reg)) 1424235783Skib#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1425235783Skib#define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1426235783Skib#define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1427235783Skib 1428235783Skib#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1429235783Skib#define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1430235783Skib 1431235783Skib#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1432235783Skib#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1433235783Skib 1434235783Skib#define I915_VERBOSE 0 1435235783Skib 1436235783Skib/** 1437235783Skib * Reads a dword out of the status page, which is written to from the command 1438235783Skib * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1439235783Skib * MI_STORE_DATA_IMM. 1440235783Skib * 1441235783Skib * The following dwords have a reserved meaning: 1442235783Skib * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1443235783Skib * 0x04: ring 0 head pointer 1444235783Skib * 0x05: ring 1 head pointer (915-class) 1445235783Skib * 0x06: ring 2 head pointer (915-class) 1446235783Skib * 0x10-0x1b: Context status DWords (GM45) 1447235783Skib * 0x1f: Last written status offset. (GM45) 1448235783Skib * 1449235783Skib * The area from dword 0x20 to 0x3ff is available for driver usage. 1450235783Skib */ 1451235783Skib#define I915_GEM_HWS_INDEX 0x20 1452235783Skib 1453235783Skib#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1454235783Skib 1455235783Skib#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1456235783Skib#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1457235783Skib#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1458235783Skib#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1459235783Skib#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1460235783Skib#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1461235783Skib#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1462235783Skib#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1463235783Skib#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1464235783Skib#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1465235783Skib#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1466235783Skib#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1467235783Skib#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1468235783Skib#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1469235783Skib#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1470235783Skib#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1471235783Skib#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1472235783Skib#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1473235783Skib#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1474277487Skib#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1475277487Skib#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1476235783Skib#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1477235783Skib 1478235783Skib/* XXXKIB LEGACY */ 1479235783Skib#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1480235783Skib (dev)->pci_device == 0x2982 || \ 1481235783Skib (dev)->pci_device == 0x2992 || \ 1482235783Skib (dev)->pci_device == 0x29A2 || \ 1483235783Skib (dev)->pci_device == 0x2A02 || \ 1484235783Skib (dev)->pci_device == 0x2A12 || \ 1485235783Skib (dev)->pci_device == 0x2A42 || \ 1486235783Skib (dev)->pci_device == 0x2E02 || \ 1487235783Skib (dev)->pci_device == 0x2E12 || \ 1488235783Skib (dev)->pci_device == 0x2E22 || \ 1489235783Skib (dev)->pci_device == 0x2E32) 1490235783Skib 1491235783Skib#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1492235783Skib 1493235783Skib#define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1494235783Skib#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1495235783Skib#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1496235783Skib 1497235783Skib#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1498235783Skib IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1499235783Skib/* XXXKIB LEGACY END */ 1500235783Skib 1501235783Skib#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1502235783Skib#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1503235783Skib#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1504235783Skib#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1505235783Skib#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1506235783Skib#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1507235783Skib 1508235783Skib#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1509235783Skib#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1510235783Skib#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1511235783Skib#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1512235783Skib 1513271705Sdumbbell#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1514235783Skib#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1515235783Skib 1516235783Skib#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1517235783Skib#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1518235783Skib 1519235783Skib/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1520235783Skib * rows, which changed the alignment requirements and fence programming. 1521235783Skib */ 1522235783Skib#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1523235783Skib IS_I915GM(dev))) 1524235783Skib#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1525235783Skib#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1526235783Skib#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1527235783Skib#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1528235783Skib#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1529235783Skib#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1530235783Skib/* dsparb controlled by hw only */ 1531235783Skib#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1532235783Skib 1533235783Skib#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1534235783Skib#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1535235783Skib#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1536235783Skib 1537277487Skib#define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split) 1538235783Skib#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1539235783Skib 1540235783Skib#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1541277487Skib#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1542235783Skib#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1543235783Skib#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1544235783Skib 1545235783Skib#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1546235783Skib 1547235783Skibstatic inline bool 1548235783Skibi915_seqno_passed(uint32_t seq1, uint32_t seq2) 1549235783Skib{ 1550235783Skib 1551235783Skib return ((int32_t)(seq1 - seq2) >= 0); 1552235783Skib} 1553235783Skib 1554277487Skibstatic inline void i915_gem_chipset_flush(struct drm_device *dev) 1555277487Skib{ 1556277487Skib if (INTEL_INFO(dev)->gen < 6) 1557277487Skib intel_gtt_chipset_flush(); 1558277487Skib} 1559277487Skib 1560277487Skibstatic inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1561277487Skib{ 1562277487Skib /* KASSERT(obj->pages != NULL, ("pin and NULL pages")); */ 1563277487Skib obj->pages_pin_count++; 1564277487Skib} 1565277487Skibstatic inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1566277487Skib{ 1567277487Skib KASSERT(obj->pages_pin_count != 0, ("zero pages_pin_count")); 1568277487Skib obj->pages_pin_count--; 1569277487Skib} 1570277487Skib 1571235783Skibu32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1572235783Skib 1573235783Skib#endif 1574